A task scheduling and resource allocation method for homogeneous multi-FPGA system

Abstract

The application discloses a task scheduling and resource allocation method for a homogeneous multi-FPGA system, and belongs to the technical field of multi-FPGA system application. The method firstly models the homogeneous multi-FPGA system and a system task to be executed; then preliminarily determines data transmission time DTT between tasks according to a communication bandwidth and a data volume; then establishes a node sequence list based on key nodes on a key path of a task graph; further divides nodes in the sequence list into slots under the limitation of a single FPGA resource, and constructs a directed acyclic graph based on the slots; finally determines a final execution position of the slots and calculates a time parameter, and obtains an optimal FPGA usage quantity. The application designs a performance-balanced scheduling scheme for the problem of inefficient task scheduling and unreasonable resource configuration of the homogeneous multi-FPGA system, and improves the resource utilization rate of the FPGA while maximizing the execution speed of a complex task.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of multi-FPGA system application, and particularly relates to a task scheduling and resource allocation method for a homogeneous multi-FPGA system. BACKGROUND

[0002] Field Programmable Gate Array (FPGA) is widely used due to its high performance, low power consumption and reconfigurable characteristics. The traditional single-FPGA system has limited resources, and is often insufficient when accelerating complex tasks. Therefore, multi-FPGA systems, especially homogeneous multi-systems composed of multiple FPGAs of the same type, are increasingly attracting attention. Multi-FPGA systems have a high degree of execution parallelism, allowing a group of multiple tasks to be executed in parallel on one FPGA, and allowing multiple groups of tasks to be executed in parallel on multiple FPGAs, thereby greatly improving the execution speed of complex tasks.

[0003] In a multi-FPGA system, it is urgent to design an efficient task scheduling and resource allocation scheme to fully utilize the resource parallelism of the FPGA and improve the resource utilization rate of the FPGA while maximizing the execution speed of complex tasks. However, most of the existing research on multi-FPGA system task scheduling and resource allocation focuses on how to save communication time and how to locally utilize high-delay tasks to hide the execution time of low-delay tasks, without fully utilizing the resource parallelism of the FPGA. A few research works utilize heuristic methods to group tasks, but the resource utilization rate of the FPGA is low, and there are problems of long algorithm running time or high hardware resource vacancy rate. In view of the above problems, the present application proposes a task scheduling and resource allocation method for a homogeneous multi-FPGA system.

[0004] FPGA system. SUMMARY

[0005] The present application aims to solve the above problems and deficiencies, and proposes a task scheduling and resource allocation method for a homogeneous multi-FPGA system. Based on modeling of the multi-FPGA system and the system tasks to be executed, the present application designs a scheme for grouping and scheduling the system tasks and allocating resources based on critical path nodes and FPGA resource constraints according to the communication dependency relationship between the tasks, to realize fast and efficient task scheduling on the multi-FPGA system.

[0006] To achieve the above purpose, the technical scheme adopted by the present application is as follows: a task scheduling and resource allocation method for a homogeneous multi-FPGA system, characterized by comprising the following steps:

[0007] (1) using F = {F1, F2,..., F m} Describe a multi-FPGA system consisting of m homogeneous FPGAs, and use FC = {RB, RC, RD, BW} to describe the characteristics of each FPGA, where RB, RC and RD are the number of BRAM, CLB and DSP resources in each FPGA, respectively, and BW is the communication bandwidth of the FPGA.

[0008] (2) Consider a set of n tasks to be executed, T = {T1, T2, ..., T...} n The system task is modeled as a directed acyclic graph G = (N, E): using N = {N T1 N T2 , ..., N Tn} Describes the set of nodes, N Ti ={ET Ti B Ti C Ti D Ti Data Ti Describe the i-th node T i Features of ET Ti For node T i Execution time in FPGA, B Ti C Ti and D Ti They are nodes T respectively i The number of BRAMs, CLBs, and DSPs required for execution in the FPGA, Data Ti For node T i The amount of output data; using E = {E T1 E T2 , ..., E T(n-1) Describe the edge set, E Ti ={E Ti-Tj1 E Ti-Tj2 , ..., E Ti-Tjr} represents node T i A set of r feedforward directed edges, where E Ti-Tjt (1≤t≤r) represents node T i To node T jt The feedforward directed edge.

[0009] (3) Calculate the weight DTT of each feedforward directed edge in the edge set E mentioned in step (2). Ti-Tj Using DTT Ti-Tj Describe node T in the task graph G. i and T i The communication time between them, as T i To T j Feedforward directed edge E Ti-Tj The weights, and based on task T i Output data volume TiDetermining the FPGA communication bandwidth (BW) and DTT Ti-Ti Value: DTT Ti-Tj =Data Ti / BW;

[0010] (4) In the task graph G described in step (2), based on the node feature N Ti The weights DTT of each feedforward directed edge described in step (3) Ti-Tj The key nodes are determined using a key node search algorithm based on the earliest and latest start times, and a node order list is built with the key nodes as the backbone.

[0011] (5) Based on the task graph G described in step (2) and the node sequence list described in step (4), with the number of individual FPGA resources as a constraint, divide all nodes into several task groups slots to be scheduled, and create a directed acyclic graph based on slots.

[0012] (6) In the slot-based directed acyclic graph described in step (5), determine which FPGA to place each slot on and the optimal number of FPGAs to use.

[0013] Furthermore, the specific implementation method of step (4) is as follows:

[0014] (4.1) In the task graph G described in step (2), the earliest start time of each node is calculated sequentially starting from the source node: the earliest start time EST of the source node T1. T1 =0, and any other node T i If there are p parent nodes, then its earliest start time EST Ti =max{EST Tx +ET Tx +DTT Tx-Ti}| 1≤x≤p ;

[0015] (4.2) Calculate the critical path length of the task graph G mentioned in step (2): CPL = max{EST} Ty +ET Ty}| 0＜y≤n ;

[0016] (4.3) In the task graph G described in step (2), the latest start time of each node is calculated sequentially, starting from the sink node: Sink node T n Latest start time LST Tn =CPL-ET Tn If any other node Ti has q child nodes, then its latest start time is LST. Ti =min{LST Tz -ET Ti -DTTTi-Tz}| 1≤z≤q ;

[0017] (4.4) In the task graph G described in step (2), determine whether each node is a critical node in turn from the source node: for any node T i , if EST Ti = LST Ti , then T i is a critical node, and it is put into the critical node order list; otherwise, T i is not a critical node, and no processing is performed.

[0018] (4.5) In the task graph G described in step (2), using the postorder traversal method, search the parent node branch of each critical node in the critical node order list described in step (4.4) in the order of left subtree-root node-right subtree, and insert it before the critical node in the critical node order list after the previous critical node, to obtain a node order list.

[0019] Further, the specific implementation method of step (5) is as follows:

[0020] (5.1) In the node order list described in step (4.5), divide the node order list into several segments with critical nodes as the dividing points, and each segment contains a critical node and its parent node branch.

[0021] (5.2) Divide each critical node and its parent node branch in each segment described in step (5.1) into several slots according to the list order, and ensure that the total amount of resources of all nodes contained in each slot is not greater than the total amount of resources of a single FPGA: if the kth slot contains s task nodes {T k1 , T k2 ,..., T ks}, then

[0022] (5.3) Find slots with higher resource vacancy rates in all slots, and try to merge slots with higher resource vacancy rates located in the same level or adjacent levels of the task graph G on the premise that the total amount of resources of all nodes contained in each slot is not greater than the total amount of resources of a single FPGA.

[0023] (5.4) According to the feedforward directed edge dependency relationship in the task graph G described in step (2), arrange the dependency relationship between the slots after merging in step (5.3), and create a slot-based directed acyclic graph taking slots as nodes.

[0024] Further, the specific implementation method of step (6) is as follows:

[0025] (6.1) Determine which FPGA each slot in the slot-based DAG described in step (5.4) is placed on: when using l (2≤l≤m) FPGAs, place the parallel slots with common predecessors but not predecessors / successors of each other on different FPGAs in turn, and place the remaining slots on other FPGAs in turn according to the execution order; after the l FPGAs are placed, start placing from the first FPGA again;

[0026] (6.2) According to the placement result described in step (6.1), determine the scheduling order in the execution process, and calculate the start and end time of each slot to obtain the maximum completion time Makespan when using l FPGAs;

[0027] (6.3) Change the size of l, repeat steps (6.1) and (6.2), traverse the results when scheduling using different numbers of FPGAs within the maximum number of FPGAs m, and determine the optimal number of FPGAs when the Makespan is the smallest. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 Flowchart of the method described in the present application

[0029] Figure 2 DAG of tasks to be executed

[0030] Figure 3 Slot-based DAG

[0031] Figure 4 Slot scheduling and resource allocation diagram DETAILED DESCRIPTION

[0032] The embodiments of the present application will be described in detail below. The embodiments are exemplary and are used to explain the present application, and cannot be understood as limiting the present application. Referring to the drawings accompanying the specification, a method for task scheduling and resource allocation in a homogeneous multi-FPGA system is described in detail below. As shown in Figure 1 The embodiments of the present application are directed to a task scheduling and resource allocation method for a reconfigurable multi-FPGA platform, which includes the following steps.

[0033] (1) Use F={F1, F2,..., Fm} to describe a multi-FPGA system composed of m homogeneous FPGAs, and use FC={RB, RC, RD, BW} to describe the characteristics of each FPGA, where RB, RC and RD are the number of BRAM, CLB and DSP resources in each FPGA, and BW is the communication bandwidth of the FPGA. m

[0034] ​Taking a multi-FPGA system F = {F1, F2, F3, F4} consisting of four Xilinx XC7K325s as an example, each FPGA contains 26150, 900, and 840 BRAM, CLB, and DSP resources, respectively. Assuming its communication bandwidth is 1000kB / s, it can be modeled using FC = {26150, 900, 840, 1000}.

[0035] (2) Consider a set of n tasks to be executed, T = {T1, T2, ..., T...} n The system task is modeled as a directed acyclic graph G = (N, E): using N = {N T1 N T2 , ..., N Tn} Describes the set of nodes, N Ti ={ET Ti B Ti C Ti D Ti Data Ti Describe the i-th node T i Features of ET Ti For node T i Execution time in FPGA, B Ti C Ti and D Ti They are nodes T respectively i The number of BRAMs, CLBs, and DSPs required for execution in the FPGA, Data Ti The output data volume of node Ti; using E = {E T1 E T2 , ..., E T(n-1) Describe the edge set, E Ti ={E Ti-Tj1 E Ti-Tj2， , ..., E Ti-Tjr} represents node T i A set of r feedforward directed edges, where E Ti-Tjt (1≤t≤r) represents node T i To node T jt The feedforward directed edge.

[0036] by Figure 2 The diagram shows 12 tasks to be executed, T = {T1, T2, ..., T...} 12 Taking the system task as an example, assume that the characteristics of each node in its node set are as follows: N T1 ={280, 250, 9150, 170, 140}, N T2 ={140, 410, 2715, 250, 20}, N T3={160, 220, 1710, 80, 20}, N T4 ={180, 320, 14450, 100, 30}, N T5 ={630, 310, 4192, 110, 90}, N T6 ={280, 240, 1080, 220, 40}, N T7 ={1360, 50, 8450, 360, 170}, N T8 ={360, 200, 8110, 270, 70}, N T9 ={1710, 60, 9725, 400, 190}, N T10 ={600, 230, 7500, 260, 150}, N T11 ={420, 140, 4815, 20, 90}, N T12 ={40, 460, 13900, 40, 0}, where the execution time is in milliseconds and the output data size is in kB; the feedforward directed edge set for each node in its edge set is as follows: E T1 ={E T1-T2 E T1-T3 E T1-T4 E T1-T5 E T1-T6}, E T2 ={E T2-T7}, E T3 ={E T3-T7}, E T4 ={E T4-T8}, E T5 ={E T5-T9}, E T6 ={E T6-T 9}, E T7 ={E T7-T10}, E T8 ={E T8-T10}, E T9 ={E T9-T10 E T9-T11}, E T10 ={E T10-T12}, E T11 ={E T11-T12}

[0037] (3) Calculate the weight DTT of each feedforward directed edge in the edge set E mentioned in step (2). Ti-Tj Using DTT Ti-Tj Describe node T in the task graph G. i and T j The communication time between them, as T i To T i Feedforward directed edge ETi-Tj The weights, and based on task T i Output data volume Ti Determining the FPGA communication bandwidth (BW) and DTT Ti-Tj Value: DTT Ti-Tj =Data Ti / BW.

[0038] like, Figure 2 In the edge set E of the task graph G shown, the feedforward directed edge set E originating from node T1 is... T1 ={E T1-T2 E T1-T3 E T1-T4 E T1-T5 E T1-T6 The weight of} is: DTT T1-Tj|j＝2，3，4，5，6 =Data T1 / BW=140 / 1000=0.14s=140ms; Similarly, the weights of the feedforward directed edge set starting from other nodes are DTT={20, 20, 30, 90, 40, 170, 70, 190, 150, 90, 0}.

[0039] (4) In the task graph G described in step (2), based on the node feature N Ti The weights DTT of each feedforward directed edge described in step (3) Ti-Tj The critical nodes are determined using a critical node search algorithm based on the earliest and latest start times, and a node order list is built with the critical nodes as the backbone.

[0040] (4.1) In the task graph G described in step (2), the earliest start time of each node is calculated sequentially starting from the source node: the earliest start time EST of the source node T1. T1 =0, and any other node T i If there are p parent nodes, then its earliest start time EST Ti =max{EST Tx +ET Tx +DTT Tx-Ti}| 1≤x≤p .

[0041] Figure 2 In the task graph G shown, EST T1 =0; Node T2 has 1 parent node T1, whose earliest start time EST T2 =420; and so on, the earliest start time of the remaining nodes are EST. T3 =420, EST T4 =420, EST T5 =420, EST T6 =420, ESTT7 =600, EST T8 =630, EST T9 =1140, EST T10 =3040, EST T11 =3040, EST T12 =3790.

[0042] (4.2) Calculate the critical path length of the task graph G mentioned in step (2): CPL = max{EST} Ty +ET Ty}| 0＜y≤n .

[0043] Figure 2 The critical path length CPL of the task graph G shown is CPL = max{EST} Ty +ET Ty}| 0＜y≤12 =3790+40=3830.

[0044] (4.3) In the task graph G described in step (2), the latest start time of each node is calculated sequentially, starting from the sink node: Sink node T n Latest start time LST Tn =CPL-ET Tn any other node T i If there are q child nodes, then their latest start time is LST. Ti =min{LST Tz -ET Ti -DTT Ti-Tz}| 1≤z≤q .

[0045] Figure 2 In the task graph G shown, the sink node T 12 Latest start time EST T12 =CPL-ET T12 =3790, node T 11 There is 1 child node T 12 Its latest start time is LST T11 =3280; the latest start time of the remaining nodes is LST respectively. T10 =3040, LST T9 =1140, LST T8 =2610, LST T7 =1510, LST T6 =820, LST T5 =420, LST T4 =2400, LST T3 =1330, LST T2 =1350, LSTT1 = 0.

[0046] (4.4) In the task graph G described in step (2), determine whether each node is a critical node in turn from the source node: for any node T i , if EST Ti = LST Ti , then T i is a critical node, and put it into the critical node order list; otherwise, T i is not a critical node, and do not process it.

[0047] Figure 2 In the task graph G shown in Fig. 1, for node T1, EST T1 = LST T1 , so T1 is a critical node, and put it into the critical node order list; for node T2, EST T2 ≠ LST T2 , so T2 is not a critical node, and do not process it; and so on, and finally the critical node order list obtained is {1, 5, 9, 10, 12}.

[0048] (4.5) In the task graph G described in step (2), using the postorder traversal method, search the parent node branch of each critical node in the critical node order list described in step (4.4) in the order of left subtree-root node-right subtree, and insert it before the critical node in the critical node order list after the previous critical node, to obtain the node order list.

[0049] Figure 2 In the task graph G shown in Fig. 1, the critical node T 10 has two parent nodes T7 and T8, of which T7 has two parent nodes T2 and T3, and T8 has one parent node T4, and the parent node branch obtained after traversal search is {2, 3, 7, 4, 8}, which is inserted before the critical node T 10 after the critical node T9; and so on, and finally the node order list obtained is {1, 5, 6, 9, 2, 3, 7, 4, 8, 10, 11, 12}.

[0050] (5) According to the task graph G described in step (2) and the node order list described in step (4), divide all nodes into a plurality of to-be-scheduled task groups slots with the number of single FPGA resources as a constraint, and create a directed acyclic graph based on the slots.

[0051] (5.1) In the node order list described in step (4.5), divide the node order list into a plurality of segments with the critical node as a demarcation point, and each segment contains a critical node and its parent node branch.

[0052] Take the node sequence list {1, 5, 6, 9, 2, 3, 7, 4, 8, 10, 11, 12} as an example, with 5 key nodes as the demarcation point, it can be divided into 5 segments, respectively {1}, {5}, {6, 9}, {2, 3, 7, 4, 8, 10}, {11, 12}.

[0053] (5.2) Divide each segment of key nodes and its parent node branch according to the list order, and ensure that the total amount of resources contained in each slot does not exceed the total amount of resources of a single FPGA: if the kth slot contains s task nodes {T k1 , T k2 ,..., T ks}, then

[0054] Figure 2 Take the 4th segment {2, 3, 7, 4, 8, 10} of the task graph G as an example, first check whether {2, 3} satisfies the resource limit, if yes, continue to try whether {2, 3, 7} satisfies the resource limit, until {2, 3, 7, 4} exceeds the resource limit, at this time, remove node 4, and divide {2, 3, 7} into a slot. Then continue to check from node 4, {4, 8} satisfies the resource limit, but {4, 8, 10} exceeds, so {4, 8} is divided into a slot, and the last {10} is divided into a slot. In this way, a total of 7 slots are divided, respectively {1}, {5}, {6, 9}, {2, 3, 7}, {4, 8}, {10}, {11, 12}.

[0055] (5.3) Find the slot with higher resource vacancy rate in all slots, and try to merge the slots with higher resource vacancy rate located in the same level or adjacent levels of the task graph G under the premise that the total amount of resources contained in each slot does not exceed the total amount of resources of a single FPGA.

[0056] Take the division result in step (5.2) as an example, remove the source slot, first try to merge slots {5} and {6, 9}, find that after merging, it satisfies the resource limit, so they are merged into a slot {5, 6, 9}; Similarly, {10} and {11, 12} can also be merged into a slot {10, 11, 12}. After merging, a total of 5 slots are obtained, respectively S1={1}, S2={2, 3, 7}, S3={4, 8}, S4={5, 6, 9}, S5={10, 11, 12}.

[0057] (5.4) According to the feed-forward directed edge dependencies in the task graph G in step (2), the dependencies between the slots after merging in step (5.3) are arranged to create a slot-based directed acyclic graph with slots as nodes.

[0058] According to the feed-forward directed edge dependencies in the task graph G in step (2), the dependencies between the slots after merging in step (5.3) are arranged to create a slot-based directed acyclic graph with slots as nodes. Figure 2 Figure 3 According to the feed-forward directed edge dependencies in the task graph G in step (2), the dependencies between the slots after merging in step (5.3) are arranged to create a slot-based directed acyclic graph with slots as nodes.

[0059] (6) In the slot-based directed acyclic graph in step (5), determine which FPGA each slot is placed on for execution and the optimal number of FPGAs used.

[0060] (6.1) Determine which FPGA each slot in the slot-based directed acyclic graph in step (5.4) is placed on for execution: when using l (2≤l≤m) FPGAs, preferentially place parallel slots with common predecessors but not as predecessors / successors on different FPGAs in turn, and place the remaining slots on other FPGAs in execution order; after l FPGAs are placed, start placing from the first FPGA.

[0061] As shown in the slot-based directed acyclic graph, Figure 3 S2, S3, S4 have a common predecessor S1 and are not predecessors / successors of each other, which are parallel slots. When l=3, first assign parallel slots S2 / S3 / S4 to FPGAs 1 / 2 / 3, then assign non-parallel slot S1 to FPGA 1, and finally assign S5 to FPGA 2.

[0062] (6.2) According to the placement results in step (6.1), determine the scheduling order in the execution process and calculate the start and end times of each slot to obtain the maximum completion time Makespan.

[0063] For the slot-based directed acyclic graph shown, Figure 3 According to the placement results in step (6.1), the final scheduling scheme is as follows: Figure 4 ​As shown: first, at time 1, S1 is executed on FPGA1; after S1 is executed, at time 2, S2, S3 and S4 are executed in parallel on FPGA1, FPGA2 and FPGA3 respectively; after the parallel execution is completed, at time 3, S5 is executed on FPGA2. At this time, the start and end times of each slot are S1{0, 280}, S2{280, 1800}, S3{420, 960}, S4{420, 2760} and S5{2950, 3590} respectively. The maximum completion time Makespan = 3590.

[0064] (6.3) Change the size of l, repeat steps (6.1) and (6.2), traverse the results when scheduling using different numbers of FPGAs within the maximum FPGA number m, and determine the optimal FPGA usage number when the Makespan is the smallest.

[0065] For example, the total FPGA number m = 4, after traversal, the Makespan obtained when l = 2, 3 and 4 is recorded as {4060, 3590, 3590}, comparison shows that the minimum Makespan can be obtained when l = 3 and 4, thus the optimal FPGA number is 3.

[0066] The above is only an embodiment of the present application, and does not limit the patent scope of the present application, any equivalent structure or equivalent flow transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for task scheduling and resource allocation for a homogeneous multi-FPGA system, characterized in that, The method comprises the following steps: (1) using F = {F1, F2,..., Fm} to describe a multi-FPGA system composed of m isomorphic FPGAs, and using FC = {RB, RC, RD, BW} to describe the characteristics of each FPGA, where RB, RC and RD are the number of BRAM, CLB and DSP resources in each FPGA, respectively, and BW is the communication bandwidth of the FPGA; m} describes a multi-FPGA system composed of m isomorphic FPGAs, and uses FC = {RB, RC, RD, BW} to describe the characteristics of each FPGA, where RB, RC and RD are the number of BRAM, CLB and DSP resources in each FPGA, respectively, and BW is the communication bandwidth of the FPGA; (2) Consider a set of n tasks to be executed, T = {T1, T2, ..., T...} n The system task is modeled as a directed acyclic graph G = (N, E): using N = {N T1 N T2 ,...,N Tn } Describes the set of nodes, N Ti ={ET Ti B Ti C Ti D Ti DataTi describes the i-th node T i Features of ET Ti For node T i Execution time in FPGA, B Ti C Ti and D Ti They are nodes T respectively i The number of BRAMs, CLBs, and DSPs required for execution in the FPGA, where DataTi is the node T. i The amount of output data; using E = {E T1 E T2 , ..., E T(n-1) Describe the edge set, E Ti ={E Ti-Tj1 E Ti-Tj2 , ..., E Ti-Tjr } represents node T i A set of r feedforward directed edges, where E Ti-Tjt Represents node T i To node T jt The feedforward directed edge, where 1≤t≤r; (3) calculating the weight DTT of each feedforward directed edge in the edge set E described in step (2) Ti-Tj : using DTT Ti-Tj describing the communication time between nodes T i and T j in the task graph G as the weight of the feedforward directed edge E i from T j to T Ti-Tj and determining the value of DTT according to the output data amount DataTi of the task T i and the FPGA communication bandwidth BW: DTT = Data Ti-Tj / BW Ti-Tj = Data Ti / BW; (4) in the task graph G described in step (2), according to the node features N Ti and the weights DTT of each feedforward directed edge described in step (3) Ti-Tj , determine the critical nodes using a critical node search algorithm based on the earliest and latest start times, and establish a node order list with the critical nodes as the backbone; (5) According to the task graph G in step (2) and the node sequence list in step (4), all nodes are divided into a plurality of to-be-scheduled task groups slots with a single FPGA resource quantity as a constraint, and a slot-based directed acyclic graph is created, and the specific method is as follows: (5.1) In the node sequence list in step (4), the node sequence list is divided into a plurality of segments with a key node as a boundary point, and each segment contains a key node and a parent node branch thereof; (5.2) divide the branch of each key node and its parent node in step (5.1) into several slots in list order, and ensure that the total amount of resources of all nodes contained in each slot is not greater than the total amount of single FPGA resources: if the kth slot contains s task nodes {T k1 , T k2 ,..., T ks}, then (5.3) All slots with a high resource vacancy rate are searched, and on the premise that the total resource quantity of all nodes contained in each slot is not greater than the total quantity of a single FPGA resource, slots with a high resource vacancy rate located at the same level or adjacent levels of the task graph G are tried to be combined; (5.4) According to the feedforward directed edge dependency relationship in the task graph G in step (2), the dependency relationship between the slots combined in step (5.3) is arranged, and a slot-based directed acyclic graph taking slots as nodes is created; (6) In the slot-based directed acyclic graph in step (5), it is determined which FPGA each slot is placed on for execution and the optimal FPGA use quantity.

2. The method for task scheduling and resource allocation for homogeneous multi-FPGA system according to claim 1, wherein, In step (4), the key node is determined by using a key node search algorithm based on the earliest and latest start time, and the node sequence list is established with the key node as a main trunk, and the method is as follows: (4.1) In the task graph G described in step (2), the earliest start time of each node is calculated sequentially starting from the source node: the earliest start time EST of the source node T1. T1 =0, and any other node T i If there are p parent nodes, then its earliest start time EST Ti =max{EST Tx +ET Tx +DTT Tx-Ti }| 1≤x≤p ; (4.2) Calculate the critical path length of the task graph G described in step (2): CPL = max{EST Ty + ET Ty}| 0＜y≤n ; (4.3) In the task graph G described in step (2), the latest start time of each node is calculated in turn from the sink node: the latest start time LST of the sink node T n Tn = CPL - ET Tn The latest start time LST of the remaining arbitrary node Ti, if it has q child nodes, is calculated as follows: Ti Tz Ti Ti-Tz 1≤z≤q ;​​​​​ (4.4) In the task graph G described in step (2), judge each node whether it is a critical node in turn from the source node: for any node T i , if EST Ti = LST Ti , then T i is a critical node, put it into the critical node order list; otherwise, T i is not a critical node, do not process it; (4.5) In the task graph G in step (2), a postorder traversal method is adopted, the parent node branch of each key node in the key node sequence list in step (4.4) is searched in the order of left subtree-right subtree-root node, and is inserted into the key node sequence list before the key node and after the previous key node, to obtain a node sequence list.

3. The method for task scheduling and resource allocation for homogeneous multi-FPGA system according to claim 1, wherein, In step (6), the method for determining which FPGA each slot is placed on for execution and the optimal FPGA use quantity is as follows: (6.1) It is determined that, in the slot-based directed acyclic graph in step (5.4), each slot is placed on which FPGA for execution: when l FPGAs are used, wherein 2≤l≤m, parallel slots with a common predecessor slot but without a predecessor / successor relationship are preferentially placed on different FPGAs in turn, and the remaining slots are placed on other FPGAs in turn according to the execution order; after the l FPGAs are placed, the placement is started from the first FPGA; (6.2) According to the placement result in step (6.1), a scheduling sequence in the execution process is determined, and the start and end times of each slot are calculated, to obtain a maximum completion time Makespan when l FPGAs are used; (6.3) The size of l is changed, steps (6.1) and (6.2) are repeated, and the results when different quantities of FPGAs are used within the maximum FPGA quantity m are traversed, to determine the optimal FPGA use quantity when the Makespan is the smallest.

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