Writing circuit, writing method and memory

Abstract

The disclosed embodiments provide a write circuit, a write method, and a memory. In the write circuit, a signal conversion circuit is used to receive an enable signal, a test mode signal, and an initial reset signal, and performs signal conversion processing according to the enable signal, the initial reset signal, and the test mode signal to obtain a first set signal and a first reset signal; a data generation circuit includes multiple shift registers, the multiple shift registers are used to receive the first set signal and the first reset signal, and the initial write data is serially converted and processed according to the multiple shift registers to generate target write data. The initial write data is in a serial state, the target write data is in a parallel state, and the target write data is the write data required by the memory built-in self-test (MBIST), thereby saving chip area and ensuring the timing requirements of compressed write.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a writing circuit, a writing method, and a memory. Background Art

[0002] With the continuous advancement of semiconductor technology, the demand for data transmission speeds in the manufacture and use of devices such as computers is increasing. Taking dynamic random access memory (DRAM) as an example, to ensure the correctness of its storage function, memory testing, such as the memory built-in self-test (MBIST), is required.

[0003] In related art, the process of generating MBIST write data can be to perform serial-to-parallel conversion on the compressed write data and then insert a specific test pattern to set the corresponding data bits to generate the write data required by MBIST. However, this will affect the timing of the compressed write and cause the data write to be delayed. Summary of the Invention

[0004] The present disclosure provides a write circuit, a write method and a memory, which can save chip area and improve the timing constraint condition of writing data during the MBIST test process.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a write circuit, the write circuit including a signal conversion circuit and a data generation circuit, the signal conversion circuit being connected to the data generation circuit, wherein:

[0007] a signal conversion circuit, configured to receive an enable signal, a test mode signal, and an initial reset signal, and perform signal conversion processing according to the enable signal, the initial reset signal, and the test mode signal to obtain a first set signal and a first reset signal;

[0008] The data generation circuit includes a plurality of shift registers, the plurality of shift registers being used to receive a first set signal and a first reset signal, and to serially convert and process the initial write data according to the plurality of shift registers to generate target write data;

[0009] The initial write data is in a serial state, the target write data is in a parallel state, and the target write data is the write data required by MBIST.

[0010] In some embodiments, the signal conversion circuit includes a first conversion sub-circuit and a second conversion sub-circuit, wherein:

[0011] A first conversion sub-circuit is configured to receive a test mode signal, convert the test mode signal, and obtain a first set signal;

[0012] The second conversion sub-circuit is used to receive the enable signal, the test mode signal and the initial reset signal, and convert the test mode signal according to the enable signal and the initial reset signal to obtain a first reset signal.

[0013] In some embodiments, the test mode signal includes a first test mode signal and a second test mode signal, wherein:

[0014] The first conversion sub-circuit is configured to convert the first test mode signal to obtain an even set signal; and convert the second test mode signal to obtain an odd set signal;

[0015] The second conversion subcircuit is used to convert the first test mode signal according to the enable signal and the initial reset signal to obtain an odd reset signal; and to convert the second test mode signal according to the enable signal and the initial reset signal to obtain an even reset signal.

[0016] In some embodiments, the first conversion sub-circuit includes a first NOT gate and a second NOT gate, and the second conversion sub-circuit includes a first NAND gate, a first NOR gate and a second NOR gate; wherein:

[0017] An input end of the first NOT gate is used to receive a first test mode signal, and an output end of the first NOT gate serves as a first output end of the first conversion sub-circuit for outputting an even set signal; an input end of the second NOT gate is used to receive a second test mode signal, and an output end of the second NOT gate serves as a second output end of the first conversion sub-circuit for outputting an odd set signal;

[0018] The first input end of the first NAND gate is used to receive an enable signal, and the second input end of the first NAND gate is used to receive an initial reset signal; the first input end of the first NOR gate is used to receive a first test mode signal, the second input end of the first NOR gate is connected to the output end of the first NAND gate, and the output end of the first NOR gate serves as the first output end of the second conversion sub-circuit for outputting an odd reset signal; the first input end of the second NOR gate is connected to the output end of the first NAND gate, the second input end of the second NOR gate is used to receive a second test mode signal, and the output end of the second NOR gate serves as the second output end of the second conversion sub-circuit for outputting an even reset signal.

[0019] In some embodiments, the second conversion sub-circuit further includes a third NOT gate; wherein:

[0020] The input end of the third NOT gate is connected to the output end of the first NAND gate, and the output end of the third NOT gate serves as the third output end of the second conversion sub-circuit for outputting the second reset signal.

[0021] In some embodiments, the data generation circuit includes a first data sub-circuit and a second data sub-circuit, wherein:

[0022] a first data sub-circuit, configured to, after receiving an odd set signal and an odd reset signal, serially convert and process the first initial write data according to the first clock signal and the second clock signal to generate first target write data;

[0023] a second data sub-circuit, configured to, after receiving an even set signal and an even reset signal, serially convert and process the second initial write data according to the first clock signal and the second clock signal to generate second target write data;

[0024] The first clock signal and the second clock signal are in anti-phase relation to each other, and the target write data is composed of the first target write data and the second target write data.

[0025] In some embodiments, the write circuit further includes a shift delay circuit, wherein:

[0026] The shift delay circuit is used to receive the first initial write data, sample and delay the first initial write data, and obtain the second initial write data.

[0027] In some embodiments, the shift delay circuit includes a sampling submodule and a delay module, wherein:

[0028] a sampling submodule, configured to receive the first initial write data and a third clock signal, and perform sampling and latching processing on the first initial write data according to a rising edge of the third clock signal to obtain sampled write data;

[0029] The delay module is used to perform delay processing on the sampled write data to obtain second initial write data.

[0030] In some embodiments, the sampling submodule includes a latch, and a reset terminal of the latch is used to receive the second reset signal.

[0031] In some embodiments, the delay module is composed of an even number of NOT gates connected in series.

[0032] In some embodiments, when the first test mode signal is in a first level state and the second test mode signal is in a second level state, the second target write data are all in the first level state;

[0033] When the first test mode signal is in the second level state and the second test mode signal is in the first level state, the first target write data are all in the first level state.

[0034] In some embodiments, the first data subcircuit includes at least one shift register, and the second data subcircuit includes at least one shift register; wherein:

[0035] In the first data sub-circuit, a first clock terminal of at least one shift register is used to receive a first clock signal, a second clock terminal of at least one shift register is used to receive a second clock signal, a set terminal of at least one shift register is used to receive an odd-numbered set signal, and a reset terminal of at least one shift register is used to receive an odd-numbered reset signal; an input terminal of the first shift register is used to receive first initial write data, an input terminal of the i-th shift register is connected to an output terminal of the (i-1)-th shift register, and an output terminal of the at least one shift register serves as an output terminal of the first data sub-circuit for outputting first target write data; wherein i is an integer greater than 1;

[0036] In the second data sub-circuit, the first clock end of at least one shift register is used to receive the first clock signal, the second clock end of at least one shift register is used to receive the second clock signal, the set end of at least one shift register is used to receive an even set signal, and the reset end of at least one shift register is used to receive an even reset signal; the input end of the first shift register is used to receive the second initial write data, the input end of the j-th shift register is connected to the output end of the j-1-th shift register, and the output end of at least one shift register serves as the output end of the second data sub-circuit for outputting the second target write data; wherein j is an integer greater than 1.

[0037] In some embodiments, the first target write data includes first bit data, third bit data, fifth bit data, and seventh bit data;

[0038] The first data sub-circuit includes a first shift register, a second shift register, a third shift register and a fourth shift register; wherein:

[0039] The input end of the first shift register is used to receive the first initial write data, the output end of the first shift register is connected to the input end of the second shift register, and the output end of the first shift register is used to output the seventh bit data;

[0040] The input end of the second shift register is used to receive the seventh bit of data, the output end of the second shift register is connected to the input end of the third shift register, and the output end of the second shift register is used to output the fifth bit of data;

[0041] The input end of the third shift register is used to receive the fifth bit of data, the output end of the third shift register is connected to the input end of the fourth shift register, and the output end of the third shift register is used to output the third bit of data;

[0042] The input end of the fourth shift register is used to receive the third bit data, and the output end of the fourth shift register is used to output the first bit data.

[0043] In some embodiments, the second target write data includes a zeroth bit data, a second bit data, a fourth bit data, and a sixth bit data;

[0044] The second data sub-circuit includes a fifth shift register, a sixth shift register, a seventh shift register, and an eighth shift register; wherein:

[0045] The input end of the fifth shift register is used to receive the second initial write data, the output end of the fifth shift register is connected to the input end of the sixth shift register, and the output end of the fifth shift register is used to output the sixth bit data;

[0046] The input end of the sixth shift register is used to receive the sixth bit of data, the output end of the sixth shift register is connected to the input end of the seventh shift register, and the output end of the sixth shift register is used to output the fourth bit of data;

[0047] The input end of the seventh shift register is used to receive the fourth bit of data, the output end of the seventh shift register is connected to the input end of the eighth shift register, and the output end of the seventh shift register is used to output the second bit of data;

[0048] The input end of the eighth shift register is used to receive the second bit data, and the output end of the eighth shift register is used to output the zeroth bit data.

[0049] In a second aspect, an embodiment of the present disclosure provides a writing method, the writing method comprising:

[0050] receiving an enable signal, a test mode signal, and an initial reset signal through a signal conversion circuit, and performing signal conversion processing according to the enable signal, the initial reset signal, and the test mode signal to obtain a first set signal and a first reset signal;

[0051] receiving a first set signal and a first reset signal through a plurality of shift registers in a data generation circuit, and serially converting and processing initial write data according to the plurality of shift registers to generate target write data;

[0052] The initial write data is in a serial state, the target write data is in a parallel state, and the target write data is the write data required by MBIST.

[0053] In a third aspect, an embodiment of the present disclosure provides a memory, which at least includes the write circuit as described in any one of the first aspects.

[0054] The present disclosure provides a write circuit, a write method, and a memory. The write circuit includes a signal conversion circuit and a data generation circuit, wherein the signal conversion circuit is connected to the data generation circuit. The signal conversion circuit is configured to receive an enable signal, a test mode signal, and an initial reset signal, and perform signal conversion processing based on the enable signal, the initial reset signal, and the test mode signal to obtain a first set signal and a first reset signal. The data generation circuit includes a plurality of shift registers, the plurality of shift registers being configured to receive the first set signal and the first reset signal, and serially converting and processing the initial write data based on the plurality of shift registers to generate target write data. The initial write data is in a serial state, the target write data is in a parallel state, and the target write data is write data required by MBIST. In this way, the test mode signal is converted into a first set signal and a first reset signal by a signal conversion circuit, and then according to the first set signal and the first reset signal, the initial write data is serially converted and processed by multiple shift registers in a data generation circuit to generate target write data; that is, the generation process of the write data required by MBIST is placed into the serial conversion process of the initial write data, so that the write circuit not only saves chip area, but also can improve the timing constraints of the write data in the MBIST test process, thereby ensuring the timing requirements of the compressed write, and finally improving the memory performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A schematic diagram of the structure of a writing circuit;

[0056] Figure 2 A schematic diagram of the structure of a write circuit provided in an embodiment of the present disclosure Figure 1 ;

[0057] Figure 3 A schematic diagram of the structure of a write circuit provided in an embodiment of the present disclosure Figure 2 ;

[0058] Figure 4 A schematic diagram of the structure of a signal conversion circuit provided in an embodiment of the present disclosure;

[0059] Figure 5 A schematic diagram of the structure of a write circuit provided in an embodiment of the present disclosure Figure 3 ;

[0060] Figure 6 A schematic diagram of the structure of a write circuit provided in an embodiment of the present disclosure Figure 4 ;

[0061] Figure 7 Detailed structural diagram of a shift register;

[0062] Figure 8A detailed structural diagram of a shift register provided in an embodiment of the present disclosure;

[0063] Figure 9 A flowchart of a writing method provided in an embodiment of the present disclosure;

[0064] Figure 10 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to explain the relevant applications and are not intended to limit the relevant applications. It should also be noted that for ease of description, only the portions relevant to the relevant applications are shown in the drawings.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0067] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0068] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0069] It should be noted that MBIST is a memory built-in self-test technology that is integrated into the memory. Here, "built-in" means that the test vectors for the memory are automatically generated by the built-in memory test logic, rather than generated by an external test machine (Auto-Test-Equipment, ATE). During MBIST testing, only the test instructions are transmitted by the machine to obtain the test results from the Test Data Output (TDO) interface.

[0070] In today's era, the exponential growth of data is driving ever-increasing demands for storage capacity. There are two common approaches to addressing this growth: expanding storage capacity, which increases costs; and compressing data to reduce storage capacity consumption and save costs. Understandably, the test data used in MBIST inputs is compressed data.

[0071] It should also be noted that serial data output is the transmission of code elements that make up data and characters bit by bit in a time sequence, parallel data transmission is the simultaneous transmission of data and character code elements with a fixed number of bits (usually 8 bits or 16 bits, etc.) to the receiving end, and serial-to-parallel conversion is the technology that completes the conversion between serial transmission and parallel transmission.

[0072] Exemplarily, the write circuit may include a reset circuit, a data generation circuit, and a configuration circuit. Figure 1 FIG. 1 shows a schematic diagram of the composition structure of a write circuit. Figure 1 As shown, the write circuit includes a reset circuit 11, a data generation circuit 12, and a configuration circuit 13. The reset circuit 11 includes a NAND gate 111 and a NOT gate 112; the data generation circuit 12 includes a first data sub-circuit 121 and a second data sub-circuit 122, wherein the first data sub-circuit 121 includes a shift register 1211, a shift register 1212, a shift register 1213, and a shift register 1214, and the second data sub-circuit 122 includes a shift register 1221, a shift register 1222, a shift register 1223, and a shift register 1224; the configuration circuit 13 includes a first configuration circuit 131 and a second configuration circuit 132, wherein the first configuration circuit 131 includes a NOT gate 1311, an AND gate 1312, a NOR gate 1313, and a NOT gate 1314, and the second configuration circuit 132 includes a NOT gate 1321, an AND gate 1322, a NOR gate 1323, and a NOT gate 1324. The specific connection relationship is as follows. Figure 1 shown.

[0073] In the reset circuit 11, the first input end of the NAND gate 111 is used to receive the cm0_ts_Comp signal, the second input end of the NAND gate 111 is used to receive the ResetN signal, and the output end of the NOT gate 112 is used to output the RN signal; wherein, the cm0_ts_Comp signal is an enable signal for the compression mode, and the RN signal generated after the system is powered on can clear the shift register in the data generation circuit to 0.

[0074] The data generation circuit 12 is a compression writing circuit that samples the data input from the transient data queue (TDQ) end, or performs serial conversion and processing. Specifically, the first data sub-circuit 121 is used to receive the data Din in a serial state and output the data D in a parallel state. <7> 、D <5> 、D <3> and D <1> The second data sub-circuit 122 is used to receive the data in the serial state DinRiseDly and output the data in the parallel state D <6> 、D <4> 、D <2> and D <0> ; Among them, the data DinRiseDly is the data obtained by sampling and delaying the data Din, and the first clock signal ClkiN and the second clock signal Clki are in an anti-phase relationship.

[0075] The first configuration circuit 131 is used to receive the Cm0_ts_DTOPO0 signal, the Cm0_ts_DTOPO1 signal and the data D<6,4,2,0>, and output the data DataIn<6,4,2,0>. The second configuration circuit 132 is used to receive the Cm0_ts_DTOPO0 signal, the Cm0_ts_DTOPO1 signal and the data D<7,5,3,1>, and output the data DataIn<7,5,3,1>.

[0076] It should be noted that when Cm0_ts_DTOPO1=1, the data DataIn<7:0> output by the configuration circuit 13 is 0x55, that is, the write circuit controls the first configuration circuit 131 to output the data DataIn<6,4,2,0>; when Cm0_ts_DTOPO0=1, the data DataIn<7:0> output by the configuration circuit 13 is 0xAA, that is, the write circuit controls the second configuration circuit 132 to output the data DataIn<7,5,3,1>.

[0077] It should also be noted that data D<6,4,2,0> and data D<7,5,3,1> refer to original compressed data (Compress data), and data DataIN<6,4,2,0> and data DataIn<7,5,3,1> refer to the compressed data finally generated after configuration by the configuration circuit 13, that is, the write data required by MBIST.

[0078] It should also be noted that the first configuration circuit 131 is only used to receive data D <6> or D <4> or D <2> or D <0> , then the corresponding output data DataIn <6> or DataIn <4> or DataIn <2> or DataIn <0> That is, there are four first configuration circuits 131 to output the data DataIn<6,4,2,0> in parallel; similarly, the second configuration circuit 132 is only used to receive the data D <7> or D <5> or D <3> or D <1> , then the corresponding output data DataIn <7> or DataIn <5> or DataIn <3> or DataIn <1> That is, there are four second configuration circuits 132 to output the data DataIn<7,5,3,1> in parallel.

[0079] Here, the data generation circuit 12 is combined with the configuration circuit 13 to insert the parallel data output by the shift register into the test mode signals Cm0_ts_DTOPO0 and Cm0_ts_DTOPO1 to generate the write data required by MBIST. However, the compressed write data will be delayed by the logic gates in the oval dotted circle in the configuration circuit 13.

[0080] Simply put, in existing DRAM MBIST testing, test data input is configured by configuring the compressed write data that has undergone serial-to-parallel conversion using specific test patterns. In other words, after the serial-to-parallel conversion of the compressed write data is completed, the test pattern is inserted to set the corresponding data bits to generate the write data required by MBIST. However, this affects the timing of the compressed write and delays the data write.

[0081] Based on this, an embodiment of the present disclosure provides a write circuit, in which a signal conversion circuit is used to receive an enable signal, a test mode signal and an initial reset signal, and performs signal conversion processing according to the enable signal, the initial reset signal and the test mode signal to obtain a first set signal and a first reset signal; a data generation circuit includes multiple shift registers, the multiple shift registers are used to receive the first set signal and the first reset signal, and the initial write data is serially converted and processed according to the multiple shift registers to generate target write data; wherein the initial write data is in a serial state, the target write data is in a parallel state, and the target write data is the write data required by MBIST. In this way, the test mode signal is converted into a first set signal and a first reset signal by a signal conversion circuit, and then according to the first set signal and the first reset signal, the initial write data is serially converted and processed by multiple shift registers in a data generation circuit to generate target write data; that is, the generation process of the write data required by MBIST is placed into the serial conversion process of the initial write data, so that the write circuit not only saves chip area, but also can improve the timing constraints of the write data in the MBIST test process, thereby ensuring the timing requirements of the compressed write, and finally improving the memory performance.

[0082] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0083] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the composition structure of a write circuit provided by an embodiment of the present disclosure Figure 1 .like Figure 2 As shown, the writing circuit 20 may include a signal conversion circuit 21 and a data generating circuit 22, wherein the signal conversion circuit 21 is connected to the data generating circuit 22, wherein:

[0084] The signal conversion circuit 21 is used to receive the enable signal, the test mode signal and the initial reset signal, and perform signal conversion processing according to the enable signal, the initial reset signal and the test mode signal to obtain a first set signal and a first reset signal;

[0085] The data generating circuit 22 includes a plurality of shift registers, which are used to receive a first set signal and a first reset signal, and to serially convert and process the initial write data according to the plurality of shift registers to generate target write data.

[0086] In the embodiment of the present disclosure, the initial write data is in a serial state, the target write data is in a parallel state, and the target write data is the write data required by MBIST.

[0087] It should be noted that in the embodiment of the present disclosure, the write circuit 20 can be applied to a memory. The memory can be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., and this is not specifically limited here.

[0088] It should also be noted that, in the disclosed embodiment, the write circuit 20 may be a write circuit for a memory built-in self-test (BIST). The disclosed embodiment relates to technical fields such as (semiconductor) memory, DRAM, Design For Test (DFT), and MBIST. Here, the write data required for MBIST can be generated during the serial-to-parallel conversion of the compressed write data, thereby saving chip area and having no effect on the timing constraints of the compressed write.

[0089] It should also be noted that in the embodiment of the present disclosure, the enable signal can be represented by cm0_ts_Comp, and the initial reset signal can be represented by ResetN. The enable signal can specifically refer to the enable signal of the compression mode. Here, the compression mode refers to compressing the initial write data, and the generated target write data is the compressed data.

[0090] It should also be noted that, in the embodiment of the present disclosure, the first set signal is used to perform setting processing on multiple shift registers in the data generating circuit 22, that is, to set multiple shift registers to 1; the first reset signal is used to perform reset processing on multiple shift registers in the data generating circuit 22, that is, to clear multiple shift registers to 0.

[0091] It should also be noted that, in the embodiment of the present disclosure, logic 1 can be represented as a high level state, and logic 0 can be represented as a low level state.

[0092] It should also be noted that, in the disclosed embodiment, the data generating circuit 22 can be used to serialize and process the initial write data in the serial state, directly generating the write data (i.e., target write data) in the parallel state required by MBIST, without using the configuration circuit in the related art to configure the compressed write data that has undergone serial-to-parallel conversion, thereby saving chip area and improving the timing constraints of the write data during the MBIST test process.

[0093] In some embodiments, for the signal conversion circuit 21, Figure 2 Based on the writing circuit 20 shown, see Figure 3 , the signal conversion circuit 21 may include a first conversion sub-circuit 211 and a second conversion sub-circuit 212, wherein:

[0094] The first conversion sub-circuit 211 is configured to receive a test mode signal, convert the test mode signal, and obtain a first set signal;

[0095] The second conversion sub-circuit 212 is configured to receive the enable signal, the test mode signal and the initial reset signal, and convert the test mode signal according to the enable signal and the initial reset signal to obtain a first reset signal.

[0096] It should be noted that in the embodiment of the present disclosure, the first set signal is related to the test mode signal. That is, the test mode signal is converted and processed by the first conversion sub-circuit 211 to generate the first set signal. The first reset signal is related to the enable signal, the test mode signal, and the initial reset signal. That is, the enable signal, the test mode signal, and the initial reset signal are converted and processed by the second conversion sub-circuit 212 to generate the first reset signal.

[0097] Furthermore, in some embodiments, Figure 4 As shown, the test mode signal may include a first test mode signal and a second test mode signal, wherein:

[0098] The first conversion sub-circuit 211 is configured to convert the first test mode signal to obtain an even set signal; and convert the second test mode signal to obtain an odd set signal;

[0099] The second conversion sub-circuit 212 is used to convert the first test mode signal according to the enable signal and the initial reset signal to obtain an odd reset signal; and to convert the second test mode signal according to the enable signal and the initial reset signal to obtain an even reset signal.

[0100] It should be noted that, in the embodiment of the present disclosure, the first test mode signal may be expressed as Cm0_ts_DTOPO1, and the second test mode signal may be expressed as Cm0_ts_DTOPO0. The first test mode signal and the second test mode signal are signals for MBIST to write data to the memory array.

[0101] It should also be noted that, in the embodiment of the present disclosure, the first set signal includes an even set signal and an odd set signal, and the first reset signal includes an even reset signal and an odd reset signal; wherein, the even set signal can be expressed as EvenSetN, the odd set signal can be expressed as OddSetN, the even reset signal can be expressed as EvenResetN, and the odd reset signal can be expressed as OddResetN.

[0102] It should also be noted that, in the disclosed embodiment, the even set signal and the odd reset signal are related to the first test mode signal. Specifically, the first test mode signal is converted and processed by the first conversion sub-circuit 211 to generate an even set signal. Based on the enable signal and the initial reset signal, the first test mode signal is converted and processed by the second conversion sub-circuit 212 to generate an odd reset signal. Similarly, the odd set signal and the even reset signal are related to the second test mode signal. Specifically, the second test mode signal is converted and processed by the first conversion sub-circuit 211 to generate an odd set signal. Based on the enable signal and the initial reset signal, the second test mode signal is converted and processed by the second conversion sub-circuit 212 to generate an even reset signal.

[0103] Furthermore, in some embodiments, for the signal conversion circuit 21, as shown in FIG. Figure 4 As shown, the first conversion sub-circuit 211 may include a first NOT gate 2111 and a second NOT gate 2112 , and the second conversion sub-circuit 212 may include a first NAND gate 2121 , a first NOR gate 2122 and a second NOR gate 2123 ; wherein:

[0104] An input end of the first NOT gate 2111 is used to receive a first test mode signal, and an output end of the first NOT gate 2111 serves as a first output end of the first conversion sub-circuit 211 for outputting an even set signal. An input end of the second NOT gate 2112 is used to receive a second test mode signal, and an output end of the second NOT gate 2112 serves as a second output end of the first conversion sub-circuit 211 for outputting an odd set signal.

[0105] The first input end of the first NAND gate 2121 is used to receive an enable signal, and the second input end of the first NAND gate 2121 is used to receive an initial reset signal; the first input end of the first NOR gate 2122 is used to receive a first test mode signal, the second input end of the first NOR gate 2122 is connected to the output end of the first NAND gate 2121, and the output end of the first NOR gate 2122 serves as the first output end of the second conversion sub-circuit 212 for outputting an odd reset signal; the first input end of the second NOR gate 2123 is connected to the output end of the first NAND gate 2121, the second input end of the second NOR gate 2123 is used to receive a second test mode signal, and the output end of the second NOR gate 2123 serves as the second output end of the second conversion sub-circuit 212 for outputting an even reset signal.

[0106] It should be noted that, in the embodiment of the present disclosure, the first conversion sub-circuit 211 may be composed of a first NOT gate 2111 and a second NOT gate 2112. The first NOT gate 2111 performs a NOT logic operation on the first test mode signal to obtain an even set signal, and the second NOT gate 2112 performs a NOT logic operation on the second test mode signal to obtain an odd set signal.

[0107] Furthermore, in some embodiments, Figure 4 As shown, the second conversion sub-circuit 212 may be composed of a first NAND gate 2121, a first NOR gate 2122, and a second NOR gate 2123. The first NAND gate 2121 performs a NAND logic operation on the enable signal and the initial reset signal to obtain an initial reset inverted signal (Reset); the first NOR gate 2122 performs a NOR logic operation on the first test mode signal and the initial reset inverted signal to obtain an odd reset signal; and the second NOR gate 2123 performs a NOR logic operation on the second test mode signal and the initial reset inverted signal to obtain an even reset signal.

[0108] It should also be noted that, in the embodiment of the present disclosure, the input end of the first NOT gate 2111 and the input end of the second NOT gate 2112 serve as the input end of the first conversion sub-circuit 211, respectively used to receive the first test mode signal and the second test mode signal; the output end of the first NOT gate 2111 and the output end of the second NOT gate 2112 serve as the output end of the first conversion sub-circuit 211, respectively used to output the even set signal and the odd set signal.

[0109] Furthermore, in some embodiments, the first input terminal and the second input terminal of the first NAND gate 2121, the first input terminal of the first NOR gate 2122, and the second input terminal of the second NOR gate 2123 serve as input terminals of the second conversion sub-circuit 212, respectively for receiving the enable signal, the initial reset signal, the first test mode signal and the second test mode signal; the output terminal of the first NOR gate 2122 and the output terminal of the second NOR gate 2123 serve as output terminals of the second conversion sub-circuit 212, respectively for outputting the odd reset signal and the even reset signal.

[0110] It should also be noted that in the embodiment of the present disclosure, the enable signal is in a high-level state, i.e., cm0_ts_Comp = 1. When the first test mode signal is in a high-level state and the second test mode signal is in a low-level state, i.e., Cm0_ts_DTOPO1 = 1 and Cm0_ts_DTOPO0 = 0, then the even set signal is in a low-level state and the odd set signal is in a high-level state, i.e., EvenSetN = 0 and OddSetN = 1. At this time, if the initial reset signal is in a high-level state, i.e., ResetN = 1, then the odd reset signal is in a low-level state and the even reset signal is in a high-level state, i.e., OddResetN = 0 and EvenResetN = 1. If the initial reset signal is in a low-level state, i.e., ResetN = 0, then the odd reset signal is in a low-level state and the even reset signal is in a low-level state, i.e., OddResetN = 0 and EvenResetN = 0.

[0111] It should also be noted that, in the embodiment of the present disclosure, when the first test mode signal is in a low level state and the second test mode signal is in a high level state, that is, Cm0_ts_DTOPO1=0, Cm0_ts_DTOPO0=1, then the even set signal is in a high level state and the odd set signal is in a low level state, that is, EvenSetN=1, OddSetN=0; at this time, if the initial reset signal is in a high level state, that is, ResetN=1, then the odd reset signal is in a high level state and the even reset signal is in a low level state, that is, OddResetN=1, EvenResetN=0; if the initial reset signal is in a low level state, that is, ResetN=0, then the odd reset signal is in a low level state and the even reset signal is in a low level state, that is, OddResetN=0, EvenResetN=0. That is, the even set signal, odd set signal, even reset signal and odd reset signal required by the embodiment of the present disclosure can be determined according to the first test mode signal, the second test mode signal and the initial reset signal in different level states.

[0112] Furthermore, in some embodiments, Figure 4As shown, the second conversion sub-circuit 212 may further include a third NOT gate 2124; wherein:

[0113] An input end of the third NOT gate 2124 is connected to the output end of the first NAND gate 2121 , and an output end of the third NOT gate 2124 serves as a third output end of the second conversion sub-circuit 212 for outputting a second reset signal.

[0114] It should be noted that, in the embodiment of the present disclosure, the second reset signal may be expressed as RN, which may be applied to the ResetN (RN) terminal of other conventional shift registers in the write circuit.

[0115] It should also be noted that in the embodiment of the present disclosure, a first NAND gate 2121 may first perform a NAND logic operation on the enable signal and the initial reset signal to obtain an initial reset inverted signal, and then a third NAND gate 2124 may perform a NAND logic operation on the initial reset inverted signal to obtain a second reset signal. It is understood that an AND logic operation may also be performed on the enable signal and the initial reset signal via an AND gate to obtain the second reset signal, and this is not specifically limited.

[0116] In some embodiments, in the writing circuit 20, for the data generating circuit 22, see Figure 5 , the data generating circuit 22 may include a first data sub-circuit 221 and a second data sub-circuit 222, wherein:

[0117] The first data sub-circuit 221 is configured to, after receiving an odd set signal and an odd reset signal, serially convert and process the first initial write data according to the first clock signal and the second clock signal to generate first target write data;

[0118] The second data sub-circuit 222 is configured to, after receiving the even set signal and the even reset signal, serially convert and process the second initial write data according to the first clock signal and the second clock signal to generate second target write data;

[0119] The first clock signal and the second clock signal are in anti-phase relationship with each other, and the target write data consists of the first target write data and the second target write data.

[0120] It should be noted that in the embodiment of the present disclosure, the first initial write data and the second initial write data are in a serial state, and the first target write data and the second target write data are in a parallel state; wherein, the first initial write data can be expressed as Din, and the second initial write data can be expressed as DinRiseDly.

[0121] It should also be noted that in the embodiment of the present disclosure, the first clock signal can be represented as ClkiN, and the second clock signal can be represented as Clki. The first clock signal and the second clock signal are in anti-phase relationship with each other. The data generation circuit 22 receives the ClkiN signal for sampling margin considerations to ensure sufficient sampling margin.

[0122] In some embodiments, as Figure 5 As shown, the write circuit 20 may further include a shift delay circuit 23, wherein:

[0123] The shift delay circuit 23 is configured to receive the first initial write data, sample and delay the first initial write data, and obtain the second initial write data.

[0124] It should be noted that, in the embodiment of the present disclosure, the second initial write data is data obtained after sampling and delay processing of the first initial write data, so that the falling edge data can be sampled in the second data sub-circuit 222 .

[0125] In some embodiments, specifically for the shift delay circuit, see Figure 6 , the shift delay circuit may include a sampling submodule 231 and a delay module 232, wherein:

[0126] The sampling submodule 231 is configured to receive the first initial write data and the third clock signal, and perform sampling and latching processing on the first initial write data according to the rising edge of the third clock signal to obtain sampled write data;

[0127] The delay module 232 is configured to perform delay processing on the sampled write data to obtain second initial write data.

[0128] It should be noted that, in the embodiment of the present disclosure, the third clock signal may be the same signal as the second clock signal, and is expressed as Clki.

[0129] It should also be noted that, in the embodiment of the present disclosure, the sampled write data is the data obtained after the first initial write data is sampled and latched by the rising edge of the third clock signal, which can be expressed as DinRise; the sampled write data is then delayed to obtain the second initial write data.

[0130] In some embodiments, as Figure 6 As shown, the sampling submodule 231 may include a latch 2311 , and a reset terminal of the latch 2311 is used to receive a second reset signal.

[0131] In some embodiments, as Figure 6 As shown, the delay module 232 is composed of an even number of NOT gates connected in series.

[0132] It should be noted that in the embodiment of the present disclosure, the input end of the latch 2311 receives the first initial write data, the first clock end of the latch 2311 receives the third clock signal, and the reset (RN) end of the latch 2311 receives the second reset signal. The latch 2311 can be reset according to the second reset signal, that is, the latch 2311 is cleared to 0.

[0133] It should also be noted that, in the embodiment of the present disclosure, since the delay module 232 includes an even number of NOT gates, the sampled write data is only delayed, and the level state of the sampled write data does not change. Figure 6 The delay module 232 is composed of two NOT gates connected in series. However, the delay module 232 can also be composed of four NOT gates connected in series, or six, eight, or other NOT gates connected in series, and this is not specifically limited in the present embodiment. In addition, the delay time between the input data and the output data of the delay module 232 is related to the specific number of NOT gates in the delay module 232. The delay time between the input data and the output data of the delay module 232 varies depending on the number of NOT gates in the delay module 232. Thus, the present embodiment can determine the specific number of NOT gates in the delay module 232 based on the actual required delay time.

[0134] In some embodiments, when the first test mode signal is in a first level state and the second test mode signal is in a second level state, the second target write data are all in the first level state;

[0135] When the first test mode signal is in the second level state and the second test mode signal is in the first level state, the first target write data are all in the first level state.

[0136] It should be noted that, in the embodiment of the present disclosure, the first level state may be a high level state, such as logic 1; the second level state may be a low level state, such as logic 0, but this is not specifically limited.

[0137] It should also be noted that in the disclosed embodiment, the first test mode signal enables writing of the second target write data, and the second test mode signal enables writing of the first target write data. That is, when Cm0_ts_DTOPO1 = 1, DataIn<7:0> = 0x55; when Cm0_ts_DTOPO0 = 1, DataIn<7:0> = 0xAA; where the data topology 0xAA can be represented as 10101010, and the data topology 0x55 can be represented as 01010101.

[0138] In some embodiments, as Figure 6As shown, the first data sub-circuit 221 may include at least one shift register, and the second data sub-circuit 222 may include at least one shift register; wherein:

[0139] In the first data sub-circuit 221, the first clock terminal of at least one shift register is used to receive the first clock signal, the second clock terminal of at least one shift register is used to receive the second clock signal, the set terminal of at least one shift register is used to receive an odd-numbered set signal, and the reset terminal of at least one shift register is used to receive an odd-numbered reset signal; the input terminal of the first shift register is used to receive the first initial write data, the input terminal of the i-th shift register is connected to the output terminal of the i-1-th shift register, and the output terminal of the at least one shift register serves as the output terminal of the first data sub-circuit for outputting the first target write data; wherein i is an integer greater than 1;

[0140] In the second data sub-circuit 222, the first clock end of at least one shift register is used to receive the first clock signal, the second clock end of at least one shift register is used to receive the second clock signal, the set end of at least one shift register is used to receive an even set signal, and the reset end of at least one shift register is used to receive an even reset signal; the input end of the first shift register is used to receive the second initial write data, the input end of the j-th shift register is connected to the output end of the j-1-th shift register, and the output end of at least one shift register is commonly used as the output end of the second data sub-circuit for outputting the second target write data; wherein j is an integer greater than 1.

[0141] It should be noted that in the embodiments of the present disclosure, the shift register may also be referred to as an odd-even flip-flop. A shift register is an information storage device with a memory function and two stable states. It is the most basic logic unit that constitutes various sequential circuits and is also an important unit circuit in digital logic circuits. Here, the shift register has two stable states, namely "0" and "1," and can flip from one stable state to the other under the action of a signal received at the clock end.

[0142] It should also be noted that in the embodiment of the present disclosure, for the shift register, it may include a first clock terminal (CK), a second clock terminal (CKN), an input terminal (D), an output terminal (Q), a set terminal (SN) and a reset terminal (RN); wherein the set terminal and the reset terminal are both valid at low level.

[0143] It should also be noted that in the embodiments of the present disclosure, the first clock end of the shift register is used to receive the first clock signal, and the second clock end of the shift register is used to receive the second clock signal. The first clock signal and the second clock signal are in anti-phase relationship with each other. The first clock end receives the first clock signal to ensure sufficient sampling margin.

[0144] In some embodiments, the first target write data may include first bit data, third bit data, fifth bit data, and seventh bit data. For the first data sub-circuit 221, as shown in FIG. Figure 6 As shown, the first data sub-circuit 221 may include a first shift register 2211, a second shift register 2212, a third shift register 2213 and a fourth shift register 2214; wherein:

[0145] The input end of the first shift register 2211 is used to receive the first initial write data, the output end of the first shift register 2211 is connected to the input end of the second shift register 2212, and the output end of the first shift register 2211 is used to output the seventh bit data;

[0146] The input end of the second shift register 2212 is used to receive the seventh bit of data, the output end of the second shift register 2212 is connected to the input end of the third shift register 2213, and the output end of the second shift register 2212 is used to output the fifth bit of data;

[0147] The input end of the third shift register 2213 is used to receive the fifth bit of data, the output end of the third shift register 2213 is connected to the input end of the fourth shift register 2214, and the output end of the third shift register 2213 is used to output the third bit of data;

[0148] The input end of the fourth shift register 2214 is used to receive the third bit data, and the output end of the fourth shift register 2214 is used to output the first bit data.

[0149] It should be noted that, in the embodiment of the present disclosure, the first bit of data can be represented by D <1> Indicates that the third bit of data can be represented by D <3> Indicates that the fifth bit of data can be represented by D <5> Indicates that the seventh bit of data can be represented by D <7> When the first test mode signal is in a low level state and the second test mode signal is in a high level state, the data D <1> 、D <3> 、D <5> and D <7> Both are in high level state.

[0150] It should also be noted that, in the embodiment of the present disclosure, the first initial write data input in series passes through the four shift registers in the first data sub-circuit 221 and finally outputs four bits of data in parallel.

[0151] In some embodiments, the second target write data may include bit 0 data, bit 2 data, bit 4 data, and bit 6 data. The second data sub-circuit 222 may include a fifth shift register 2221, a sixth shift register 2222, a seventh shift register 2223, and an eighth shift register 2224; wherein:

[0152] The input end of the fifth shift register 2221 is used to receive the second initial write data, the output end of the fifth shift register 2221 is connected to the input end of the sixth shift register 2222, and the output end of the fifth shift register 2221 is used to output the sixth bit data;

[0153] The input end of the sixth shift register 2222 is used to receive the sixth bit of data, the output end of the sixth shift register 2222 is connected to the input end of the seventh shift register 2223, and the output end of the sixth shift register 2222 is used to output the fourth bit of data;

[0154] The input end of the seventh shift register 2223 is used to receive the fourth bit of data, the output end of the seventh shift register 2223 is connected to the input end of the eighth shift register 2224, and the output end of the seventh shift register 2223 is used to output the second bit of data;

[0155] The input end of the eighth shift register 2224 is used to receive the second bit data, and the output end of the eighth shift register 2224 is used to output the zeroth bit data.

[0156] It should be noted that, in the embodiment of the present disclosure, the zeroth bit data can be represented by D <0> Indicates that the second bit of data can be represented by D <2> Indicates that the fourth bit of data can be represented by D <4> Indicates that the sixth bit of data can be represented by D <6> When the first test mode signal is in a high level state and the second test mode signal is in a low level state, the data D <0> 、D <2> 、D <4> and D <6> Both are in high level state.

[0157] It should also be noted that, in the embodiment of the present disclosure, the second initial write data input in series passes through the four shift registers in the second data sub-circuit 222 and finally outputs four bits of data in parallel.

[0158] It can be understood that when the first test mode signal is in a low level state and the second test mode signal is in a high level state, the data D <1> 、D <3> 、D <5> and D <7> Both are in high level state, data D <0> 、D <2> 、D <4> and D <6> are both in a low state, then the data topology 0xAA required by MBIST can be obtained; when the first test mode signal is in a high state and the second test mode signal is in a low state, the data D <1> 、D <3> 、D <5> and D <7> Both are in low level state, data D <0> 、D <2> 、D <4> and D <6> If both are in a high-level state, the data topology 0x55 required by MBIST can be obtained. Among them, the data topology 0xAA can be expressed as 10101010, and the data topology 0x55 can be expressed as 01010101; that is, the data topology 0xAA has D<7,5,3,1> as 1 and D<6,4,2,0> as 0, and the data topology 0x55 has D<6,4,2,0> as 1 and D<7,5,3,1> as 0.

[0159] An embodiment of the present disclosure provides a write circuit, which converts a test mode signal into a first set signal and a first reset signal through a signal conversion circuit, and then serializes and processes the initial write data through multiple shift registers in a data generation circuit according to the first set signal and the first reset signal to generate target write data; that is, the generation process of the write data required by MBIST is placed into the serialization and parallelization process of the initial write data, so that the write circuit not only saves chip area, but also can improve the timing constraints of the write data during the MBIST test process, thereby being able to ensure the timing requirements of compressed write, and ultimately improving the memory performance.

[0160] In another embodiment of the present disclosure, see Figure 7 , which shows a detailed structural diagram of a shift register, wherein the shift register ffrq1 is applied to the data generating circuit 12 in the aforementioned embodiment.

[0161] like Figure 7As shown, the shift register ffrq1 may include a first clock terminal Ck, a second clock terminal CkN, an input terminal D, an output terminal Q, and a reset terminal RN. Specifically, the shift register ffrq1 also includes a gated inverter a1, a NOT gate a2, a gated inverter a3, a NOR gate a4, a gated inverter a5, a gated NAND gate a6, and a NOT gate a7. The first control terminal of gated inverter a1, the second control terminal of gated inverter a3, the second control terminal of gated inverter a5, and the first control terminal of gated NAND gate a6 are connected to the second clock terminal CkN; the second control terminal of gated inverter a1, the first control terminal of gated inverter a3, the first control terminal of gated inverter a5, and the second control terminal of gated NAND gate a6 are connected to the first clock terminal Ck; the input terminal of gated inverter a1 is connected to the input terminal D; the input terminal of NOT gate a2 is connected to the reset terminal RN; and the second input terminal of gated NAND gate a6 and the output terminal of NOT gate a7 are connected to the output terminal Q. For detailed connection relationship, see Figure 7 .

[0162] It should be noted that in the embodiments of the present disclosure, the first control terminals of the gated inverter (e.g., a1, a3, a5) and the gated NAND gate (e.g., a6) are all forward control terminals, and the second control terminals of the gated inverter (e.g., a1, a3, a5) and the gated NAND gate (e.g., a6) are all reverse control terminals.

[0163] It should also be noted that in the embodiment of the present disclosure, the output end of the NOT gate a2 outputs the R signal, and the second input end of the gated NAND gate a6 inputs the RN signal; wherein the R signal and the RN signal are inverted signals of each other, and the RN signal is used to clear the shift register ffrql to 0.

[0164] In some embodiments, participating Figure 8 , which shows a detailed structural diagram of a shift register provided by an embodiment of the present disclosure. The shift register ffrsql is applied to the data generating circuit 22 in the aforementioned embodiment.

[0165] like Figure 8As shown, the shift register ffrsql includes a first clock terminal Ck, a second clock terminal CkN, an input terminal D, an output terminal Q, a reset terminal RN, and a set terminal SN. Specifically, the shift register ffrsql includes a gated inverter b1, a NOT gate b2, a gated inverter b3, an AND gate b4, a NOR gate b5, a NOT gate b6, a gated inverter b7, a gated NAND gate b8, an OR gate b9, and a NOT gate b10. Among them, the first control terminal of the gated inverter b1, the second control terminal of the gated inverter b3, the second control terminal of the gated inverter b7, and the first control terminal of the gated NAND gate b8 are connected to the second clock terminal CkN; the second control terminal of the gated inverter b1, the first control terminal of the gated inverter b3, the first control terminal of the gated inverter b7, and the second control terminal of the gated NAND gate b8 are connected to the first clock terminal Ck; the input terminal of the gated inverter b1 is connected to the input terminal D; the input terminal of the NOT gate b2 is connected to the reset terminal RN; the input terminal of the NOT gate b6 is connected to the set terminal SN; the second input terminal of the OR gate b9 and the output terminal of the NOT gate b10 are connected to the output terminal Q. For detailed connection relationships, see Figure 8 .

[0166] It should be noted that in the embodiments of the present disclosure, the first control terminals of the gated inverter (e.g., b1, b3, b7) and the gated NAND gate (e.g., b8) are all forward control terminals, and the second control terminals of the gated inverter (e.g., b1, b3, b7) and the gated NAND gate (e.g., b8) are all reverse control terminals.

[0167] It should also be noted that in the disclosed embodiment, the second input of NOR gate b5 receives the R signal, and the first input of gated NAND gate b8 receives the RN signal; the R and RN signals are mutually inverted signals, and the RN signal is used to clear the shift register ffrsql to 0. The second input of AND gate b4 receives the SN signal, the output of NOR gate b6 outputs the S signal, and the first input of OR gate b9 receives the S signal; the S and SN signals are mutually inverted signals, and the SN signal is used to set the shift register ffrsql to 1.

[0168] In summary, according to Figure 7 and Figure 8 By comparison, the shift register ffrsql has an additional set terminal SN compared to the shift register ffrql. Therefore, in the write circuit 20, the test mode (Test mode) of the MBIST write data can be first converted into the EvenSetN signal and the OddSetN signal that control the parity trigger, and then the write data of each bit required by MBIST is output through the control signal, thereby realizing the data topology 0x55 and 0xAA required by MBIST.

[0169] In another embodiment of the present disclosure, see Figure 9, which shows a flow chart of a writing method provided by an embodiment of the present disclosure. Figure 9 As shown, the method may include:

[0170] S301 , receiving an enable signal, a test mode signal, and an initial reset signal through a signal conversion circuit, performing signal conversion processing according to the enable signal, the initial reset signal, and the test mode signal to obtain a first set signal and a first reset signal.

[0171] S302 , receiving a first set signal and a first reset signal through a plurality of shift registers in a data generation circuit, and serially converting and processing the initial write data according to the plurality of shift registers to generate target write data.

[0172] It should be noted that, in the embodiment of the present disclosure, the initial write data is in a serial state, the target write data is in a parallel state, and the target write data is the write data required by MBIST.

[0173] It should also be noted that the write method provided in the embodiment of the present disclosure can be applied to the write circuit 20 of the aforementioned embodiment. By utilizing the new circuit design in the write circuit 20, the chip area can be reduced and the timing constraints of writing data during the MBIST test process can be improved.

[0174] In some embodiments, the signal conversion circuit includes a first conversion sub-circuit and a second conversion sub-circuit, and the method may further include:

[0175] receiving a test mode signal through a first conversion sub-circuit, converting and processing the test mode signal to obtain a first set signal;

[0176] The enable signal, the test mode signal and the initial reset signal are received by the second conversion sub-circuit, and the test mode signal is converted and processed according to the enable signal and the initial reset signal to obtain a first reset signal.

[0177] In some embodiments, the test mode signal includes a first test mode signal and a second test mode signal, and the method may further include:

[0178] performing conversion processing on the first test mode signal through the first conversion sub-circuit to obtain an even set signal; and performing conversion processing on the second test mode signal to obtain an odd set signal;

[0179] According to the enable signal and the initial reset signal, the second conversion sub-circuit converts the first test mode signal to obtain an odd reset signal; and converts the second test mode signal to obtain an even reset signal.

[0180] In some embodiments, the data generation circuit includes a first data sub-circuit and a second data sub-circuit, and the method may further include:

[0181] After receiving the odd set signal and the odd reset signal, the first data sub-circuit serially converts and processes the first initial write data according to the first clock signal and the second clock signal to generate the first target write data;

[0182] After receiving the even set signal and the even reset signal, the second data sub-circuit serially converts and processes the second initial write data according to the first clock signal and the second clock signal to generate second target write data.

[0183] It should be noted that, in the embodiment of the present disclosure, the first clock signal and the second clock signal are in anti-phase relationship with each other, and the target write data consists of the first target write data and the second target write data.

[0184] In some embodiments, the write circuit further includes a shift delay circuit, and the method may further include:

[0185] The first initial write data is received through the shift delay circuit, and the first initial write data is sampled and delayed to obtain the second initial write data.

[0186] In some embodiments, the shift delay circuit includes a sampling submodule and a delay module, and the method may further include:

[0187] receiving the first initial write data and the third clock signal through the sampling submodule, and performing sampling and latching processing on the first initial write data according to the rising edge of the third clock signal to obtain sampled write data;

[0188] The sampled write data is delayed by the delay module to obtain second initial write data.

[0189] The embodiment of the present disclosure provides a write method, specifically a write method for internal self-built testing, which receives an enable signal, a test mode signal and an initial reset signal through a signal conversion circuit, performs signal conversion processing according to the enable signal, the initial reset signal and the test mode signal, and obtains a first set signal and a first reset signal; receives the first set signal and the first reset signal through multiple shift registers in a data generation circuit, and performs serial conversion and parallel processing on the initial write data according to the multiple shift registers to generate target write data; that is, the generation process of the write data required by MBIST is placed in the serial conversion and parallel processing of the initial write data, so that the write circuit not only saves chip area, but also can improve the timing constraint conditions of the write data during the MBIST test process, thereby being able to ensure the timing requirements of the compressed write, and ultimately improving the memory performance.

[0190] In another embodiment of the present disclosure, see Figure 10 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Figure 10 As shown, the memory 40 includes the write circuit 20 described in any one of the aforementioned embodiments.

[0191] In some embodiments, the memory 40 may include a DRAM chip. The DRAM chip may conform not only to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but also to memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, which are not specifically limited herein.

[0192] In the embodiment of the present disclosure, for the memory 40, the test mode signal is converted into a first set signal and a first reset signal through a signal conversion circuit, and then the initial write data is serialized and processed through multiple shift registers in the data generation circuit according to the first set signal and the first reset signal to generate target write data; that is, the generation process of the write data required by MBIST is placed in the serialization and parallelization process of the initial write data, so that the write circuit not only saves chip area, but also can improve the timing constraints of the write data during the MBIST test process, thereby ensuring the timing requirements of the compressed write, and ultimately improving the memory performance.

[0193] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0194] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0195] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0196] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0197] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0198] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0199] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A writing circuit, characterized in that: The writing circuit includes a signal conversion circuit and a data generating circuit, wherein the signal conversion circuit is connected to the data generating circuit, wherein: The signal conversion circuit is configured to receive an enable signal, a test mode signal, and an initial reset signal, and perform signal conversion processing according to the enable signal, the initial reset signal, and the test mode signal to obtain a first set signal and a first reset signal; The data generating circuit includes a plurality of shift registers, the plurality of shift registers being used to receive the first set signal and the first reset signal, and to serially convert and process the initial write data according to the plurality of shift registers to generate target write data; The initial write data is in a serial state, the target write data is in a parallel state, and the target write data is write data required by a memory built-in self test (MBIST).

2. The write circuit according to claim 1, wherein: The signal conversion circuit includes a first conversion sub-circuit and a second conversion sub-circuit, wherein: The first conversion sub-circuit is configured to receive the test mode signal, perform conversion processing on the test mode signal, and obtain the first set signal; The second conversion sub-circuit is configured to receive the enable signal, the test mode signal, and the initial reset signal, and convert the test mode signal according to the enable signal and the initial reset signal to obtain the first reset signal.

3. The write circuit according to claim 2, wherein: The test mode signal includes a first test mode signal and a second test mode signal, wherein: The first conversion sub-circuit is configured to convert the first test mode signal to obtain an even set signal; and convert the second test mode signal to obtain an odd set signal; The second conversion sub-circuit is used to convert the first test mode signal according to the enable signal and the initial reset signal to obtain an odd reset signal; and to convert the second test mode signal according to the enable signal and the initial reset signal to obtain an even reset signal.

4. The writing circuit according to claim 3, wherein: The first conversion sub-circuit includes a first NOT gate and a second NOT gate, and the second conversion sub-circuit includes a first NAND gate, a first NOR gate and a second NOR gate; wherein: The input end of the first NOT gate is used to receive the first test mode signal, and the output end of the first NOT gate serves as the first output end of the first conversion sub-circuit for outputting the even set signal; the input end of the second NOT gate is used to receive the second test mode signal, and the output end of the second NOT gate serves as the second output end of the first conversion sub-circuit for outputting the odd set signal; The first input end of the first NAND gate is used to receive the enable signal, and the second input end of the first NAND gate is used to receive the initial reset signal; the first input end of the first NOR gate is used to receive the first test mode signal, the second input end of the first NOR gate is connected to the output end of the first NAND gate, and the output end of the first NOR gate serves as the first output end of the second conversion sub-circuit for outputting the odd reset signal; the first input end of the second NOR gate is connected to the output end of the first NAND gate, the second input end of the second NOR gate is used to receive the second test mode signal, and the output end of the second NOR gate serves as the second output end of the second conversion sub-circuit for outputting the even reset signal.

5. The writing circuit according to claim 4, wherein: The second conversion sub-circuit further includes a third NOT gate; wherein: The input end of the third NOT gate is connected to the output end of the first NAND gate, and the output end of the third NOT gate serves as the third output end of the second conversion sub-circuit for outputting a second reset signal.

6. The writing circuit according to claim 5, characterized in that The data generating circuit includes a first data sub-circuit and a second data sub-circuit, wherein: The first data sub-circuit is configured to, after receiving the odd set signal and the odd reset signal, serially convert and process the first initial write data according to the first clock signal and the second clock signal to generate first target write data; the second data sub-circuit is configured to, after receiving the even set signal and the even reset signal, serially convert and process the second initial write data according to the first clock signal and the second clock signal to generate second target write data; The first clock signal and the second clock signal are in anti-phase relationship with each other, and the target write data is composed of the first target write data and the second target write data.

7. The writing circuit according to claim 6, wherein: The write circuit further includes a shift delay circuit, wherein: The shift delay circuit is used to receive the first initial write data, sample and delay the first initial write data, and obtain the second initial write data.

8. The writing circuit according to claim 7, wherein: The shift delay circuit includes a sampling submodule and a delay module, wherein: The sampling submodule is configured to receive the first initial write data and a third clock signal, and perform sampling and latching processing on the first initial write data according to a rising edge of the third clock signal to obtain sampled write data; The delay module is configured to perform delay processing on the sampled write data to obtain the second initial write data.

9. The writing circuit according to claim 8, wherein: The sampling submodule includes a latch, and a reset terminal of the latch is used to receive the second reset signal.

10. The writing circuit according to claim 8, wherein: The delay module is composed of an even number of NOT gates connected in series.

11. The writing circuit according to claim 6, wherein: When the first test mode signal is in a first level state and the second test mode signal is in a second level state, the second target write data are all in the first level state; When the first test mode signal is in the second level state and the second test mode signal is in the first level state, the first target write data are all in the first level state.

12. The write circuit according to claim 11, wherein: The first data sub-circuit includes at least one shift register, and the second data sub-circuit includes at least one shift register; wherein: In the first data sub-circuit, the first clock terminal of the at least one shift register is used to receive the first clock signal, the second clock terminal of the at least one shift register is used to receive the second clock signal, the set terminal of the at least one shift register is used to receive the odd set signal, and the reset terminal of the at least one shift register is used to receive the odd reset signal; the input terminal of the first shift register is used to receive the first initial write data, the input terminal of the i-th shift register is connected to the output terminal of the (i-1)-th shift register, and the output terminals of the at least one shift register serve as the output terminals of the first data sub-circuit for outputting the first target write data; wherein i is an integer greater than 1; In the second data sub-circuit, the first clock end of the at least one shift register is used to receive the first clock signal, the second clock end of the at least one shift register is used to receive the second clock signal, the set end of the at least one shift register is used to receive the even set signal, and the reset end of the at least one shift register is used to receive the even reset signal; the input end of the first shift register is used to receive the second initial write data, the input end of the j-th shift register is connected to the output end of the j-1-th shift register, and the output end of the at least one shift register serves as the output end of the second data sub-circuit for outputting the second target write data; wherein j is an integer greater than 1.

13. The writing circuit according to claim 12, wherein: The first target write data includes first bit data, third bit data, fifth bit data and seventh bit data; The first data sub-circuit includes a first shift register, a second shift register, a third shift register and a fourth shift register; wherein: The input end of the first shift register is used to receive the first initial write data, the output end of the first shift register is connected to the input end of the second shift register, and the output end of the first shift register is used to output the seventh bit data; The input end of the second shift register is used to receive the seventh bit of data, the output end of the second shift register is connected to the input end of the third shift register, and the output end of the second shift register is used to output the fifth bit of data; The input end of the third shift register is used to receive the fifth bit of data, the output end of the third shift register is connected to the input end of the fourth shift register, and the output end of the third shift register is used to output the third bit of data; The input end of the fourth shift register is used to receive the third bit data, and the output end of the fourth shift register is used to output the first bit data.

14. The writing circuit according to claim 12, wherein: The second target write data includes a zeroth bit data, a second bit data, a fourth bit data and a sixth bit data; The second data sub-circuit includes a fifth shift register, a sixth shift register, a seventh shift register and an eighth shift register; wherein: The input end of the fifth shift register is used to receive the second initial write data, the output end of the fifth shift register is connected to the input end of the sixth shift register, and the output end of the fifth shift register is used to output the sixth bit data; The input end of the sixth shift register is used to receive the sixth bit of data, the output end of the sixth shift register is connected to the input end of the seventh shift register, and the output end of the sixth shift register is used to output the fourth bit of data; The input end of the seventh shift register is used to receive the fourth bit of data, the output end of the seventh shift register is connected to the input end of the eighth shift register, and the output end of the seventh shift register is used to output the second bit of data; The input end of the eighth shift register is used to receive the second bit data, and the output end of the eighth shift register is used to output the zeroth bit data.

15. A writing method, characterized in that: The method comprises: receiving an enable signal, a test mode signal, and an initial reset signal through a signal conversion circuit, and performing signal conversion processing according to the enable signal, the initial reset signal, and the test mode signal to obtain a first set signal and a first reset signal; receiving the first set signal and the first reset signal through a plurality of shift registers in a data generation circuit, and serially converting and processing the initial write data according to the plurality of shift registers to generate target write data; The initial write data is in a serial state, the target write data is in a parallel state, and the target write data is write data required by MBIST.

16. A memory, characterized in that: The memory comprises the write circuit according to any one of claims 1 to 14.

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