Pixel driving circuit, display panel and driving method thereof, and display device

Abstract

The present application provides a pixel driving circuit, a display panel and a driving method thereof, and a display device. The pixel driving circuit includes a data writing unit, a driving unit, a first storage unit, a light emitting control unit, a light emitting unit, a first switch unit, a second switch unit, a third switch unit, and a second storage unit. Each frame of the display screen includes a refresh frame, and the refresh frame includes a reset phase, an initialization phase, a compensation phase, a data writing phase, and a light emitting phase arranged in chronological order. In the compensation phase, the second switch control signal controls the second switch unit to turn on to transmit the second reference voltage signal to the first node, and the first switch control signal controls the first switch unit to turn on so that the voltage of the second node is discharged through the driving unit and the first switch unit to the sum of the second reference voltage and the threshold voltage of the driving unit. The pixel driving circuit can extend the compensation time of the threshold voltage and improve the compensation performance.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel driving circuit, a display panel and a driving method thereof, and a display device. Background Art

[0002] In recent years, display technology has evolved from hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) to low-temperature polycrystalline silicon (LTPS) TFTs, and then to low-temperature polycrystalline oxide (LTPO) TFTs. Specifically, LTPO TFTs constitute the next generation backplane technology for active-matrix organic light-emitting diode (AMOLED) display panels.

[0003] At present, different refresh rates are required in different display scenarios: fast-motion image scenarios, such as games and display scrolling, require a higher refresh rate; while low-power standby scenarios, such as always-on display and text mode, may only require a low refresh rate of 1Hz. Therefore, AMOLED display panels composed of LTPO TFTs are usually driven in a variable refresh rate mode, that is, driven at high frame rates and low frame rates to reduce power consumption.

[0004] However, when the refresh rate is high, the required frame rate increases and the scanning time of each row of pixel driving circuits is shortened. In most pixel driving circuits, the compensation time and the scanning time are the same, which will lead to a reduction in compensation time and a decrease in compensation performance. It cannot reduce the change in threshold voltage, thus causing uneven brightness. Summary of the invention

[0005] The present application provides a pixel driving circuit, a display panel and a driving method thereof, and a display device, aiming to solve the problem in the prior art that when a display panel with a variable refresh rate is driven at a high refresh rate, the compensation time is reduced and the compensation performance is reduced.

[0006] In order to solve the above technical problems, the first technical solution provided by the present application is to provide a pixel driving circuit. The pixel driving circuit includes:

[0007] A data writing unit, having a control end electrically coupled to a scan signal, a first end electrically coupled to a data signal, and a second end connected to a first node;

[0008] A driving unit, wherein the control end is connected to the first node, the first end is connected to the second node, and the second end is connected to the third node;

[0009] A first storage unit, a first end of which is connected to the first node, and a second end of which is connected to the second node;

[0010] A light emitting control unit, wherein a control end is electrically coupled to the first light emitting control signal, a first end is connected to the third node, and a second end is connected to the fourth node;

[0011] A light emitting unit, wherein the first electrode is connected to the fourth node, and the second electrode is electrically coupled to the second power signal;

[0012] A first switch unit, a control end of which is electrically coupled to a first switch control signal, a first end of which is electrically coupled to a first reference voltage signal, and a second end of which is connected to a third node;

[0013] A second switch unit, a control end of which is electrically coupled to a second switch control signal, a first end of which is electrically coupled to a second reference voltage signal, and a second end of which is connected to the first node;

[0014] a third switch unit, a control end of which is electrically coupled to the second light-emitting control signal, a first end of which is electrically coupled to the first power signal, and a second end of which is connected to the second node;

[0015] A second storage unit, a first end of which is electrically coupled to the first power signal and a second end of which is connected to the second node;

[0016] Each display frame includes a refresh frame, and the refresh frame includes a reset phase, an initialization phase, a compensation phase, a data writing phase, and a light emitting phase arranged in chronological order;

[0017] In the compensation stage, the second switch control signal controls the second switch unit to turn on to transmit the second reference voltage signal to the first node, and the first switch control signal controls the first switch unit to turn on so that the voltage of the second node is discharged through the driving unit and the first switch unit to the sum of the second reference voltage and the threshold voltage of the driving unit.

[0018] In some embodiments:

[0019] In the reset stage, the first light-emitting control signal controls the light-emitting control unit to turn on, and the first switch control signal controls the first switch unit to turn on, so as to transmit the initialization voltage to the fourth node; wherein the first reference voltage signal includes the initialization voltage;

[0020] In the initialization stage, the second switch control signal controls the second switch unit to turn on, so as to transmit the second reference voltage signal to the first node; the second light emitting control signal controls the third switch unit to turn on, so as to transmit the first power signal to the second node;

[0021] In the data writing phase, the scan signal controls the data writing unit to start, so as to write the data signal into the first node;

[0022] In the light-emitting stage, the second light-emitting control signal controls the third switch unit to turn on, the first light-emitting control signal controls the first switch unit to turn on, and the first storage unit discharges to keep the driving unit turned on and drive the light-emitting unit to emit light.

[0023] In some embodiments, the data writing unit includes a switching transistor, the driving unit includes a driving transistor, the light emitting control unit includes a light emitting control transistor, the first switching unit includes a first transistor, the second switching unit includes a second transistor, the third switching unit includes a third transistor, the first storage unit includes a storage capacitor, and the second storage unit includes a coupling capacitor;

[0024] Among them, the switch transistor and the second transistor are N-type low-temperature polycrystalline oxide transistors, and the drive transistor, the light-emitting control transistor, the first transistor and the third transistor are all P-type low-temperature polycrystalline silicon transistors.

[0025] In some embodiments, when the refresh rate of the pixel driving circuit is less than a preset value, each frame of the displayed picture further includes at least one skip frame, and the skip frame includes a lag compensation stage;

[0026] In the hysteresis compensation stage, the first switch control signal controls the first switch unit to turn on to transmit the bias voltage to the second node; wherein the first reference voltage signal also includes a bias voltage, and the value of the bias voltage is greater than the value of the data signal and greater than the voltage value of the first node.

[0027] In some embodiments, the number of skipped frames in each display frame is inversely proportional to the refresh rate of the pixel driving circuit.

[0028] In order to solve the above technical problem, the second technical solution provided by the present application is: to provide a display panel. The display panel includes:

[0029] substrate;

[0030] The pixel driving layer is arranged on the substrate and includes a plurality of pixel driving circuits involved in the above technical solution.

[0031] In order to solve the above technical problems, the third technical solution provided by the present application is: to provide a method for driving a display panel. The driving method includes: controlling a plurality of pixel driving circuits to display images frame by frame;

[0032] The step of controlling the plurality of driving circuits to display each frame of the display picture includes:

[0033] In the reset stage, the first light-emitting control signal controls the light-emitting control unit to turn on, and the first switch control signal controls the first switch unit to turn on, and transmits the initialization voltage to the fourth node; wherein the first reference voltage signal includes the initialization voltage;

[0034] In the initialization stage, the second switch control signal controls the second switch unit to turn on and transmit the second reference voltage signal to the first node, and the second light emitting control signal controls the third switch unit to turn on and transmit the first power signal to the second node;

[0035] In the compensation stage, the second switch control signal controls the second switch unit to remain turned on to maintain the potential of the first node, the first switch control signal controls the first switch unit to be turned on, and the voltage of the first node is discharged to the sum of the second reference voltage and the threshold voltage of the drive unit through the drive unit and the first switch unit;

[0036] In the data writing phase, the scan signal controls the data writing unit to start, and writes the data signal into the first node;

[0037] In the light-emitting stage, the second light-emitting control signal controls the third switch unit to turn on, the first light-emitting control signal controls the first switch unit to turn on, the first storage unit discharges, the driving unit is maintained turned on, and the light-emitting unit is driven to emit light.

[0038] In some embodiments, a plurality of pixel driving circuits are arranged in an array;

[0039] The driving method also includes:

[0040] In response to a current refresh rate of the display panel being greater than a preset value, a compensation phase of each row of pixel driving circuits is controlled to overlap with compensation phases of other rows of pixel driving circuits; wherein the overlapping duration is adjusted according to the current refresh rate.

[0041] In some embodiments, the driving method further comprises:

[0042] In response to a current refresh rate of the display panel being less than a preset value, inserting a corresponding number of skip frames in each frame of the display according to the current refresh rate; wherein the skip frames include a lag compensation stage;

[0043] In the hysteresis compensation stage, the first switch control signal controls the first switch unit to turn on and transmit the bias voltage to the second node; wherein the first reference voltage signal also includes a bias voltage, and the value of the bias voltage is greater than the value of the data signal and greater than the voltage value of the first node.

[0044] In order to solve the above technical problem, the second technical solution provided by the present application is to provide a display device. The display device includes:

[0045] A display panel, which is the display panel involved in the above technical solution;

[0046] The driving module is coupled to the display panel and is used to drive the display panel, and the driving method is the driving method involved in the above technical solution.

[0047] Beneficial effects of the present application: Different from the prior art, the present application provides a pixel driving circuit, a display panel and a driving method thereof, and a display device. The pixel driving circuit includes a data writing unit, a driving unit, a first storage unit, a light emitting control unit, a light emitting unit, a first switch unit, a second switch unit, a third switch unit, and a second storage unit. Wherein, each frame of the display picture displayed by the pixel driving circuit includes a refresh frame, and the refresh frame includes a reset phase, an initialization phase, a compensation phase, a data writing phase, and a light emitting phase arranged in chronological order; in the embodiment of the present application, in the compensation phase, the pixel driving circuit controls the second switch unit to be turned on by the second switch control signal to transmit the second reference voltage signal to the first node, and controls the first switch control signal to be turned on, so that the voltage of the second node is discharged to the first reference voltage signal terminal through the driving unit and the first switch unit, and under the coupling action of the second storage unit, the voltage of the second node is discharged to the sum of the second reference voltage and the threshold voltage of the driving unit, so as to compensate the threshold voltage of the driving unit; and in the compensation phase, compensation is achieved by the second switch control signal and the first switch on control signal, and no voltage on the data line is required. And there is no timing correlation with the scanning time, so the compensation time is no longer limited by the scanning time. The duration of the compensation phase can be adjusted by adjusting the first switch unit control signal and the second switch unit control signal, thereby ensuring the duration of the compensation phase. It can effectively avoid the problem of reduced compensation time leading to decreased compensation performance when driving at a high refresh rate, so that the driving unit can also generate a stable driving current when driving at a high refresh rate, thereby improving the image display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0049] Figure 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present application;

[0050] Figure 2 is a structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application;

[0051] Figure 3 is a driving timing diagram of a pixel driving circuit provided in an embodiment of the present application in a refresh frame phase;

[0052] Figure 4 yes Figure 2 A schematic diagram of a state of a pixel driving circuit in a reset phase provided by an embodiment;

[0053] Figure 5 yes Figure 2 A schematic diagram of the state of a pixel driving circuit in an initialization stage provided by an embodiment;

[0054] Figure 6 yes Figure 2 A schematic diagram of the state of a pixel driving circuit in a compensation stage provided by an embodiment;

[0055] Figure 7 yes Figure 2 A schematic diagram of the state of a pixel driving circuit in a data writing stage provided by an embodiment;

[0056] Figure 8 yes Figure 2 A schematic diagram of the state of a pixel driving circuit in a light emitting stage provided by an embodiment;

[0057] Fig. 9 It is a schematic diagram of the IV characteristic curve of an existing P-type transistor;

[0058] Fig.10 is a driving timing diagram of a pixel driving circuit in a skip frame stage provided by an embodiment of the present application;

[0059] Fig.11 yes Figure 2 A schematic diagram of the state of a pixel driving circuit in a hysteresis compensation stage provided by an embodiment;

[0060] Fig.12 is a schematic flow chart of a method for driving a display panel provided in one embodiment of the present application;

[0061] Fig.13 It is a schematic diagram of the structure of a display device provided in one embodiment of the present application.

[0062] Reference numerals:

[0063] 100-display panel; 10-substrate; 20-pixel driving layer; 21-pixel driving circuit; 211-data writing unit; 212-driving unit; 213-light emitting control unit; 214-first switching unit; 215-second switching unit; 216-third switching unit; 217-first storage unit; 218-second storage unit; 219-light emitting unit; 200-driving module;

[0064] T1-switching transistor; T2-driving transistor; T3-light-emitting control transistor; T4-first transistor; T5-second transistor; T6-third transistor; C1-storage capacitor; C2-coupling capacitor; P1-first node; P2-second node; P3-third node; P4-fourth node;

[0065] R(n-1)-first light-emitting control signal; R(n)-second light-emitting control signal; S1(n)-first switch control signal; S2(n)-second switch control signal; DV-first reference voltage signal; Vref-second reference voltage signal; Vin-initialization voltage; Vb-bias voltage; VDD-first power supply signal; VSS-second power supply signal; t1-reset phase; t2-initialization phase; t3-compensation phase; t4-data writing phase; t5-light-emitting phase; tB-hysteresis compensation phase. DETAILED DESCRIPTION

[0066] The scheme of the embodiment of the present application is described in detail below in conjunction with the drawings of the specification.

[0067] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0068] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0069] The terms "first", "second" and "third" in this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second" and "third" can explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of this application are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0070] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0071] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0072] See also Figure 1 , Figure 1 : is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. In this embodiment, a display panel 100 is provided, and the display panel 100 includes a substrate 10 and a pixel driving layer 20. Among them, the substrate 10 is used to carry the pixel driving layer 20. The substrate 10 can be a glass substrate or a flexible substrate, which can be specifically configured according to actual needs. For example, a flexible substrate can be used as the substrate 10 to achieve the foldable function or the rolling function of the display panel 100. The pixel driving layer 20 is arranged on one side of the substrate 10, and can be specifically arranged on one side surface of the substrate 10. The pixel driving layer 20 includes a plurality of pixel driving circuits 21 for displaying images; the plurality of pixel driving circuits 21 can be arranged in a preset array arrangement to further enhance the display effect. The specific structure and function of the pixel driving circuit 21 are described in the following embodiments, and please refer to the detailed description below.

[0073] See also Figure 2 , Figure 2 2 is a schematic diagram of a pixel driving circuit according to an embodiment of the present application. In this embodiment, a pixel driving circuit 21 is provided, and the pixel driving circuit 21 includes a data writing unit 211, a driving unit 212, a first storage unit 217, a light emitting control unit 213, a light emitting unit 219, a first switch unit 214, a second switch unit 215, a third switch unit 216, and a second storage unit 218.

[0074] The data writing unit 211 has a control end electrically coupled to the scan signal Scan, a first end electrically coupled to the data signal Vdata, and a second end connected to the first node P1.

[0075] The driving unit 212 has a control end connected to the first node P1, a first end connected to the second node P2, and a second end connected to the third node P3.

[0076] The first storage unit 217 has a first end connected to the first node P1 and a second end connected to the second node P2.

[0077] The light emitting control unit 213 has a control end electrically coupled to the first light emitting control signal R(n-1), a first end connected to the third node P3, and a second end connected to the fourth node P4.

[0078] The light emitting unit 219 includes a first electrode and a second electrode, the first electrode is connected to the fourth node P4, and the second electrode is electrically coupled to the second power signal VSS.

[0079] The first switch unit 214 has a control terminal electrically coupled to the first switch control signal S1 (n), a first terminal electrically coupled to the first reference voltage signal DV, and a second terminal connected to the third node P3.

[0080] The second switch unit 215 has a control terminal electrically coupled to the second switch control signal S2 (n), a first terminal electrically coupled to the second reference voltage signal Vref, and a second terminal connected to the first node P1 .

[0081] The third switch unit 216 has a control end electrically coupled to the second light emitting control signal R(n), a first end electrically coupled to the first power signal VDD, and a second end connected to the second node P2.

[0082] The second storage unit 218 has a first terminal electrically coupled to the first power signal VDD, and a second terminal connected to the second node P2.

[0083] Please refer to Figure 3 , Figure 3 1 is a driving timing diagram of a pixel driving circuit in a refresh frame stage provided by an embodiment of the present application. Each display frame displayed by the pixel driving circuit 21 includes a refresh frame, and the refresh frame includes a reset stage t1, an initialization stage t2, a compensation stage t3, a data writing stage t4, and a light emitting stage t5 arranged in chronological order.

[0084] In the compensation stage t3, the second switch control signal S2(n) controls the second switch unit 215 to turn on so as to transmit the second reference voltage signal Vref to the first node P1, and the first switch control signal S1(n) controls the first switch unit 214 to turn on so that the voltage of the second node P2 is discharged to the sum of the second reference voltage and the threshold voltage Vth of the drive unit 212 through the drive unit 212 and the first switch unit 214.

[0085] It can be understood that in the compensation stage t3, the pixel driving circuit 21 controls the second switch unit 215 to turn on by the second switch control signal S2(n) to transmit the second reference voltage signal Vref to the first node P1, and controls the first switch unit 214 to turn on by the first switch control signal S1(n), so that the voltage of the second node P2 is discharged to the first reference voltage signal DV terminal through the driving unit 212 and the first switch unit 214, and the voltage of the second node P2 is discharged to the sum of the second reference voltage and the threshold voltage Vth of the driving unit 212, that is, Vref+Vth, under the coupling effect of the second storage unit 218, so as to compensate the threshold voltage Vth of the driving unit 212. In the compensation stage t3, compensation is achieved by the second switch control signal S2(n) and the first switch on control signal, and no voltage on the data line is required. And there is no timing correlation with the scanning time, so the compensation time is no longer limited by the scanning time. The duration of the compensation stage t3 can be adjusted by adjusting the control signal of the first switch unit 214 and the control signal of the second switch unit 215, thereby ensuring the duration of the compensation stage t3. It can effectively avoid the problem of reduced compensation time leading to reduced compensation performance during high refresh rate driving, so that the driving unit 212 can also generate a stable driving current during high refresh rate driving, thereby improving the image display quality of the display panel 100.

[0086] Specifically, in the embodiment of the present application, the data writing unit 211 includes a switching transistor T1, the driving unit 212 includes a driving transistor T2, the light emitting control unit 213 includes a light emitting control transistor T3, the first switching unit 214 includes a first transistor T4, the second switching unit 215 includes a second transistor T5, the third switching unit 216 includes a third transistor T6, the first storage unit 217 includes a storage capacitor C1, and the second storage unit 218 includes a coupling capacitor C2.

[0087] Among them, the transistors of each of the above-mentioned units and the driving transistor T2 can be P-type transistors and / or N-type transistors. At the same time, silicon-based transistors, such as a-Si:H transistors, LTPS transistors, or oxide transistors, can also be used. The specific settings can be made according to the actual circuit design needs. In this embodiment, the switch transistor T1 and the second transistor T5 are N-type low-temperature polycrystalline oxide transistors (LTPO TFTs), and the driving transistor T2, the light-emitting control transistor T3, the first transistor T4, and the third transistor T6 are all P-type low-temperature polycrystalline silicon transistors (LTPS TFTs), so that the display panel 100 can be driven in a variable refresh rate mode to reduce power consumption. At the same time, by making the switch transistor T1 and the second transistor T5 low-temperature polycrystalline oxide transistors (LTPO TFTs), the leakage current at the first node P1 can be reduced, that is, the leakage current at the control end (gate) of the driving transistor T2 can be reduced, thereby reducing the probability of the flicker phenomenon caused by the leakage current and improving the image quality. Furthermore, by making the switch transistor T1 and the second transistor T5 N-type transistors and the other transistors P-type transistors, the scan signal Scan only needs to jump to a high level in the data writing phase t4, and maintain a low level at other times, and the second switch control signal S2 (n) only needs to jump to a high level in the reset phase t1 and the compensation phase t3, and maintain a low level at other times, which can further reduce the driving power consumption.

[0088] See also Figure 3 and Figure 4 , Figure 4 yes Figure 2 A state diagram of a pixel driving circuit in a reset phase provided in an embodiment. Specifically, in the reset phase t1 of the pixel driving circuit 21, the first light control signal R(n-1) controls the light control unit 213 to turn on, and the first switch control signal S1(n) controls the first switch unit 214 to turn on, so as to transmit the initialization voltage Vin to the fourth node P4; wherein the first reference voltage signal DV includes the initialization voltage Vin.

[0089] Specifically, in the reset phase t1, the scan signal Scan and the second switch control signal S2(n) are at a low level, and the second light control signal R(n) is at a high level, so that the switch transistor T1, the second transistor T5 and the third transistor T6 are in the off state; the first light control signal R(n-1) and the first switch control signal S1(n) are at a low level, so that the light control transistor T3 and the first transistor T4 are turned on. At this time, the first reference voltage signal DV provides an initialization voltage Vin to transmit the initialization voltage Vin to the first electrode of the light emitting unit 219 through the first transistor T4 and the light control transistor T3, so as to realize the voltage initialization of the first electrode of the light emitting unit 219, thereby improving the low grayscale non-uniformity. In a specific embodiment, when the light emitting unit 219 needs to display a black image, the initialization voltage Vin can be made less than or equal to the turn-on voltage of the light emitting unit 219 to prevent current from flowing through the light emitting unit 219, so that the light emitting unit 219 displays a black picture.

[0090] See also Figure 3 and Figure 5 , Figure 5 yes Figure 2 A schematic diagram of the state of the pixel driving circuit in the initialization stage provided in the embodiment. Specifically, in the initialization stage t2 of the pixel driving circuit 21, the second switch control signal S2(n) controls the second switch unit 215 to turn on, so as to transmit the second reference voltage signal Vref to the first node P1; the second light emitting control signal R(n) controls the third switch unit 216 to turn on, so as to transmit the first power supply signal VDD to the second node P2.

[0091] Specifically, in the initialization stage t2, the second switch control signal S2(n) is at a high level, the second transistor T5 is turned on, and the second reference voltage signal Vref is transmitted to the first node P1 through the second transistor T5; the scan signal Scan is at a low level, and the switch transistor T1 is in an off state; the first switch control signal S1(n) and the first light control signal R(n-1) are at a high level, and the first transistor T4 and the light control transistor T3 are in an off state; the second light control signal R(n) is at a low level, the third transistor T6 is turned on, and the first power supply signal VDD is transmitted to the second node P2 through the third transistor T6; in this stage, the voltage of the control terminal (gate) and the voltage of the first terminal (source) of the driving transistor T2 are initialized to the second reference voltage signal Vref and the first power supply signal VDD, respectively. At the same time, in this stage, since the light control transistor T3 is in an off state, the light emitting unit 219 is completely turned off, achieving true black brightness.

[0092] See also Figure 3 and Figure 6 , Figure 6 yes Figure 2A state diagram of a pixel driving circuit in a compensation stage provided in an embodiment. Specifically, in the compensation stage t3 of the pixel driving circuit 21, the second switch control signal S2(n) controls the second switch unit 215 to turn on, so as to transmit the second reference voltage signal Vref to the first node P1, and the first switch control signal S1(n) controls the first switch unit 214 to turn on, so that the voltage of the second node P2 is discharged to the sum of the second reference voltage and the threshold voltage Vth of the driving unit 212 through the driving unit 212 and the first switch unit 214.

[0093] Specifically, in the compensation stage t3, the first light-emitting control signal R(n-1) and the second light-emitting control signal R(n) are both at a high level, and the light-emitting control transistor T3 and the third transistor T6 are turned off. The second switch control signal S2(n) remains at a high level, the second switch transistor T1 remains turned on, and the second reference voltage signal Vref still acts on the first node P1, so that the voltage of the first node P1 remains at the second reference voltage signal Vref; the first switch control signal S1(n) is at a low level, and the first transistor T4 is turned on. At this time, due to the coupling effect of the coupling capacitor C2, the potential of the second node P2 increases, so that the gate-source voltage (V GS ) is greater than the threshold voltage Vth, the driving transistor T2 starts to generate current, and the second node P2 is discharged through the driving transistor T2 and the first transistor T4 until it is discharged to the sum of the second reference voltage signal Vref and the threshold voltage Vth. The driving transistor T2 is turned off, that is, at this time, the voltage of the second node P2 is the sum of the second reference voltage and the threshold voltage Vth, thereby compensating for the threshold voltage Vth of the driving transistor T2.

[0094] It can be seen that, in this stage, the scanning signal Scan is always kept at a low potential to turn off the switching transistor T1, that is, the compensation method does not require any voltage on the data line, so the compensation time of the threshold voltage Vth of the driving transistor T2 is not limited by the scanning time, so the compensation time of the multi-row pixel driving circuit 21 can overlap to enhance the compensation effect of the threshold voltage Vth of the driving transistor T2, so that the driving transistor T2 can generate a stable driving current when driven at a high refresh rate, thereby significantly improving the motion image quality of the display panel 100. Moreover, in this stage, the light-emitting control transistor T3 is in the off state, and the first reference voltage signal DV terminal is the initialization voltage Vin, which is less than the second power supply voltage, so the current generated by the driving transistor T2 flows into the first reference voltage signal DV terminal, rather than the light-emitting unit 219, and the light-emitting unit 219 still maintains a completely black state in this stage, and no light leakage occurs.

[0095] See also Figure 3 and Figure 7 , Figure 7yes Figure 2 Schematic diagram of the state of the pixel driving circuit in the data writing stage provided by the embodiment. Specifically, in the compensation stage t3, the scanning signal Scan controls the data writing unit 211 to turn on to write the data signal Vdata into the first node P1.

[0096] Specifically, in the data writing stage t4, the second switch control signal S2(n) is at a low level, and the second transistor T5 is turned off; the scan signal Scan becomes a high level, the switch transistor T1 is turned on, and the data signal Vdata is written to the first node P1 through the switch transistor T1 to store the data signal Vdata in the storage capacitor C1.

[0097] See also Figure 3 and Figure 8 , Figure 8 yes Figure 2 Schematic diagram of the state of the pixel driving circuit in the light-emitting stage provided in the embodiment. Specifically, in the light-emitting stage t5, the second light-emitting control signal R(n) controls the third switch unit 216 to turn on, the first light-emitting control signal R(n-1) controls the first switch unit 214 to turn on, and the first storage unit 217 discharges to maintain the driving unit 212 to remain turned on, and drives the light-emitting unit 219 to emit light.

[0098] Specifically, in the light-emitting stage t5, the second switch control signal S2(n) and the scan signal Scan are at a low level, so that the second transistor T5 and the switch transistor T1 are turned off; the first light-emitting control signal R(n-1) and the second light-emitting control signal R(n) are at a low level, so that the light-emitting control transistor T3 and the third transistor T6 are turned on, and the first power supply voltage signal acts on the second node P2 through the third transistor T6, and the storage capacitor C1 is discharged to maintain the driving transistor T2 to remain turned on, and the light-emitting units 219 in all the sub-pixel driving circuits 21 of the corresponding row begin to emit light. At the same time, through the compensation effect of the threshold voltage Vth in the compensation stage t3, the driving transistor T2 can generate a stable driving current, and the resistance of the first power supply signal VDD line will not affect the uniformity of the displayed image.

[0099] Specifically, the light-emitting unit 219 includes a current-driven light-emitting device such as a light-emitting diode (LED), a sub-millimeter light-emitting diode (Mini-LED), a micro-light-emitting diode (Micro-LED), or an organic light-emitting diode (OLED). In this embodiment, the light-emitting unit 219 is an OLED, and the first electrode of the light-emitting unit 219 can be an anode, and the second electrode can be a cathode. In other embodiments, the first electrode of the light-emitting unit 219 can also be a cathode, and the second electrode can be an anode.

[0100] When the display panel 100 is driven at a low refresh rate, the lower the frame rate, the longer the first storage unit 217 needs to store the data signal Vdata. Unlike LTPS TFT, indium gallium zinc oxide (IGZO) TFT can achieve low frame rate driving due to its extremely low leakage current. However, in the pixel driving circuit 21 using LTPO TFT as the switching transistor T1, the LTPS-based driving transistor T2 still has a hysteresis problem. Generally, the brightness change caused by the hysteresis of the driving transistor T2 is not obvious at a conventional refresh rate, while the brightness change caused by the hysteresis of the driving transistor T2 at a low refresh rate will produce a more obvious flicker phenomenon. Therefore, when the pixel driving circuit 21 is driven at a low refresh rate, the current of the driving transistor T2 should be stabilized as quickly as possible in the image change device to minimize the perceived flicker. This hysteresis can be attributed to carrier capture or de-capture, which affects the threshold voltage Vth and causes transient brightness changes.

[0101] See also Fig. 9 , Fig. 9 Schematic diagram of IV characteristic curve of existing P-type transistor. First, sampling of threshold voltage Vth: As shown in the figure, the solid line in the figure represents the IV characteristic curve of driving transistor T2 in the threshold voltage Vth sampling and data signal Vdata writing stage. At this time, the threshold voltage Vth [point (1) in the figure] is sampled, and the gate-source voltage V is adjusted according to the sampled threshold voltage Vth and the data voltage. GS [Point (2) in the figure] is controlled to emit the current I from the required light emitting unit 219 DS_2 Start by providing the desired brightness.

[0102] Then, in the light-emitting cycle, the dotted line in the figure is the IV characteristic curve of the light-emitting stage t5. After the data signal Vdata is written, due to the hysteresis effect of the driving transistor T2, the stress applied to the driving transistor T2 changes the IV characteristic curve of the driving transistor T2 from I DS_2 Change to I DS_3 , thereby changing the brightness. The transient brightness change caused by the hysteresis of the driving transistor T2 will not produce visible flicker at a normal refresh rate, because the perceived brightness fluctuation is far below the flicker threshold. However, at a low refresh rate, the user's sensitivity to flicker is greatly increased, the hysteresis effect is aggravated, and the greater the brightness fluctuation, the more obvious the flicker. This requires the leakage current of the driving transistor T2 at a low refresh rate, thereby improving the hysteresis effect of the driving transistor T2. However, the hysteresis effect is an inherent characteristic of the LTPS TFT. In order to solve this technical problem, the present application proposes the following implementation method, please refer to the detailed description below for details.

[0103] See also Fig.10 and Fig.11 . Fig.10is a driving timing diagram of a pixel driving circuit in a skip frame stage provided by an embodiment of the present application, Fig.11 yes Figure 2 A state diagram of a pixel driving circuit in a hysteresis compensation stage provided in an embodiment. In an embodiment of the present application, when the refresh rate of the pixel driving circuit 21 is less than a preset value, each frame of the display screen also includes at least one skip frame, and the skip frame includes a hysteresis compensation stage tB. In the hysteresis compensation stage tB, the first switch control signal S1(n) controls the first switch unit 214 to turn on, so as to transmit the bias voltage Vb to the second node P2; wherein the first reference voltage signal DV also includes a bias voltage Vb, and the value of the bias voltage Vb is greater than the value of the data signal Vdata, and greater than the voltage value of the first node P1.

[0104] Specifically, when the pixel driving circuit 21 needs to be driven at a low refresh rate, the number of skip frames inserted in each frame of the display picture can be determined specifically according to the refresh rate. It can be understood that the lower the refresh rate, the longer the time of a frame display picture, and the more skip frames are inserted in a frame display panel 100, that is, the refresh rate can be reduced by inserting skip frames in the frame display picture, and the number of skip frames in each frame of the display picture is inversely proportional to the refresh rate of the pixel driving circuit 21. Among them, the duration of the skip frame and the duration of the refresh frame can be the same or different. In the embodiment of the present application, the duration of the skip frame is the same as the duration of the refresh frame to facilitate the calculation of the number of skip frames inserted and the setting of each stage in the skip frame; at the same time, the specific position of the lag compensation stage tB in the skip frame can be set according to actual design needs.

[0105] At the same time, during the frame skipping stage, the change in the driving current caused by the hysteresis effect of the driving transistor T2 can be compensated. Fig.10 and Fig.11 As shown, the skip frame includes a subsequent compensation stage t3. In the subsequent compensation stage t3, the first switch control signal S1(n) is at a low level, the first transistor T4 is turned on, and the driving transistor T2 is in a conducting state, so as to transmit the bias voltage Vb provided by the first reference voltage terminal to the second node P2 through the first transistor T4 and the driving transistor T2, so as to compensate for the hysteresis of the driving transistor T2, thereby reducing the flicker phenomenon. Among them, the value of the bias voltage Vb is greater than the value of the data signal Vdata, and greater than the voltage value of the first node P1, so that the gate-source voltage V GS Maintain a stable state.

[0106] See also Fig.12 , Fig.121 is a flow chart of a method for driving a display panel provided in one embodiment of the present application. In this embodiment, a method for driving a display panel 100 is provided, and the method for driving the display panel 100 involved in the above embodiment. The method for driving includes:

[0107] S1: in response to the current refresh rate of the display panel 100 being greater than a preset value, controlling the compensation phase t3 of each row of pixel driving circuits 21 to overlap with the compensation phase t3 of other rows of pixel driving circuits 21;

[0108] S2: In response to the current refresh rate of the display panel 100 being less than a preset value, inserting a corresponding number of skip frames in each display frame according to the current refresh rate; wherein the skip frames include a lag compensation stage tB;

[0109] S3: Control multiple pixel driving circuits 21 to display pictures frame by frame.

[0110] The driving method drives the display panel 100 to display images in a variable refresh rate manner. Among them, when the current refresh rate of the display panel 100 is greater than the preset value, the compensation stage t3 of each row of pixel driving circuits 21 is controlled to overlap with the compensation stage t3 of other rows of pixel driving circuits 21. Specifically, the driving method of the pixel driving circuit 21 is the same as the driving method involved in the above embodiment, and the same technical effect can be achieved. For details, please refer to the detailed introduction above, thereby extending the compensation time of the threshold voltage Vth of each row of pixel driving circuits 21, which can effectively improve the compensation performance, thereby reducing the flicker problem caused by unstable driving current. Specifically, the overlapping time can be adjusted according to the current refresh rate and compensation effect requirements.

[0111] When driving at a high refresh rate, step S3 specifically includes:

[0112] S31: In the reset phase t1, the first light control signal R(n-1) controls the light control unit 213 to turn on, and the first switch control signal S1(n) controls the first switch unit 214 to turn on, and transmits the initialization voltage Vin to the fourth node P4; wherein the first reference voltage signal DV includes the initialization voltage Vin;

[0113] S32: In the initialization phase t2, the second switch control signal S2(n) controls the second switch unit 215 to turn on, and transmits the second reference voltage signal Vref to the first node P1, and the second light emitting control signal R(n) controls the third switch unit 216 to turn on, and transmits the first power signal VDD to the second node P2;

[0114] S33: In the compensation stage t3, the second switch control signal S2(n) controls the second switch unit 215 to remain turned on, maintaining the potential of the first node P1, and the first switch control signal S1(n) controls the first switch unit 214 to be turned on, and the voltage of the first node P1 is discharged to the sum of the second reference voltage and the threshold voltage Vth of the drive unit 212 through the drive unit 212 and the first switch unit 214;

[0115] S34: in the data writing phase t4, the scan signal Scan controls the data writing unit 211 to start, and writes the data signal Vdata into the first node P1;

[0116] S35: In the light-emitting stage t5, the second light-emitting control signal R(n) controls the third switch unit 216 to turn on, the first light-emitting control signal R(n-1) controls the first switch unit 214 to turn on, the first storage unit 217 discharges, the driving unit 212 is maintained turned on, and the light-emitting unit 219 is driven to emit light.

[0117] Specifically, the specific driving process of steps S31 to S35 can be referred to Figure 3-8 As well as the relevant text descriptions above, I will not repeat them here.

[0118] In the case of low refresh rate driving, in order to compensate for the hysteresis effect of the driving transistor T2, step S3 further includes:

[0119] S36: In the lag compensation stage tB, the first switch control signal S1(n) controls the first switch unit 214 to turn on, and transmits the bias voltage Vb to the second node P2; wherein the first reference voltage signal DV also includes the bias voltage Vb, and the value of the bias voltage Vb is greater than the value of the data signal Vdata, and greater than the voltage value of the first node P1.

[0120] Specifically, the specific driving process of step S36 can be referred to Fig.10 and Fig.11 The above-mentioned preset value of the refresh rate can be set according to the performance of the pixel driving circuit 21. For example, when the refresh rate of the pixel driving circuit 21 is higher than a certain value, there will be a flicker problem caused by obvious insufficient compensation, and the preset value can be set to this value; when the refresh rate of the pixel driving circuit 21 is lower than a certain value, there will be a flicker problem caused by obvious hysteresis of the driving transistor T2, and this value can be used as the preset value; specifically, the above two preset values ​​can be determined through test experiments, and the two preset values ​​can be the same or different, which is determined specifically according to the experimental results.

[0121] See also Fig.13 , Fig.131 is a schematic diagram of a display device according to an embodiment of the present application. In this embodiment, a display device is provided, and the display device includes a display panel 100 and a driving module 200 .

[0122] Among them, the display panel 100 is the display panel 100 involved in the above embodiment, and has the same structure and function as the display panel 100 involved in the above embodiment, and can achieve the same technical effect. For details, please refer to the detailed description above.

[0123] Among them, the driving module 200 is coupled to the display panel 100 for driving the display panel 100, and the driving method is the driving method involved in the above embodiment, and has the same technical effect as the driving method involved in the above embodiment. For details, please refer to the detailed description above.

[0124] The above are only implementation methods of the present application, and are not intended to limit the patent protection scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A pixel driving circuit, comprising: A data writing unit, having a control end electrically coupled to a scan signal, a first end electrically coupled to a data signal, and a second end connected to a first node; A driving unit, wherein the control end is connected to the first node, the first end is connected to the second node, and the second end is connected to the third node; a first storage unit, a first end of which is connected to the first node, and a second end of which is connected to the second node; A light emitting control unit, wherein a control end is electrically coupled to the first light emitting control signal, a first end is connected to the third node, and a second end is connected to the fourth node; A light emitting unit, wherein the first electrode is connected to the fourth node, and the second electrode is electrically coupled to a second power signal; Characterized in that the pixel driving circuit further comprises: A first switch unit, a control end of which is electrically coupled to a first switch control signal, a first end of which is electrically coupled to a first reference voltage signal, and a second end of which is connected to the third node; A second switch unit, a control end of which is electrically coupled to a second switch control signal, a first end of which is electrically coupled to a second reference voltage signal, and a second end of which is connected to the first node; a third switch unit, a control end of which is electrically coupled to the second light-emitting control signal, a first end of which is electrically coupled to the first power signal, and a second end of which is connected to the second node; A second storage unit, a first end of which is electrically coupled to the first power signal, and a second end of which is connected to the second node; Each display frame includes a refresh frame, and the refresh frame includes a reset phase, an initialization phase, a compensation phase, a data writing phase, and a light emitting phase arranged in chronological order; In the compensation stage, the second switch control signal controls the second switch unit to turn on, so as to transmit the second reference voltage signal to the first node, and the first switch control signal controls the first switch unit to turn on, so as to discharge the voltage of the second node to the sum of the second reference voltage and the threshold voltage of the drive unit through the drive unit and the first switch unit; When the refresh rate of the pixel driving circuit is less than a preset value, each frame of the displayed picture further includes at least one skip frame, and the skip frame includes a lag compensation stage; In the hysteresis compensation stage, the first switch control signal controls the first switch unit to turn on so as to transmit the bias voltage to the second node; wherein the first reference voltage signal also includes the bias voltage, and the value of the bias voltage is greater than the value of the data signal and greater than the voltage value of the first node.

2. The pixel driving circuit according to claim 1, characterized in that: In the reset stage, the first light-emitting control signal controls the light-emitting control unit to turn on, and the first switch control signal controls the first switch unit to turn on, so as to transmit the initialization voltage to the fourth node; wherein the first reference voltage signal includes the initialization voltage; In the initialization stage, the second switch control signal controls the second switch unit to turn on, so as to transmit the second reference voltage signal to the first node; the second light emitting control signal controls the third switch unit to turn on, so as to transmit the first power signal to the second node; In the data writing phase, the scan signal controls the data writing unit to start up, so as to write the data signal into the first node; In the light-emitting stage, the second light-emitting control signal controls the third switch unit to turn on, the first light-emitting control signal controls the first switch unit to turn on, and the first storage unit discharges to maintain the driving unit turned on to drive the light-emitting unit to emit light.

3. The pixel driving circuit according to claim 1, characterized in that: The data writing unit includes a switch transistor, the driving unit includes a driving transistor, the light emitting control unit includes a light emitting control transistor, the first switch unit includes a first transistor, the second switch unit includes a second transistor, the third switch unit includes a third transistor, the first storage unit includes a storage capacitor, and the second storage unit includes a coupling capacitor; The switch transistor and the second transistor are N-type low-temperature polycrystalline oxide transistors, and the drive transistor, the light-emitting control transistor, the first transistor and the third transistor are P-type low-temperature polycrystalline silicon transistors.

4. The pixel driving circuit according to claim 1, characterized in that: The number of skipped frames in each frame of display picture is inversely proportional to the refresh rate of the pixel driving circuit.

5. A display panel, characterized in that: include: substrate; The pixel driving layer is arranged on the substrate and comprises a plurality of pixel driving circuits as claimed in any one of claims 1 to 4.

6. A method for driving a display panel, wherein the display panel is the display panel according to claim 5, characterized in that: The driving method comprises: controlling a plurality of pixel driving circuits to display pictures frame by frame; The step of controlling the plurality of driving circuits to display each frame of the display picture includes: In the reset stage, the first light-emitting control signal controls the light-emitting control unit to turn on, and the first switch control signal controls the first switch unit to turn on, so as to transmit the initialization voltage to the fourth node; wherein the first reference voltage signal includes the initialization voltage; In the initialization stage, the second switch control signal controls the second switch unit to turn on and transmit the second reference voltage signal to the first node, and the second light emitting control signal controls the third switch unit to turn on and transmit the first power signal to the second node; In the compensation stage, the second switch control signal controls the second switch unit to remain turned on, maintaining the potential of the first node, the first switch control signal controls the first switch unit to be turned on, and the voltage of the first node is discharged to the sum of the second reference voltage and the threshold voltage of the drive unit through the drive unit and the first switch unit; In the data writing phase, the scan signal controls the data writing unit to start, and writes the data signal into the first node; In the light-emitting stage, the second light-emitting control signal controls the third switch unit to turn on, the first light-emitting control signal controls the first switch unit to turn on, the first storage unit is discharged, the driving unit is maintained turned on, and the light-emitting unit is driven to emit light; The driving method further includes: In response to a current refresh rate of the display panel being less than a preset value, inserting a corresponding number of skip frames in each frame of display according to the current refresh rate; wherein the skip frames include a lag compensation stage; In the hysteresis compensation stage, the first switch control signal controls the first switch unit to turn on and transmit the bias voltage to the second node; wherein the first reference voltage signal also includes the bias voltage, and the value of the bias voltage is greater than the value of the data signal and greater than the voltage value of the first node.

7. The driving method according to claim 6, characterized in that: A plurality of the pixel driving circuits are arranged in an array; The driving method further includes: In response to a current refresh rate of the display panel being greater than a preset value, the compensation phase of each row of the pixel driving circuit is controlled to overlap with the compensation phase of other rows of the pixel driving circuit; wherein the overlapping duration is adjusted according to the current refresh rate.

8. A display device, characterized in that: include: The display panel is the display panel as claimed in claim 5; A driving module is coupled to the display panel and is used to drive the display panel, and a driving method is the driving method as claimed in claim 6 or 7.

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