A method and device for implementing forwarding table resource expansion

Abstract

The present application discloses a method and device for implementing forwarding table resource expansion. The method includes setting a global virtual resource pool; obtaining a host IP address prefix, a next hop MAC address, a corresponding VLAN, and an egress port based on a software adjacency table entry; applying for a virtual next hop index from the global virtual resource pool for the next hop MAC address and the corresponding VLAN; generating a first longest prefix match (LPM) table entry when the total number of applied virtual next hops does not exceed the total number of global next hop indexes in the hardware global resource pool; wherein the host IP address prefix points to the virtual next hop index and the egress port; and synchronizing the first LPM table entry and the MAC address and VLAN of the next hop pointed to by the virtual next hop index to each switching chip.

Description

Technical Field

[0001] The present application relates to communication technology, and more specifically to a method and device for implementing forwarding table resource expansion. Background Art

[0002] In a distributed device, the processor of the service board receives the ARP (Address Resolution Protocol) message or ND (Neighbor Discovery) message sent by the switching chip, generates a software ARP table entry or software ND table entry as a software adjacency table entry, and then applies for a global next hop index from the next hop resource pool of the service board. The index is used to point to the MAC address of the Layer 3 interface corresponding to the IP address of the software adjacency table entry and the VLAN to which it belongs.

[0003] The processor of the service board configures LPM (Longest Prefix Match) entries for Layer 3 forwarding for each switching chip on the board, records the IP address, global next hop index, and egress port in the software adjacency entry, and writes the MAC address of the Layer 3 interface corresponding to the IP address of the software adjacency entry and the VLAN to which it belongs to the storage location pointed to by the global next hop index of each switching chip.

[0004] In this way, when a switching chip on the service board searches for a matching LPM entry in the LPM table based on the destination IP address of the forwarded IP packet, if the egress port is a port of another switching chip, the global next hop index and egress port in the found LPM entry are sent to the switching chip where the egress port is located; if the egress port is a local switching chip port, the MAC address of the Layer 3 interface and the VLAN to which it belongs are read according to the global next hop index of the LPM entry, the Ethernet header is re-encapsulated, and the packet is forwarded through the port of the LPM entry.

[0005] However, the next-hop index of each service board in the distributed device is divided into a global next-hop index for unicast routing and a local next-hop index for multicast or some local services. The number of global next-hop index resources allocated based on adjacency table entries is limited. When there is no available global next-hop index on a switching chip, the LPM table entry cannot be synchronized to it, resulting in packet loss and affecting service stability. Summary of the Invention

[0006] The purpose of this application is to provide a method and device for implementing forwarding table resource expansion to avoid forwarding table synchronization failure caused by insufficient global next hop index of a switching chip.

[0007] To achieve the above-mentioned purpose, the present application provides a method for implementing forwarding table resource expansion, the method comprising: setting a global virtual resource pool; the total number of virtual next hop indexes of the global virtual resource pool is equal to the total number of next hop indexes of the hardware global resource pool; the first n virtual next hop indexes of the global virtual resource pool correspond one-to-one to the n global next hop indexes of the hardware global resource pool; obtaining the host IP address prefix, the MAC address of the next hop and the VLAN to which it belongs, and the egress port based on the software adjacency table entry; applying for the virtual next hop index from the global virtual resource pool for the MAC address and the VLAN to which it belongs; when the total number of applied virtual next hops does not exceed the total number of global next hop indexes in the hardware global resource pool, generating a first longest prefix match LPM table entry; wherein the host IP address prefix points to the virtual next hop index and the egress port; synchronizing the first LPM table entry and the MAC address and the VLAN to which the next hop pointed to by the virtual next hop index to each switching chip.

[0008] To achieve the above-mentioned purpose, the present application also provides a device for implementing forwarding table resource expansion, which can be applied as a business board including a processor, a memory, and multiple switching chips; wherein the processor performs the following operations by running the processor executable instructions in the memory to set a global virtual resource pool; the total number of virtual next hop indexes of the global virtual resource pool is equal to the total number of next hop indexes of the hardware global resource pool; the first n virtual next hop indexes of the global virtual resource pool correspond one-to-one to the n global next hop indexes of the hardware global resource pool; based on the software adjacency table entry, the host IP address prefix, the MAC address of the next hop and the VLAN to which it belongs, and the egress port are obtained; for the MAC address and the VLAN to which it belongs, a virtual next hop index is applied from the global virtual resource pool; when the total number of applied virtual next hops does not exceed the total number of global next hop indexes in the hardware global resource pool, a first longest prefix match LPM table entry is generated; wherein the host IP address prefix points to the virtual next hop index and the egress port; the first LPM table entry and the MAC address and the VLAN to which the virtual next hop index points to are synchronized to each switching chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A schematic diagram of an embodiment of a method for implementing forwarding entry resource expansion provided by the present application;

[0010] Figure 2 A schematic diagram of the synchronization of the longest prefix match table entry with a virtual next hop index provided by this application;

[0011] Figure 3 A schematic diagram of the synchronization of the longest prefix match table entry with a local next hop index provided by this application;

[0012] Figure 4A schematic diagram of performing layer-3 unicast forwarding based on the longest prefix match table provided in this application;

[0013] Figure 5 A schematic diagram of an embodiment of a device for implementing forwarding table resource expansion provided by the present application. DETAILED DESCRIPTION

[0014] The present invention will be described in detail with reference to a plurality of examples shown in the accompanying drawings. In the following detailed description, a number of specific details are provided to provide a comprehensive understanding of the present invention. Known methods, steps, components, and circuits are not described in detail in the examples to avoid obscuring the understanding of the examples.

[0015] Among the terms used, the term "including" means including but not limited to; the term "containing" means including but not limited to; the terms "above," "within," and "below" are inclusive; the terms "greater than" and "less than" are exclusive. The term "based on" means based on at least a portion.

[0016] Figure 1 This is a schematic diagram of an embodiment of a method for implementing forwarding table resource expansion provided by the present application; the method includes:

[0017] Step 101, setting a global virtual resource pool;

[0018] The total number of virtual next-hop indexes in the global virtual resource pool is equal to the total number of next-hop indexes in the hardware global resource pool; the first n virtual next-hop indexes in the global virtual resource pool correspond one-to-one to the n global next-hop indexes in the hardware global resource pool;

[0019] Step 102: Obtain the host IP address prefix, the next hop MAC address, the VLAN to which it belongs, and the egress port based on the software adjacency table entry.

[0020] Step 103: Request a virtual next hop index from the global virtual resource pool for the MAC address and VLAN of the next hop.

[0021] Step 104: When the total number of applied virtual next hops does not exceed the total number of global next hop indexes in the hardware global resource pool, a first longest prefix match LPM entry is generated;

[0022] Step 105: Synchronize the first LPM entry and the MAC address and VLAN to which the next hop pointed to by the virtual next hop index to each switching chip.

[0023] Figure 2 A schematic diagram of the synchronization of the longest prefix matching table entry with a virtual next hop index provided by this application.

[0024] The switch chip 11 of the service board 1 receives the ARP message 201 from the terminal T1 through the port a, and the switch chip 11 sends the ARP request message 201 to the processor 14 of the service board 1 .

[0025] The processor 14 receives an ARP request message 201, wherein the sender IP address is the IP address 10.1.1.7 of the VLAN100 layer 3 interface of port b, the sender MAC address is MAC B of the VLAN100 layer 3 interface of port b; and the target IP address is the IP address 10.1.1 of port a.

[0026] The processor 14 learns the software ARP entry 202 based on the sender IP address 10.1.1.7, the sender MAC address MAC B, port a, and the VLAN 100 to which port a belongs; that is, 10.1.1.7->(MAC B, VLAN 100), port a.

[0027] The processor 14 generates an ARP response message for the ARP request message 201, and sends the ARP response message to the switch chip 11 where porta is located according to the software ARP table entry 202; the switch chip 11 sends the ARP response message to the terminal T1, and the terminal T1 learns the ARP table entry; the specific process refers to the ARP protocol principle, which will not be repeated in this application.

[0028] The memory (not shown) of service board 1 records global virtual resource pool 151. The total number of virtual next-hop indexes in global virtual resource pool 151 is equal to the total number of next-hop indexes in the hardware global resource pools of switch chips 11-13; the first n virtual next-hop indexes in global virtual resource pool 151 correspond one-to-one to the first n global next-hop indexes in the hardware global resource pools of switch chips 11-13.

[0029] The memory of service board 1 records the chip local resource pool 152. The chip local resource pool 152 records the idle local next hop indexes of the switching chips 11, 12, and 13. The processor 14 searches the chip local resource pool 152 according to the switching chip identifier as the index.

[0030] Similarly, the memory (not shown) of service board 2 records global virtual resource pool 251. The total number of virtual next hop indexes in global virtual resource pool 251 is equal to the total number of next hop indexes in the hardware global resource pools of switch chips 21, 22, and 23; the first n virtual next hop indexes in global virtual resource pool 251 correspond one-to-one to the first n global next hop indexes in the hardware global resource pools of switch chips 21-23.

[0031] The memory of service board 2 records the chip local resource pool 252. The chip local resource pool 252 records the idle local next hop indexes of the switching chips 21, 22, and 23. The processor 24 searches the chip local resource pool 152 for the local next hop index of each switching chip based on the identifiers of the switching chips 21, 22, and 23.

[0032] Processor 14 applies for a virtual next-hop index n from global virtual resource pool 151 for MAC B and VLAN 100 of software ARP entry 202 ; that is, in software ARP entry 202 , MAC B and VLAN 100 are the MAC address and VLAN of the next-hop interface to IP address 10.1.1.7.

[0033] The processor 14 determines that the n applied virtual next hop indexes do not exceed the total number n of global next hop indexes in the hardware global resource pool.

[0034] The processor 14 sets the state of the virtual next-hop index n in the global virtual resource pool 151 to placeholder.

[0035] Processor 14 generates LPM entry 203, namely, 10.1.1.7 / 32->virtual next-hop index n, port a. Processor 14 synchronizes MAC address B and VLAN 100 corresponding to LPM entry 203 and virtual next-hop index n to switching chips 11, 12, and 13.

[0036] Each of the switch chips 11 , 12 , and 13 records the LPM entry 203 in the local LPM table, and records MAC B and VLAN 100 in the storage location pointed to by virtual next-hopindex n.

[0037] Processor 14 synchronizes the software ARP entry 202 and the virtual next-hop index virtualnext-hop index n to processor 24 through the inter-board CPU link.

[0038] The processor 24 determines, based on the index value of the virtual next-hop index n, that the applied virtual next-hop index does not exceed the total number n of global next-hop indexes in the hardware global resource pool.

[0039] Processor 24 sets the status of virtual next-hop index n in global virtual resource pool 251 to placeholder. Based on the synchronized software ARP entry 202 and virtual next-hop index n, processor 24 generates LPM entry 203 (i.e., 10.1.1.7 / 32->virtual next-hop index n, port a). Processor 24 synchronizes MAC address B and VLAN 100 corresponding to LPM entry 203 and virtual next-hop index n to switch chips 21, 22, and 23. Switch chips 21, 22, and 23 each record LPM entry 203 in their local LPM tables and MAC address B and VLAN 100 in the storage location pointed to by virtual next-hop index n.

[0040] Figure 3 A schematic diagram of the synchronization of the longest prefix matching table entry with a local next hop index provided by this application.

[0041] The switch chip 11 of the service board 1 receives the ARP message 301 from the terminal T2 through the port a, and the switch chip 11 sends the ARP request message 301 to the processor 14 of the service board 1 .

[0042] The processor 14 receives an ARP request message 301, wherein the sending end IP address is the IP address 10.1.1.8 of the VLAN100 layer 3 interface of port c, the sending end MAC address is MAC C of the VLAN100 layer 3 interface of port c; the target end IP address is the IP address 10.1.1.7 of the VLAN100 of porta.

[0043] The processor 14 learns a software ARP entry 302 based on the sender IP address 10.1.1.8, the sender MAC address MAC C, port a, and the corresponding VLAN 100; that is, 10.1.1.8->(MAC C, VLAN 100), port a.

[0044] The processor 14 generates an ARP response message for the ARP request message 301 and sends the ARP response message to the switch chip 11 where porta is located according to the software ARP table entry 302. The switch chip 11 sends the ARP response message to the terminal T2, and the terminal T2 learns the ARP table entry.

[0045] Processor 14 applies for virtual next-hop index n+1 from global virtual resource pool 151 for MAC C of software ARP entry 302 and VLAN 100 . Index value n+1 exceeds the total number of global next-hop indices n.

[0046] Processor 14 searches for an idle local next-hop index (local next-hop index 11) for switch chip 21 in chip local resource pool 152 and generates LPM entry 304, which contains the information 10.1.1.8 / 32->local next-hop index 11 and port a. Processor 14 synchronizes LPM entry 304, the MAC address C (corresponding to local next-hop index 11), and VLAN 100 to switch chip 11. Switch chip 11 records LPM entry 304 in its local LPM table and the MAC address C and VLAN 100 in the storage location pointed to by local next-hop index 11.

[0047] Processor 14 searches for an idle local next-hop index (local next-hop index 13) for switch chip 22 in chip local resource pool 152 and generates LPM entry 305, which specifies 10.1.1.8 / 32 -> local next-hop index 13 and port a. Processor 14 synchronizes LPM entry 305, the MAC address C (corresponding to local next-hop index 13), and VLAN 100 to switch chip 12. Switch chip 12 records LPM entry 305 in its local LPM table and MAC address C and VLAN 100 in the storage location pointed to by local next-hop index 13.

[0048] Processor 14 searches for an idle local next-hop index (local next-hop index 17) for switch chip 13 in chip local resource pool 152 and generates LPM entry 306, which specifies 10.1.1.8 / 32 -> local next-hop index 17 and port a. Processor 14 synchronizes LPM entry 306, the MAC address C (corresponding to local next-hop index 17), and VLAN 100 to switch chip 13. Switch chip 13 records LPM entry 306 in its local LPM table and MAC address C and VLAN 100 in the storage location pointed to by local next-hop index 17.

[0049] Processor 14 synchronizes the software ARP entry 302 and the virtual next-hop index virtualnext-hop index n+1 to processor 24 through the inter-board CPU link.

[0050] The processor 24 determines, based on the index value of virtual next-hop index n+1, that the applied virtual next-hop index has exceeded the total number n of global next-hop indexes in the hardware global resource pool.

[0051] Processor 24 searches for an idle local next-hop index (local next-hop index 1) for switch chip 21 in chip local resource pool 252 and generates LPM entry 306, which contains the value 10.1.1.8 / 32 -> local next-hop index 1 and port a. Processor 24 synchronizes LPM entry 306, MAC address C (corresponding to local next-hop index 1), and VLAN 100 to switch chip 21. Switch chip 21 records LPM entry 306 in its local LPM table and MAC address C and VLAN 100 in the storage location pointed to by local next-hop index 1.

[0052] Processor 24 searches for an idle local next-hop index (local next-hop index 3) for switch chip 22 in chip local resource pool 252 and generates LPM entry 307, which contains the value 10.1.1.8 / 32 -> local next-hop index 3 and port a. Processor 24 synchronizes LPM entry 307, MAC address C (corresponding to local next-hop index 3), and VLAN 100 to switch chip 22. Switch chip 22 records LPM entry 307 in its local LPM table and MAC address C and VLAN 100 in the storage location pointed to by local next-hop index 3.

[0053] Processor 24 searches for an idle local next-hop index (local next-hop index 7) for switch chip 23 in chip local resource pool 252 and generates LPM entry 308, which contains the value 10.1.1.8 / 32 -> local next-hop index 7 and port a. Processor 24 synchronizes LPM entry 308, MAC address C (corresponding to local next-hop index 7), and VLAN 100 to switch chip 23. Switch chip 23 records LPM entry 308 in its local LPM table and MAC address C and VLAN 100 in the storage location pointed to by local next-hop index 7.

[0054] Figure 2-Figure 3 The embodiment uses an ARP request message as an example to illustrate the implementation process of synchronizing LPM entries. Figure 2-Figure 3 The service board of the distributed device shown in the figure generates an adjacency table entry based on the ARP response message or the ND message of the IPv6 protocol. Figure 2-Figure 3 In this way, the LPM table entries are synchronized to the switching chip based on the generated / synchronized adjacency table entries. Figure 4 This is a schematic diagram of performing three-layer unicast forwarding based on the longest prefix match table entry provided by this application.

[0055] The switching chip 13 receives the Ethernet message 401 , finds that the destination MAC address of the Ethernet message 401 is a Layer 3 MAC address, and performs Layer 3 forwarding for the Ethernet message 401 .

[0056] The switch chip 13 searches the LPM table entry 203 according to the destination IP address 10.1.1.7 of the Ethernet message 401 and determines that the next hop index Virtual Next-hop index n in the LBM table entry is the global next hop index; the egress port is located at the switch chip 11.

[0057] Because the first n virtual next-hop indexes of the global virtual resource pool 151 correspond one-to-one to the first n global next-hop indexes of the hardware global resource pool, Virtual Next-hop index n is identified as the global next-hop index.

[0058] The switch chip 13 sends the Ethernet packet 401 , the Virtual Next-hop index n, and the egress port port a to the switch chip 11 .

[0059] Switch chip 11 receives Ethernet packet 401, Virtual Next-hop index n, and egress port porta. It reads the next hop address, MAC address B, and VLAN 100, from the storage location pointed to by Virtual Next-hop index n. Switch chip 11 re-encapsulates Ethernet packet 401 with an Ethernet header, where the source MAC address is MAC A, the destination MAC address is MAC B, and the VLAN is VLAN 100.

[0060] Switch chip 11 sends the re-encapsulated Ethernet message 4011 to terminal T1 through port a. When the destination IP address of the Ethernet message received by other switch chips matches the LPM table entry 203, the same process is performed.

[0061] Figure 4 In the example, the switching chip 23 receives the Ethernet message 402 , finds that the destination MAC address of the Ethernet message 4021 is a Layer 3 MAC address, and performs Layer 3 forwarding for the Ethernet message 402 .

[0062] Switch chip 23 searches LPM entry 308 according to destination IP address 10.1.1.8 of Ethernet packet 402 , and determines that the next-hop index local Next-hop index 7 in LBM entry 308 is the local next-hop index; egress port port a is located in switch chip 11 .

[0063] Switch chip 23 reads the next hop MAC address C and VLAN 100 from the storage location pointed to by local Next-hop index 7. Switch chip 23 re-encapsulates the Ethernet header for Ethernet packet 402, where the source MAC address is the MAC address of the Layer 3 interface of VLAN 100 on switch chip 23, the destination MAC address is MAC C, and the VLAN is VLAN 100.

[0064] The switch chip 23 sends the re-encapsulated Ethernet message 4021 to the switch chip 11 where the egress port porta is located through the inter-board chip link.

[0065] The switching chip 11 sends the re-encapsulated Ethernet message 4021 to the terminal T1 through port a.

[0066] Figure 2-Figure 4 In the embodiment, when the software ARP table entry on the processor 14 or 24 ages, the switching chip on the local board is notified to delete the LPM table entry corresponding to the IP address in the ARP table entry.

[0067] Figure 5A schematic diagram of an embodiment of a device for implementing forwarding entry resource expansion provided by the present application. The device can be applied as a service board including a processor, a memory, and multiple switching chips; wherein the processor performs the following operations by running processor-executable instructions in the memory to set a global virtual resource pool; the total number of virtual next hop indexes in the global virtual resource pool is equal to the total number of next hop indexes in the hardware global resource pool; the first n virtual next hop indexes in the global virtual resource pool correspond one-to-one to the n global next hop indexes in the hardware global resource pool; based on the software adjacency table entry, the host IP address prefix, the MAC address of the next hop, the VLAN to which it belongs, and the egress port are obtained; for the MAC address and the VLAN to which it belongs, a virtual next hop index is applied from the global virtual resource pool; when the total number of applied virtual next hops does not exceed the total number of global next hop indexes in the hardware global resource pool, a first longest prefix match (LPM) table entry is generated; wherein the host IP address prefix points to the virtual next hop index and the egress port; and the first LPM table entry and the MAC address and the VLAN to which the next hop pointed to by the virtual next hop index are synchronized to each switching chip.

[0068] The processor further performs the following operations by running the stored instructions: when the total number of applied virtual next hops exceeds the total number of global next hop indexes in the hardware global resource pool; for the MAC address of the next hop and the VLAN to which it belongs, a free local next hop index is searched for each switching chip; a second LPM table entry is generated for each switching chip; in each second LPM table entry, the host IP address prefix points to the local next hop index and the egress port of each switching chip, and the local next hop index of each switching chip points to the MAC address of the next hop and the VLAN to which it belongs; and each second LPM table entry and its local next hop index pointing to the MAC address and the VLAN to which it belongs are synchronized to each switching chip.

[0069] The processor executes the following operations by running the instructions: the table entry synchronization module is further used to delete the adjacency table entry that reaches the aging time; and notify each switching chip to delete the LPM table entry corresponding to the aged adjacency table entry.

[0070] Any one of the multiple switching chips can be used to determine whether to perform three-layer forwarding for a received Ethernet message; based on the next hop of the destination IP address of the Ethernet message, find a first LPM table entry; determine that the output port of the first LPM table entry is located in other switching chips; and send the Ethernet message, the virtual next hop index and the output port of the first LPM table entry to the switching chip where the output port of the first LPM table entry is located.

[0071] Any of the multiple switching chips can be used for any switching chip to determine that three-layer forwarding is performed for a received Ethernet message; based on the next hop of the destination IP address of the Ethernet message, a second LPM table entry is found; it is determined that the output port of the second LPM table entry is located in another switching chip; according to the next hop MAC and the VLAN to which it belongs, the Ethernet message is re-encapsulated; and the re-encapsulated Ethernet message is sent to the switching chip where the output port of the second LPM table entry is located.

[0072] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for implementing forwarding table resource expansion, characterized in that: The method comprises, Setting a global virtual resource pool; the total number of virtual next hop indexes of the global virtual resource pool is equal to the total number of next hop indexes of the hardware global resource pool; The first n virtual next hop indexes of the global virtual resource pool correspond one-to-one to the first n global next hop indexes of the hardware global resource pool; Obtain the host IP address prefix, next-hop MAC address, VLAN, and egress port based on the software adjacency table entry. Applying for a virtual next hop index from the global virtual resource pool for the MAC address and VLAN of the next hop; When the total number of applied virtual next hops does not exceed the total number of global next hop indexes in the hardware global resource pool, generating a first longest prefix match LPM table entry; wherein the host IP address prefix points to the virtual next hop index and the egress port; The first LPM table entry and the MAC address and VLAN to which the next hop pointed to by the virtual next hop index are synchronized to each switching chip.

2. The method according to claim 1, characterized in that The method further comprises, When the total number of applied virtual next hops exceeds the total number of global next hop indexes in the hardware global resource pool; For the MAC address and VLAN of the next hop, find the idle local next hop index of each switch chip; Generate a second LPM table entry for each switch chip; in each second LPM table entry, the host IP address prefix points to the local next hop index of each switch chip and the egress port, and the local next hop index of each switch chip points to the MAC address of the next hop and the VLAN to which it belongs; Each second LPM table entry and its local next hop index pointing to the MAC address of the next hop and the VLAN to which it belongs are synchronized to each switching chip.

3. The method according to claim 1, characterized in that The method further comprises, Delete the adjacency table entries that have reached the aging time. Notify each switch chip to delete the LPM entry corresponding to the aged adjacency entry.

4. The method according to claim 1, wherein The method further comprises, Any switching chip determines to perform Layer 3 forwarding for the received Ethernet message; Find the first LPM table entry based on the next hop of the destination IP address of the Ethernet message; Determining that the egress port of the first LPM entry is located in another switch chip; The Ethernet message, the virtual next hop index and the egress port of the first LPM table entry are sent to the switch chip where the egress port of the first LPM table entry is located.

5. The method according to claim 2, characterized in that The method further comprises, Any switching chip determines to perform Layer 3 forwarding for the received Ethernet message; Find the second LPM table entry based on the next hop of the destination IP address of the Ethernet message; Determining that the egress port of the second LPM entry is located in another switch chip; Re-encapsulating the Ethernet message according to the next-hop MAC and the VLAN to which it belongs of the second LPM table entry; The re-encapsulated Ethernet message is sent to the switching chip where the egress port of the second LPM entry is located.

6. A device for implementing forwarding table resource expansion, characterized in that: The device can be applied as a service board including a processor, a memory, and a plurality of switching chips; wherein the processor performs the following operations by running the processor-executable instructions in the memory: Setting a global virtual resource pool; the total number of virtual next hop indexes of the global virtual resource pool is equal to the total number of next hop indexes of the hardware global resource pool; the first n virtual next hop indexes of the global virtual resource pool correspond one-to-one to the first n global next hop indexes of the hardware global resource pool; Obtain the host IP address prefix, next-hop MAC address, VLAN, and egress port based on the software adjacency table entry. Applying for a virtual next hop index from the global virtual resource pool for the MAC address and VLAN of the next hop; When the total number of applied virtual next hops does not exceed the total number of global next hop indexes in the hardware global resource pool, generating a first longest prefix match LPM table entry; wherein the host IP address prefix points to the virtual next hop index and the egress port; The first LPM table entry and the MAC address and VLAN to which the next hop pointed to by the virtual next hop index are synchronized to each switching chip.

7. The device according to claim 6, characterized in that The processor further performs the following operations by executing the store instruction: When the total number of applied virtual next hops exceeds the total number of global next hop indexes in the hardware global resource pool; For the MAC address and VLAN of the next hop, find an idle local next hop index on each switch chip; Generate a second LPM table entry for each switch chip; in each second LPM table entry, the host IP address prefix points to the local next hop index of each switch chip and the egress port, and the local next hop index of each switch chip points to the MAC address of the next hop and the VLAN to which it belongs; Each second LPM table entry and its local next hop index pointing to the MAC address of the next hop and the VLAN to which it belongs are synchronized to each switching chip.

8. The device according to claim 6, characterized in that The processor executes the following operations by executing the instructions: The table entry synchronization module is also used to delete the adjacency table entries that have reached the aging time; and notify each switching chip to delete the LPM table entries corresponding to the aged adjacency table entries.

9. The device according to claim 6, characterized in that Any of the plurality of switch chips may be configured to determine to perform layer 3 forwarding for the received Ethernet message; and find the first LPM table entry based on a next hop of a destination IP address of the Ethernet message; Determining that the egress port of the first LPM entry is located in another switch chip; The Ethernet message, the virtual next hop index and the egress port of the first LPM table entry are sent to the switch chip where the egress port of the first LPM table entry is located.

10. The device according to claim 7, characterized in that Any of the plurality of switching chips may be used to determine that any switching chip performs layer 3 forwarding for a received Ethernet message; and find the second LPM table entry based on a next hop of a destination IP address of the Ethernet message; Determining that the egress port of the second LPM entry is located in another switch chip; Re-encapsulating the Ethernet message according to the next-hop MAC and the VLAN to which it belongs of the second LPM table entry; The re-encapsulated Ethernet message is sent to the switching chip where the egress port of the second LPM entry is located.

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