Configuration space request response method and PCIE switch chip

Abstract

An embodiment of the present application provides a method for responding to a configuration space request and a PCIE switching chip, the method being applied to a PCIE switching chip, comprising: a physical uplink bridge device, a PCIE interconnection network, a plurality of physical downlink bridge devices, and a responder, wherein the uplink bridge device is connected to a host via an uplink port, the physical uplink bridge device is connected to a plurality of physical downlink bridge devices via a PCIE interconnection network, the physical uplink bridge device receives a configuration space request from the host via an uplink port, the configuration space request carries a target bus number; when the physical uplink bridge device determines that the target bus number is a bus number associated with the PCIE interconnection network, the physical uplink bridge device sends the configuration space request to the responder; the responder determines a target configuration space associated with the target bus number, and uses the target configuration space to respond to the configuration space request sent by the host.

Description

Technical Field

[0001] The embodiments of the present application relate to the computer field, and in particular, to a configuration space request response method and a PCIE switching chip. Background Art

[0002] Peripheral component interconnect express (PCIe) switching chips are moving towards an increasingly large number of ports. On the one hand, this is because the continuous improvement of semiconductor processes has made large-scale chips feasible, but more importantly, it is due to the application demands on computing power and storage capacity, which require servers to support larger-scale interconnections and high-speed mutual access between devices.

[0003] However, due to the characteristics of the PCIe protocol itself, when the number of ports in a single switch chip exceeds a certain number, some new problems will arise. The device number of the PCIe protocol is only 5 bits, so more than 32 bridge devices cannot be connected to a bus. In other words, when the number of downstream ports of a switch chip exceeds 32, the topology structure cannot be implemented. The traditional method is to expand through multi-level bridge devices, such as Figure 1 As shown in the figure, the first-level bridge device expands bus 3, bus 6 and bus 8, and then each bus is expanded by 3 groups of second-level bridge devices to 32 buses (downstream ports), a total of 96 downstream ports. This traditional method is equivalent to implementing multiple cascaded expansion switching chips in one switching chip, but it omits the upstream-downstream port pairs required for inter-chip interconnection. This method is also a direct implementation of the logical topology defined by the PCIe protocol, so it can indeed achieve good scalability within the scope of the protocol.

[0004] However, this method has an obvious flaw: because the second-level bridge devices exist in groups in the topology, the access to devices within the group and between groups is not equal. When the target device is not among the devices connected to the current second-level bridge device, it is necessary to cross the first-level bridge device for mutual access. Therefore, when multiple devices need to visit each other across groups, even if the {source and destination} of these accesses are different, they will share the bandwidth provided by the same path, and this path will become a congestion point. When using a switching chip with this architecture, users need to put devices with a large number of mutual access needs in one group as much as possible to avoid the limited bandwidth for mutual access between groups becoming a bottleneck. This constraint does not meet the original intention of the need for large-scale device interconnection, resulting in large-scale interconnection in actual applications, but not true large-scale mutual access.

[0005] There is currently no effective solution to the above problems. Summary of the invention

[0006] The embodiments of the present application provide a configuration space request response method and a PCIE switching chip, so as to at least solve the problem of network congestion caused by mutual access between PCIE switching chip groups in the related art.

[0007] According to an embodiment of the present application, a method for responding to a configuration space request is provided, which is applied to a high-speed serial computer expansion bus standard PCIE switching chip, wherein the PCIE switching chip comprises: a physical upstream bridge device, a PCIE interconnection network, a plurality of physical downstream bridge devices, and a responder, wherein the upstream bridge device is connected to a host via an upstream port, and the physical upstream bridge device is connected to the plurality of physical downstream bridge devices via the PCIE interconnection network to achieve full interconnection between the plurality of physical downstream bridge devices, comprising: the physical upstream bridge device receives a configuration space request from the host via the upstream port, wherein the configuration space request carries a target bus number; when the physical upstream bridge device determines that the target bus number is a bus number related to the PCIE interconnection network, the physical upstream bridge device sends the configuration space request to the responder; the responder determines a target configuration space corresponding to the target bus number, and uses the target configuration space to respond to the configuration space request sent by the host, so that the host determines that there is a bridge device corresponding to the target configuration space in the PCIE interconnection network.

[0008] In an exemplary embodiment, the PCIE interconnection network is virtualized into multiple bridge devices, including: a virtual downstream bridge device, a virtual upstream bridge device, the physical upstream bridge device is connected to N of the virtual downstream bridge devices, each of the virtual downstream bridge devices is connected to a virtual upstream bridge device, the N virtual downstream bridge devices are respectively connected to the N virtual upstream bridge devices through N buses, and each of the virtual upstream bridge devices is connected to M of the physical downstream bridge devices, wherein N and M are integers greater than or equal to 1, and before the physical upstream bridge device sends the configuration space request to the responder The method further comprises: the physical uplink bridge device receives the bus number of each line from N lines connected to the physical uplink bridge device, and obtains the bus numbers of the N lines, wherein the bus number of each line includes: the bus number connected to the physical uplink bridge device, and the bus number of the virtual downlink bridge device, the virtual uplink bridge device, and the M physical uplink bridge devices on the line; the physical uplink bridge device determines whether the target bus number is a bus number related to the PCIE interconnection network according to the target bus number and the bus numbers on the N lines.

[0009] In an exemplary embodiment, the physical upstream bridge device determines whether the target bus number is a bus number related to the PCIE interconnect network based on the target bus number and the bus numbers on the N lines, including: when the target bus number is a target secondary bus number and the bus numbers on the N lines include secondary bus numbers of each bridge device, the physical upstream bridge device determines the target device based on the secondary bus numbers of each bridge device, wherein each of the bridge devices includes: the physical upstream bridge device, the virtual downstream bridge device, the virtual upstream bridge device, and the physical downstream bridge device; when the target device is the virtual downstream bridge device or the virtual upstream bridge device, the physical upstream bridge device determines that the target secondary bus number is a bus number related to the PCIE interconnect network.

[0010] In an exemplary embodiment, the physical upstream bridge device determines the target device according to the secondary bus number of each bridge device, including: when the target secondary bus number is the secondary bus number of the physical upstream bridge device, the physical upstream bridge device determines the target device among the N virtual downstream bridge devices connected to the physical upstream bridge device according to the first device number carried in the configuration space request.

[0011] In an exemplary embodiment, the physical upstream bridge device determines the target device among the N virtual downstream bridge devices connected to the physical upstream bridge device according to the first device number carried in the configuration space request, including: the physical upstream bridge device determines the virtual downstream bridge device whose device number is the first device number among the N virtual downstream bridge devices as the target device, wherein the connections between the physical upstream bridge device and the N virtual downstream bridge devices all use the same bus number.

[0012] In an exemplary embodiment, the physical upstream bridge device determines the target device according to the secondary bus number of each bridge device, including: when the target secondary bus number is the secondary bus number of the ith virtual downstream bridge device, the physical upstream bridge device determines the ith virtual upstream bridge device connected to the ith virtual downstream bridge device as the target device, wherein i is an integer, the ith virtual downstream bridge device is any one of the N virtual downstream bridge devices, the N virtual upstream bridge devices include the ith virtual upstream bridge device, and the bus numbers of the virtual downstream bridge devices and the virtual upstream bridge devices on different lines among the N lines are different.

[0013] In an exemplary embodiment, the physical upstream bridge device determines the target device according to the secondary bus number of each bridge device, and also includes: when the target secondary bus number is the secondary bus number of the j-th virtual upstream bridge device, the physical upstream bridge device determines the target device among the M physical downstream bridge devices connected to the j-th virtual upstream bridge device according to the second device number carried in the configuration space request, wherein j is an integer.

[0014] In an exemplary embodiment, the physical upstream bridge device determines the target device among the M physical downstream bridge devices connected to the j-th virtual upstream bridge device according to the second device number carried in the configuration space request, including: the physical upstream bridge device determines the physical downstream bridge device whose device number is the second device number among the M physical downstream bridge devices connected to the j-th virtual upstream bridge device as the target device, wherein the connections between the j-th virtual upstream bridge device and the M physical downstream bridge devices all use the same bus number, and the bus numbers of the connections between the virtual upstream bridge devices and the physical downstream bridge devices on different lines among the N lines are different.

[0015] In an exemplary embodiment, after determining the target device among the M physical downstream bridge devices connected to the j-th virtual upstream bridge device, the method further includes: when the target device is the k-th physical downstream bridge device among the M physical downstream bridge devices connected to the j-th virtual upstream bridge device, the physical upstream bridge device sends the configuration space request to the k-th physical downstream bridge device, wherein k is an integer, and the k-th physical downstream bridge device is any physical downstream bridge device among the M physical downstream bridge devices connected to the j-th virtual upstream bridge device; the k-th physical downstream bridge device responds to the configuration space request sent by the host using the configuration space of the k-th physical downstream bridge device.

[0016] In an exemplary embodiment, the physical upstream bridge device determines the target device according to the secondary bus numbers of each bridge device, and also includes: when the kth physical downstream bridge device among the M physical downstream bridge devices connected to the jth virtual upstream bridge device is also connected to multiple other physical downstream bridge devices, and the target secondary bus number is in the bus number range of the kth physical downstream bridge device, the physical upstream bridge device determines the target device among the other physical downstream bridge devices according to the target secondary bus number and the third device number carried in the configuration space request, wherein j and k are integers, the jth virtual upstream bridge device is any virtual upstream bridge device among the N virtual upstream bridge devices, and the bus number range of the kth physical downstream bridge device includes: bus numbers between the secondary bus number of the kth physical downstream bridge device and the slave bus number of the kth physical downstream bridge device.

[0017] In an exemplary embodiment, after the physical upstream bridge device determines the target device among the other physical downstream bridge devices based on the target secondary bus number and the third device number carried in the configuration space request, the method further includes: when the target device is the Sth physical downstream bridge device among multiple other physical downstream bridge devices connected to the kth physical downstream bridge device, the physical upstream bridge device sends the configuration space request to the Sth physical downstream bridge device, wherein S is an integer, and the Sth physical downstream bridge device is any physical downstream bridge device among the multiple other physical downstream bridge devices connected to the kth physical downstream bridge device; the Sth physical downstream bridge device uses the configuration space of the Sth physical downstream bridge device to respond to the configuration space request sent by the host.

[0018] In an exemplary embodiment, the physical upstream bridge device determines the target device according to the secondary bus number of each bridge device, and also includes: when the physical downstream bridge device is connected to the endpoint device through a downstream port and the target secondary bus number is the kth physical downstream bridge device among the M physical downstream bridge devices connected to the jth virtual upstream bridge device, determining the port device connected to the kth physical downstream bridge device as the target device, wherein k is an integer.

[0019] In an exemplary embodiment, after determining the port device connected to the kth physical downstream bridge device as the target device, the method further includes: the physical upstream bridge device sends the configuration space request to the port device connected to the kth physical downstream bridge device; and the port device responds to the configuration space request sent by the host using the configuration space of the port device.

[0020] In an exemplary embodiment, the responder determines the target configuration space corresponding to the target bus number, including: the responder searches for a virtual bridge device corresponding to the target bus number in a storage area, wherein the virtual bridge device includes: a virtual downlink bridge device, a virtual uplink bridge device; and determines the configuration space corresponding to the virtual bridge device corresponding to the target bus number as the target configuration space, wherein the storage area of ​​the responder stores the correspondence between the bus number, the virtual bridge device and the configuration space.

[0021] According to another embodiment of the present application, a PCIE switching chip is provided, comprising: a physical upstream bridge device, a PCIE interconnection network, multiple physical downstream bridge devices, and a responder, wherein the upstream bridge device is connected to a host through an upstream port, and the physical upstream bridge device is connected to the multiple physical downstream bridge devices through the PCIE interconnection network to achieve full interconnection between the multiple physical downstream bridge devices, wherein the physical upstream bridge device is used to receive a configuration space request from the host through the upstream port, wherein the configuration space request carries a target bus number; the physical upstream bridge device is provided with a decoder, and the decoder is used to send the configuration space request to the responder when it is determined that the target bus number is a bus number related to the PCIE interconnection network; the responder is used to determine a target configuration space corresponding to the target bus number, and use the target configuration space to respond to the configuration space request sent by the host, so that the host determines that there is a bridge device corresponding to the target configuration space in the PCIE interconnection network.

[0022] In an exemplary embodiment, the PCIE interconnection network is virtualized into multiple bridge devices, including: a virtual downstream bridge device and a virtual upstream bridge device, the physical upstream bridge device is connected to N virtual downstream bridge devices, each of the virtual downstream bridge devices is connected to a virtual upstream bridge device, the N virtual downstream bridge devices are respectively connected to the N virtual upstream bridge devices through N buses, and each virtual upstream bridge device is connected to M physical downstream bridge devices, wherein N and M are integers greater than or equal to 1; the decoder of the physical upstream bridge device is also used to receive the bus number of each line from the N lines connected to the physical upstream bridge device to obtain the bus numbers of the N lines, wherein the bus number of each line includes: the bus number connected to the physical upstream bridge device, and the bus connecting the virtual downstream bridge device, the virtual upstream bridge device, and the M physical upstream bridge devices on the line; determine whether the target bus number is a bus number in the PCIE interconnection network according to the target bus number and the bus numbers on the N lines.

[0023] In an exemplary embodiment, the responder is provided with a storage area, in which the correspondence between the bus number, the virtual bridge device and the configuration space is recorded, and further includes: the responder is used to search the storage area for the virtual bridge device corresponding to the target bus number, wherein the virtual bridge device includes: the virtual downlink bridge device and the virtual uplink bridge device; and the configuration space corresponding to the virtual bridge device corresponding to the target bus number is determined as the target configuration space.

[0024] According to another embodiment of the present application, a transponder is provided, which is applied to a high-speed serial computer expansion bus standard PCIE switching chip, wherein the PCIE switching chip comprises: a physical upstream bridge device, a PCIE interconnection network, a plurality of physical downstream bridge devices, and the transponder, wherein the upstream bridge device is connected to a host through an upstream port, and the physical upstream bridge device is connected to the plurality of physical downstream bridge devices through the PCIE interconnection network to achieve full interconnection between the plurality of physical downstream bridge devices, and comprises: a receiving module, which is used to receive a configuration space request from the physical upstream bridge device, wherein the physical upstream bridge device receives the configuration space request from the host through the upstream port, and the configuration space request carries a target bus number, and the physical upstream bridge device sends the configuration space request to the transponder when determining that the target bus number is a bus number related to the PCIE interconnection network; and a response module, which is used to determine a target configuration space corresponding to the target bus number, and use the target configuration space to respond to the configuration space request sent by the host, so that the host determines that there is a bridge device corresponding to the target configuration space in the PCIE interconnection network.

[0025] In an exemplary embodiment, the responder also includes: a storage area for storing the correspondence between bus numbers, virtual bridge devices and configuration spaces; a search module for searching the storage area for a virtual bridge device corresponding to the target bus number, wherein the virtual bridge device includes: a virtual downlink bridge device and a virtual uplink bridge device; a determination module for determining the configuration space corresponding to the virtual bridge device corresponding to the target bus number as the target configuration space.

[0026] According to another embodiment of the present application, a physical uplink bridge device is provided, which is applied to a high-speed serial computer expansion bus standard PCIE switching chip, wherein the PCIE switching chip comprises: the physical uplink bridge device, a PCIE interconnection network, a plurality of physical downlink bridge devices, and a responder, wherein the uplink bridge device is connected to a host through an uplink port, and the physical uplink bridge device is connected to the plurality of physical downlink bridge devices through the PCIE interconnection network to achieve full interconnection between the plurality of physical downlink bridge devices, and comprises: a receiving module, which is used to receive a configuration space request from the host through the uplink port, wherein the configuration space request carries a target bus number; a decoding module, which is used to determine that the target bus number is a bus number related to the PCIE interconnection network; and a sending module, which is used to send the configuration space request to the responder when determining that the target bus number is a bus number related to the PCIE interconnection network, so as to determine a target configuration space corresponding to the target bus number through the responder, and use the target configuration space to respond to the configuration space request sent by the host, so that the host determines that there is a bridge device corresponding to the target configuration space in the PCIE interconnection network.

[0027] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0028] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0029] According to yet another embodiment of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0030] Through this application, since the PCIE switching chip includes: a physical upstream bridge device, a PCIE internet network, multiple physical downstream bridge devices, and a responder, the upstream bridge device is connected to the host through an upstream port, and the physical upstream bridge device is connected to multiple physical downstream bridge devices through the PCIE internet network, full interconnection between multiple physical downstream bridge devices is achieved.

[0031] The physical uplink bridge device receives a configuration space request from the host through the uplink port, and the configuration space request carries a target bus number; when the physical uplink bridge device determines that the target bus number is a bus number related to the PCIE interconnection network, the physical uplink bridge device sends the configuration space request to the responder; the responder determines the target configuration space corresponding to the target bus number, and uses the target configuration space to respond to the configuration space request sent by the host, so that the host determines that there is a bridge device corresponding to the target configuration space in the PCIE interconnection network. The full interconnection of all bridge devices by PCIE can be achieved, and the mutual access between devices can be achieved without the problem of network congestion caused by the limitation of the total bandwidth of the interconnection between groups. Therefore, the problem of network congestion caused by the mutual access between PCIE switching chips in the related technology can be solved, and the effect of achieving full interconnection of devices and saving resources occupied by a large number of physical bridge devices in the chip can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram of the topological structure of a PCIe switching chip according to an embodiment of the present application;

[0033] Figure 2 is a schematic diagram of a fully interconnected PCIe network according to an embodiment of the present application;

[0034] Figure 3 is a flowchart of a method for responding to a configuration space request according to an embodiment of the present application;

[0035] Figure 4 is a bus decoding block diagram according to an embodiment of the present application;

[0036] Figure 5 is a logical topology diagram of a virtual bridge device according to an embodiment of the present application;

[0037] Figure 6 It is a schematic diagram of decoding logic according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0040] The abbreviations involved in this application are explained as follows:

[0041] PCIe: Peripheral Component Interconnect Express, Chinese high-speed serial computer expansion bus standard;

[0042] CPU: full name Central Processing Unit, Chinese central processing unit;

[0043] SoC: full name System on Chip, Chinese system on chip;

[0044] AMBA: Advanced Microcontroller Bus Architecture, Chinese advanced microcontroller bus architecture.

[0045] The method embodiments provided in the embodiments of the present application can be applied to high-speed serial computer expansion bus standard PCIE switching chips, such as Figure 2 The figure shows a schematic diagram of the interconnection architecture within the PCIE switching chip. The PCIE switching chip includes: a physical upstream bridge device, a PCIE interconnection network, multiple physical downstream bridge devices, and a transponder. The upstream bridge device is connected to the host through an upstream port, and the physical upstream bridge device is connected to multiple physical downstream bridge devices through the PCIE interconnection network to achieve full interconnection between multiple physical downstream bridge devices.

[0046] Figure 2 The physical upstream bridge device and the physical downstream bridge device shown are connected via a PCIe interconnect network. The PCIe interconnect network is used to carry PCIe data (including configuration messages, etc.) that needs to "pass through" the switching chip between the upstream and downstream ports. The typical feature of this interconnect network is to achieve full interconnection between multiple bridge devices. This full interconnection can achieve peer-to-peer access between devices without showing obvious grouping differences related to device location. This application uses a fully interconnected network to connect all bridge devices.

[0047] The above architecture uses SoC interconnection to send the configuration space request sent to the internal bridge device from the bridge device connected to the upstream port to the transponder or the corresponding physical bridge device. The SoC interconnection can use a common on-chip interconnection bus such as an AMBA bus.

[0048] In this embodiment, a method for responding to a configuration space request is provided. Figure 3 is a flowchart of a method for responding to a configuration space request according to an embodiment of the present application, such as Figure 3 As shown, the process includes the following steps:

[0049] Step S202, the physical upstream bridge device receives a configuration space request from the host through the upstream port, wherein the configuration space request carries a target bus number;

[0050] Step S204, when the physical upstream bridge device determines that the target bus number is a bus number related to the PCIE interconnection network, the physical upstream bridge device sends the configuration space request to the responder;

[0051] Step S206, the responder determines the target configuration space corresponding to the target bus number, and uses the target configuration space to respond to the configuration space request sent by the host, so that the host determines that there is a bridge device corresponding to the target configuration space in the PCIE interconnection network.

[0052] Wherein, the responder determines the target configuration space corresponding to the target bus number, including: the responder searches for the virtual bridge device corresponding to the target bus number in the storage area, wherein the virtual bridge device includes: a virtual downlink bridge device, a virtual uplink bridge device; the configuration space corresponding to the virtual bridge device corresponding to the target bus number is determined as the target configuration space, wherein the storage area of ​​the responder stores the correspondence between the bus number, the virtual bridge device and the configuration space.

[0053] like Figure 4 The figure shows a bus decoding block diagram, the above-mentioned responder is the configuration message responder shown in the figure, the above-mentioned storage area is the configuration space memory shown in the figure, and the configuration space memory shown in the figure records the corresponding relationship between the secondary bus number, the virtual bridge device and the configuration space. The target configuration space can be determined by the target bus number and the virtual bridge device, and the above-mentioned configuration space request is responded to by the target configuration space. The configuration message responder can be implemented using a central processing unit CPU or a hardware logic circuit.

[0054] Through the above steps, by configuring the message responder, multiple bridge devices are virtualized in the PCIe interconnection network to "cheat" the host to respond to the configuration space request sent by the host. All bridge devices are implemented in a fully interconnected topology in a PCIe interconnection network to avoid the access bottleneck introduced by grouping.

[0055] As an optional implementation, Figure 5 As shown in the logical topology diagram of the virtual bridge device, the PCIE internet network is virtualized into multiple bridge devices: a virtual downstream bridge device and a virtual upstream bridge device. The virtual downstream bridge device and the virtual upstream bridge device are virtual bridge devices in the PCIE internet network, and are not real bridge devices.

[0056] Each virtual downlink bridge device is connected to a virtual uplink bridge device, N virtual downlink bridge devices are respectively connected to N virtual uplink bridge devices through N buses, and each virtual uplink bridge device is connected to M physical downlink bridge devices, where N and M are integers greater than or equal to 1 and can be set according to actual conditions. Each physical downlink bridge device is connected to an endpoint device through a downlink port.

[0057] Before the physical uplink bridge device sends the configuration space request to the responder, the method further includes:

[0058] As an optional implementation, the physical uplink bridge device receives the bus number of each line from the N lines connected to the physical uplink bridge device, and obtains the bus numbers of the N lines, wherein the bus number of each line includes: the bus number connected to the physical uplink bridge device, and the bus number of the virtual downlink bridge device, the virtual uplink bridge device, and the M physical uplink bridge devices on the line;

[0059] Specifically, Figure 5 Taking the logical topology diagram shown as an example, the first line of the N lines includes: a physical uplink bridge device, a virtual downlink bridge device_1, a virtual uplink bridge device_1, a physical downlink bridge device_1, and the bus numbers connected therebetween constitute a line (the bus numbers involved in the line include: the bus number Bus 1 connected to the physical uplink bridge device, the bus number Bus 2 between the physical uplink bridge device and the virtual downlink bridge device_1, the bus number Bus 3 between the virtual downlink bridge device_1 and the virtual uplink bridge device_1, and the bus number Bus 4 between the virtual uplink bridge device_1 and the physical downlink bridge device_1). By analogy, the physical uplink bridge device receives the bus number of each line from the N lines connected to the physical uplink bridge device, and obtains the bus numbers of the N lines.

[0060] As another optional implementation, the physical uplink bridge device determines whether the target bus number is a bus number related to the PCIE interconnection network according to the target bus number and the bus numbers on the N lines, including the following steps:

[0061] In the case where the target bus number is a target secondary bus number and the bus numbers on the N lines include secondary bus numbers of each bridge device, the physical upstream bridge device determines the target device according to the secondary bus numbers of each bridge device, wherein each of the bridge devices includes: the physical upstream bridge device, the virtual downstream bridge device, the virtual upstream bridge device, and the physical downstream bridge device;

[0062] In the case that the target device is the virtual downstream bridge device or the virtual upstream bridge device, the physical upstream bridge device determines that the target secondary bus number is a bus number associated with the PCIE interconnect network.

[0063] The secondary bus number is the bus number to which the downstream port of the bridge device is connected. Figure 5 As shown in the example, the secondary bus number of the physical upstream bridge device is Bus 2, the secondary bus number of the virtual downstream bridge device_1 is Bus 3, and the secondary bus number of the virtual upstream bridge device_1 is Bus 4.

[0064] For example, if the target bus number carried by the configuration space request is the target secondary bus number, assume that the target secondary bus number is Bus 2, which is the secondary bus number of the physical upstream bridge device. Alternatively, assume that the target secondary bus number is Bus 3, which is the secondary bus number of the virtual downstream bridge device_1. Alternatively, assume that the target secondary bus number is Bus 4, which is the secondary bus number of the virtual upstream bridge device_1.

[0065] As another optional implementation, the configuration space request also carries a device number (corresponding to the first device number). Since the same secondary bus number is downstream connected to multiple bridge devices, the target device can be determined among the multiple devices downstream connected to the target secondary bus number through the device number.

[0066] As an optional implementation, when the target secondary bus number is the secondary bus number of the physical upstream bridge device, the physical upstream bridge device determines the target device among the N virtual downstream bridge devices connected to the physical upstream bridge device according to the first device number carried in the configuration space request. Specifically, the target device may be determined among the N virtual downstream bridge devices connected to the physical upstream bridge device in the following manner: the physical upstream bridge device determines the virtual downstream bridge device whose device number is the first device number among the N virtual downstream bridge devices as the target device, wherein the connections between the physical upstream bridge device and the N virtual downstream bridge devices all use the same bus number.

[0067] Taking the above target secondary bus number as Bus 2 as an example, Bus 2 is the secondary bus number of the physical upstream bridge device.

[0068] Since the downstream of Bus 2 is connected to virtual downstream bridge device_1, virtual downstream bridge device_2 and virtual downstream bridge device_3 (the connections between the physical upstream bridge device and virtual downstream bridge device_1, virtual downstream bridge device_2 and virtual downstream bridge device_3 all use bus number Bus 2), combined with the first device number carried in the configuration space request, the target device can be determined from multiple virtual downstream bridge devices (virtual downstream bridge device_1, virtual downstream bridge device_2 and virtual downstream bridge device_3) connected downstream of Bus 2.

[0069] Assuming that the first device number is the device number of the virtual downstream bridge device_1 (assuming that the device number of the virtual downstream bridge device_1 is Device0), the device corresponding to the first device number (virtual downstream bridge device_1) is determined as the target device. Since the target device (virtual downstream bridge device_1) is a virtual bridge device in the PCIE interconnection network, the target bus number is determined to be the bus number related to the PCIE interconnection network.

[0070] As another optional implementation, when the target secondary bus number is the secondary bus number of the i-th virtual downstream bridge device, the physical upstream bridge device determines the i-th virtual upstream bridge device connected to the i-th virtual downstream bridge device as the target device, wherein i is an integer, the i-th virtual downstream bridge device is any one of the N virtual downstream bridge devices, the N virtual upstream bridge devices include the i-th virtual upstream bridge device, and the bus numbers of the connections between the virtual downstream bridge devices and the virtual upstream bridge devices on different lines among the N lines are different.

[0071] The i-th virtual downlink bridge device is any downlink bridge device among the N virtual downlink bridge devices connected to the physical uplink bridge device. Figure 5 As shown in the figure as an example, the i-th virtual downstream bridge device can be any virtual bridge device among virtual downstream bridge device_1, virtual downstream bridge device_2 and virtual downstream bridge device_3. Figure 5 As shown, the bus numbers of the virtual downlink bridge devices and the virtual uplink bridge devices on different lines in the N lines are different, the bus number between the virtual downlink bridge device_1 and the virtual uplink bridge device_1 is Bus 3, the bus number between the virtual downlink bridge device_2 and the virtual uplink bridge device_2 is Bus 6, and the bus number between the virtual downlink bridge device_3 and the virtual uplink bridge device_3 is Bus 8. Taking the target secondary bus number as Bus 3 as an example, the i-th virtual downlink bridge device is the virtual downlink bridge device_1, and the virtual uplink bridge device_1 connected to the virtual downlink bridge device_1 is determined as the target device.

[0072] As another optional implementation, when the target secondary bus number is the secondary bus number of the j-th virtual upstream bridge device, the physical upstream bridge device determines the target device among the M physical downstream bridge devices connected to the j-th virtual upstream bridge device according to the second device number carried in the configuration space request, where j is an integer.

[0073] The physical upstream bridge device determines the physical downstream bridge device whose device number is the second device number among the M physical downstream bridge devices connected to the jth virtual upstream bridge device as the target device.

[0074] The physical upstream bridge device determines the target device among the M physical downstream bridge devices connected to the j-th virtual upstream bridge device according to the second device number carried in the configuration space request, including: the physical upstream bridge device determines the physical downstream bridge device whose device number is the second device number among the M physical downstream bridge devices connected to the j-th virtual upstream bridge device as the target device, wherein the connections between the j-th virtual upstream bridge device and the M physical downstream bridge devices all use the same bus number, and the bus numbers of the connections between the virtual upstream bridge devices and the physical downstream bridge devices on different lines among the N lines are different.

[0075] by Figure 5 For example, the j-th virtual uplink bridge device can be Figure 5 Any virtual bridge device among the virtual upstream bridge device_1, virtual upstream bridge device_2, and virtual upstream bridge device_3 shown. It can be seen from the figure that the bus numbers of the connections between the virtual upstream bridge devices and the physical downstream bridge devices on different lines are different. For example, the bus number between the virtual bridge device_1 and the physical downstream bridge device connected to it (including the physical downstream bridge device_1 to the physical downstream bridge device_M) is Bus_4, the bus number between the virtual upstream bridge device_2 and the physical downstream bridge device connected to it (including the physical downstream bridge device_M+1 to the physical downstream bridge device_2M) is Bus_7, and the bus number between the virtual upstream bridge device_3 and the physical downstream bridge device connected to it (including the physical downstream bridge device_2M+1 to the physical downstream bridge device_3M) is Bus_9.

[0076] Since the virtual upstream bridge device is connected to M physical downstream bridge devices through the same bus number, it is necessary to determine the target device among the M physical downstream bridge devices in combination with the second device number carried in the configuration space request. Figure 5 Taking the virtual upstream bridge device_1 shown in as an example, assuming that the second device number carried in the configuration space request is the device number of the physical downstream bridge device_1 (for example, Device 1), the physical downstream bridge device_1 is determined as the target device.

[0077] As an optional implementation manner, after determining the target device among the M physical downlink bridge devices connected to the jth virtual uplink bridge device, the method further includes:

[0078] In the case that the target device is the kth physical downlink bridge device among the M physical downlink bridge devices connected to the jth virtual uplink bridge device, the physical uplink bridge device sends the configuration space request to the kth physical downlink bridge device, wherein k is an integer, and the kth physical downlink bridge device is any physical downlink bridge device among the M physical downlink bridge devices connected to the jth virtual uplink bridge device; the kth physical downlink bridge device uses the configuration space of the kth physical downlink bridge device to respond to the configuration space request sent by the host.

[0079] The kth physical downstream bridge device may be any physical downstream bridge device among the M physical downstream bridge devices connected to the virtual upstream bridge device. Since the physical downstream bridge device is a real bridge device, it can use its own configuration space to respond to the configuration space request sent by the host.

[0080] As another optional implementation, the physical upstream bridge device determines the target device according to the secondary bus number of each bridge device, and further includes:

[0081] In the case that the kth physical downstream bridge device among the M physical downstream bridge devices connected to the jth virtual upstream bridge device is also connected to multiple other physical downstream bridge devices, and the target secondary bus number is within the bus number range of the kth physical downstream bridge device, the physical upstream bridge device determines the target device among the other physical downstream bridge devices according to the target secondary bus number and the third device number carried in the configuration space request, wherein j and k are integers, the jth virtual upstream bridge device is any virtual upstream bridge device among the N virtual upstream bridge devices, and the bus number range of the kth physical downstream bridge device includes: bus numbers between the secondary bus number of the kth physical downstream bridge device and the slave bus number of the kth physical downstream bridge device.

[0082] After the physical upstream bridge device determines the target device in the other physical downstream bridge devices according to the target secondary bus number and the third device number carried in the configuration space request, the method further includes:

[0083] When the target device is the Sth physical downlink bridge device among multiple other physical downlink bridge devices connected to the kth physical downlink bridge device, the physical uplink bridge device sends the configuration space request to the Sth physical downlink bridge device, wherein S is an integer, and the Sth physical downlink bridge device is any physical downlink bridge device among the multiple other physical downlink bridge devices connected to the kth physical downlink bridge device; the Sth physical downlink bridge device uses the configuration space of the Sth physical downlink bridge device to respond to the configuration space request sent by the host.

[0084] In the above embodiment, the downstream port of the physical downstream bridge device can also be connected to other physical downstream bridge devices, and the endpoint devices can be connected through other physical downstream bridges. Similar to the above embodiment, the target device can be determined from multiple other physical downstream bridge devices connected to the kth physical downstream bridge device in combination with the device number (third device number) carried in the configuration space request, and the configuration space request can be sent to the target device. Since the target device is a real physical downstream bridge device, the configuration space request sent by the host can be responded to through the configuration space of the target device.

[0085] In this embodiment, a PCIE switching chip is also provided. Figure 2 The PCIE switching chip shown includes: a physical uplink bridge device, a PCIE interconnection network, multiple physical downlink bridge devices, and a transponder. The uplink bridge device is connected to the host through an uplink port, and the physical uplink bridge device is connected to the multiple physical downlink bridge devices through the PCIE interconnection network to achieve full interconnection between the multiple physical downlink bridge devices, wherein:

[0086] The physical upstream bridge device is used to receive a configuration space request from the host through the upstream port, wherein the configuration space request carries a target bus number; the physical upstream bridge device is provided with a decoder, and the decoder is used to send the configuration space request to the responder when it is determined that the target bus number is a bus number related to the PCIE interconnection network; the responder is used to determine a target configuration space corresponding to the target bus number, and use the target configuration space to respond to the configuration space request sent by the host, so that the host determines that there is a bridge device corresponding to the target configuration space in the PCIE interconnection network.

[0087] In an optional implementation, the PCIE interconnection network is virtualized into multiple bridge devices, including: a virtual downstream bridge device and a virtual upstream bridge device, the physical upstream bridge device is connected to N of the virtual downstream bridge devices, each of the virtual downstream bridge devices is connected to a virtual upstream bridge device, the N virtual downstream bridge devices are respectively connected to the N virtual upstream bridge devices through N buses, and each of the virtual upstream bridge devices is connected to M of the physical downstream bridge devices, wherein N and M are integers greater than or equal to 1.

[0088] The decoder of the physical uplink bridge device is further used to receive the bus number of each line from the N lines connected to the physical uplink bridge device, and obtain the bus numbers of the N lines, wherein the bus number of each line includes: the bus number connected to the physical uplink bridge device, and the bus connected between the virtual downlink bridge device, the virtual uplink bridge device, and the M physical uplink bridge devices on the line;

[0089] Determine whether the target bus number is a bus number in the PCIE interconnection network according to the target bus number and the bus numbers on the N lines.

[0090] In an optional implementation, the transponder is provided with a storage area, in which the corresponding relationship between the bus number, the virtual bridge device and the configuration space is recorded, and further includes:

[0091] The responder is used to search the storage area for a virtual bridge device corresponding to the target bus number, wherein the virtual bridge device includes the virtual downlink bridge device and the virtual uplink bridge device; and determine the configuration space corresponding to the virtual bridge device corresponding to the target bus number as the target configuration space.

[0092] In this embodiment, a transponder is also provided, which is applied to a high-speed serial computer expansion bus standard PCIE switching chip, such as Figure 4The PCIE switching chip shown includes: a physical upstream bridge device, a PCIE interconnection network, multiple physical downstream bridge devices, and the responder, wherein the upstream bridge device is connected to the host through an upstream port, and the physical upstream bridge device is connected to the multiple physical downstream bridge devices through the PCIE interconnection network to achieve full interconnection between the multiple physical downstream bridge devices, and the responder includes: a receiving module, used to receive a configuration space request from the physical upstream bridge device, wherein the physical upstream bridge device receives the configuration space request from the host through the upstream port, and the configuration space request carries a target bus number. When the physical upstream bridge device determines that the target bus number is a bus number related to the PCIE interconnection network, the configuration space request is sent to the responder; a response module, used to determine a target configuration space corresponding to the target bus number, and use the target configuration space to respond to the configuration space request sent by the host, so that the host determines that there is a bridge device corresponding to the target configuration space in the PCIE interconnection network.

[0093] As an optional implementation, the responder also includes: a storage area for storing the correspondence between bus numbers, virtual bridge devices and configuration spaces; a search module for searching the storage area for a virtual bridge device corresponding to the target bus number, wherein the virtual bridge device includes: a virtual downlink bridge device and a virtual uplink bridge device; a determination module for determining the configuration space corresponding to the virtual bridge device corresponding to the target bus number as the target configuration space.

[0094] In this embodiment, a physical uplink bridge device is also provided, which is applied to a high-speed serial computer expansion bus standard PCIE switching chip. The PCIE switching chip includes: the physical uplink bridge device, a PCIE interconnection network, multiple physical downlink bridge devices, and a responder. The uplink bridge device is connected to the host through an uplink port, and the physical uplink bridge device is connected to the multiple physical downlink bridge devices through the PCIE interconnection network to achieve full interconnection between the multiple physical downlink bridge devices. The physical uplink bridge device includes: a receiving module, which is used to receive a configuration space request from the host through the uplink port, wherein the configuration space request carries a target bus number; a decoding module, which is used to determine that the target bus number is a bus number related to the PCIE interconnection network; and a sending module, which is used to send the configuration space request to the responder when it is determined that the target bus number is a bus number related to the PCIE interconnection network, so as to determine the target configuration space corresponding to the target bus number through the responder, and use the target configuration space to respond to the configuration space request sent by the host, so that the host determines that there is a bridge device corresponding to the target configuration space in the PCIE interconnection network.

[0095] The bridge device in the PCIE interconnection network within the PCIE chip in this application is a "virtual" bridge device. The "virtual" bridge device does not exist physically, but responds to the host configuration space request in a "deceptive" manner to virtualize a bridge device visible to the host.

[0096] The topology structure recognized by the host through the PCIe device enumeration process is not the actual internal interconnection structure. For the same switching chip, the topology structure recognized by the host can be changed by modifying the software in the chip.

[0097] Cross-group access between devices (groups identified by the host) does not have the bottlenecks of traditional methods. That is, when multiple devices access across groups at the same time, there will be no significant difference in bandwidth compared to access within multiple devices.

[0098] Compared with the traditional implementation method, the main advantages of the present invention are: it can realize the mutual access between devices without the bottleneck problem caused by the limitation of the total bandwidth of the interconnection between groups, improve the bandwidth of cross-group access of devices, and realize the full interconnection of indifferent devices. The use of virtual bridge devices can save the actual logical resources occupied by a large number of physical bridge devices in the chip and reduce the chip cost. It has better scalability. When it is necessary to design a larger-scale switching chip, there is no need to redesign the topology structure, which reduces the chip R&D cost.

[0099] As another optional implementation, the following method can be used to virtualize the PCIE interconnection network: Figure 5 The virtual bridge device shown:

[0100] Determine how many pairs of virtual downstream bridge devices and upstream bridge devices need to be implemented, and the corresponding relationship between the physical downstream bridge devices and the virtual upstream bridge devices.

[0101] The responder needs to calculate the parameters of each virtual bridge device based on the above virtual topology information, such as its own device number, the number of connected downstream bridge devices and the device number range, etc.

[0102] For configuration information that is not related to the virtual topology, the data can be pre-stored in a specific storage area for reading by the responder.

[0103] When the physical upstream bridge device receives a configuration space request, it will decode it to distinguish the target device of the configuration space read and write request. For the configuration space request sent to the virtual bridge device, the physical upstream bridge device will route it to the responder, and the responder will organize the response message based on the pre-stored information and send it to the host through the physical upstream bridge device. Thus, the host can recognize the virtual topology.

[0104] For example, the host first sends a configuration space request with bus number 1 to the physical upstream bridge device. The physical upstream device captures the configuration space request in the uninitialized state, so it thinks that its own bus number is 1, and then switches to the initialized state. The subsequent request with bus number 1 is answered by the physical upstream bridge device, and then the host recognizes the physical upstream bridge device.

[0105] The host sets the secondary bus number of the physical upstream bridge device to 2 and the slave bus number to 3, and requires the physical upstream bridge device to forward the configuration space request with bus number 2 and device number 0. According to the decoding logic, the configuration space request is forwarded to the responder. The responder responds based on the calculated information and pre-stored information, so that the host can recognize the virtual downstream bridge device of Bus 2, Device 0.

[0106] By analogy, the host recognizes all virtual downstream bridge devices with bus number Bus 2.

[0107] Then, according to the depth-first principle, the host sets the slave bus number of the upstream bridge device to 3, and sets the secondary bus number and slave bus number of the virtual downstream bridge device of Bus 2, Device 0 to 3. Then, a configuration space request with the target bus number of 3 is sent. This request is also routed to the responder, and similar to the above method, the host recognizes the virtual upstream bridge device.

[0108] The host then sets the slave bus number of the physical upstream bridge device and the virtual downstream bridge device to 4, and sets the secondary bus number and slave bus number of the virtual upstream bridge device to 4, and sends a configuration space request with the target bus number being 4. The request is directly routed to the downstream bridge device, which responds.

[0109] Then the host sets the slave bus number of the physical upstream bridge device and the virtual downstream bridge device to 4, and sets the secondary bus number and slave bus number of the virtual upstream bridge device to 4, and sends a configuration space request with the target bus number as 4. The request is directly routed to the downstream bridge device, which responds to it. The enumeration of the entire logical topology is completed in this way.

[0110] The decoding method used in this application is as follows. Taking the decoding of the upstream bridge device as an example, the downstream bridge device can be obtained by analogy.

[0111] The transponder is divided into two parts: the configuration message processor and the configuration space memory. The configuration message processor is the CPU or hardware logic circuit. The configuration space memory is the register used to store the necessary configuration space content of each virtual bridge device. The configuration space memory needs to provide the "secondary bus number" of each virtual bridge device to the outside, and these secondary bus numbers are connected to the upstream bridge device for decoding.

[0112] The physical downstream bridge device also needs to contain configuration space memory accessed through the SoC interconnect interface. The primary bus number, secondary bus number and slave bus number of this memory space need to be connected to the upstream bridge device.

[0113] A decoder needs to be implemented inside the physical upstream bridge device, which receives information from the configuration message responder and the downstream bridge device, as well as the upstream bridge secondary bus number information in its own configuration space. For all data packets from the upstream port (including the configuration space request), the decoder will decode and split the data packets so that the data packets reach the configuration message responder or the SoC interconnection interface of the downstream bridge device through the SoC interconnection interface, or the data packets reach the PCIe interconnection interface of the downstream bridge device through the PCIe interconnection interface and are sent to the downstream port through the downstream bridge device.

[0114] like Figure 6 The decoding logic shown is as follows:

[0115] First, determine whether the message is a configuration space read / write message. If not, decode it directly according to the bus number in the message and send it to the corresponding downstream port. If it is a configuration space request, determine whether the target secondary bus number carried in the configuration space request is the secondary bus number of the physical upstream bridge device. If so, it means that the virtual downstream bridge device is hit, and the message needs to be routed to the responder. The responder finds the content of the corresponding virtual bridge device according to the device number carried in the configuration space request and responds.

[0116] If the target secondary bus number is the secondary bus number of the virtual downstream bridge device, it means that the virtual upstream bridge device connected to the virtual downstream bridge device has been hit, so the configuration space request needs to be routed to the responder. Then the corresponding virtual bridge device content is found according to the target secondary bus number for response.

[0117] Otherwise, determine whether the target secondary bus number is the secondary bus number of the virtual upstream bridge device. If it is, it means that the physical downstream bridge device connected to the virtual upstream bridge device is hit. At this time, according to the target secondary bus number and the device carried in the configuration space request, the corresponding physical downstream bridge device can be found. The configuration space request is sent to the SoC interconnection interface of the physical downstream bridge device through the SoC interconnection bus and finally reaches the configuration space of the physical downstream bridge device. The configuration space request of the host is responded to through the configuration space of the physical downstream bridge device.

[0118] Otherwise, it is determined whether the target secondary bus is in the range of [secondary bus number, subordinate bus number] of the physical downstream bridge device. If so, it means that the configuration space request hits the endpoint device under the physical downstream bridge device. Therefore, the message needs to be sent to the physical downstream bridge device through the PCIe interconnection, and finally sent to the corresponding endpoint device through the downstream port.

[0119] Through the above embodiments, it is possible to achieve mutual access between devices without the bottleneck problem caused by the limitation of the total bandwidth of the interconnection between groups. The bandwidth of cross-group access of devices is improved, and full interconnection of devices without distinction is achieved. The use of virtual bridge devices can save the actual logical resources occupied by a large number of physical bridge devices in the chip and reduce chip costs. Better scalability, when it is necessary to design a larger-scale switching chip, this application does not need to redesign the topology structure, reducing chip research and development costs.

[0120] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0121] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0122] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0123] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0124] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0125] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0126] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0127] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0128] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for responding to a configuration space request, characterized in that: A PCIE switching chip is applied to a high-speed serial computer expansion bus standard. The PCIE switching chip includes: a physical uplink bridge device, a PCIE interconnection network, multiple physical downlink bridge devices, and a transponder. The uplink bridge device is connected to a host through an uplink port. The physical uplink bridge device is connected to the multiple physical downlink bridge devices through the PCIE interconnection network to achieve full interconnection between the multiple physical downlink bridge devices, including: The physical upstream bridge device receives a configuration space request from the host through the upstream port, wherein the configuration space request carries a target bus number; When the physical upstream bridge device determines that the target bus number is a bus number related to the PCIE interconnect network, the physical upstream bridge device sends the configuration space request to the responder; The responder determines a target configuration space corresponding to the target bus number, and uses the target configuration space to respond to the configuration space request sent by the host, so that the host determines that there is a bridge device corresponding to the target configuration space in the PCIE interconnection network; Among them, the PCIE interconnection network is virtualized into multiple bridge devices, including: a virtual downstream bridge device, a virtual upstream bridge device, the physical upstream bridge device is connected to N of the virtual downstream bridge devices, each of the virtual downstream bridge device is connected to a virtual upstream bridge device, the N virtual downstream bridge devices are respectively connected to the N virtual upstream bridge devices through N buses, and each of the virtual upstream bridge devices is connected to M of the physical downstream bridge devices, wherein N and M are integers greater than or equal to 1.

2. The method according to claim 1, characterized in that Before the physical uplink bridge device sends the configuration space request to the responder, the method further includes: The physical uplink bridge device receives the bus number of each line from the N lines connected to the physical uplink bridge device, and obtains the bus numbers of the N lines, wherein the bus number of each line includes: the bus number connected to the physical uplink bridge device, and the bus numbers of the virtual downlink bridge device, the virtual uplink bridge device, and the M physical uplink bridge devices on the line; The physical upstream bridge device determines whether the target bus number is a bus number related to the PCIE interconnection network according to the target bus number and the bus numbers on the N lines.

3. The method according to claim 2, characterized in that The physical uplink bridge device determines whether the target bus number is a bus number related to the PCIE interconnection network according to the target bus number and the bus numbers on the N lines, including: In the case where the target bus number is a target secondary bus number and the bus numbers on the N lines include secondary bus numbers of each bridge device, the physical upstream bridge device determines the target device according to the secondary bus numbers of each bridge device, wherein each of the bridge devices includes: the physical upstream bridge device, the virtual downstream bridge device, the virtual upstream bridge device, and the physical downstream bridge device; In the case that the target device is the virtual downstream bridge device or the virtual upstream bridge device, the physical upstream bridge device determines that the target secondary bus number is a bus number associated with the PCIE interconnect network.

4. The method according to claim 3, characterized in that: The physical upstream bridge device determines the target device according to the secondary bus number of each bridge device, including: When the target secondary bus number is the secondary bus number of the physical upstream bridge device, the physical upstream bridge device determines the target device among the N virtual downstream bridge devices connected to the physical upstream bridge device according to the first device number carried in the configuration space request.

5. The method according to claim 4, characterized in that The physical uplink bridge device determines the target device from the N virtual downlink bridge devices connected to the physical uplink bridge device according to the first device number carried in the configuration space request, including: The physical upstream bridge device determines the virtual downstream bridge device with the first device number among the N virtual downstream bridge devices as the target device, wherein the connections between the physical upstream bridge device and the N virtual downstream bridge devices all use the same bus number.

6. The method according to claim 3, characterized in that The physical upstream bridge device determines the target device according to the secondary bus number of each bridge device, including: In the case where the target secondary bus number is the secondary bus number of the i-th virtual downstream bridge device, the physical upstream bridge device determines the i-th virtual upstream bridge device connected to the i-th virtual downstream bridge device as the target device, wherein i is an integer, the i-th virtual downstream bridge device is any one of the N virtual downstream bridge devices, the N virtual upstream bridge devices include the i-th virtual upstream bridge device, and the bus numbers of the connections between the virtual downstream bridge devices and the virtual upstream bridge devices on different lines among the N lines are different.

7. The method according to claim 3, characterized in that The physical upstream bridge device determines the target device according to the secondary bus number of each bridge device, and also includes: In the case where the target secondary bus number is the secondary bus number of the j-th virtual upstream bridge device, the physical upstream bridge device determines the target device among the M physical downstream bridge devices connected to the j-th virtual upstream bridge device according to the second device number carried in the configuration space request, where j is an integer.

8. The method according to claim 7, characterized in that The physical upstream bridge device determines the target device from the M physical downstream bridge devices connected to the jth virtual upstream bridge device according to the second device number carried in the configuration space request, including: The physical upstream bridge device determines the physical downstream bridge device whose device number is the second device number among the M physical downstream bridge devices connected to the j-th virtual upstream bridge device as the target device, wherein the connections between the j-th virtual upstream bridge device and the M physical downstream bridge devices all use the same bus number, and the bus numbers of the connections between the virtual upstream bridge devices and the physical downstream bridge devices on different lines among the N lines are different.

9. The method according to claim 7 or 8, characterized in that: After determining the target device among the M physical downlink bridge devices connected to the jth virtual uplink bridge device, the method further includes: In the case where the target device is the kth physical downlink bridge device among the M physical downlink bridge devices connected to the jth virtual uplink bridge device, the physical uplink bridge device sends the configuration space request to the kth physical downlink bridge device, wherein k is an integer, and the kth physical downlink bridge device is any physical downlink bridge device among the M physical downlink bridge devices connected to the jth virtual uplink bridge device; The kth physical downstream bridge device uses the configuration space of the kth physical downstream bridge device to respond to the configuration space request sent by the host.

10. The method according to claim 3, characterized in that: The physical upstream bridge device determines the target device according to the secondary bus number of each bridge device, and also includes: In the case that the kth physical downstream bridge device among the M physical downstream bridge devices connected to the jth virtual upstream bridge device is also connected to multiple other physical downstream bridge devices, and the target secondary bus number is within the bus number range of the kth physical downstream bridge device, the physical upstream bridge device determines the target device among the other physical downstream bridge devices according to the target secondary bus number and the third device number carried in the configuration space request, wherein j and k are integers, the jth virtual upstream bridge device is any virtual upstream bridge device among the N virtual upstream bridge devices, and the bus number range of the kth physical downstream bridge device includes: bus numbers between the secondary bus number of the kth physical downstream bridge device and the slave bus number of the kth physical downstream bridge device.

11. The method according to claim 10, characterized in that After the physical upstream bridge device determines the target device in the other physical downstream bridge devices according to the target secondary bus number and the third device number carried in the configuration space request, the method further includes: In the case where the target device is the Sth physical downlink bridge device among multiple other physical downlink bridge devices connected to the kth physical downlink bridge device, the physical uplink bridge device sends the configuration space request to the Sth physical downlink bridge device, wherein S is an integer, and the Sth physical downlink bridge device is any physical downlink bridge device among multiple other physical downlink bridge devices connected to the kth physical downlink bridge device; The Sth physical downstream bridge device uses the configuration space of the Sth physical downstream bridge device to respond to the configuration space request sent by the host.

12. The method according to claim 3, characterized in that The physical upstream bridge device determines the target device according to the secondary bus number of each bridge device, and also includes: When the physical downstream bridge device is connected to the endpoint device through a downstream port and the target secondary bus number is the kth physical downstream bridge device among the M physical downstream bridge devices connected to the jth virtual upstream bridge device, the port device connected to the kth physical downstream bridge device is determined as the target device, where k is an integer.

13. The method according to claim 12, characterized in that After determining the port device connected to the kth physical downlink bridge device as the target device, the method further includes: The physical upstream bridge device sends the configuration space request to the port device to which the kth physical downstream bridge device is connected; The port device uses the configuration space of the port device to respond to the configuration space request sent by the host.

14. The method according to claim 1, characterized in that The responder determines a target configuration space corresponding to the target bus number, including: The responder searches for a virtual bridge device corresponding to the target bus number in a storage area, wherein the virtual bridge device includes: a virtual downlink bridge device and a virtual uplink bridge device; The configuration space corresponding to the virtual bridge device corresponding to the target bus number is determined as the target configuration space, wherein the corresponding relationship between the bus number, the virtual bridge device and the configuration space is stored in the storage area of ​​the responder.

15. A PCIE switching chip, It is characterized in that include: A physical uplink bridge device, a PCIE interconnection network, a plurality of physical downlink bridge devices, and a transponder, wherein the uplink bridge device is connected to a host through an uplink port, and the physical uplink bridge device is connected to the plurality of physical downlink bridge devices through the PCIE interconnection network to achieve full interconnection between the plurality of physical downlink bridge devices, wherein: The physical upstream bridge device is used to receive a configuration space request from the host through the upstream port, wherein the configuration space request carries a target bus number; The physical uplink bridge device is provided with a decoder, and the decoder is used for sending the configuration space request to the responder when it is determined that the target bus number is a bus number related to the PCIE interconnection network; The responder is used to determine a target configuration space corresponding to the target bus number, and use the target configuration space to respond to the configuration space request sent by the host, so that the host determines that there is a bridge device corresponding to the target configuration space in the PCIE interconnection network; Among them, the PCIE interconnection network is virtualized into multiple bridge devices, including: a virtual downstream bridge device, a virtual upstream bridge device, the physical upstream bridge device is connected to N of the virtual downstream bridge devices, each of the virtual downstream bridge device is connected to a virtual upstream bridge device, the N virtual downstream bridge devices are respectively connected to the N virtual upstream bridge devices through N buses, and each of the virtual upstream bridge devices is connected to M of the physical downstream bridge devices, wherein N and M are integers greater than or equal to 1.

16. The PCIE switching chip according to claim 15, characterized in that: The PCIE interconnection network is virtualized into multiple bridge devices, including: a virtual downstream bridge device and a virtual upstream bridge device, the physical upstream bridge device is connected to N virtual downstream bridge devices, each of the virtual downstream bridge devices is connected to a virtual upstream bridge device, the N virtual downstream bridge devices are respectively connected to the N virtual upstream bridge devices through N buses, and each of the virtual upstream bridge devices is connected to M physical downstream bridge devices, wherein N and M are integers greater than or equal to 1; The decoder of the physical uplink bridge device is further used to receive the bus number of each line from the N lines connected to the physical uplink bridge device, and obtain the bus numbers of the N lines, wherein the bus number of each line includes: the bus number connected to the physical uplink bridge device, and the bus connected between the virtual downlink bridge device, the virtual uplink bridge device, and the M physical uplink bridge devices on the line; Determine whether the target bus number is a bus number in the PCIE interconnection network according to the target bus number and the bus numbers on the N lines.

17. The PCIE switching chip according to claim 15, characterized in that: The transponder is provided with a storage area, in which the corresponding relationship between the bus number, the virtual bridge device and the configuration space is recorded, and further includes: The responder is used to search the storage area for a virtual bridge device corresponding to the target bus number, wherein the virtual bridge device includes: a virtual downlink bridge device and a virtual uplink bridge device; The configuration space corresponding to the virtual bridge device corresponding to the target bus number is determined as the target configuration space.

18. A transponder, characterized in that: A PCIE switching chip is applied to a high-speed serial computer expansion bus standard. The PCIE switching chip includes: a physical uplink bridge device, a PCIE interconnection network, a plurality of physical downlink bridge devices, and the transponder. The uplink bridge device is connected to a host through an uplink port. The physical uplink bridge device is connected to the plurality of physical downlink bridge devices through the PCIE interconnection network to achieve full interconnection between the plurality of physical downlink bridge devices, including: a receiving module, configured to receive a configuration space request from the physical uplink bridge device, wherein the physical uplink bridge device receives the configuration space request from the host through an uplink port, the configuration space request carries a target bus number, and the physical uplink bridge device sends the configuration space request to the responder when determining that the target bus number is a bus number related to the PCIE interconnection network; a response module, configured to determine a target configuration space corresponding to the target bus number, and use the target configuration space to respond to the configuration space request sent by the host, so that the host determines that a bridge device corresponding to the target configuration space exists in the PCIE interconnection network; Among them, the PCIE interconnection network is virtualized into multiple bridge devices, including: a virtual downstream bridge device, a virtual upstream bridge device, the physical upstream bridge device is connected to N of the virtual downstream bridge devices, each of the virtual downstream bridge device is connected to a virtual upstream bridge device, the N virtual downstream bridge devices are respectively connected to the N virtual upstream bridge devices through N buses, and each of the virtual upstream bridge devices is connected to M of the physical downstream bridge devices, wherein N and M are integers greater than or equal to 1.

19. The transponder according to claim 18, characterized in that Also includes: A storage area for storing the correspondence between bus numbers, virtual bridge devices, and configuration spaces; A search module, used for searching a virtual bridge device corresponding to the target bus number in a storage area, wherein the virtual bridge device includes: a virtual downlink bridge device and a virtual uplink bridge device; The determination module is used to determine the configuration space corresponding to the virtual bridge device corresponding to the target bus number as the target configuration space.

20. A physical uplink bridge device, characterized in that: A PCIE switching chip is applied to a high-speed serial computer expansion bus standard. The PCIE switching chip includes: a physical uplink bridge device, a PCIE interconnection network, a plurality of physical downlink bridge devices, and a transponder. The uplink bridge device is connected to a host through an uplink port. The physical uplink bridge device is connected to the plurality of physical downlink bridge devices through the PCIE interconnection network to achieve full interconnection between the plurality of physical downlink bridge devices, including: A receiving module, configured to receive a configuration space request from the host through the uplink port, wherein the configuration space request carries a target bus number; A decoding module, used to determine that the target bus number is a bus number related to the PCIE interconnection network; a sending module, configured to send the configuration space request to the responder when it is determined that the target bus number is a bus number related to the PCIE interconnection network, so as to determine the target configuration space corresponding to the target bus number through the responder, and use the target configuration space to respond to the configuration space request sent by the host, so that the host determines that there is a bridge device corresponding to the target configuration space in the PCIE interconnection network; Among them, the PCIE interconnection network is virtualized into multiple bridge devices, including: a virtual downstream bridge device, a virtual upstream bridge device, the physical upstream bridge device is connected to N of the virtual downstream bridge devices, each of the virtual downstream bridge device is connected to a virtual upstream bridge device, the N virtual downstream bridge devices are respectively connected to the N virtual upstream bridge devices through N buses, and each of the virtual upstream bridge devices is connected to M of the physical downstream bridge devices, wherein N and M are integers greater than or equal to 1.

21. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 14 when executed by a processor.

22. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 14 are implemented.

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