Multi-thread partitioning method under storage and computing integrated structure

Abstract

The multi-thread partitioning method under the storage-computation integrated structure disclosed in the present invention includes: splitting the parallel nodes in the annotation call graph into multiple basic blocks, running them on multiple threads, and running the data set to calculate the data transmission volume between the basic blocks; selecting the thread with the highest number of executions to execute in the in-memory computing unit, using the partitioning result as the initial solution, and calculating the total execution time of the partitioning scheme; in each iteration, screening out the threads with the execution times exceeding the threshold T H The threads are distributed to the set of threads executed by the in-memory computing unit. In the current optimal solution {I} opt Based on the random inversion of the threads in the thread set, the i-th feasible solution {I} i ; Calculate the partitioning scheme corresponding to the feasible solution {I} i Execution time T i , calculate the execution time T i and the execution time T of the current optimal solution opt If the difference ΔT is positive, the feasible solution {I} i As the current optimal solution and update the current optimal execution time T i . Divide the parallel basic blocks to reduce the waiting time between programs.

Description

Technical Field

[0001] The present invention belongs to the technical field of storage and computing integration. More specifically, the present invention relates to a multi-thread partitioning method under a storage and computing integration structure. Background Art

[0002] The processing-in-memory (PIM) architecture integrates high-concurrency, high-performance computing units within memory to complete data computing nearby or even on-site. The PIM architecture can achieve performance acceleration of one to two orders of magnitude for some applications and reduce data transportation energy consumption by about 80%.

[0003] While the integrated storage-computing architecture improves computing performance, it also presents a series of challenges, the most important of which is the matching of the integrated storage-computing hardware with the storage-computing separation software system. This also raises the issue of computing resource scheduling, specifically where computing is performed. In an integrated storage-computing architecture, computing resources are distributed, requiring processors to collaborate to improve computing performance.

[0004] In previous computational partitioning, the annotation call graph was usually directly partitioned using a partitioning algorithm. The disadvantage of this method is that since the processing time between nodes may differ by more than 1,000 times, the nodes need to wait for each other, resulting in a decrease in computational efficiency. Summary of the Invention

[0005] The present invention provides a multi-thread partitioning method under a storage-computing integrated structure, aiming to improve the above-mentioned problems.

[0006] The present invention is implemented as follows: a multi-thread partitioning method in a storage-computing integrated structure, the method comprising the following steps:

[0007] (1) Treating basic blocks as nodes in an annotation call graph, splitting the parallelizable nodes in the annotation call graph into multiple basic blocks, running them on multiple threads, and running a data set to calculate the amount of data transfer between threads. This data set is used to test the program corresponding to the basic block and assign values ​​to the attribute set of the annotation call graph;

[0008] (2) Select the thread with the highest number of executions to execute in the in-memory computing unit, use the partition result as the initial solution, and calculate the total execution time T of the partition scheme. all ;

[0009] (3) In each iteration, the number of executions exceeding the threshold T is selected. H The threads are distributed to the set of threads executed by the in-memory computing unit. In the current optimal solution {I} opt Based on the random inversion of the threads in the thread set, the i-th feasible solution {I}i ;

[0010] (4) Calculate the partitioning scheme corresponding to the feasible solution {I} i Execution time T i , calculate the execution time T i and the execution time T of the current optimal solution opt If the difference ΔT is negative, then the feasible solution is {I} i That is the current optimal solution and the current optimal time is updated to the execution time T i , if the difference ΔT is positive, then the feasible solution {I} i As the current optimal solution and update the current optimal execution time T i .

[0011] Furthermore, the total execution time of the divided plan is T all The calculation formula is as follows:

[0012] T all =T CPU +T PIM +T M

[0013] Among them, T CPU is the total execution time of the on-chip processor, T PIM is the total execution time of the in-memory computing unit, T M It is the total data transmission time between the on-chip processor and the computing unit in memory.

[0014] Furthermore, the total data transmission time between the on-chip processor and the in-memory computing unit is T M The calculation formula is as follows:

[0015]

[0016] Among them, W PIM Represents the set of threads in the computing unit, W CPU represents the set of threads in the on-chip processor, w p Represents the set W PIM The pth thread in w p ∈W PIM , w c Represents the set W CPU The cth thread in w c ∈W CPU ;d(w c ,w p ) represents thread w c To thread w p The amount of data transmission between C ,W P)) represents the set W PIM Threads in the set W CPU The maximum amount of data transfer in the thread in S u,v It represents the data transmission volume from basic block u to basic block v, u∈S, S is divided into the basic block set of the on-chip processor, v∈T, T is divided into the basic block set of the in-memory computing unit, and BW represents the read and write bandwidth of the memory computing unit.

[0017] Furthermore, the total execution time of the on-chip processor is T CPU The calculation formula is as follows:

[0018]

[0019] Where u{w} represents the threads of the basic block u divided into on-chip processors, Represents thread u{ w The processing time on the on-chip processor, S, is divided into the set of basic blocks of the on-chip processor;

[0020] When the instruction corresponding to thread w in basic block u is executed in the on-chip processor, I u{w} The value of is 0; when thread w in basic block u is executed on the in-memory computing unit, then I u{w} The value of is 1.

[0021] Furthermore, the total execution time of the in-memory computing unit is T PIM The calculation formula is as follows:

[0022]

[0023] Among them, v{w} represents the threads of the basic block v divided into the in-memory computing units, It represents the processing time of the thread on the in-memory computing unit, and T is divided into the basic blocks of the in-memory computing unit;

[0024] When the instruction corresponding to thread w in basic block v is executed in the on-chip processor, I v{w} The value of is 0; when thread w in basic block v is executed on the in-memory computing unit, then I v{w} The value of is 1.

[0025] Furthermore, if ΔT = 0, the feasible solution {I} i and the current optimal solution {I} opt The data handling power consumption ΔE corresponding to the partitioning scheme is calculated, and the partitioning scheme with lower data handling power consumption is taken as the current optimal solution.

[0026] Furthermore, the calculation formula of probability r is as follows:

[0027]

[0028] Among them, k is the correction coefficient, which represents the current inverse I j The percentage of basic block execution times to the maximum execution times, ΔT is the number of feasible solutions {I} i The corresponding execution time T i and the execution time T of the current optimal solution opt The difference.

[0029] The present invention measures the data transmission volume in the annotation call graph of the data call graph through a data set, divides the parallel code blocks (basic blocks), can greatly reduce the waiting time between programs, and greatly improves the running efficiency of the program. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The construction process of the annotated call graph provided by the embodiment of the present invention, (a) is the connectivity of the dataset nodes, and (b) is the edge weights between the nodes where multiple threads are located;

[0031] Figure 2 A flowchart of a method for obtaining a program partitioning solution with the shortest execution time provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The specific implementation methods of the present invention will be further explained in detail below by describing the embodiments with reference to the accompanying drawings, so as to help those skilled in the art to have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention.

[0033] In order to perform quantifiable computational partitioning between on-chip processors and in-memory computing units in the memory-computing integrated architecture, the execution process of the memory-computing integrated program is first converted into the program's annotated call graph, and then the computational partitioning of the memory-computing integrated program is achieved through graph partitioning of the annotated call graph.

[0034] An annotated call graph is a directed acyclic graph (DAG) that represents the execution and dependencies of different subroutines during program execution. Essentially, an annotated call graph is a program dependency graph (PDG), consisting of three components: a node set, an edge set, and a set of attributes. Each node represents a sub-procedure or subroutines of a program. Some nodes can be computed in parallel, and these nodes can be distributed to different processors to improve program parallelism. Each edge in the annotated call graph represents a dependency relationship between nodes, including control dependencies and data dependencies. The edge weight represents the amount of data transferred. By using additional attributes to partition nodes in the annotated call graph, the computation partitioning problem is transformed into a community problem, effectively partitioning computation between on-chip processors and in-memory computing units. Because the bandwidth within the same processor is much greater than the bandwidth between different processors, the default data transfer time for nodes within the same processor is zero.

[0035] Once the segmentation of the annotation call graph is determined, the total execution time of the storage-computation program can be expressed using formula (1), as follows:

[0036] T all =T CPU +T PIM +T M (1)

[0037] Total execution time T of the storage and computing program all It consists of three parts: the total execution time T of the on-chip processor (CPU) CPU , the total execution time T of the in-memory computation unit (PIM) PIM , the total time T for data transmission between the on-chip processor and the in-memory computing unit M .

[0038] Among them, T CPU The total execution time of all basic blocks u∈S in the point set S on the on-chip processor is Indicates; T PIM The total execution time of all basic blocks v∈T in the point set T on the in-memory computing unit Indicates that there are parallel basic blocks, which are represented by {u}, {v}, w∈u|w∈v, and let S u,v Represents the data size transferred between basic blocks u and v, BW represents the read and write bandwidth of the memory computing unit, then It can be regarded as the total time T for data transmission between the on-chip processor and the computing unit in memory M .

[0039] In summary, the total execution time of the storage-computation program is T all It can be expressed by formula (2):

[0040]

[0041] Among them, (u,v) represents the edge between node u and node v.

[0042] Because the annotation call graph is a large-scale sparse graph, time complexity needs to be considered. In the actual partitioning process, this type of problem is NP-hard, meaning that no known polynomial-time algorithm can find the optimal solution. Therefore, using a heuristic algorithm to handle this type of problem can find a suitable solution within an acceptable time frame. As shown in formula (2), the optimization goal is to minimize the execution time of the storage-computation integrated program. Ultimately, the execution location of each non-pseudo node (basic block) i in the annotation call graph must be determined.

[0043] Let variable I v{w} is a binary variable representing the execution location of the basic block v, and the set {w} represents the running location of the thread. Set n to be the total number of parallel basic blocks. When I v{w} When the value of is 0, it means that the instruction corresponding to thread {w} in basic block v is executed in the on-chip processor; v{w} The value of is 1, which means that the thread {w} in the basic block v is executed on the in-memory computing unit. Therefore, the computation partitioning problem of the memory-computation integrated program can be transformed into: find a binary variable set {I v{w}}(v∈V&w∈v), so that the total execution time of formula (2) is minimized.

[0044] The edge weight is calculated from the data set, Figure 1 As shown in (a), the basic block (program) is composed of 4 threads (9, 9', 9", 9'"), and the basic block is executed by four threads. The basic block is split into four parallel basic blocks (A, B, C, D), and each thread corresponds to a basic block (a node in the annotation call graph). The data exchange between threads is done by Figure 1 (b) shows that the data transmission volume between threads 9' and 9" is d4. Figure 1 The portion cut by the red dotted line in (a) is the data transfer volume between the two threads, which is expressed as The amount of data transferred between threads can generally be expressed as:

[0045]

[0046] Among them, d (i,j)Indicates the amount of data transferred between thread i and thread j. Thread i and thread j may or may not belong to the same basic block. In the weighted annotated call graph, it is the node r where thread i is located. i and the node r where the j thread is located j The amount of data represented by the edges between Indicates that the node r where the i thread is located i Go to the node r where the j thread is located j The vector modulo,

[0047] Introducing variable I v{w} After that, the total execution time of the on-chip processor is T CPU 、T PIM and T M It can be expressed by formula (4) to formula (7). In addition, in order to characterize the blocks that can only be executed in the on-chip processor and cannot be executed in the in-memory computing unit (such as the starting basic block and the end basic block, etc.), another binary variable C is introduced to each basic block. v , used to limit I v{w} The value of is shown in formula (7). v When the value of is 1, the thread {w k} can be executed in the in-memory computing unit; otherwise I v{w} The value can only be 0, which means it can only be executed in the on-chip processor.

[0048]

[0049] Where u{w} represents the threads of the basic block u divided into on-chip processors, represents the processing time of thread u{w} in the on-chip processor, S is divided into the basic blocks of the on-chip processor; when the instruction corresponding to thread w in basic block u is executed in the on-chip processor, then I u{w} The value of I is 0; when thread w in basic block u is executed on the in-memory computing unit, u{w} The value of is 1.

[0050]

[0051] Among them, v{w} represents the threads of the basic block v divided into the in-memory computing units, represents the processing time of thread v{w} on the internal computing unit, T is divided into the basic blocks of the internal computing unit; when the instruction corresponding to thread w in basic block v is executed in the on-chip processor, then I v{w} The value of I is 0; when thread w in basic block v is executed on the in-memory computing unit, v{w} The value of is 1.

[0052]

[0053] Among them, W PIM Represents the set of threads in the computing unit, W CPU represents the set of threads in the on-chip processor, w p Represents the set W PIM The pth thread in w p ∈W PIM , w c Represents the set W CPU The cth thread in w c ∈W CPU ;d(w c ,w p ) represents thread w c To thread w p The amount of data transmission between C ,W P )) represents the set W PIM Threads in the set W CPU The maximum amount of data transfer in the thread in S u,v It represents the data transmission volume from basic block u to basic block v, u∈S, S is divided into the basic block set of the on-chip processor, v∈T, T is divided into the basic block set of the in-memory computing unit, and BW represents the read and write bandwidth of the memory computing unit.

[0054] It should be noted that a basic block may have multiple threads, and the threads belonging to the same basic block may be divided into the on-chip processor and the in-memory computing unit respectively. In this case, the basic block belongs to both the in-memory computing unit and the on-chip processor.

[0055] Combining formulas (1), (4) to (6), we can solve the calculation partitioning result of a given storage-computation program {I v}(v∈V), according to each basic block v corresponds to The value can ultimately determine the basic blocks running on the in-memory processor. When the memory-computing integrated program is converted into an annotated call graph, it has a large number of basic blocks and a large solution space. Solving it often requires multiple iterations to converge on the optimal solution. Figure 2 The flowchart of the method for obtaining the program partitioning scheme with the shortest execution time provided by the embodiment of the present invention is as follows:

[0056] (1) Split the parallelizable nodes of the annotation call graph into multiple basic blocks, which are run on multiple threads. The number of threads is proportional to the size of the parallelizable basic blocks, with the ratio set to α. To facilitate the division, the running parts of the threads are considered as basic blocks. The data set is used to calculate the amount of data transfer between threads. The data set is used to test the corresponding program of the basic blocks and assign values ​​to the attribute set of the annotation call graph.

[0057] (2) Select the thread with the highest number of executions among all threads and execute it in the in-memory computing unit, marking its I u If 0 is 0, the partition result is used as the initial solution, and the total execution time of the calculation partition scheme is calculated according to formula (1), formula (4) to formula (6).

[0058] (3) Iterate and solve according to the idea of ​​simulated annealing algorithm: In each iteration, first filter out the number of executions that exceeds the threshold T H And can be distributed to the thread set executed in memory, and randomly select a basic block in the thread set to obtain its number j .

[0059] (4) In the current optimal solution {I} opt Based on the optimal partitioning scheme, the value of the variable I of the thread numbered by j is negated, and a new feasible solution {I} is formed. i .

[0060] (5) Calculate the feasible solution {I} i The execution time of the corresponding partitioning scheme is compared with the existing optimal time T opt Compare and get the difference ΔT. If the difference ΔT is negative, it means that the feasible solution {I} i The execution time is lower than the current optimal solution, and the feasible solution {I} is selected. i As the current optimal solution and update the existing optimal time T opt ;

[0061] (6) If the feasible solution {I} i and the current optimal solution {I} opt The execution time of the two solutions is the same, then the feasible solution {I} i and the current optimal solution {I} opt The corresponding data handling power consumption ΔE is taken, and the solution with lower data handling power consumption is taken as the current optimal solution; if the difference ΔT is positive, it means that the feasible solution {I} i The execution time is longer than the current optimal solution, and the new state is accepted with a certain probability r, that is, the feasible solution {I} i As the current optimal solution; the calculation formula of probability r is: The calculation formula of probability r is an empirical formula, where k is the current inverse of I j The percentage of basic block execution times to the maximum execution times, ΔT is the number of feasible solutions {I} i The corresponding execution time T i and the execution time T of the current optimal solution opt This design is to make the basic blocks with more execution times get higher update weights, so as to avoid falling into the local optimum. maxiterations, the algorithm will eventually get a converged solution {I} opt , which corresponds to the optimal computational partitioning.

[0062] The present invention has been described exemplarily. Obviously, the specific implementation of the present invention is not limited to the above-mentioned method. As long as various non-substantial improvements are made using the method concept and technical solution of the present invention, or the concept and technical solution of the present invention are directly applied to other occasions without improvement, they are all within the scope of protection of the present invention.

Claims

1. A multi-thread partitioning method under a storage-computing integrated structure, characterized in that: The method comprises the following steps: (1) Treat basic blocks as nodes in an annotation call graph, split the parallelizable nodes in the annotation call graph into multiple basic blocks, run them on multiple threads, run the dataset to calculate the amount of data transfer between threads, and assign the values ​​to the attributes of the annotation call graph; (2) Select the thread with the highest number of executions to execute in the in-memory computing unit, use the partitioning scheme as the initial solution, and calculate the total execution time T of the partitioning scheme. all ; (3) In each iteration, the number of executions exceeding the threshold T is selected. H The threads are distributed to the set of threads executed by the in-memory computing unit. In the current optimal solution {I} opt Based on the random inversion of the threads in the thread set, the i-th feasible solution {I} i ; (4) Calculate the partitioning scheme corresponding to the feasible solution {I} i Execution time T i , calculate the execution time T i and the execution time T of the current optimal solution opt If the difference ΔT is negative, then the feasible solution is {I} i That is the current optimal solution and the current optimal time is updated to the execution time T i , if the difference ΔT is positive, then the feasible solution {I} i As the current optimal solution and update the current optimal execution time T i ; The total execution time of the partitioning scheme is T all The calculation formula is as follows: T all =T CPU +T PIM +T M Among them, T CPU is the total execution time of the on-chip processor, T PIM is the total execution time of the in-memory computing unit, T M is the total time for data transfer between the on-chip processor and the computing unit in memory; The total data transmission time between the on-chip processor and the in-memory computing unit is T M The calculation formula is as follows: Among them, W PIM Represents the set of threads in the in-memory computing unit, W CPU represents the set of threads in the on-chip processor, w p Represents the set W PIM The pth thread in w p ∈W PIM , w c Represents the set W CPU The cth thread in w c ∈W CPU ;d(w c ,w p ) represents thread w c To thread w p The amount of data transmission between C ,W P )) represents the set W PIM Threads in the set W CPU The maximum amount of data transfer in the thread in S u,v It represents the data transmission volume from basic block u to basic block v, u∈S, S is divided into the basic block set of the on-chip processor, v∈T, T is divided into the basic block set of the in-memory computing unit, and BW represents the read and write bandwidth of the memory computing unit.

2. The multi-thread partitioning method under the storage and computing integrated structure according to claim 1, characterized in that: The total execution time of the on-chip processor is T CPU The calculation formula is as follows: Where u{w} represents the threads of the basic block u divided into on-chip processors, represents the processing time of thread u{w} on the on-chip processor, S is divided into the basic blocks of the on-chip processor; When the instruction corresponding to thread w in basic block u is executed in the on-chip processor, I u{w} The value of is 0; when thread w in basic block u is executed on the in-memory computing unit, then I u{w} The value of is 1.

3. The multi-thread partitioning method under the storage and computing integrated structure according to claim 1 is characterized in that: Total execution time T of the in-memory computing unit PIM The calculation formula is as follows: Among them, v{w} represents the threads of the basic block v divided into the in-memory computing units, It represents the processing time of the thread on the in-memory computing unit, and T is divided into the basic blocks of the in-memory computing unit; When the instruction corresponding to thread w in basic block v is executed in the on-chip processor, I v{w} The value of is 0; when thread w in basic block v is executed on the in-memory computing unit, then I v{w} The value of is 1.

4. The multi-thread partitioning method under the storage and computing integrated structure according to claim 1 is characterized in that: If ΔT=0, compare the feasible solution {I} i and the current optimal solution {I} opt The data handling power consumption ΔE corresponding to the partitioning scheme is calculated, and the partitioning scheme with lower data handling power consumption is taken as the current optimal solution.

5. The multi-thread partitioning method under the storage and computing integrated structure according to claim 1 is characterized in that: The calculation formula of probability r is as follows: Among them, k is the correction coefficient, which represents the current inverse I j The percentage of basic block execution times to the maximum execution times, ΔT is the number of feasible solutions {I} i The corresponding execution time T i and the execution time T of the current optimal solution opt The difference.

Images