Charge pump voltage regulator circuit
By selecting the charge pump voltage stabilization circuit of the driving clock frequency by controlling the signal, the problems of high ripple of the charge pump output voltage and poor voltage stabilization accuracy are solved, and a more stable charge pump output voltage is achieved.
Patent Information
- Application Number
- CN202411141127.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2044-08-20
AI Technical Summary
The existing charge pump voltage stabilization circuits tend to cause high ripple and poor voltage stabilization accuracy when adjusting the output voltage, and the frequent turn-on and turn-off clock frequency lead to unstable charge pump output voltage and long restart time.
The oscillation frequency supply circuit, Mux circuit, charge pump, voltage divider circuit and comparison circuit are adopted to select the driving clock frequency through the control signal to achieve stable voltage divider and precise adjustment of the charge pump output voltage.
Reduces ripple of the charge pump output voltage, improves stability accuracy, and reduces the restart time of the charge pump to ensure the stability of the output voltage.
Smart Images
Figure CN118748032B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuits, and in particular to a charge pump voltage stabilizing circuit. Background Art
[0002] In NOR Flash or NAND storage devices, different voltages are required for reading, writing and erasing Flash cells, which are generated by charge pumps. In the design of the charge pump, it is necessary to ensure that the charge pump can reach the required voltage under the worst PVT conditions. This will cause the voltage generated by the charge pump under other working conditions to be higher than the required voltage, thus affecting the basic properties and reliability of the Flash cell. In order for the charge pump to generate a stable voltage, a charge pump voltage regulator circuit needs to be added to the output of the charge pump.
[0003] From the working principle of the charge pump, we can know that to adjust the output voltage of the charge pump, we can adjust the power supply voltage VDD, the number of charge pump capacitors N, the capacitor C, and the load current , and the driving clock frequency f. Therefore, in the prior art, the following two methods are often used to adjust the output voltage of the charge pump. The first method is to adjust the output voltage of the charge pump by adjusting the load current. When the output voltage of the charge pump is higher than the specified voltage, the path from the output end of the charge pump to the ground is opened to discharge the current. Specifically, the output voltage of the charge pump is divided, and the divided potential is input into the comparator for comparison with the reference potential. When the potential after the voltage division is greater than the reference potential, the comparator outputs a high level, opens the nmos tube, and the charge pump output forms a path to the ground, generating a large discharge current, and pulling down the output voltage of the charge pump. The second method is to control the clock charge pump voltage stabilization circuit by comparing the output voltage of the charge pump with the reference voltage, and then feeding back the comparison result to control the opening and closing of the driving clock frequency. When the output voltage of the charge pump is too high, the driving clock frequency is turned off, and the charge pump starts to discharge. When the output voltage of the charge pump is lower than the reference voltage, the driving clock frequency is turned on, and the charge pump restarts and then works normally, thereby stabilizing the output voltage of the charge pump.
[0004] However, the first method in the prior art directly opens the output end of the charge pump to discharge the output current and stop providing the output voltage, which may result in high ripple in the final output voltage of the charge pump. The second method continuously turns on and off the clock frequency, resulting in the charge pump being in only two states: discharge and normal operation, which may result in poor voltage regulation accuracy of the final output voltage of the charge pump, long restart time of the charge pump, and unstable output voltage of the charge pump. Summary of the invention
[0005] The object of the present invention is to provide a charge pump voltage stabilizing circuit which can improve the stability accuracy of the charge pump output voltage and reduce the ripple of the charge pump output voltage.
[0006] In order to achieve the above object, the present invention provides a charge pump voltage stabilizing circuit, comprising:
[0007] An oscillation frequency providing circuit, used for providing a plurality of oscillation frequencies;
[0008] A Mux circuit, used for receiving a plurality of the oscillation frequencies and control signals, wherein the oscillation frequencies correspond to the values of the control signals one by one, and the Mux circuit is further used for selecting the corresponding oscillation frequency as the driving clock frequency according to the value of the control signal, and outputting the driving clock frequency;
[0009] A charge pump, used to boost the input voltage of the charge pump to a corresponding value according to the driving clock frequency, and output a voltage;
[0010] a voltage divider circuit, used for dividing the output voltage of the charge pump to obtain a plurality of charge pump divided voltages; and
[0011] The comparison circuit is used to compare the divided voltages of the charge pumps with the reference voltage respectively to obtain a plurality of comparison values, and use the comparison values as control signals of the Mux circuit.
[0012] Optionally, the charge pump voltage stabilization circuit further includes a logic circuit for performing logic calculations on a plurality of the comparison values, and the comparison values after the logic calculations are used as control signals of the Mux circuit.
[0013] Optionally, in the charge pump voltage stabilization circuit, the oscillation frequency providing circuit includes:
[0014] A bandgap circuit for providing a reference voltage;
[0015] an oscillator, for generating a clock pulse signal according to the bias provided by the reference voltage;
[0016] The frequency divider is used to convert the clock pulse signal into a plurality of oscillation frequencies.
[0017] Optionally, in the charge pump voltage stabilization circuit, the bandgap circuit is also used to provide the reference voltage.
[0018] Optionally, in the charge pump voltage stabilization circuit, the control signal is a digital signal.
[0019] Optionally, in the charge pump voltage stabilizing circuit, the voltage divider circuit includes a first resistor to an Nth resistor, the first resistor to the Nth resistor are sequentially connected in series between the output voltage of the charge pump and ground, and the end of the first resistor to the N-1th resistor close to the ground outputs the charge pump voltage divider, wherein N is a positive integer greater than or equal to 3.
[0020] Optionally, in the charge pump voltage stabilizing circuit, the value range of the first resistor to the Nth resistor is 1 kΩ~10 kΩ.
[0021] Optionally, in the charge pump voltage stabilization circuit, the comparison circuit includes N-1 comparators, one input terminal of each comparator is connected to a charge pump voltage divider, the other input terminal is connected to a reference voltage, and the output terminal outputs a comparison value.
[0022] Optionally, in the charge pump voltage stabilization circuit, the reference voltage connected to the input terminal of each comparator is the same.
[0023] Optionally, in the charge pump voltage stabilization circuit, when the charge pump divided voltage is greater than or equal to the reference voltage, the comparator outputs 1, and when the charge pump divided voltage is less than the reference voltage, the comparator outputs 0.
[0024] The charge pump voltage stabilization circuit provided in the present invention includes: an oscillation frequency providing circuit for providing several oscillation frequencies; a Mux circuit for receiving several oscillation frequencies and a control signal, selecting the corresponding oscillation frequency as the driving clock frequency according to the value of the control signal, and outputting the driving clock frequency, wherein the oscillation frequency corresponds to the value of the control signal one by one; a charge pump for boosting the input voltage to the corresponding value according to the driving clock frequency, and outputting the voltage; a voltage divider circuit for dividing the output voltage of the charge pump to obtain several charge pump divided voltages; and a comparison circuit for comparing several charge pump divided voltages with a reference voltage respectively to obtain several comparison values, and using the comparison values as the control signal of the Mux circuit. The present invention controls the selection of the driving clock frequency by using a control signal, so that the charge pump can output different voltages, reduces the ripple of the charge pump output voltage, and improves the stability accuracy of the charge pump output voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 is a schematic diagram of a charge pump voltage stabilizing circuit according to an embodiment of the present invention;
[0026] In the figure: 110 - oscillation frequency providing circuit, 111 - bandgap circuit, 112 - oscillator, 113 - frequency divider, 120 - Mux circuit, 130 - charge pump, 140 - voltage divider circuit, 150 - comparison circuit, 160 - logic circuit. DETAILED DESCRIPTION
[0027] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.
[0028] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.
[0029] Furthermore, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can be intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can be one or more intervening layers. In addition, references to being "on" and "under" each layer can be made based on the accompanying drawings.
[0030] Please refer to Figure 1 The present invention provides a charge pump voltage stabilizing circuit, comprising:
[0031] An oscillation frequency providing circuit 110, for providing a plurality of oscillation frequencies;
[0032] The Mux circuit 120 is used to receive a plurality of oscillation frequencies and control signals, select a corresponding oscillation frequency as a driving clock frequency according to the value of the control signal, and output the driving clock frequency, wherein the oscillation frequency corresponds to the value of the control signal one by one;
[0033] A charge pump 130, the charge pump 130 has an input voltage terminal and an output voltage terminal. The input voltage of the charge pump 130 is VDD. The charge pump 130 boosts the input voltage of the charge pump 130 to a corresponding value according to the driving clock frequency output by the Mux circuit 120, and outputs a voltage;
[0034] A voltage divider circuit 140 is used to divide the output voltage of the charge pump to obtain a plurality of charge pump divided voltages; and
[0035] The comparison circuit 150 is used to compare the divided voltages of several charge pumps with the reference voltage respectively to obtain several comparison values, and use the comparison values as control signals of the Mux circuit.
[0036] In an embodiment of the present invention, the oscillation frequency providing circuit 110 includes: a bandgap circuit 111, which is used to provide a reference voltage, and the reference voltage is used as a bias for an oscillator 112; the oscillator 112 is used to generate a clock pulse signal according to the bias provided by the reference voltage; and a frequency divider 113 is used to convert the clock pulse signal into a plurality of oscillation frequencies, and the frequencies of the plurality of oscillation frequencies are different. The frequency divider 113 can process the clock pulse signal by dividing it into two, four, or eight, and the processed clock signals are clock signals with different frequencies. In an embodiment of the present invention, the bandgap circuit 111 is also used to provide a reference voltage as a reference voltage Vref of the comparator, and the reference voltage Vref is approximately 1.8V. The method of providing the reference voltage Vref by the bandgap circuit 111 is a prior art and will not be described in detail here.
[0037] Furthermore, the charge pump voltage regulator circuit of the embodiment of the present invention further includes a logic circuit 160, which is used to perform logic calculations on a plurality of comparison values generated by the comparator to generate a comparison value after the logic calculation, and the comparison value after the logic calculation is used as a control signal of the Mux circuit 120. The logic circuit 160 of the embodiment of the present invention can combine the comparison values generated by the comparators to obtain a value that is easier to handle and more intuitive as a control signal. In the embodiment of the present invention, the control signal is a digital signal.
[0038] In the embodiment of the present invention, the Mux circuit 120 has two input terminals, which receive a plurality of oscillation frequencies and control signals respectively, select the corresponding oscillation frequency as the driving clock frequency according to the value of the control signal, and output the driving clock frequency, wherein the oscillation frequency corresponds to the value of the control signal one by one, and the corresponding relationship can be stored in a table. For example, if there are two comparators, the output values of the two comparators may be 0 and 0, 0 and 1, 1 and 0, or 1 and 1, and the values calculated by the logic circuit 160 may be 00, 01, 10, and 11 in sequence, and 00, 01, 10, and 11 are used as the values of the control signal of the Mux circuit. Therefore, the circuit of the embodiment of the present invention can obtain the values of multiple control signals. When the value of the control signal obtained by the Mux circuit 120 is 00, the corresponding driving clock frequency can be selected. When the value of the control signal obtained by the Mux circuit 120 is 01, another corresponding driving clock frequency can be selected. Similarly, when the value of the control signal obtained by the Mux circuit 120 is 10 and 11, other corresponding driving clock frequencies will be selected. The charge pump then boosts the input voltage of the charge pump to a corresponding voltage as the output voltage of the charge pump according to the selected driving clock frequency. The corresponding relationship between the value of the control signal and the driving clock frequency, and the corresponding relationship between the driving clock frequency and the boost of the charge pump can be set according to actual needs.
[0039] In an embodiment of the present invention, the voltage divider circuit includes a first resistor to an Nth resistor, which are sequentially connected in series between the output voltage of the charge pump and the ground, and one end of the first resistor to the N-1th resistor close to the ground outputs the charge pump voltage divider, wherein N is a positive integer greater than or equal to 3. In the embodiment of the present invention, three resistors are selected as an example, that is, the value of N is 3. The resistance range of the three resistors can be 1kΩ~10kΩ. Of course, in other embodiments of the present invention, the resistors can be other value ranges. The three resistors are the first resistor R1, the second resistor R2 and the third resistor R3, which are sequentially connected in series between the output voltage of the charge pump and the ground. That is, the first end of the first resistor R1 is connected to the output end of the charge pump 130, the second end of the first resistor R1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is grounded. The second end of the first resistor R1 and the second end of the second resistor R2 output the charge pump voltage divider respectively, so two charge pump voltage dividers are output here. In other embodiments of the present invention, the value of N may be other values except 3, and the specific value depends on the actual circuit.
[0040] In an embodiment of the present invention, the comparison circuit includes N-1 comparators, one input end of each comparator is connected to a charge pump voltage divider, the other input end is connected to a reference voltage, and the output end outputs a comparison value. The embodiment of the present invention selects two comparators as an embodiment, one input end of one comparator is connected to the above-mentioned charge pump voltage divider, and the other input end is connected to the reference voltage. One input end of another comparator is connected to the above-mentioned another charge pump voltage divider, and the other input end is connected to the reference voltage. The reference voltages connected to the input ends of each comparator are the same, and are all generated by the bandgap circuit 111. When the charge pump voltage divider is greater than or equal to the reference voltage, the comparator outputs 1, and when the charge pump voltage divider is less than the reference voltage, the comparator outputs 0. Therefore, if there are two comparators, the two comparators will output 0 or 1 respectively. The values of the control signal obtained by the combination of the two comparators will have 4. Compared with the prior art, directly opening the charge pump output end to discharge the output current and stop providing the output voltage reduces the ripple of the charge pump output voltage. Compared with the prior art that directly shuts down the driving clock frequency to stop the charge pump from working, the charge pump in the embodiment of the present invention has a more stable voltage boost, a more stable output voltage, and a higher stability accuracy. In addition, the charge pump in the embodiment of the present invention does not need to be restarted, thereby reducing the restart time.
[0041] In summary, the charge pump voltage stabilization circuit provided in the embodiment of the present invention includes: an oscillation frequency providing circuit for providing several oscillation frequencies; a Mux circuit for receiving several oscillation frequencies and a control signal, selecting the corresponding oscillation frequency as the driving clock frequency according to the value of the control signal, and outputting the driving clock frequency, wherein the oscillation frequency corresponds to the value of the control signal one by one; a charge pump for boosting the input voltage to the corresponding value according to the driving clock frequency, and outputting the voltage; a voltage divider circuit for dividing the output voltage of the charge pump to obtain several charge pump divided voltages; and a comparison circuit for comparing several charge pump divided voltages with a reference voltage respectively to obtain several comparison values, and using the comparison values as the control signal of the Mux circuit. The present invention controls the selection of the driving clock frequency by using a control signal, so that the charge pump can output different voltages, reduces the ripple of the charge pump output voltage, and improves the stability accuracy of the charge pump output voltage.
[0042] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.
Claims
1. A charge pump voltage stabilizing circuit, characterized in that: include: An oscillation frequency providing circuit, used for providing a plurality of oscillation frequencies; A Mux circuit, used for receiving a plurality of the oscillation frequencies and control signals, wherein the oscillation frequencies correspond to the values of the control signals one by one, and the Mux circuit is further used for selecting the corresponding oscillation frequency as the driving clock frequency according to the value of the control signal, and outputting the driving clock frequency; A charge pump, used to boost the input voltage of the charge pump to a corresponding value according to the driving clock frequency, and output a voltage; A voltage divider circuit, used for dividing the output voltage of the charge pump to obtain a plurality of charge pump divided voltages; as well as A comparison circuit, used for comparing the divided voltages of the charge pumps with a reference voltage respectively to obtain a plurality of comparison values, and using the comparison values as control signals of the Mux circuit; It also includes a logic circuit for performing logic calculation on a plurality of the comparison values, wherein the comparison values after the logic calculation are used as control signals of the Mux circuit, and the logic circuit combines the comparison values generated by the comparators; The oscillation frequency providing circuit comprises: A bandgap circuit for providing a reference voltage; an oscillator, for generating a clock pulse signal according to the bias provided by the reference voltage; The frequency divider is used to convert the clock pulse signal into a plurality of oscillation frequencies.
2. The charge pump voltage stabilizing circuit according to claim 1, characterized in that: The bandgap circuit is further configured to provide the reference voltage.
3. The charge pump voltage stabilizing circuit according to claim 1, wherein: The control signal is a digital signal.
4. The charge pump voltage stabilizing circuit according to claim 1, wherein: The voltage divider circuit includes a first resistor to an Nth resistor, which are connected in series between the output voltage of the charge pump and the ground in sequence, and one end of the first resistor to the N-1th resistor close to the ground outputs the charge pump voltage divider, wherein N is a positive integer greater than or equal to 3.
5. The charge pump voltage stabilizing circuit according to claim 4, characterized in that: The value range of the first resistor to the Nth resistor is 1 kΩ~10 kΩ.
6. The charge pump voltage stabilizing circuit according to claim 5, characterized in that: The comparison circuit comprises N-1 comparators, one input terminal of each comparator is connected to a charge pump voltage divider, the other input terminal is connected to a reference voltage, and the output terminal outputs a comparison value.
7. The charge pump voltage stabilizing circuit according to claim 6, wherein: The reference voltage connected to the input terminal of each comparator is the same.
8. The charge pump voltage stabilizing circuit according to claim 6, wherein: When the charge pump divided voltage is greater than or equal to the reference voltage, the comparator outputs 1, and when the charge pump divided voltage is less than the reference voltage, the comparator outputs 0.