Fully parallel vector outer product calculation method based on electrochemical random access memory

Abstract

The present invention discloses a fully parallel vector outer product calculation operation method based on electrochemical random access memory, including constructing a memory array with electrochemical random access memory and its gate-select transistor as basic units, and a corresponding random pulse update method. Among them, the conductivity change of the electrochemical random access memory is highly linearly related to the number of stimulation pulses. When no stimulation pulse is applied, the device channel conductance remains unchanged, showing non-volatile characteristics. Through random pulse programming, the device's conductance update and online training can be performed in situ, the vector outer product calculation is completed in parallel, and the calculation result is stored in the device's conductance, and subsequent network in-memory calculation acceleration is performed, avoiding additional data handling, and effectively reducing operation complexity and device programming delay. In addition, this solution can be extended to the network training paradigm related to the Hebbian learning rule to accelerate the training process of related algorithms.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic devices, and specifically relates to a fully parallel vector outer product calculation operation method for an electrochemical random access memory. The method can perform vector outer product calculations in full parallel and store the calculation results in situ in the device channel conductance for subsequent network in-memory calculation acceleration, avoiding additional data transfer and effectively reducing operation complexity and device programming delay. Background Art

[0002] The rapid development of deep learning has enabled significant breakthroughs in intelligent edge and end devices, reshaping industrial production and daily life. However, edge computing neural network training relies heavily on cloud service platforms, making it less adaptable to rapidly changing real-world environments. Training energy efficiency is also severely constrained by the traditional von Neumann architecture (separate memory and processing units). Currently, most deep learning hardware accelerators are focused on network inference. In-memory computing based on Ohm's and Kirchhoff's laws is a promising technology approach. By accelerating matrix-vector multiplications in situ and in full parallelism within memory arrays, it can significantly improve network computational efficiency. However, most proposed online training methods based on novel memory arrays require complex negative feedback calibration, which limits their parallelism and results in low device programming energy efficiency.

[0003] To improve the adaptability of edge devices and the training speed of memory arrays, a fully parallel online neural network training solution is urgently needed. Currently, most neural network algorithm optimizations are based on gradient backpropagation, where most operations are based on vector outer products. This involves the outer product between the backpropagated gradient vector and the input vector, which serves as the gradient matrix for the weights of that layer. Therefore, it is necessary to explore the physical properties of new memory devices to enable them to perform vector outer product operations in situ within the array, store the results in the device, and update the device state, thereby achieving fully parallel online training. Summary of the Invention

[0004] To fill a gap in the existing technology, this paper proposes for the first time a fully parallel vector outer product calculation method based on electrochemical random-access memory (ECRAM). This method can update the device conductance in situ and perform online training. The calculation results are stored in the device conductance, and subsequent network in-memory calculations are accelerated, avoiding additional data transfer and effectively reducing operation complexity and device programming delays. In addition, this solution can be extended to network training paradigms related to the Hebbian learning rule, accelerating the training process of related algorithms.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a fully parallel vector outer product calculation operation method based on ECRAM, which includes a memory array composed of ECRAM and gate-select transistors and a corresponding random pulse update method.

[0006] In the memory array composed of the above-mentioned ECRAM and gate-select transistor, the ECRAM is a three-terminal memory device, mainly including a source, a drain, a channel layer, a gate electrolyte layer, a passivation layer and a gate; by applying a stimulation signal to the gate, the mobile ions (such as hydrogen ions, lithium ions, etc.) in the gate electrolyte layer move under the action of the electric field, completing the doping and dedoping of the channel layer, thereby affecting the band structure of the channel material and dynamically adjusting the conductivity of the channel; when a strong gate stimulus is applied, the ions will be stably present in the channel, and when the stimulus is removed, the channel conductivity state can also be maintained for a long time; its source is usually grounded, and the drain is usually biased at a small constant voltage to read and monitor the channel conductivity state. The material of the channel layer can be, but is not limited to, WO x 、NbO x , VO x 、MoO x , ZnO, IGZO, ITO, MoS2, 1≤x≤3, and its thickness is in the range of 10 to 100 nm; the gate electrolyte layer is preferably a solid electrolyte membrane, and its material can be but not limited to LiPON, LATP (Li 1+x Al x Ti 2-x (PO4)3,0≤x≤0.5, lithium aluminum titanium phosphate), PSG (Phospho Silicate Glass, phosphorus silicon glass), the thickness of the gate electrolyte layer is in the range of 50 to 300 nm; the material of the passivation layer can be but is not limited to SiO2, Al2O3, Si3N4, HfO2, Ta2O5, and its thickness is in the range of 1 to 20 nm; the materials of the gate, source and drain can be but are not limited to Ti, Cr, Sc, Al, Pd, Au, Pt, Ag, W, TiN, TaN, and the electrode thickness is in the range of 100 to 300 nm.

[0007] In the memory array composed of the above ECRAM and gate-gating transistors, the gate-gating transistors preferably use silicon-based NMOS planar devices or silicon-based FinFET structured devices, as well as thin-film transistors based on metal semiconductor oxides ZnO, a-IGZO, and ITO, or field-effect transistors based on two-dimensional material channels MoS2 and WSe2. The integrated structure of ECRAM and gate-gating transistors can be referred to Figure 4The source of the gate-select transistor is connected to the gate of the ECRAM. The ECRAM gate stimulus is primarily applied to the drain of the gate-select transistor. This constitutes a 1T1E (one-transistor-one-ECRAM) cell, which is the basic unit in the memory array studied in this invention. The drain and gate of the gate-select transistor serve as the EG and TG terminals, respectively, for pulse signal input.

[0008] To implement parallel vector outer product multiplication, the ECRAM devices in the memory array are required to have a highly linear relationship between their conductance change and the number of stimulation pulses. That is, the conductance change is proportional to the number of stimulation pulses, including both increases and decreases in conductance. When no stimulation pulses are applied, the device channel conductance remains unchanged, exhibiting non-volatile characteristics.

[0009] The signals applied to the EG and TG terminals are respectively denoted as V EG and V TG , where V EG Responsible for programming ECRAM, including enhancement and inhibition programming of channel conductance; V TG Responsible for gating the gate transistor, V for enhancement and inhibition programming EG , turns on and off the gate of the transistor V TG The magnitude of V EG The channel conductance of ECRAM will be programmed only when V is high. Otherwise, the channel conductance of ECRAM will remain unchanged. EG Positive value, inhibits programming V EG Negative value, turns on the gate of the transistor V TG Meet V TG =V EG +V on , where V on is the turn-on voltage of the gate-gated transistor, while the turn-off voltage of the gate-gated transistor is V TG Meet V TG <V EG .

[0010] In a memory array consisting of ECRAM and gate-select transistors, see Figure 7 The ECRAM drains of the 1T1E cells in each row are connected together, and the EG terminals of the 1T1E cells in each row are connected together. The ECRAM sources of the 1T1E cells in each column are connected together, and the TG terminals of the 1T1E cells in each column are connected together. The ECRAM drains of the 1T1E cells in each row are connected to the bit line selector as the input of external information.

[0011] Based on the memory array composed of the ECRAM and gate-select transistors, the operation method for implementing a fully parallel vector outer product calculation mainly includes the following steps:

[0012] 1) Both input vectors are normalized so that each element is between -1 and 1. They are then quantized into a finite number of states. The number of quantized states is related to the final computational accuracy. A greater number of quantized states results in higher computational accuracy, but this also incurs additional hardware mapping overhead. Because neural network gradient updates are inherently susceptible to noise, the number of quantized states is typically set between 20 and 200.

[0013] 2) Converting the normalized and quantized vector into a random pulse sequence with corresponding numerical probabilities, wherein logic "1" represents that the amplitude of the applied stimulation signal is non-zero, and logic "0" represents that the amplitude of the applied stimulation signal is zero. The corresponding numerical probability refers to the proportion of logic "1" in the entire pulse sequence.

[0014] For 1T1E cell updates, two conditions must be met simultaneously to program the ECRAM. First, the gate-enabling transistor must be on, and second, a stimulus signal must be present at the cell's TG terminal. For random pulses, meeting these two conditions is equivalent to performing a logical AND operation on two pulse trains. Therefore, the ratio of the number of pulses that effectively program the 1T1E cell to the total number of pulse trains is approximately equal to the product of the probabilities of the two pulse trains, and this number increases with the length of the pulse train.

[0015] 3) The two random pulse sequences in step 2) are applied to the EG and TG terminals of the memory array, respectively, matching the vectors of different dimensions with the array dimensions. Based on the principle in step 5), the change in conductance of the ECRAM in the array corresponds to the product of the elements at corresponding positions in the vectors, and the two are directly proportional.

[0016] Therefore, through random pulse programming, the vector outer product calculation is completed in parallel based on the memory array, and the final result is stored in the memory array, which is conducive to the future realization of the reverse propagation calculation of the in-situ acceleration network, and the calculated gradient is accumulated on the conductivity of the device and subsequent in-memory inference acceleration is performed.

[0017] The fully parallel vector outer product calculation operation method based on ECRAM proposed in the present invention has the following advantages:

[0018] The present invention's fully parallel vector outer product calculation operation method, based on the 1T1E unit, can perform in-situ device conductance updates and online training. The calculation results are stored in the device's conductance for subsequent network in-memory calculation acceleration. Compared with traditional device-by-device programming schemes, this avoids additional data transfer, effectively reducing operational complexity and device programming delays. In addition, this scheme can be extended to network training paradigms related to the Hebbian learning rule, that is, the weight update amount is proportional to the product of the input and output before and after the synapse, which can accelerate the training process of related algorithms. Overall, the operation method of the present invention expands the application scope of in-memory calculations, extends traditional vector-matrix multiplication to vector outer product calculations, and provides a new physical acceleration calculation paradigm based on device characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the ECRAM structure and basic electrical operation in an embodiment of the present invention, wherein: 1-drain, 2-channel layer, 3-gate electrolyte layer, 4-passivation layer, 5-gate.

[0020] Figure 2 The ECRAM channel current in the embodiment of the present invention shows excellent linearity as the number of stimulation pulses applied changes, wherein the enhancement pulse and the inhibitory pulse are 10V / 5ms and -7V / 5ms respectively.

[0021] Figure 3 1 and 2 show the retention characteristics of different conductance states of the ECRAM channel in an embodiment of the present invention.

[0022] Figure 4 The 1T1E unit is an integrated unit of ECRAM and gate-select transistor in the embodiment of the present invention. The external stimulus is mainly applied to the EG terminal and the TG terminal. The corresponding signals are V EG and V TG .

[0023] Figure 5 Schematic diagram of the enhanced signal waveform and corresponding conductance change of random pulse update in an embodiment of the present invention.

[0024] Figure 6 Schematic diagram of the suppression signal waveform and corresponding conductance change of random pulse update in an embodiment of the present invention.

[0025] Figure 7 This is a fully parallel vector outer product calculation operation method based on an electrochemical random access memory array in an embodiment of the present invention, including random pulse sequences input from the TG terminal and the EG terminal respectively.

[0026] Figure 8 Schematic diagram of an implementation method for calculating the outer product of vectors containing different positive and negative units in an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following content further illustrates the present invention through specific embodiments in conjunction with the accompanying drawings.

[0028] Figure 1 This is a schematic diagram of the ECRAM structure in this embodiment. 5nm Ti and 25nm Au are used as the source and drain 1, 40nm WO3 is used as the channel layer 2, 120nm LiPON is used as the gate electrolyte layer 3, 20nm SiO2 is used as the passivation layer 4, and 10nm Ti and 200nm Au are used as the gate 5. A stimulus is applied to the gate 5, the source is grounded, and a bias voltage of 0.1V is applied to the drain 1 to monitor the channel conductance state.

[0029] The channel current of the ECRAM in this embodiment changes with the stimulation pulse, such as Figure 2 As shown in the figure, the enhancement pulse is 10V / 5ms and the inhibition pulse is -7V / 5ms. It can be seen that the channel conductance of ECRAM is highly linearly related to the number of stimulation pulses. This physical property is the basis for realizing the subsequent vector outer product.

[0030] like Figure 3 As shown, the conductance in different states all exhibits stable non-volatile characteristics, and the channel conductance state can remain stable after the stimulus is removed.

[0031] Figure 4 The 1T1E unit is an integrated unit of ECRAM and gate-select transistor in this embodiment. Random pulse sequences are applied to the EG and TG terminals in the figure, and the corresponding signals are recorded as V EG and V TG , where V EG Mainly responsible for programming ECRAM, including enhancement and inhibition programming of channel conductance; V TG Mainly responsible for gating the gate-gating transistor, for the enhancement and inhibition programming V EG , turns on and off the gate of the transistor V TG The magnitude of V EG Only then will the channel conductance of the ECRAM be programmed, otherwise the channel conductance of the ECRAM will remain unchanged.

[0032] For enhanced programming of random pulse sequences, such as Figure 5 As shown, the level amplitude of the logic "1" of the EG port is positive, recorded as V EG1 , the level amplitude of logic "0" is 0V; the turn-on amplitude of the gate-select transistor is V TG1 satisfy:

[0033] V TG1 -V EG1 ≥V ON

[0034] Where V ON Indicates the turn-on voltage of the gate-select transistor. Only V EG and V TG When the logic "1" appears at the same time (that is, V EG =V EG1 , V TG =V TG1 ), the channel conductance will increase, in other cases, including V EG =“1”&V TG =“0”,V EG =“0”&V TG = "1" and V EG =“0”&V TG = "0", the channel conductance remains unchanged, so the final conductance change is proportional to the number of logical "1"s that appear simultaneously on both channels, that is:

[0035] ΔG + ∝P EG ×P TG

[0036] where ΔG + represents the increase in channel conductance, P EG and P TG They represent the probability of logic "1" appearing in the input sequence of port EG and port TG respectively.

[0037] For the suppression type programming of random pulse trains, such as Figure 6 As shown, the level amplitude of the logic "1" of the EG port is negative, recorded as V EG1 , the level amplitude of logic "0" is 0V; the turn-on amplitude of the gate-select transistor is V TG1 satisfy:

[0038] V TG1 -V EG1 ≥V ON

[0039] Where V ON Indicates the turn-on voltage of the gate-select transistor. TG = 0V, the gate transistor is turned on; V TG When the gate transistor is negative, it will be turned off. EG A logic "1" and V TG The channel conductance will decrease only when the logic "0" appears at the same time. In other cases, including V EG =“1”&VTG =“1”,V EG =“0”&V TG = "1" and V EG =“0”&V TG = "0", the channel conductance remains unchanged, so the final conductance change is proportional to the number of simultaneous logical "1" and logical "0" states, that is:

[0040] ΔG - ∝P EG ×(1-P TG )

[0041] where ΔG - represents the reduction in channel conductance, P EG and P TG They represent the probability of logic "1" appearing in the input sequences of EG port and TG port respectively.

[0042] Based on the random pulse programming method discussed above, Figure 7 This is a fully parallel random pulse sequence update method based on a 1T1E cell array in this embodiment, which is used to accelerate the cross product between corresponding vectors. Assuming two vectors A and B, whose dimensions are n and m respectively, the corresponding 1T1E array dimension is n×m, including n rows and m columns of 1T1E cells. The two input vectors A and B are normalized so that the values ​​of each element are between -1 and 1, and then quantized into 100 state values, and then converted into a random pulse sequence with corresponding probabilities, which are input into Figure 7 As shown in FIG, the EG end and the TG end have different element signs in the vector, so it is necessary to divide it into four steps to complete the conductance update of the ECRAM in the array in sequence.

[0043] Specifically, if Figure 8 As shown, consider the multiplication of positive elements in A and B, which are respectively denoted as a i and b j , where a i >0,b j >0, respectively converted into probability a i and b j The enhanced random pulse sequence is input to Figure 7 As shown in the EG and TG terminals, and from the previous discussion, it can be seen that the final corresponding position device conductance increase ΔG ij+ satisfy:

[0044] ΔG ij+ ∝a i ×b j

[0045] Then consider the multiplication between the negative elements in A and B, which are respectively denoted as a i and b j , where a i <0,b j <0, respectively converted into probability -a i and -b j The enhanced random pulse sequence is input to Figure 7 As shown in the EG and TG terminals, and from the previous discussion, it can be seen that the final corresponding position device conductance increase ΔG ij+ satisfy:

[0046] ΔG ij+ ∝a i ×b j

[0047] Then consider the multiplication between the negative elements in A and the positive elements in B, which are respectively denoted as a i and b j , where a i <0,b j >0, respectively converted into probability -a i and 1-b j The suppressive random pulse sequence is input to Figure 7 As shown in the EG and TG terminals, and from the previous discussion, it can be seen that the conductivity reduction of the device at the corresponding position is ΔG. ij- satisfy:

[0048] ΔG ij- ∝(-a i )×b j

[0049] Then consider the multiplication between the positive elements in A and the negative elements in B, which are respectively denoted as a i and b j , where a i >0,b j <0, respectively converted into probability a i and 1+b j The suppressive random pulse sequence is input to Figure 7 As shown in the EG and TG terminals, and from the previous discussion, it can be seen that the conductivity reduction of the device at the corresponding position is ΔG. ij- satisfy:

[0050] ΔG ij- ∝a i ×(-b j )

[0051] Finally, all devices on the chip complete the corresponding conductance update, and the change in device conductance is proportional to the original vector outer product result, including the sign of the product is also reflected in the direction of conductance change. That is, through random pulse programming, the vector outer product calculation is completed in parallel, and the final result is stored in the memory array, which is conducive to the future realization of in-situ acceleration of the network's back propagation calculation, and the calculated gradient is accumulated on the device's conductance and subsequent in-memory inference acceleration is performed, effectively improving the energy efficiency and speed of online training of edge devices, and avoiding the frequent transfer of data between storage units and computing modules.

[0052] Finally, it should be noted that the purpose of disclosing the embodiments is to facilitate a further understanding of the present invention. However, those skilled in the art will appreciate that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments; the scope of protection claimed by the present invention shall be determined by the scope defined in the claims.

Claims

1. A fully parallel vector outer product calculation method, implemented based on a memory array consisting of an electrochemical random access memory and its gate-select transistors, characterized in that: The basic unit of the memory array is a 1T1E unit consisting of an electrochemical random access memory and its gate-selecting transistor, wherein the electrochemical random access memory is a three-terminal memory device, the gate of which is connected to the source of the gate-selecting transistor; the drain and gate of the gate-selecting transistor serve as the EG terminal and TG terminal for random pulse signal input respectively; the signals applied to the EG terminal and the TG terminal are respectively denoted as V EG and V TG , where V EG Responsible for programming electrochemical random access memory, including enhancement and inhibition programming of channel conductance; V TG Responsible for gating the gate transistor, V for enhancement and inhibition programming EG , turns on and off the gate of the transistor V TG The magnitude of V EG Only then will the channel conductance of the electrochemical random access memory be programmed, otherwise the channel conductance of the electrochemical random access memory will remain unchanged; in the memory array, the drains of the electrochemical random access memories of the 1T1E cells in each row are connected together and connected to the bit line selector, and the EG ends of the 1T1E cells in each row are connected together; the sources of the electrochemical random access memories of the 1T1E cells in each column are connected together, and the TG ends of the 1T1E cells in each column are connected together; The memory array is used to implement a fully parallel vector outer product calculation by the following operations: 1) Normalize the two input vectors so that the values ​​of their elements are between -1 and 1, and then quantize them into a finite number of state values; 2) converting the normalized and quantized vector into a random pulse sequence with corresponding numerical probabilities, where a logical "1" represents that the amplitude of the applied stimulation signal is non-zero, and a logical "0" represents that the amplitude of the applied stimulation signal is zero. The corresponding numerical probability refers to the proportion of logical "1" in the entire pulse sequence; 3) applying the two random pulse sequences from step 2) to the EG and TG terminals of the memory array, respectively, matching the vectors of different dimensions with the array dimensions, so that the change in conductance of the electrochemical random access memory in the array corresponds to the product of the elements at corresponding positions in the vectors, and the two are in direct proportion; Thus, through random pulse programming, vector outer product calculations are completed in parallel based on the memory array, and the final results are stored in the memory array.

2. The fully parallel vector outer product calculation operation method according to claim 1, wherein: The electrochemical random access memory includes a source electrode, a drain electrode, a channel layer, a gate electrolyte layer, a passivation layer and a gate electrode, wherein the source electrode and the drain electrode are respectively located at the two ends of the channel layer, the gate electrolyte layer is located on the channel layer, and the gate electrolyte layer contains mobile ions; the passivation layer covers the gate electrolyte layer, and the gate is located on the passivation layer.

3. The fully parallel vector outer product calculation operation method according to claim 2, wherein: In the electrochemical random access memory, the material of the channel layer is selected from tungsten oxide, niobium oxide, vanadium oxide, molybdenum oxide, zinc oxide, molybdenum disulfide, IGZO, and ITO; the gate electrolyte layer is a solid electrolyte membrane, and its material is selected from LiPON, LATP, and PSG; the passivation layer material is selected from SiO2, Al2O3, Si3N4, HfO2, and Ta2O5; the materials of the source, drain, and gate are selected from Ti, Cr, Sc, Al, Pd, Au, Pt, W, TiN, and TaN.

4. The fully parallel vector outer product calculation operation method according to claim 1, wherein: The gate selection transistor adopts a silicon-based NMOS planar device, a silicon-based FinFET structure device, a metal semiconductor oxide-based thin film transistor or a field effect transistor based on a two-dimensional material channel.

5. The fully parallel vector outer product calculation operation method according to claim 1, wherein: Step 1) The quantized state value is set to 20-200.

6. The fully parallel vector outer product calculation operation method according to claim 1, wherein: In step 3), for an n-dimensional vector A and an m-dimensional vector B, the corresponding memory array dimensions are n×m, i.e., it includes n rows and m columns of 1T1E units; the two random pulse sequences converted from vectors A and B are applied to the EG and TG terminals of the memory array, respectively.

7. The fully parallel vector outer product calculation operation method according to claim 1, wherein: Enhanced Programming V EG Positive value, inhibits programming V EG Negative value, turns on the gate of the transistor V TG Meet V TG =V EG +V on , where V on is the turn-on voltage of the gate-gated transistor, while the turn-off voltage of the gate-gated transistor is V TG Meet V TG <V EG .

Images