Arbitrary Bit Width Conversion Method, Device, Computer Equipment and Storage Medium

Abstract

The present invention relates to the technical field of data processing, and discloses a method, apparatus, computer device and storage medium for arbitrary bit-width conversion. The method includes: determining the input bit-width, output bit-width, number of consecutive data inputs, data insertion length, and data deletion length of the data to be processed; determining the depth of the first-in-first-out queue and the length of the shift register group according to the input bit-width, output bit-width, and number of consecutive data inputs, and establishing a corresponding first-in-first-out queue and shift register group; inputting the data to be processed into the first-in-first-out queue, reading the data to be processed in the first-in-first-out queue through the shift register group, and performing data insertion or deletion operations on the data to be processed according to the size relationship between the input bit-width and the output bit-width, so as to convert the bit-width of the data to be processed into output data with the output bit-width. This enables bit-width conversion and data insertion and deletion to be performed simultaneously.

Description

Technical Field

[0001] The present invention relates to the field of data processing, and particularly to a method, apparatus, computer device and storage medium for arbitrary bit-width conversion. Background Art

[0002] In digital integrated circuit design, especially in the process of data stream processing, bit-width conversion of data and deletion / insertion of some data in the data stream are often involved. Typically, such as preprocessing and postprocessing of Quasi-Cyclic Low Density Parity Check (QC-LDPC) coding. The preprocessing needs to fill the input data length to the standard information bit length, and at the same time convert the input bit-width to the block size of the QC-LDPC code, and then hand it over to the coding core to complete the coding. The postprocessing can convert the block size back to the output bit-width required externally and delete the bits filled in the information field to save storage or bandwidth. If the encoder is applicable to NAND Flash, the redundancy size (Spare Size) of the NAND Flash can be adapted by filling at the head of the parity bits according to the page size of the NAND Flash.

[0003] Traditional methods generally can only complete bit-width conversion and cannot perform data insertion and deletion, or use the ping-pong method to complete bit-width conversion, which occupies more logic / storage resources or performs input / output judgment every clock cycle, with complex control interaction and high latency. Summary of the Invention

[0004] In a first aspect, the present application provides an arbitrary bit-width conversion method, including:

[0005] Determine the input bit-width, output bit-width, number of consecutive data inputs, data insertion length, and data deletion length of the data to be processed;

[0006] According to the input bit-width, the output bit-width, and the number of consecutive data inputs, determine the depth of the first-in-first-out queue and the length of the shift register group, and establish the corresponding first-in-first-out queue and shift register group;

[0007] When a data insertion operation is required, the data to be processed is input into the first-in-first-out queue, the data to be processed in the first-in-first-out queue is read through the shift register group, and an insertion operation is performed on the data to be processed according to the input bit-width and the data insertion length;

[0008] When a data deletion operation is required, the data to be processed is input into the first-in-first-out queue, the data to be processed is read through the shift register group, and a deletion operation is performed on the data to be processed according to the size relationship between the input bit width and the output bit width and the data deletion length, and the output data with the bit width of the data to be processed converted to the output bit width is obtained.

[0009] Further, the performing an insertion operation on the data to be processed according to the input bit width and the data insertion length includes:

[0010] Determining an insertion position for data insertion;

[0011] Determining the number of consecutive data insertions according to the input bit width and the data insertion length, and performing the corresponding number of data insertion operations when the insertion position reaches the head of the first-in-first-out queue.

[0012] Further, after determining the insertion position for data insertion, it further includes:

[0013] Determining whether the current head of the input-output queue is the insertion position. If not, performing a data reading operation until the current head data is the insertion position.

[0014] Further, the performing a deletion operation on the data to be processed according to the data deletion length includes:

[0015] Determining a deletion position for the data to be deleted;

[0016] If the deletion position is at the head of the shift register group, deleting the data of the deletion length.

[0017] Further, after determining the deletion position for the data to be deleted, it further includes:

[0018] If the deletion position is not at the head of the shift register group, performing a data writing operation until the head of the current data stream is the deletion position.

[0019] Further, the determining the depth of the first-in-first-out queue and the length of the shift register group according to the input bit width, the output bit width, and the number of consecutive data inputs includes:

[0020] Calculating the depth of the first-in-first-out queue and the length of the shift register group according to the following expressions;

[0021]

[0022] Wherein, D is the depth of the FIFO queue, L is the length of the shift register bank, W1 is the input bit width, W2 is the output bit width, and N is the number of consecutive data inputs.

[0023] Further, the converting the bit width of the data to be processed into output data with the output bit width includes:

[0024] According to the output bit width, control the amount of data read in a single data read so that the amount of data read in a single data read is equal to the output bit width.

[0025] In a second aspect, the present application further provides an arbitrary bit width conversion device, including:

[0026] A data processing module, configured to determine the input bit width, output bit width, number of consecutive data inputs, data insertion length, and data deletion length of the data to be processed;

[0027] An initialization module, configured to determine the depth of the FIFO queue and the length of the shift register bank according to the input bit width, the output bit width, and the number of consecutive data inputs, and establish a corresponding FIFO queue and shift register bank;

[0028] A data insertion module, configured to, when a data insertion operation needs to be performed, input the data to be processed into the FIFO queue, read the data to be processed in the FIFO queue through the shift register bank, and perform an insertion operation on the data to be processed according to the input bit width and the data insertion length;

[0029] A data deletion module, configured to, when a data deletion operation needs to be performed, input the data to be processed into the FIFO queue, read the data to be processed through the shift register bank, and perform a deletion operation on the data to be processed according to the magnitude relationship between the input bit width and the output bit width and the data deletion length, and convert the data to be processed with the completed bit width into output data with the output bit width.

[0030] In a third aspect, the present application further provides a computer device, including a processor and a memory, where the memory stores a computer program, and when the computer program runs on the processor, it executes the arbitrary bit width conversion method described above.

[0031] In a fourth aspect, the present application further provides a readable storage medium, which stores a computer program, and when the computer program runs on a processor, it executes the arbitrary bit width conversion method described above.

[0032] The present invention relates to the technical field of data processing, and discloses a method for converting any bit width. The method includes: determining the input bit width, output bit width, number of consecutive data inputs, data insertion length, and data deletion length of the data to be processed; determining the depth of the first-in-first-out queue and the length of the shift register group according to the input bit width, output bit width, and number of consecutive data inputs, and establishing a corresponding first-in-first-out queue and shift register group; when a data insertion operation is required, the data to be processed is input into the first-in-first-out queue, and an insertion operation is performed on the data to be processed according to the input bit width and the data insertion length; when a data deletion operation is required, the data to be processed is read through the shift register group, and a deletion operation is performed on the data to be processed according to the size relationship between the input bit width and the output bit width and the data deletion length, and the output data with the bit width of the data to be processed converted to the output bit width is obtained. This enables the bit width conversion and data insertion and deletion to be executed simultaneously, improving the work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the protection scope of the present invention. In each drawing, similar components are numbered similarly.

[0034] Figure 1 FIG. shows a schematic flowchart of a method for converting any bit width according to an embodiment of the present application;

[0035] Figure 2 FIG. shows a schematic diagram of the data flow direction according to an embodiment of the present application;

[0036] Figure 3 FIG. shows a schematic diagram of a bit width conversion according to an embodiment of the present application;

[0037] Figure 4 FIG. shows a schematic diagram of the state machine change according to an embodiment of the present application;

[0038] Figure 5 FIG. shows another schematic diagram of the state machine change according to an embodiment of the present application;

[0039] Figure 6 FIG. shows a schematic diagram of the data insertion and data deletion process according to an embodiment of the present application;

[0040] Figure 7 FIG. shows a schematic diagram of the structure of an arbitrary bit width conversion device according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0042] Generally, the components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0043] In the following text, the terms "including", "having" and their cognates that can be used in various embodiments of the present invention are only intended to represent specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be construed as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0044] In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0045] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the various embodiments of the present invention belong. The terms (such as those defined in a general-use dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present invention.

[0046] This application is applied to the bit-width conversion of data involved in the data stream processing process, as well as the deletion and insertion operations of some data in the data stream. This application determines the input bit-width, output bit-width, number of consecutive data inputs, data insertion length, and data deletion length of the data to be processed; according to the input bit-width, the output bit-width, and the number of consecutive data inputs, determines the depth of the first-in-first-out queue and the length of the shift register group, and establishes the corresponding first-in-first-out queue and shift register group; the data to be processed is input into the first-in-first-out queue, the shift register group reads the data to be processed in the first-in-first-out queue, and according to the input bit-width and the data insertion length, performs an insertion operation on the data to be processed; according to the data deletion length, performs a deletion operation on the data to be processed, and according to the size relationship between the input bit-width and the output bit-width, converts the bit-width of the data to be processed into output data with the output bit-width. At the same time, it realizes bit-width conversion and data insertion and deletion operations, thereby saving time and improving work efficiency.

[0047] Next, specific embodiments are used to illustrate the technical solution of this application.

[0048] Embodiment 1

[0049] As Figure 1 shown, any bit-width conversion method in this embodiment includes:

[0050] Step S100, determine the input bit-width, output bit-width, number of consecutive data inputs, data insertion length, and data deletion length of the data to be processed.

[0051] The technical solution of this embodiment is applied to the process of data stream processing, especially involving bit-width conversion and deletion and insertion operations of some data in the data stream. Among them, the input bit-width and the output bit-width are determined according to the front-back relationship of the data stream processing. The processing bit-width of the front-stage module corresponds to the input bit-width, and the processing bit-width of the back-stage module corresponds to the output bit-width. When the input bit-width is less than the output bit-width, bit-width expansion is required. When the input bit-width is greater than the output bit-width, bit-width reduction is required.

[0052] When processing data, in order to meet some processing conditions, some data filling operations are required. For example, in scenarios where the parity-check matrix stipulates the information-bit length and other scenarios with requirements for data formats, data filling is required for the data. Therefore, according to the data formats that need to be adapted, the corresponding data insertion length is obtained. Similarly, data insertion usually inserts a string of meaningless characters. For example, if a string of "0" is inserted, then after the data processing is completed, this string of "0" also needs to be deleted, so there is a data deletion length.

[0053] Specifically, data stream processing generally includes preprocessing and postprocessing. When preprocessing the data to be processed, the data needs to convert the input bit width into the output bit width. At the same time, in order to make the data match the corresponding data format, data needs to be inserted into the data to be processed so that the data format meets the processing requirements. After the data processing is completed, it enters the postprocessing stage. At this time, in addition to bit width conversion, the data inserted during preprocessing also needs to be deleted.

[0054] Specifically, as Figure 2 shown, the input with input bit width W1 enters the input first-in-first-out (FIFO) queue, and then is processed by the FIFO queue and input into the shift register bank. After being processed by the shift register bank, it is input to the target position with a bit width of W2. For the two application scenarios of data preprocessing and postprocessing, the flow direction and processing order of the data stream are the same as those in Figure 2 this.

[0055] Step S200: Determine the depth of the first-in-first-out queue and the length of the shift register bank according to the input bit width, the output bit width, and the number of consecutive data inputs, and establish the corresponding first-in-first-out queue and shift register bank.

[0056] In this embodiment, whether it is the scenario where the input bit width is greater than the output bit width or the opposite scenario, when the data stream executes the above two steps, it will be processed through a first-in-first-out queue and a shift register bank to complete the read and write operations of the data stream, as well as the above-mentioned bit width conversion and data insertion and deletion operations. Different bit widths have different requirements for the parameters of the above-mentioned first-in-first-out queue and shift register bank. That is, when performing the above data processing, data overflow should not occur in the first-in-first-out queue and the shift register bank. Therefore, it is necessary to calculate the required depth D of the first-in-first-out queue and the required length L of the shift register bank according to the input bit width and the output bit width respectively.

[0057] Specifically, the calculation expressions for the depth and length are as follows:

[0058]

[0059] In the formula, D is the depth of the first-in-first-out queue, L is the length of the shift register bank, W1 is the input bit width, W2 is the output bit width, and N is the number of consecutive data inputs.

[0060] It can be seen from the above formula that for different sizes of the input bit width and the output bit width, the calculated values of D and L will also be different.

[0061] Taking the LDPC encoding process in the NAND Flash controller as an example, the single data stream for encoding contains 32,748 bits of user data, 96 bits of Flash Metadata (Fmeta), and 32 bits of Cyclic Redundancy Check (CRC). The data bit width is 32 bits. Preprocessing requires filling 32 bits of "0" at the head of the single data stream to adapt to the information bit length of 32,928 bits specified by the parity-check matrix, and at the same time converting the 32-bit width to 147 bits.

[0062] Then during the preprocessing:

[0063] If there is no overflow, the depth D of the first-in-first-out queue is:

[0064]

[0065] The length L of the shift register group is:

[0066]

[0067] Similarly, in the post-processing process, post-processing needs to remove the 32 bits of "0" at the head, and at the same time fill 146 bits of "0" in front of the parity bits to adapt to the page size of the NAND Flash medium, and at the same time convert the 147-bit width to 32 bits. Therefore, the input bit width and output bit width of the post-processing are exactly the opposite of those in the preprocessing. If there is no overflow, the depth D of the first-in-first-out queue is:

[0068]

[0069] The length L of the shift register group is:

[0070] L = W1 + W2 = 147 + 32 = 179;

[0071] It should be noted here that W1 and W2 in the post-processing are opposite to those in the preprocessing.

[0072] As can be seen from the above formula, for different size relationships of W1 and W2, corresponding calculation operations are performed to determine the depth of the first-in-first-out queue and the length of the shift register group required for processing, ensuring that there is no overflow during subsequent processing and ensuring the safety and stability of the data processing process.

[0073] Step S300, when a data insertion operation is required, the data to be processed is input into the first-in-first-out queue, the data to be processed in the first-in-first-out queue is read through the shift register group, and an insertion operation is performed on the data to be processed according to the input bit width and the data insertion length;

[0074] When performing data stream processing operations, the data to be processed first enters a first-in, first-out (FIFO) queue and is then read by a shift register bank. When the data passes through the FIFO queue and reaches the shift register bank, some data insertion processing operations are performed. Depending on the actual processing content, there are a preprocessing stage and a postprocessing stage. Regardless of the processing stage, the insertion position of the data insertion is determined; according to the input bit width and the data insertion length, the number of consecutive data insertions is determined, and when the insertion position reaches the head of the FIFO queue, the corresponding number of data insertion operations are performed.

[0075] When performing the preprocessing step, before data insertion, the data first exists in the FIFO queue. According to the nature of the FIFO queue, the data is sequentially output from the head of the queue to the subsequent shift register bank. Therefore, at this time, it is first determined whether the current head of the queue is the position where data needs to be inserted. If the current head of the queue is not the position where data needs to be inserted, a data read operation is performed, and the data at the head of the queue is removed from the queue one by one until the head of the current data stream is the data insertion position. At this time, the data insertion operation can start. When data is inserted, the inserted data is generated at the head of the queue. It can be understood that the maximum amount of data inserted at one time is limited by the input bit width. Therefore, the maximum inserted data amount is the same as the input bit width. So, according to the size of the input bit width, the number of data insertions required can be determined. After the insertion is completed, the FIFO queue continues to perform the read operation until all the data is removed from the FIFO queue and reaches the shift register bank, thereby completing the data insertion operation during the removal process.

[0076] In this embodiment, the above insertion process can be implemented by a state machine, specifically as Figure 4 shown. The initial state is the starting state, triggered by a one-step reset signal. When the FIFO is not empty, it enters the read state or the insertion state. It can be understood that it only enters the insertion state when the head is the position where data needs to be inserted. At this time, if W1 is less than W2, then in these two states, it is necessary to continuously read or insert times and then enter the waiting state. Otherwise, it only needs to read or insert once and enter the waiting state. In the waiting state, after waiting for a certain number of clock cycles, it is determined whether the read or insert operation is completed. If it is completed, it enters the end state. Otherwise, it returns to the read state or the insertion state. After entering the end state, read and insert completion signals are given and it returns to the initial state to wait for the next data stream processing.

[0077] Specifically, still taking the example in step S200 as an illustration, at this time, in order to adapt to the information bit length specified by the parity check matrix, the preprocessing needs to fill 32 bits of "0" at the head of a single data stream. Then, in this step, it will first determine that 32 bits of "0" need to be filled and where this part of the data needs to be filled. Since in this example, 32 bits of "0" are filled at the head, these data will be inserted at the head of the queue at the beginning. After the insertion is completed, the corresponding data reading operation will be performed. Among them, the input bit width is 32 bits, so the data filling operation can be completed through one insertion.

[0078] The principle of the post-processing operation is similar to that of the preprocessing. Continuing the above example, when in the post-processing operation, it will be necessary to remove 32 bits of "0" at the head and fill 146 bits of "0" in front of the parity bits to adapt to the page size of the NAND Flash medium. Therefore, the data insertion size is 146 bits, and the position is in the middle of the data stream. And at this time, the input bit width is 147, so the insertion operation can be completed within one insertion. After the insertion is completed, the reading operation starts until the data reading is completed. In the above example, two insertions are performed, the sizes of the inserted data are different, and the corresponding processing is also different.

[0079] Step S400, when a data deletion operation needs to be performed, the data to be processed is input into the first-in-first-out queue, the data to be processed is read through the shift register group, a deletion operation is performed on the data to be processed according to the data deletion length, and the bit width of the data to be processed is converted into output data with the output bit width according to the size relationship between the input bit width and the output bit width. For the deletion operation, first, it is necessary to determine the deletion position of the data to be deleted; if the deletion position is at the head of the shift register group, then delete the data of the deletion length. If the deletion position is not at the head of the shift register group, then a data write operation is performed until the head of the current data stream is the deletion position.

[0080] First, the principle of bit width conversion is described. As Figure 3 shown, denote the effective data length K in the shift register group. If W1 < W2, the shift logic is as Figure 3 shown. Assume that at time i - 2, K = W2 - 1, and the input data length at this time is W1. Then at time i - 1, K = W2 + W1 - 1. If no write operation occurs at time i and the condition K ≥ W2 is satisfied, then the shift-out operation of the shift register group is triggered, and the shift-out length is W2. At this time, K = W1 - 1. At time i + 1, the shift-in operation continues until at a certain moment no write operation occurs and K ≥ W2, then the shift-out operation is triggered, that is, multiple writes trigger one shift-out. If W1 > W2, the shift logic is the same as when W1 < W2, except that one write will trigger multiple shift-outs.

[0081] In this embodiment, a state machine can be used to implement the deletion operation. Specifically, as Figure 5 shown, it starts from the initial state, which is triggered by an asynchronous reset signal. After detecting that the shift register group is ready with data, it determines whether data needs to be discarded from the head. If so, it jumps to the deletion state; if not, it jumps to the write state. The write state will write the data to be written into the shift register completely according to the input bit width. The deletion state will skip the characters to be deleted according to the deletion length and write the remaining valid bits into the shift register group, discarding the rest. If there are multiple data to be deleted in a single data stream, the state of the state machine will migrate repeatedly between the deletion state and the write state until the processing of the word data stream is completed, and then it will enter the end state. After giving the signal that the word data stream processing is completed in the end state, it jumps back to the initial state.

[0082] Specifically, the corresponding deletion operation is carried out following the insertion operation in step 300. During preprocessing, only data needs to be written into the shift register group, and no data deletion operation is required. Therefore, only write operations need to be performed in the preprocessing state.

[0083] If in the post-processing state, there are W1 = 147 and W2 = 32. At this time, the bit width written each time is 147. So for each write, K is detected 5 times. If K≥32, a shift-out is triggered, and 32 bits of data are shifted out each time, thus achieving a reduction in bit width. At the same time, in the post-processing state, the 32-bit "0" filled during preprocessing also needs to be removed. First, it is judged whether the data to be deleted is at the head of the data stream. If so, a 32-bit data deletion operation is performed. After deletion, the remaining 114 valid bits are written into the shift register group. If the head of the data stream is not the deletion position, 146 bits of valid data are directly written until the queue position where the deletion operation needs to be performed is reached, and then the corresponding operations as described above are carried out to delete the corresponding data and write the remaining valid data into the shift register group. In this way, while the bit width conversion is completed, the data deletion operation is also executed.

[0084] Similarly, if there are W1 = 32 and W2 = 147, the bit width written into the shift register group each time is 32. Since W2 / W1 = 4.5, K is detected once every 4 writes. If K≥147, a shift-out is triggered, and 147-bit wide data is shifted out each time, thus achieving an increase in bit width. And because the length of the data to be deleted is known, it does not affect the execution of the data deletion operation. As long as the corresponding length of data is deleted, the data deletion operation is completed.

[0085] Among them, as Figure 6As shown in the figure, it is a set of pre - processing and post - processing processes for steps S300 and S400, including the change processes of data insertion, data deletion, and bit - width conversion. When the data to be processed flows in, through pre - processing, data insertion and bit - width conversion are performed to obtain the pre - processed data. After the data processing is completed, when post - processing is executed, corresponding data insertion, data deletion, and bit - width conversion operations are performed again to obtain the post - processed data. In the whole process, data insertion, data deletion, and bit - width conversion are completed synchronously with the data transfer. It can be understood that the first - in - first - out queue and the shift register group are mainly used for the read - write operations of the data stream. In this embodiment, during the read - write operations of the data stream, operations of data insertion, data deletion, and bit - width conversion are incorporated, so that these steps can be perfectly integrated, rather than first performing bit - width conversion, then data insertion and deletion, or performing data insertion and deletion first and then bit - width conversion. These two steps can be carried out simultaneously, reducing resource occupancy and thus increasing work efficiency.

[0086] Embodiment 2

[0087] As Figure 7 shown, this embodiment also provides an arbitrary bit - width conversion device, including:

[0088] A data processing module 10, configured to determine the input bit - width, output bit - width, number of consecutive data inputs, data insertion length, and data deletion length of the data to be processed;

[0089] An initialization module 20, configured to determine the depth of the first - in - first - out queue and the length of the shift register group according to the input bit - width, the output bit - width, and the number of consecutive data inputs, and establish a corresponding first - in - first - out queue and shift register group;

[0090] A data insertion module 30, configured to, when a data insertion operation is required, input the data to be processed into the first - in - first - out queue, read the data to be processed in the first - in - first - out queue through the shift register group, and perform an insertion operation on the data to be processed according to the input bit - width and the data insertion length;

[0091] A data deletion module 40, configured to, when a data deletion operation is required, input the data to be processed into the first - in - first - out queue, read the data to be processed through the shift register group, and perform a deletion operation on the data to be processed according to the size relationship between the input bit - width and the output bit - width and the data deletion length, and convert the bit - width of the completed data to be processed into output data with the output bit - width.

[0092] The present application also provides a computer device, including a processor and a memory. The memory stores a computer program, and when the computer program runs on the processor, it executes the arbitrary bit-width conversion method described above.

[0093] The present application also provides a readable storage medium that stores a computer program, and when the computer program runs on a processor, it executes the arbitrary bit-width conversion method described above.

[0094] In several embodiments provided by the present application, it should be understood that the disclosed device and method can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and structure diagrams in the drawings show the possible architectures, functions, and operations of the device, method, and computer program product according to multiple embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the blocks may occur in a different order than marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the structure diagram and / or flowchart, as well as the combination of blocks in the structure diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0095] In addition, in each embodiment of the present invention, each functional module or unit may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0096] If the function is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs, etc., which can store program codes.

[0097] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, and all should be covered within the protection scope of the present invention.

Claims

1. A method for converting any bit width, characterized in that, Including: Determine the input bit width, output bit width, number of consecutive data inputs, data insertion length, and data deletion length of the data to be processed; According to the input bit width, the output bit width, and the number of consecutive data inputs, determine the depth of the first-in-first-out queue and the length of the shift register group, and establish the corresponding first-in-first-out queue and shift register group; When a data insertion operation is required, the data to be processed is input into the first-in-first-out queue, the data to be processed in the first-in-first-out queue is read through the shift register group, and an insertion operation is performed on the data to be processed according to the input bit width and the data insertion length; When a data deletion operation is required, the data to be processed is input into the first-in-first-out queue, the data to be processed is read through the shift register group, a deletion operation is performed on the data to be processed according to the data deletion length, and according to the size relationship between the input bit width and the output bit width, the bit width of the data to be processed is converted into output data with the output bit width; The determining the depth of the first-in-first-out queue and the length of the shift register group according to the input bit width, the output bit width, and the number of consecutive data inputs includes: Calculating the depth of the first-in-first-out queue and the length of the shift register group according to the following expression; In the formula, D is the depth of the first-in-first-out queue, L is the length of the shift register group, W1 is the input bit width, W2 is the output bit width, and N is the number of consecutive data inputs.

2. The arbitrary bit-width conversion method according to claim 1, characterized in that, The performing an insertion operation on the data to be processed according to the input bit width and the data insertion length includes: Determine the insertion position of the data insertion; According to the input bit width and the data insertion length, determine the number of consecutive data insertions, and when the insertion position reaches the head of the first-in-first-out queue, perform the corresponding number of data insertion operations.

3. The arbitrary bit-width conversion method according to claim 2, wherein After determining the insertion position of the data insertion, it further includes: Determine whether the current head of the input-output queue is the insertion position. If not, perform a data reading operation until the current head data is the insertion position.

4. The arbitrary bit-width conversion method according to claim 1, wherein The performing a deletion operation on the data to be processed according to the data deletion length includes: Determine the deletion position of the data to be deleted; If the deletion position is at the head of the shift register group, delete the data of the deletion length.

5. The arbitrary bit-width conversion method according to claim 4, wherein After determining the deletion position of the data to be deleted, it further includes: If the deletion position is not at the head of the shift register group, perform a data writing operation until the head of the current data stream is the deletion position.

6. The arbitrary bit-width conversion method according to claim 1, characterized in that, The converting the bit width of the data to be processed into output data with the output bit width includes: If the input bit width is greater than the output bit width, after performing a data reading operation once, output the data to be processed read in sequence according to the output bit width; If the input bit width is less than the output bit width, perform multiple data reading operations until the length of the data to be processed read is the same as the output bit width, and then output the data to be processed.

7. An arbitrary bit-width conversion device, characterized in that, Including: A data processing module, configured to determine the input bit width, output bit width, number of consecutive data inputs, data insertion length, and data deletion length of the data to be processed; An initialization module, configured to determine the depth of the first-in-first-out queue and the length of the shift register group according to the input bit width, the output bit width, and the number of consecutive data inputs, and establish a corresponding first-in-first-out queue and shift register group; A data insertion module, configured to, when a data insertion operation needs to be performed, input the data to be processed into the first-in-first-out queue, read the data to be processed in the first-in-first-out queue through the shift register group, and perform an insertion operation on the data to be processed according to the input bit width and the data insertion length; A data deletion module, configured to, when a data deletion operation needs to be performed, input the data to be processed into the first-in-first-out queue, read the data to be processed through the shift register group, and perform a deletion operation on the data to be processed according to the size relationship between the input bit width and the output bit width and the data deletion length, and convert the bit width of the completed data to be processed into output data with the output bit width; The determining the depth of the first-in-first-out queue and the length of the shift register group according to the input bit width, the output bit width, and the number of consecutive data inputs includes: Calculating the depth of the first-in-first-out queue and the length of the shift register group according to the following expression; In the formula, D is the depth of the first-in-first-out queue, L is the length of the shift register group, W1 is the input bit width, W2 is the output bit width, and N is the number of consecutive data inputs.

8. A computer device, characterized in that, It includes a processor and a memory, and the memory stores a computer program, and when the computer program runs on the processor, it executes the arbitrary bit width conversion method according to any one of claims 1 to 6.

9. A readable storage medium, characterized in that, It stores a computer program, and when the computer program runs on the processor, it executes the arbitrary bit width conversion method according to any one of claims 1 to 6.

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