Pixel circuit, driving method and display panel

Abstract

The present application provides a pixel circuit, a driving method, and a display panel. The pixel circuit includes a driving subcircuit, a first energy storage subcircuit, a second energy storage subcircuit, a data writing subcircuit, a first compensation control subcircuit, a second compensation control subcircuit, a first initialization subcircuit, and a first light-emitting control subcircuit. The sampling path includes a first initialization subcircuit, a first compensation control subcircuit, a second compensation control subcircuit, and a driving subcircuit. The writing path includes a data writing subcircuit and a second energy storage subcircuit for implementing data voltage writing. In the present application, sampling and writing are implemented through different paths, so that the time for threshold voltage compensation is not limited by the time for data voltage writing, thereby improving the image quality at high frequency and high resolution.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to a pixel circuit, a driving method, and a display panel. Background Art

[0002] Active-matrix organic light-emitting diodes (AMOLEDs) are the leading display technology of the future, thanks to their high image quality, fast response time for moving images, low power consumption, wide viewing angles, and ultra-thin design. In current AMOLED panel driver circuits, the pixel circuitry consists of four phases: reset, sampling, writing, and emitting light. A common approach is to perform sampling and writing simultaneously. However, as display products increase in size and form factors, simultaneous sampling and synchronization results in insufficient sampling time at high frequencies and high resolutions, compromising image quality. Summary of the Invention

[0003] The present application provides a pixel circuit, a driving method and a display panel, which realize sampling and writing through different paths. The time of threshold voltage compensation is not limited by the time of data voltage writing, so that the image quality is better at high frequency and high resolution.

[0004] In a first aspect, the present application provides a pixel circuit for driving a light-emitting device to emit light, comprising: a driving subcircuit, a first energy storage subcircuit, a second energy storage subcircuit, a data writing subcircuit, a first compensation control subcircuit, a second compensation control subcircuit, a first initialization subcircuit, and a first light-emitting control subcircuit. The control terminal of the driving subcircuit is electrically connected to a first node, the first terminal of the driving subcircuit is electrically connected to a fourth node, and the second terminal of the driving subcircuit is electrically connected to a third node, for controlling the generation of a driving current for the light-emitting device under the control of the potential of the first node. The first terminal of the first energy storage subcircuit is electrically connected to a second node, the second terminal of the first energy storage subcircuit is electrically connected to a fifth node, and the first energy storage subcircuit is configured to store electrical energy. The first terminal of the second energy storage subcircuit is electrically connected to the fifth node, the second terminal of the second energy storage subcircuit is electrically connected to the third node, and the second energy storage subcircuit is configured to store electrical energy. The control terminal of the data writing subcircuit is electrically connected to the third scan line, the first terminal of the data writing subcircuit is electrically connected to the data line, and the second terminal of the data writing subcircuit is electrically connected to the second node, for writing the data voltage provided by the data line to the second node under the control of the third scan line. The control terminal of the first compensation control subcircuit is electrically connected to the second scan line, the first terminal of the first compensation control subcircuit is electrically connected to the fifth node, and the second terminal of the first compensation control subcircuit is electrically connected to the first node, for controlling the connection and disconnection between the first node and the fifth node under the control of the second scan line. The control terminal of the second compensation control subcircuit is electrically connected to the first scan line, the first terminal of the second compensation control subcircuit is electrically connected to the first node, and the second terminal of the first compensation control subcircuit is electrically connected to the fourth node, for controlling the connection and disconnection between the first node N1 and the fourth node under the control of the first scan line. The control terminal of the first initialization subcircuit is electrically connected to the second scan line, the first terminal of the first initialization subcircuit is electrically connected to the reference voltage line, and the second terminal of the first initialization subcircuit is electrically connected to the fifth node, for writing the reference voltage provided by the reference voltage line to the fifth node under the control of the second scan line. The control terminal of the first light-emitting control subcircuit is electrically connected to the first light-emitting control line, the first terminal of the first light-emitting control subcircuit is electrically connected to the second node, and the second terminal of the first light-emitting control subcircuit is electrically connected to the first node, for controlling the connection and disconnection between the first node and the second node under the control of the first light-emitting control line. The light-emitting device is arranged between the first voltage terminal and the fourth node, or the light-emitting device is arranged between the second voltage terminal and the third node.

[0005] In one possible embodiment, the pixel circuit further includes a second light-emitting control subcircuit, wherein a control terminal of the second light-emitting control subcircuit is electrically connected to the first light-emitting control line. When the light-emitting device is disposed between the first voltage terminal and the fourth node, a first terminal of the second light-emitting control subcircuit is electrically connected to the cathode of the light-emitting device, and a second terminal of the second light-emitting control subcircuit is electrically connected to the fourth node, for controlling the connection and disconnection between the cathode of the light-emitting device and the fourth node under the control of the first light-emitting control line. When the light-emitting device is disposed between the second voltage terminal and the third node, a first terminal of the second light-emitting control terminal is electrically connected to the first voltage terminal, and a second terminal of the second light-emitting control terminal is electrically connected to the fourth node, for controlling the connection and disconnection between the first voltage terminal and the fourth node under the control of the first light-emitting control line.

[0006] In one possible embodiment, the pixel circuit further includes a third light-emitting control subcircuit, wherein a control terminal of the third light-emitting control subcircuit is electrically connected to a second light-emitting control line, and a first terminal of the third light-emitting control subcircuit is electrically connected to a third node. When the light-emitting device is disposed between the first voltage terminal and the fourth node, a second terminal of the third light-emitting control subcircuit is electrically connected to the second voltage terminal, for controlling connection and disconnection between the third node and the second voltage terminal under control of the second light-emitting control line. When the light-emitting device is disposed between the second voltage terminal and the third node, a second terminal of the third light-emitting control subcircuit is electrically connected to an anode of the light-emitting device, for controlling connection and disconnection between the third node and the anode of the light-emitting device under control of the second light-emitting control line.

[0007] In one possible embodiment, the pixel circuit further includes a second initialization sub-circuit, wherein the control end of the second initialization sub-circuit is electrically connected to the fourth scan line, the first end of the second initialization sub-circuit is electrically connected to the third node, and the second end of the second initialization sub-circuit is electrically connected to the initial voltage end, and is used to write the initial voltage received from the initial voltage end into the third node under the control of the fourth scan line.

[0008] In one possible embodiment, the pixel circuit further includes a third initialization subcircuit, wherein a control terminal of the third initialization subcircuit is electrically connected to a fourth scan line. When the light-emitting device is disposed between the first voltage terminal and the fourth node, a first terminal of the third initialization subcircuit is electrically connected to the cathode of the light-emitting device, and a second terminal of the third initialization subcircuit is electrically connected to the compensation voltage line, for writing a compensation voltage received from the compensation voltage terminal to the cathode of the light-emitting device under control of the fourth scan line. When the light-emitting device is disposed between the second voltage terminal and the third node, a first terminal of the third initialization subcircuit is electrically connected to the anode of the light-emitting device, and a second terminal of the third initialization subcircuit is electrically connected to the initial voltage line, for writing an initial voltage received from the initial voltage terminal to the anode of the light-emitting device under control of the fourth scan line.

[0009] In one possible implementation, the driving subcircuit includes a first transistor, the first light-emission control subcircuit includes a second transistor, the first initialization subcircuit includes a third transistor, the first compensation control subcircuit includes a fourth transistor, the second compensation control subcircuit includes a fifth transistor, the first energy storage subcircuit includes a first capacitor, and the second energy storage subcircuit includes a second capacitor. The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the third node. The control electrode of the second transistor is electrically connected to the third scan line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second node. The control electrode of the third transistor is electrically connected to the second scan line, the first electrode of the third transistor is electrically connected to the reference voltage line, and the second electrode of the third transistor is electrically connected to the fifth node. The control electrode of the fourth transistor is electrically connected to the second scan line, the first electrode of the fourth transistor is electrically connected to the fifth node, and the second electrode of the fourth transistor is electrically connected to the first node. The control electrode of the fifth transistor is electrically connected to the first scan line, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the fourth node. The first electrode of the first capacitor is electrically connected to the second node, the second electrode of the first capacitor is electrically connected to the fifth node, the first electrode of the second capacitor is electrically connected to the fifth node, and the second electrode of the second capacitor is electrically connected to the third node.

[0010] In one possible embodiment, the second light-emission control subcircuit includes a sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the first light-emission control line. When the light-emitting device is disposed between the first voltage terminal and the fourth node, a first electrode of the sixth transistor is electrically connected to a cathode of the light-emitting device, and a second electrode of the sixth transistor is electrically connected to the fourth node. When the light-emitting device is disposed between the second voltage terminal and the third node, a first electrode of the sixth transistor is electrically connected to the first voltage terminal, and a second electrode of the sixth transistor is electrically connected to the fourth node.

[0011] In one possible implementation, the third light-emission control subcircuit includes a seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the second light-emission control line, and a first electrode of the seventh transistor is electrically connected to the third node. When the light-emitting device is disposed between the first voltage terminal and the fourth node, the second electrode of the sixth transistor is electrically connected to the second voltage terminal. When the light-emitting device is disposed between the second voltage terminal and the third node, the second electrode of the sixth transistor is electrically connected to an anode of the light-emitting device.

[0012] In one possible implementation, the second initialization sub-circuit includes an eighth transistor, wherein a control electrode of the eighth transistor is electrically connected to the fourth scan line, a first electrode of the eighth transistor is electrically connected to the third node, and a second electrode of the eighth transistor is electrically connected to the initial voltage terminal.

[0013] In one possible embodiment, the third initialization subcircuit includes a ninth transistor, wherein a control electrode of the ninth transistor is electrically connected to the fourth scan line. When the light-emitting device is disposed between the first voltage terminal and the fourth node, a first electrode of the ninth transistor is electrically connected to a cathode of the light-emitting device, and a second electrode of the ninth transistor is electrically connected to the compensation voltage line. When the light-emitting device is disposed between the second voltage terminal and the third node, a first electrode of the ninth transistor is electrically connected to an anode of the light-emitting device, and a second electrode of the ninth transistor is electrically connected to the initial voltage line.

[0014] A second aspect of the present application provides a method for driving a pixel circuit, the pixel circuit comprising a driving subcircuit, a first energy storage subcircuit, a second energy storage subcircuit, a data writing subcircuit, a first compensation control subcircuit, a second compensation control subcircuit, a first initialization subcircuit, and a first light emission control subcircuit. The control terminal of the driving subcircuit is electrically connected to a first node, the first terminal of the driving subcircuit is electrically connected to a fourth node, and the second terminal of the driving subcircuit is electrically connected to a third node. The first terminal of the first energy storage subcircuit is electrically connected to a second node, and the second terminal of the first energy storage subcircuit is electrically connected to a fifth node. The first terminal of the second energy storage subcircuit is electrically connected to the fifth node, and the second terminal of the second energy storage subcircuit is electrically connected to the third node. The control terminal of the data writing subcircuit is electrically connected to a third scan line, the first terminal of the data writing subcircuit is electrically connected to a data line, and the second terminal of the data writing subcircuit is electrically connected to the second node. The control terminal of the first compensation control subcircuit is electrically connected to a second scan line, the first terminal of the first compensation control subcircuit is electrically connected to the fifth node, and the second terminal of the first compensation control subcircuit is electrically connected to the first node. The control terminal of the second compensation control subcircuit is electrically connected to the first scan line, the first terminal of the second compensation control subcircuit is electrically connected to the first node, and the second terminal of the first compensation control subcircuit is electrically connected to the fourth node. The control terminal of the first initialization subcircuit is electrically connected to the second scan line, the first terminal of the first initialization subcircuit is electrically connected to the reference voltage line, and the second terminal of the first initialization subcircuit is electrically connected to the fifth node. The light-emitting device is disposed between the first voltage terminal and the fourth node, or between the second voltage terminal and the third node. The control terminal of the first light-emitting control subcircuit is electrically connected to the first light-emitting control line, the first terminal of the first light-emitting control subcircuit is electrically connected to the second node, and the second terminal of the first light-emitting control subcircuit is electrically connected to the first node. The pixel circuit includes a reset phase, a sampling phase, and a data writing phase within a display cycle. The driving method includes: in the reset phase, under the control of the second control line, controlling the first initialization subcircuit to write the reference voltage received from the reference voltage line into the first node via the first compensation control subcircuit. During the sampling phase, under the control of the first scan line and the second scan line, the first initialization sub-circuit is controlled to write the reference voltage received from the reference voltage line into the third node via the first compensation control sub-circuit, the second compensation control sub-circuit, and the driving sub-circuit to perform threshold voltage compensation. During the data writing phase, under the control of the third scan line, the data writing sub-circuit is controlled to write the data voltage received from the data line into the second node.

[0015] In one possible embodiment, the pixel circuit further includes a second light-emitting control subcircuit, wherein the control terminal of the second light-emitting control subcircuit is electrically connected to the first light-emitting control line. When the light-emitting device is disposed between the first voltage terminal and the fourth node, the first terminal of the second light-emitting control subcircuit is electrically connected to the cathode of the light-emitting device, and the second terminal of the second light-emitting control subcircuit is electrically connected to the fourth node. When the light-emitting device is disposed between the second voltage terminal and the third node, the first terminal of the second light-emitting control terminal is electrically connected to the first voltage terminal, and the second terminal of the second light-emitting control terminal is electrically connected to the fourth node. The display cycle further includes a light-emitting phase, and the driving method further includes: during the light-emitting phase, under the control of the first light-emitting control line, controlling the first light-emitting control subcircuit, the second light-emitting control circuit, and the driving subcircuit to cooperate to conduct the first voltage terminal and the second voltage terminal to drive the light-emitting device to emit light.

[0016] In one possible embodiment, the light-emitting device is disposed between a first voltage terminal and the fourth node, and the pixel circuit further includes a third light-emitting control subcircuit, wherein a control terminal of the third light-emitting control subcircuit is electrically connected to a second light-emitting control line, a first terminal of the third light-emitting control subcircuit is electrically connected to the third node, and a second terminal of the third light-emitting control subcircuit is electrically connected to the second voltage terminal. The driving method further includes: during the reset phase, under the control of the second light-emitting control line, controlling the second light-emitting control subcircuit to write the second voltage received from the second voltage terminal to the third node. During the light-emitting phase, under the control of the second control line, controlling the second voltage terminal to be connected to the third node.

[0017] In a possible implementation manner, the sampling phase and the data writing phase at least partially overlap.

[0018] A third aspect of the present application provides a display panel, comprising a plurality of pixel circuits according to any possible implementation of the first aspect, and light-emitting devices electrically connected to the pixel circuits.

[0019] A fourth aspect of the present application provides a computer-readable medium having a computer program stored thereon, wherein when the computer program is executed by a computer, the driving method of the pixel circuit according to any embodiment of the second aspect of the present application is implemented.

[0020] A fifth aspect of the present application provides a computer program product, comprising: a computer program code, which, when executed on a computer, enables implementation of a method for driving a pixel circuit as in any one of the embodiments of the second aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the drawings without creative work.

[0022] Figure 1 is a schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0023] Figure 2 1 is a schematic structural diagram of a pixel circuit 100 provided in an embodiment of the present application;

[0024] Figure 3 is a circuit diagram of a pixel circuit 100 provided in an embodiment of the present application;

[0025] Figure 4 is a timing diagram of the pixel circuit 100 provided in an embodiment of the present application;

[0026] Figure 5 is a schematic structural diagram of a pixel circuit 200 provided in an embodiment of the present application;

[0027] Figure 6 is a circuit diagram of a pixel circuit 200 provided in an embodiment of the present application;

[0028] Figure 7 is a timing diagram of the pixel circuit 200 provided in an embodiment of the present application;

[0029] Figure 8 3 is a schematic structural diagram of a pixel circuit 300 provided in an embodiment of the present application;

[0030] Figure 9 is a circuit diagram of a pixel circuit 300 provided in an embodiment of the present application;

[0031] Figure 10 is a timing diagram of the pixel circuit 300 provided in an embodiment of the present application;

[0032] Figure 11 4 is a schematic structural diagram of a pixel circuit 400 provided in an embodiment of the present application;

[0033] Figure 12 4 is a circuit diagram of a pixel circuit 400 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0035] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification of this application and the appended claims, the singular expressions "a", "an", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one, two or more. The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship.

[0036] References to "one embodiment," "some embodiments," "one embodiment," or "some embodiments" described in the embodiments of the present application mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in some other embodiments," and "in some other embodiments" appearing at different points in this specification do not necessarily all refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0037] In the description of the embodiments of the present application, "electrical connection" includes situations where components are electrically connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the electrically connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0038] Unless otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0039] Unless otherwise specified, all technical features and optional technical features of this application can be combined with each other to form a new technical solution.

[0040] In the circuit structure (e.g., pixel circuit) provided in the embodiments of the present disclosure, the transistors used in the circuit structure may be thin film transistors (TFT), field effect transistors (MOS), or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as an example.

[0041] In the circuit structure provided in the embodiments of the present disclosure, the first electrode of each transistor used is one of the source and the drain, and the second electrode of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.

[0042] In the circuit structure provided by the embodiments of the present disclosure, the first node, the second node and other nodes do not represent actual components, but represent related connected junctions in the circuit diagram. That is, these nodes are nodes formed by the equivalent of related connected junctions in the circuit diagram.

[0043] The transistors included in the circuit structure provided in the embodiments of the present disclosure may all be N-type transistors, or may all be P-type transistors, or may be partly N-type transistors and partly P-type transistors. In the present disclosure, "effective level" refers to the level at which a transistor can be turned on. Among them, a P-type transistor can be turned on under the control of a low-level signal, and an N-type transistor can be turned on under the control of a high-level signal. The following is a schematic explanation using the example of the transistors included in the circuit structure provided in the embodiments of the present disclosure being all N-type transistors.

[0044] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, certain well-known parts may not be shown in the drawings.

[0045] Active Matrix Organic Light Emitting Display (OLED) display panels have many advantages, including self-luminescence, low driving voltage, high luminous efficiency, short response time, high clarity and contrast, nearly 180° viewing angle, wide operating temperature range, and the ability to achieve flexible display and large-area full-color display. They are recognized by the industry as the display device with the most development potential. AMOLED display panels have multiple pixels arranged in an array, and each pixel is driven by an OLED pixel circuit. Because the threshold voltage Vth of the driving thin-film transistor is prone to drift, resulting in changes in the driving current, it is easy to cause uneven brightness of the AMOLED display panel, resulting in poor display and affecting image quality. Therefore, the threshold voltage Vth needs to be compensated.

[0046] As display sizes increase (for example, from 2048 to 3296 lines) and display formats change (for example, from landscape to portrait), the 1H time decreases. In current AMOLED panel driver circuits, the pixel circuit includes four stages: reset, sampling, writing, and emitting. A common mode is to perform sampling and writing simultaneously, making the sampling time less than the scanning time for one line. This results in insufficient threshold voltage compensation time at high frequencies and high resolutions, affecting image quality.

[0047] In view of this, the present application proposes a pixel circuit, a driving method and a display device, which realize sampling and writing through different paths, so that the threshold voltage compensation time is not limited by the data voltage writing time, thereby realizing high-frequency driving.

[0048] The pixel circuit, driving method and display device described in this application will be described in detail below with reference to the accompanying drawings.

[0049] Figure 1 Schematic diagram of a pixel circuit provided by an embodiment of the present application. Figure 1 As shown, the pixel circuit includes a driving subcircuit, a data writing subcircuit, a first energy storage subcircuit, a second energy storage subcircuit, a first compensation control subcircuit, a second compensation control subcircuit, a first initialization subcircuit and a first light emission control subcircuit.

[0050] The control terminal of the driver sub-circuit is electrically connected to the first node N1, the first terminal of the driver sub-circuit is electrically connected to the fourth node N4, and the second terminal of the driver sub-circuit is electrically connected to the third node N3. The driver sub-circuit is configured to control the generation of a driving current for driving the light-emitting device under the control of the potential of the first node N1.

[0051] The data write subcircuit has a control terminal electrically connected to the third scan line, a first terminal electrically connected to the data line Data, and a second terminal electrically connected to the second node N2. The data write subcircuit is configured to control connectivity and disconnection between the data line and the second node N2 under control of the third scan line.

[0052] The first end of the first energy storage sub-circuit is electrically connected to the second node N2, and the second end of the first energy storage sub-circuit is electrically connected to the fifth node N5. The first energy storage sub-circuit can be used to store the data voltage Vdata corresponding to the data line Data.

[0053] The first terminal of the second energy storage subcircuit is electrically connected to the fifth node N5, and the second terminal of the second energy storage subcircuit is electrically connected to the third node N3. The second energy storage subcircuit can store the voltage of the second terminal of the driving subcircuit and prevent the voltage of the second terminal of the driving subcircuit from being easily changed.

[0054] A control terminal of the first initialization sub-circuit is electrically connected to the second scan line, a first terminal of the first initialization sub-circuit is electrically connected to the reference voltage terminal, and a second terminal of the first initialization sub-circuit is electrically connected to the fifth node N5. The first initialization sub-circuit is configured to write a reference voltage provided by the reference voltage terminal into the fifth node N5 under control of the second scan line.

[0055] A control terminal of the first compensation control subcircuit is electrically connected to the second scan line, a first terminal of the first compensation control subcircuit is electrically connected to the fifth node N5, and a second terminal of the first compensation control subcircuit is electrically connected to the first node N1. The first compensation control subcircuit is configured to control connectivity and disconnection between the first node N1 and the fifth node N5 under control of the second scan line.

[0056] A control terminal of the second compensation control subcircuit is electrically connected to the first scan line, a first terminal of the second compensation control subcircuit is electrically connected to the first node N1, and a second terminal of the first compensation control subcircuit is electrically connected to the fourth node N4. The second compensation control subcircuit is configured to control connectivity and disconnection between the first node N1 and the fourth node N4 under control of the first scan line.

[0057] The control terminal of the first light-emitting control terminal is electrically connected to the first light-emitting control line, the first terminal of the first light-emitting control terminal is electrically connected to the second node N2, and the second terminal of the first compensation control sub-circuit is electrically connected to the first node N1. The first light-emitting control terminal is used to control the connection and disconnection between the first node N1 and the second node N2 under the control of the first light-emitting control line.

[0058] It can be understood that the embodiment of the present application does not limit the location of the light-emitting device ML in the pixel circuit.

[0059] In some possible embodiments, the light emitting device ML may be disposed between the first voltage terminal VDD and the first terminal of the driving sub-circuit. In this case, the light emitting device ML is referred to as an inverted OLED in this application.

[0060] In some possible embodiments, the light-emitting device ML may be disposed between the second voltage terminal VSS and the second terminal of the driving sub-circuit. In this case, the light-emitting device ML is referred to as a common OLED in this application.

[0061] In some possible embodiments, the pixel circuit may further include a second light emitting control subcircuit.

[0062] A control terminal of the second light-emitting control subcircuit is electrically connected to the first light-emitting control line. A first terminal of the second light-emitting control subcircuit is electrically connected to the cathode of the light-emitting device ML. A second terminal of the second light-emitting control subcircuit is electrically connected to the fourth node N4. The second light-emitting control terminal is used to control the connection and disconnection between the cathode of the light-emitting device ML and the fourth node N4 under the control of the first light-emitting control line.

[0063] In a pixel circuit including a conventional OLED, a control terminal of a second light-emitting control subcircuit is electrically connected to a first light-emitting control line, a first terminal of the second light-emitting control subcircuit is electrically connected to a first voltage terminal, and a second terminal of the second light-emitting control subcircuit is electrically connected to a fourth node N4. The second light-emitting control subcircuit is configured to control connection and disconnection between the first voltage terminal and the fourth node N4 under control of the first light-emitting control line.

[0064] In some possible embodiments, the pixel circuit may further include a third light emitting control subcircuit.

[0065] In a pixel circuit including an inverted OLED, a control terminal of a third light-emitting control subcircuit is electrically connected to a second light-emitting control line, a first terminal of the third light-emitting control subcircuit is electrically connected to a third node N3, and a second terminal of the third light-emitting control subcircuit is electrically connected to a second voltage terminal. The third light-emitting control subcircuit is configured to control connection and disconnection between the third node N3 and the second voltage terminal under control of the second light-emitting control line.

[0066] In a pixel circuit including a conventional OLED, a control terminal of the third light-emission control subcircuit is electrically connected to the second light-emission control line, a first terminal of the third light-emission control subcircuit is electrically connected to a third node N3, and a second terminal of the third light-emission control subcircuit is electrically connected to the anode of the light-emitting device ML. The third light-emission control subcircuit is configured to control connection and disconnection between the third node N3 and the anode of the light-emitting device ML under control of the second light-emission control line.

[0067] In some possible embodiments, the pixel circuit may further include a second initialization sub-circuit.

[0068] The control terminal of the second initialization sub-circuit is electrically connected to the fourth scan line, the first terminal of the second initialization sub-circuit is electrically connected to the third node N3, and the second terminal of the second initialization sub-circuit is electrically connected to the initial voltage terminal. The second initialization sub-circuit is configured to write an initial voltage received from the initial voltage terminal into the third node N3 under the control of the fourth scan line.

[0069] In some possible embodiments, the pixel circuit may further include a third initialization sub-circuit.

[0070] In a pixel circuit including an inverted OLED, a control terminal of a third initialization subcircuit is electrically connected to a fourth scan line, a first terminal of the third initialization subcircuit is electrically connected to the cathode of the light-emitting device ML, and a second terminal of the third initialization subcircuit is electrically connected to a compensation voltage line. The third initialization subcircuit is configured to write a compensation voltage received from the compensation voltage terminal to the cathode of the light-emitting device ML under control of the fourth scan line.

[0071] In a pixel circuit including a conventional OLED, a control terminal of the third initialization subcircuit is electrically connected to the fourth scan line, a first terminal of the third initialization subcircuit is electrically connected to the anode of the light-emitting device ML, and a third terminal of the third initialization subcircuit is electrically connected to the initial voltage terminal. The third initialization subcircuit is configured to write an initial voltage received from the initial voltage terminal to the anode of the light-emitting device ML under control of the fourth scan line.

[0072] Figure 2 1 is a schematic diagram of the structure of a pixel circuit 100 provided in an embodiment of the present application. Figure 2 As shown, the pixel circuit includes a driving subcircuit, a data writing subcircuit, a first energy storage subcircuit, a second energy storage subcircuit, a first compensation control subcircuit, a second compensation control subcircuit, a first initialization subcircuit, a first light-emitting control subcircuit, a second light-emitting control subcircuit and a third light-emitting control subcircuit.

[0073] Figure 3 1 is a circuit diagram of a pixel circuit 100 provided in an embodiment of the present application. Figure 3 As shown, the pixel circuit includes transistors M1 to M8, a first capacitor Cst1 and a second capacitor Cst2.

[0074] See also Figure 3 The driving sub-circuit includes a driving transistor M1, wherein a control electrode of M1 is electrically connected to a node N1, a first electrode of M1 is electrically connected to a node N4, and a second electrode of M1 is electrically connected to a node N3.

[0075] Continue to see Figure 3The first light emission control subcircuit includes a transistor M2, wherein a control electrode of M2 is electrically connected to a first light emission control line EM1, a first electrode of M2 is electrically connected to a node N2, and a second electrode of M2 is electrically connected to a node N1. When transistor M2 is turned on by the light emission control line EM1, the voltage at node N2 can be transmitted to node N1.

[0076] Continue to see Figure 3 The first initialization sub-circuit includes a transistor M3, wherein a control electrode of M3 is electrically connected to the second scan line gate2, a first electrode of M3 is electrically connected to a reference voltage terminal, and a second electrode of M3 is electrically connected to a node N5. When transistor M3 is turned on by the second scan line gate2, a reference voltage Vref corresponding to the reference voltage terminal can be written to the node N5.

[0077] Continue to see Figure 3 The third light-emission control subcircuit includes a transistor M4, wherein a control electrode of M4 is electrically connected to the second light-emission control line EM2, a first electrode of M4 is electrically connected to the second voltage terminal, and a second electrode of M4 is electrically connected to node N3. When transistor M4 is turned on by the second light-emission control line EM2, a voltage VSS corresponding to the second voltage terminal can be written to node N3.

[0078] Continue to see Figure 3 The data writing sub-circuit includes a transistor M5, wherein a control electrode of M5 is electrically connected to the third scan line gate3, a first electrode of M5 is electrically connected to the data line Data, and a second electrode of M5 is electrically connected to the node N2. When transistor M5 is turned on by the third scan line gate3, a data voltage Vdata corresponding to the data line Data can be written to the node N2.

[0079] Continue to see Figure 3 The second compensation control sub-circuit includes a transistor M6, wherein a control electrode of M6 is electrically connected to the first scan line gate1, a first electrode of M6 is electrically connected to node N1, and a second electrode of M6 is electrically connected to node N4. When transistor M6 is turned on by the first scan line gate1, the voltage at node N1 can be transmitted to node N4.

[0080] Continue to see Figure 3 The second light-emission control subcircuit includes a transistor M7, wherein a control electrode of M7 is electrically connected to the first light-emission control line EM1, a first electrode of M7 is electrically connected to the first voltage terminal, and a second electrode of M7 is electrically connected to the node N4. When transistor M4 is turned on by the first light-emission control line EM1, a voltage VDD corresponding to the first voltage terminal can be written to the node N4.

[0081] Continue to see Figure 3The first compensation control subcircuit includes a transistor M8, wherein a control electrode of M8 is electrically connected to the second scan line gate2, a first electrode of M8 is electrically connected to node N5, and a second electrode of M8 is electrically connected to node N1. When transistor M8 is turned on by the second scan line gate2, the voltage at node N5 can be transmitted to node N1.

[0082] The embodiment of the present application also provides a driving method for a pixel circuit, which is applied to Figure 3 The pixel circuit shown.

[0083] like Figure 4 As shown, the driving method of the pixel circuit may include an initialization phase T1, a sampling phase T2, a writing phase T3 and a light emitting phase T4.

[0084] During initialization phase T1, gate2 and EM2 provide high-level signals, while gate1, gate3, and EM1 all provide low-level signals. Since gate2 provides a high-level signal, transistors M3 and M8 are in an on-state, allowing reference voltage Vref to be written to node N5 and transmitted from node N5 to node N1. At this point, the potential of node N1 is Vref. Since EM2 provides a high-level signal, transistor M4 is turned on, and the second voltage VSS is written to node N3. At this point, the potential of node N3 is VSS. Simultaneously, the second capacitor C2 can be initialized by the voltage difference between the second voltage VSS and the reference voltage Vref. In this case, transistors M4 and M7 are in an off-state, so the light-emitting device ML remains in a non-luminous state.

[0085] During sampling phase T2, gate1 and gate2 provide high-level signals, while gate3, EM1, and EM2 all provide low-level signals. Because gate2 provides a high-level signal, transistors M3 and M8 are in an on-state, and reference voltage Vref can be written to node N1. Furthermore, because gate1 provides a high-level signal, transistor M6 is in an on-state, and the voltage at node N1 can be transmitted to node N4. Reference voltage Vref can have a high voltage capable of turning on transistor M1, and node N1 (or the control electrode of transistor M1) is applied with this high voltage. Therefore, transistor M1 can output current from its first terminal to its second terminal. The current output from transistor M1 can then be transmitted to node N3 to charge node N3. At this point, the potential of node N3 increases from the second voltage VSS to Vref-ΔV and gradually approaches Vref-Vth. Simultaneously, the voltage stored in second capacitor C2 can gradually approach Vth, where Vth is the threshold voltage of transistor M1. In the sampling phase T2 , the potential at the node N1 is Vref, and the potential at the node N3 is Vref−ΔV.

[0086] During the data writing phase T3, gate1, gate2, and gate3 all provide high-level signals, and EM1 and EM2 both provide low-level signals. Since gate1 and gate2 both provide high-level signals, threshold voltage compensation continues at this time. Since gate3 switches from providing a low-level signal to providing a high-level signal, transistor M5 switches to the on state, and the data voltage Vdata corresponding to the data line data can be written to node N2. At the same time, the first capacitor C1 can be charged with a voltage of the data voltage Vdata. At the end of the data writing phase, the potential at node N1 is Vref, the potential at node N2 is Vdata, and the potential at node N3 is Vref-Vth.

[0087] Based on the above scheme, although the sampling phase T2 and the data writing phase T3 overlap, the threshold voltage compensation and data voltage writing can be achieved through different paths. At this time, the sampling duration is no longer limited by the duration of the data voltage writing, which can ensure sufficient threshold voltage compensation time and better image quality.

[0088] During the light-emitting phase T4, EM1 and EM2 provide high-level signals, and gate1, gate2, and gate3 all provide low-level signals. Because EM1 and EM2 provide high-level signals, transistors M7 and M8 can be turned on, forming a current path from the first voltage terminal, the light-emitting device ML, transistor T1, to the second voltage terminal. Furthermore, transistor M3 can be turned on, causing the data voltage Vdata stored in the first capacitor C1 to be written to the control electrode of transistor M1 (i.e., node N1). At this time, the magnitude of the current flowing through transistor M1 can be determined based on the data voltage Vdata, allowing the light-emitting device ML to generate light with a predetermined brightness in response to the current.

[0089] It can be understood that the potential difference between nodes N2 and N3 is Vdata-Vref+Vth. Furthermore, during the light-emitting phase T4, transistor M4 is turned on, and the potential of node N3 gradually reaches the second voltage VSS. The potential of node N2 then becomes VSS+Vdata-Vref+Vth. Since transistor M2 is turned on, node N2 and node N1 are connected, and the potential of node N1 is equal to the potential of node N2.

[0090] At this time, the gate-source voltage of the transistor M1 is Vgs=(VSS+Vdata−Vref+Vth)−VSS=Vdata−Vref+Vth.

[0091] Then the light emitting current of the light emitting device ML can be expressed as:

[0092] Ioled=K(Vgs-Vth)^2=K(Vdata-Vref+Vth-Vth)^2=K(Vdata-Vref)^2, where K represents the current coefficient of the transistor M1.

[0093] Based on the above solution, the final light-emitting current of the light-emitting device ML is independent of the first voltage VDD, that is, the light-emitting current of the light-emitting device ML is not affected by the resistance-capacitance load (RC loading) in the panel, which can solve the display unevenness problem caused by the VDD voltage drop, thereby better driving on medium and large-sized OLED panels.

[0094] Figure 5 2 is a schematic diagram of the structure of a pixel circuit 200 provided in an embodiment of the present application. The difference between the pixel circuit 100 and the pixel circuit 200 is that the pixel circuit 200 adds a second initialization subcircuit and removes the third light emitting control subcircuit.

[0095] Figure 6 2 is a circuit diagram of the pixel circuit 200 provided in an embodiment of the present application. It can be understood that, except for the transistor M4, the connection method of the transistors M1 to M8 can be referred to Figure 3 The relevant content will not be elaborated on here.

[0096] See also Figure 6 The second initialization sub-circuit includes a transistor M9, wherein a control electrode of M9 is electrically connected to a fourth control line, a first electrode of M9 is electrically connected to node N3, and a second electrode of M9 is electrically connected to an initial voltage line. The control electrode of transistor M9 can receive a scan signal via the fourth control line. When transistor M9 is turned on by the fourth control line, an initial voltage Vint provided by the initial voltage line can be written to node N3.

[0097] It can be understood that the control electrodes of the transistor M2 and the transistor M7 can be electrically connected to the same light-emitting control line or to different light-emitting control lines, which is not limited in the embodiment of the present application.

[0098] Figure 7 is a working timing diagram of the pixel circuit 200. Figure 7 As shown, the driving method of the pixel circuit may include an initialization phase T1, a sampling phase T2, a writing phase T3 and a light emitting phase T4.

[0099] During initialization phase T1, gates 2 and 4 provide high-level signals, while gates 1, 3, and EM1 all provide low-level signals. As can be seen, since gate 2 provides a high-level signal, node N1 is initialized to reference voltage Vref. Simultaneously, since gate 4 provides a high-level signal, node N3 is initialized to initialization voltage Vinit.

[0100] During sampling phase T2, gates 1 and 2 provide high-level signals, while gates 3, 4, and EM1 all provide low-level signals. Since gates 1 and 2 both provide high-level signals, the reference voltage line charges node N3 through transistors M3, M8, M6, and M1, causing the potential at node N3 to gradually increase from Vinit to Vref-ΔV and then gradually approach Vref-Vth. During sampling phase T2, the potential at node N1 is Vref, and the potential at node N3 is Vref-ΔV.

[0101] During the data writing phase T3, gate1, gate2, and gate3 all provide high-level signals, while gate4 and EM1 all provide low-level signals. Since gate1 and gate2 both provide high-level signals, threshold voltage compensation continues at this time. Since gate3 provides a high-level signal, the data voltage Vdata is written to node N2 through the turned-on transistor M5. At the same time, the first capacitor C1 can be charged with a voltage corresponding to the data voltage Vdata. At the end of the data writing phase, the potential at node N1 is Vref, the potential at node N2 is Vdata, and the potential at node N3 is Vref-Vth.

[0102] Based on the above scheme, although the sampling phase T2 and the data writing phase T3 overlap, the threshold voltage compensation and data voltage writing can be achieved through different paths. At this time, the sampling duration is no longer limited by the duration of the data voltage writing, which can ensure sufficient threshold voltage compensation time and better image quality.

[0103] During the light-emitting phase T4, EM1 provides a high-level signal, and gate1, gate2, gate3, and gate4 all provide low-level signals. Because EM1 provides a high-level signal, transistor M7 turns on, forming a current path from the first voltage terminal, the light-emitting device ML, transistor T1, to the second voltage terminal. Furthermore, transistor M3 turns on, allowing the data voltage Vdata stored in the first capacitor C1 to be written to the control electrode of transistor M1 (i.e., node N1). At this time, the current flowing through transistor M1 can be determined by the data voltage Vdata, allowing the light-emitting device ML to generate light with a predetermined brightness in response to the current.

[0104] Similarly, the light-emitting current of the light-emitting device ML can be expressed as K(Vdata-Vref)^2, that is, the light-emitting current of the light-emitting device ML is not affected by the resistance-capacitance load (RC loading) in the panel, which can solve the display unevenness problem caused by the VDD voltage drop, thereby better driving on medium and large-sized OLED panels.

[0105] Figure 8 3 is a schematic diagram of the structure of the pixel circuit 300 provided in an embodiment of the present application. The difference between the pixel circuit 100 and the pixel circuit 300 is that the pixel circuit 300 is further provided with a third initialization sub-circuit.

[0106] Figure 9 3 is a circuit diagram of a pixel circuit 300 provided in an embodiment of the present application. It is understood that the connection method of transistors M1 to M8 can be referred to Figure 3 The relevant content will not be elaborated on here.

[0107] See also Figure 9 The third initialization sub-circuit includes a transistor M9, wherein a control electrode of M9 is electrically connected to a fourth control line, a first electrode of M9 is electrically connected to the cathode of the light-emitting device ML, and a second electrode of M9 is electrically connected to the compensation voltage line. The control electrode of transistor M9 can receive a scan signal via the fourth control line. When transistor M9 is turned on by the fourth control line, the compensation voltage Vcomp provided by the initialization voltage line can be transmitted to the cathode of the light-emitting device ML.

[0108] Figure 10 is a timing diagram of the pixel circuit 300. Figure 10 As shown, the driving method of the pixel circuit may include an initialization phase T1, a sampling phase T2, a writing phase T3 and a light emitting phase T4.

[0109] During initialization phase T1, gates 2, 4, and EM2 provide high-level signals, while gates 1, 3, and EM1 all provide low-level signals. As can be appreciated, since gates 2 and EM2 provide high-level signals, node N1 is initialized to reference voltage Vref, and node N3 is initialized to second voltage VSS. Simultaneously, since gate 4 provides a high-level signal, the cathode of light-emitting device ML is initialized to compensation voltage Vcomp.

[0110] During sampling phase T2, gate1, gate2, and gate4 provide high-level signals, while gate3 and EM1 both provide low-level signals. Because gate1 and gate2 both provide high-level signals, the reference voltage line charges node N3 through transistors M3, M8, M6, and M1, causing the potential at node N3 to gradually increase from Vinit to Vref-ΔV and then gradually approach Vref-Vth. During sampling phase T2, the potential at node N1 is Vref, and the potential at node N3 is Vref-ΔV. Simultaneously, because gate4 provides a high-level signal, the cathode of light-emitting device ML is initialized to the compensation voltage Vcomp.

[0111] During the data writing phase T3, gate1, gate2, gate3, and gate4 all provide high-level signals, and gate4 and EM1 both provide low-level signals. Since gate1 and gate2 both provide high-level signals, threshold voltage compensation continues at this time. Since gate3 provides a high-level signal, the data voltage Vdata is written to node N2 through the turned-on transistor M5. At the same time, the first capacitor C1 can be charged with a voltage corresponding to the data voltage Vdata. At the end of the data writing phase, the potential at node N1 is Vref, the potential at node N2 is Vdata, and the potential at node N3 is Vref-Vth. At the same time, since gate4 provides a high-level signal, the cathode of the light-emitting device ML is initialized by the compensation voltage Vcomp.

[0112] Based on the above scheme, although the sampling phase T2 and the data writing phase T3 overlap, threshold voltage compensation and data voltage writing can be achieved through different paths. In this case, the sampling duration is no longer limited by the data voltage writing duration, ensuring sufficient time for threshold voltage compensation and improving image quality. Furthermore, during the non-luminous phase, the cathode potential of the light-emitting device ML is initialized by the compensation voltage Vcomp, which can improve the brightness uniformity of the light-emitting element OLED during the luminous phase.

[0113] During the light-emitting phase T4, EM1 provides a high-level signal, and gate1, gate2, gate3, and gate4 all provide low-level signals. Because EM1 provides a high-level signal, transistor M7 turns on, forming a current path from the first voltage terminal, the light-emitting device ML, transistor T1, to the second voltage terminal. Furthermore, transistor M3 turns on, allowing the data voltage Vdata stored in the first capacitor C1 to be written to the control electrode of transistor M1 (i.e., node N1). At this time, the current flowing through transistor M1 can be determined by the data voltage Vdata, allowing the light-emitting device ML to generate light with a predetermined brightness in response to the current.

[0114] Similarly, the light-emitting current of the light-emitting device ML can be expressed as K(Vdata-Vref)^2, that is, the light-emitting current of the light-emitting device ML is not affected by the resistance-capacitance load (RC loading) in the panel, which can solve the display unevenness problem caused by the VDD voltage drop, thereby better driving on medium and large-sized OLED panels.

[0115] It can be understood that gate4 can also provide a high-level signal in any period from T1 to T3, and initialize the cathode potential of the light-emitting device ML through the compensation voltage Vcomp, so that the driving mode is flexible.

[0116] Figure 112 is a schematic diagram of the structure of the pixel circuit 400 provided in an embodiment of the present application. The difference between the pixel circuit 200 and the pixel circuit 400 is that the pixel circuit 400 is a pixel circuit including a common OLED and includes a third initialization sub-circuit.

[0117] Figure 12 4 is a circuit diagram of a pixel circuit 400 provided in an embodiment of the present application. It is understood that the connection method of the transistors M1 to M8 can refer to Figure 2 The relevant content will not be elaborated on here.

[0118] See also Figure 12 The light emitting device ML is provided between the transistor M4 and the second voltage terminal.

[0119] Continue to see Figure 12 The third initialization sub-circuit includes a transistor M9, a control electrode of which is electrically connected to a fourth control line, a first electrode of which is electrically connected to the anode of the light-emitting device ML, and a second electrode of which is electrically connected to an initialization voltage line. The control electrode of the transistor M9 can receive a scan signal via the fourth control line. When the fourth control line turns on the transistor M9, an initialization voltage Vinit provided by the initialization voltage line can be transmitted to the anode of the light-emitting device ML.

[0120] It can be understood that the driving method of the pixel circuit 400 can refer to the driving method of the pixel circuit 300, which will not be described in detail here.

[0121] Based on the above solution, the pixel circuit provided in the embodiment of the present application can be a pixel circuit including a common OLED, which has strong flexibility and a wide range of applications.

[0122] An embodiment of the present application further provides a display panel, comprising a plurality of pixel circuits as described in the above embodiment, and light-emitting devices electrically connected to the pixel circuits.

[0123] An embodiment of the present application further provides a computer program product, which includes: computer program code, which enables the computer to execute the method in the above embodiment when the computer program code is run on a computer.

[0124] An embodiment of the present application further provides a computer-readable medium, wherein the computer-readable medium stores a program code. When the computer program code runs on a computer, the computer executes the method in the above embodiment.

[0125] Although the present application has been described with reference to preferred embodiments, various modifications may be made thereto and components or steps may be substituted with equivalents without departing from the scope of the present application. In particular, the various technical features described in the various embodiments may be combined in any manner, provided there are no conflicts in structure or method steps. The present application is not limited to the specific embodiments disclosed herein, but encompasses all technical solutions within the scope of the claims.

Claims

1. A pixel circuit for driving a light-emitting device to emit light, characterized in that: include: a driving subcircuit, a first energy storage subcircuit, a second energy storage subcircuit, a data writing subcircuit, a first compensation control subcircuit, a second compensation control subcircuit, a first initialization subcircuit, and a first light emission control subcircuit; The control terminal of the driving sub-circuit is connected to the first node, the first terminal of the driving sub-circuit is connected to the fourth node, and the second terminal of the driving sub-circuit is connected to the third node, and is used to control the generation of a driving current for driving the light-emitting device under the control of the potential of the first node; The first end of the first energy storage subcircuit is connected to the second node, the second end of the first energy storage subcircuit is connected to the fifth node, and the first energy storage subcircuit is used to store electrical energy; A first end of the second energy storage sub-circuit is connected to the fifth node, a second end of the second energy storage sub-circuit is connected to the third node, and the second energy storage sub-circuit is used to store electrical energy; The control end of the data writing sub-circuit is connected to the third scan line, the first end of the data writing sub-circuit is connected to the data line, and the second end of the data writing sub-circuit is connected to the second node, and is used to write the data voltage provided by the data line into the second node under the control of the third scan line; The control terminal of the first compensation control subcircuit is connected to the second scan line, the first terminal of the first compensation control subcircuit is connected to the fifth node, and the second terminal of the first compensation control subcircuit is connected to the first node, and is used to control the connection and disconnection between the first node and the fifth node under the control of the second scan line; The control terminal of the second compensation control subcircuit is connected to the first scan line, the first terminal of the second compensation control subcircuit is connected to the first node, and the second terminal of the first compensation control subcircuit is connected to the fourth node, and is used to control the connection and disconnection between the first node N1 and the fourth node under the control of the first scan line; a control terminal of the first initialization sub-circuit connected to the second scan line, a first terminal of the first initialization sub-circuit connected to the reference voltage line, and a second terminal of the first initialization sub-circuit connected to the fifth node, for writing a reference voltage provided by the reference voltage line into the fifth node under control of the second scan line; The control terminal of the first light-emitting control subcircuit is connected to the first light-emitting control line, the first terminal of the first light-emitting control subcircuit is connected to the second node, and the second terminal of the first light-emitting control subcircuit is connected to the first node, for controlling connection and disconnection between the first node and the second node under the control of the first light-emitting control line; The light emitting device is disposed between the first voltage terminal and the fourth node, or the light emitting device is disposed between the second voltage terminal and the third node.

2. The pixel circuit according to claim 1, wherein: The pixel circuit further includes a second light emitting control subcircuit, wherein a control terminal of the second light emitting control subcircuit is electrically connected to the first light emitting control line; When the light-emitting device is provided between the first voltage terminal and the fourth node, the first terminal of the second light-emitting control subcircuit is electrically connected to the cathode of the light-emitting device, and the second terminal of the second light-emitting control subcircuit is electrically connected to the fourth node, for controlling the connection and disconnection between the cathode of the light-emitting device and the fourth node under the control of the first light-emitting control line; When the light-emitting device is arranged between the second voltage terminal and the third node, the first end of the second light-emitting control subcircuit is electrically connected to the first voltage terminal, and the second end of the second light-emitting control subcircuit is electrically connected to the fourth node, and is used to control the connection and disconnection between the first voltage terminal and the fourth node under the control of the first light-emitting control line.

3. The pixel circuit according to claim 1, wherein: The pixel circuit further includes a third light emitting control subcircuit, wherein a control terminal of the third light emitting control subcircuit is electrically connected to the second light emitting control line, and a first terminal of the third light emitting control subcircuit is electrically connected to the third node; When the light-emitting device is arranged between the first voltage terminal and the fourth node, the second terminal of the third light-emitting control subcircuit is electrically connected to the second voltage terminal, and is used to control the connection and disconnection between the third node and the second voltage terminal under the control of the second light-emitting control line; When the light-emitting device is arranged between the second voltage terminal and the third node, the second end of the third light-emitting control subcircuit is electrically connected to the anode of the light-emitting device, and is used to control the connection and disconnection between the third node and the anode of the light-emitting device under the control of the second light-emitting control line.

4. The pixel circuit according to claim 1, wherein: The pixel circuit further includes a second initialization subcircuit, wherein: The control end of the second initialization sub-circuit is electrically connected to the fourth scan line, the first end of the second initialization sub-circuit is electrically connected to the third node, and the second end of the second initialization sub-circuit is electrically connected to the initial voltage end, and is used to write the initial voltage received from the initial voltage end into the third node under the control of the fourth scan line.

5. The pixel circuit according to claim 1, wherein: The pixel circuit further includes a third initialization sub-circuit, wherein a control terminal of the third initialization sub-circuit is electrically connected to the fourth scan line; When the light-emitting device is arranged between the first voltage terminal and the fourth node, the first terminal of the third initialization sub-circuit is electrically connected to the cathode of the light-emitting device, and the second terminal of the third initialization sub-circuit is electrically connected to the compensation voltage line, so as to write the compensation voltage received from the compensation voltage terminal into the cathode of the light-emitting device under the control of the fourth scan line; When the light-emitting device is arranged between the second voltage terminal and the third node, the first end of the third initialization sub-circuit is electrically connected to the anode of the light-emitting device, and the second end of the third initialization sub-circuit is electrically connected to the initial voltage line, and is used to write the initial voltage received from the initial voltage terminal into the anode of the light-emitting device under the control of the fourth scan line.

6. The pixel circuit according to claim 1, wherein: The driving subcircuit includes a first transistor, the first light emitting control subcircuit includes a second transistor, the first initialization subcircuit includes a third transistor, the first compensation control subcircuit includes a fourth transistor, the second compensation control subcircuit includes a fifth transistor, the first energy storage subcircuit includes a first capacitor, and the second energy storage subcircuit includes a second capacitor, wherein: The control electrode of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the third node; The control electrode of the second transistor is electrically connected to the third scan line, the first electrode of the second transistor is electrically connected to the data line, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the second scan line, the first electrode of the third transistor is electrically connected to the reference voltage line, and the second electrode of the third transistor is electrically connected to the fifth node; A control electrode of the fourth transistor is electrically connected to the second scan line, a first electrode of the fourth transistor is electrically connected to the fifth node, and a second electrode of the fourth transistor is electrically connected to the first node; A control electrode of the fifth transistor is electrically connected to the first scan line, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to the fourth node; A first electrode of the first capacitor is electrically connected to the second node, and a second electrode of the first capacitor is electrically connected to the fifth node; A first electrode of the second capacitor is electrically connected to the fifth node, and a second electrode of the second capacitor is electrically connected to the third node.

7. The pixel circuit according to claim 2, wherein: The second light emitting control subcircuit includes a sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the first light emitting control line; When the light emitting device is disposed between the first voltage terminal and the fourth node, the first electrode of the sixth transistor is electrically connected to the cathode of the light emitting device, and the second electrode of the sixth transistor is electrically connected to the fourth node; When the light emitting device is disposed between the second voltage terminal and the third node, the first electrode of the sixth transistor is electrically connected to the first voltage terminal, and the second electrode of the sixth transistor is electrically connected to the fourth node.

8. The pixel circuit according to claim 3, wherein: The third light emitting control subcircuit includes a seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the second light emitting control line, and a first electrode of the seventh transistor is electrically connected to the third node; When the light emitting device is disposed between the first voltage terminal and the fourth node, the second electrode of the seventh transistor is electrically connected to the second voltage terminal; When the light emitting device is disposed between the second voltage terminal and the third node, the second electrode of the seventh transistor is electrically connected to the anode of the light emitting device.

9. The pixel circuit according to claim 4, wherein: The second initialization sub-circuit includes an eighth transistor, wherein a control electrode of the eighth transistor is electrically connected to the fourth scan line, a first electrode of the eighth transistor is electrically connected to the third node, and a second electrode of the eighth transistor is electrically connected to the initial voltage terminal.

10. The pixel circuit according to claim 5, wherein: The third initialization sub-circuit includes a ninth transistor, wherein a control electrode of the ninth transistor is electrically connected to the fourth scan line; When the light emitting device is disposed between the first voltage terminal and the fourth node, the first electrode of the ninth transistor is electrically connected to the cathode of the light emitting device, and the second electrode of the ninth transistor is electrically connected to the compensation voltage line; When the light emitting device is disposed between the second voltage terminal and the third node, the first electrode of the ninth transistor is electrically connected to the anode of the light emitting device, and the second electrode of the ninth transistor is electrically connected to the initial voltage line.

11. A method for driving a pixel circuit, characterized in that: The pixel circuit includes a driving subcircuit, a first energy storage subcircuit, a second energy storage subcircuit, a data writing subcircuit, a first compensation control subcircuit, a second compensation control subcircuit, a first initialization subcircuit and a first light emission control subcircuit; The control terminal of the driving sub-circuit is connected to the first node, the first terminal of the driving sub-circuit is connected to the fourth node, and the second terminal of the driving sub-circuit is connected to the third node; The first end of the first energy storage sub-circuit is connected to the second node, and the second end of the first energy storage sub-circuit is connected to the fifth node; The first end of the second energy storage sub-circuit is connected to the fifth node, and the second end of the second energy storage sub-circuit is connected to the third node; The control end of the data writing sub-circuit is connected to the third scan line, the first end of the data writing sub-circuit is connected to the data line, and the second end of the data writing sub-circuit is connected to the second node; The control end of the first compensation control subcircuit is connected to the second scan line, the first end of the first compensation control subcircuit is connected to the fifth node, and the second end of the first compensation control subcircuit is connected to the first node; The control terminal of the second compensation control subcircuit is connected to the first scan line, the first terminal of the second compensation control subcircuit is connected to the first node, and the second terminal of the first compensation control subcircuit is connected to the fourth node; The control end of the first initialization sub-circuit is connected to the second scan line, the first end of the first initialization sub-circuit is connected to the reference voltage line, and the second end of the first initialization sub-circuit is connected to the fifth node; The light emitting device is arranged between the first voltage terminal and the fourth node, or the light emitting device is arranged between the second voltage terminal and the third node; The control terminal of the first light emitting control subcircuit is connected to the first light emitting control line, the first terminal of the first light emitting control subcircuit is connected to the second node, and the second terminal of the first light emitting control subcircuit is connected to the first node; The pixel circuit includes a reset phase, a sampling phase, and a data writing phase in one display cycle, and the driving method includes: In the reset phase, under the control of the second scan line, the first initialization sub-circuit is controlled to write the reference voltage received from the reference voltage line into the first node through the first compensation control sub-circuit; In the sampling phase, under the control of the first scan line and the second scan line, the first initialization sub-circuit is controlled to write the reference voltage received from the reference voltage line into the third node through the first compensation control sub-circuit, the second compensation control sub-circuit, and the driving sub-circuit to perform threshold voltage compensation; In the data writing phase, under the control of the third scan line, the data writing sub-circuit is controlled to write the data voltage received from the data line into the second node.

12. The driving method according to claim 11, wherein: The pixel circuit further includes a second light emitting control subcircuit, wherein a control terminal of the second light emitting control subcircuit is electrically connected to the first light emitting control line; When the light emitting device is provided between the first voltage terminal and the fourth node, the first terminal of the second light emitting control subcircuit is electrically connected to the cathode of the light emitting device, and the second terminal of the second light emitting control subcircuit is electrically connected to the fourth node; When the light emitting device is arranged between the second voltage terminal and the third node, the first terminal of the second light emitting control subcircuit is electrically connected to the first voltage terminal, and the second terminal of the second light emitting control subcircuit is electrically connected to the fourth node; The display cycle also includes a light emitting phase, and the driving method further includes: In the light-emitting stage, under the control of the first light-emitting control line, the first light-emitting control subcircuit, the second light-emitting control subcircuit and the driving subcircuit are controlled to cooperate to turn on the first voltage terminal and the second voltage terminal to drive the light-emitting device to emit light.

13. The driving method according to claim 12, wherein: The light-emitting device is arranged between the first voltage terminal and the fourth node, the pixel circuit further includes a third light-emitting control subcircuit, the control terminal of the third light-emitting control subcircuit is electrically connected to the second light-emitting control line, the first terminal of the third light-emitting control subcircuit is electrically connected to the third node, and the second terminal of the third light-emitting control subcircuit is electrically connected to the second voltage terminal; The driving method further includes: In the reset phase, under the control of the second light emitting control line, the second light emitting control subcircuit is controlled to write the second voltage received from the second voltage terminal into the third node; In the light emitting stage, under the control of the second scan line, the second voltage terminal is controlled to be connected to the third node.

14. The driving method according to claim 11, wherein: The sampling phase at least partially overlaps with the data writing phase.

15. A display panel, characterized in that: include: A plurality of pixel circuits according to any one of claims 1 to 10, and A light emitting device is electrically connected to the pixel circuit.

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