Radiation-hardened SiC super-junction JFET structure and preparation method

Abstract

A kind of anti-radiation reinforced SiC super-junction JFET structure and preparation method, from bottom to top are in order: drain metallization layer, N+ substrate layer, N buffer layer, P column region, N column region, P-base region, current expansion region, N+ source region, P+ gate region, isolation dielectric layer, gate metallization layer, source metallization layer.P column region and N column region are arranged alternately on the upper surface of N buffer layer, P column region is symmetrically arranged, and N column region is arranged between two P column regions.P column region and P-base region form a P-type doped region as a whole, and are connected with source metallization layer.Electrically conductive channel structure is formed between P+ gate region and P-base region, and the opening and closing of channel are realized by controlling the voltage on P+ gate region.The application effectively solves the problem of electric field concentration caused by high-energy charged particle bombardment in the device, reduces local high temperature, and greatly improves the anti-single-particle radiation capability of SiC JFET.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, specifically relating to a radiation-hardened SiC superjunction JFET structure and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) is a wide-bandgap semiconductor material with advantages such as high critical breakdown electric field, high thermal conductivity, and strong radiation resistance. Silicon carbide junction field-effect transistors (SiC JFETs) are high-voltage power devices made of SiC. They do not have the reliability limitations of SiC MOSFETs due to their gate oxide layer and exhibit high channel electron mobility. Therefore, SiC JFETs are particularly suitable for power electronic systems requiring high temperature, high frequency, and high reliability.

[0003] When power semiconductor devices are used in space, they are mainly affected by two different types of radiation effects: total dose (TID) and single-event effect (SEE). Since SiC JFETs have no gate oxide layer, the TID effect is negligible. Single-event burn-out (SEB) is one type of single-event effect that leads to permanent failure of SiC JFETs.

[0004] SiC JFETs are depletion-mode devices, requiring a negative voltage to be applied to the gate PN junction to keep them in a blocking state. When high-energy charged particles bombard a SiC JFET in the blocking state, they collide and ionize in the depletion region inside the device, generating a large number of electron-hole pairs. Under the combined influence of the negative gate bias voltage and the positive drain bias voltage, the electrons and holes move rapidly in opposite directions, creating a strong positive feedback electric field on the gate and drain sides. This causes a sharp increase in local lattice temperature, leading to device burn-out failure. Therefore, how to harden SiC JFETs to resist single-event burn-out has become a pressing problem for aerospace applications.

[0005] like Figure 1 The diagram shown is a schematic of a traditional planar SiC JFET structure, which can be used as a comparative device of the present invention. It includes a P+ gate region 1, an N+ source region 2, a P-base region 4, an N-drift region 04, an N+ substrate layer 8, a drain metallization layer 9, a gate metallization layer 10, a source metallization layer 11, and an isolation dielectric layer 12, wherein the P-base region 4 is internally connected to the P+ gate region 1. Summary of the Invention

[0006] The technical problem solved by this application is to overcome the shortcomings of the prior art and provide a radiation-hardened SiC superjunction JFET structure to solve the problem of single-particle burn-out caused by high-energy charged particle radiation in space applications.

[0007] The technical solution provided in this application is as follows:

[0008] In one aspect, a radiation-hardened SiC superjunction JFET structure is provided, comprising:

[0009] Drain metallization layer;

[0010] An N+ substrate layer is located on the upper surface of the drain metallization layer;

[0011] An N-buffer layer is located on the upper surface of the N+ substrate layer;

[0012] P-pillar areas and N-pillar areas are alternately arranged on the upper surface of the N buffer layer. The P-pillar areas are symmetrically arranged on the left and right, and the N-pillar areas are arranged between the two P-pillar areas. The width of the P-pillar area is 1 / 2 of the width of the N-pillar area, and the width of the P-pillar area and the N-pillar area are the same.

[0013] The P-base region is located on the upper surface of a portion of the P-pillar region and a portion of the N-pillar region.

[0014] The current extension region is located on the upper surface of a portion of the N-pillar region and a portion of the P-base region;

[0015] The N+ source region is located on the upper surface of a portion of the P-base region;

[0016] The P+ gate region is located on the upper surface of a portion of the current extension region, and its top is flush with the top of the N+ source region.

[0017] A gate metallization layer (10) is located on the upper surface of a portion of the P+ gate region;

[0018] The source trench extends through the N+ source region and the P-base region, with the bottom of the trench contacting the P-pillar region.

[0019] The source metallization layer (11) is located inside the source trench and on the upper surface of the N+ source region, and is in contact with the N+ source region, the P-base region and the P-pillar region;

[0020] An isolation dielectric layer (12) is located on the upper surface of the current extension region, the P+ gate region, and the gate metallization layer (10), and isolates the gate metallization layer (10) and the source metallization layer (11).

[0021] The P-pillar region and the P-base region together form a P-type doped region, which is connected to the source metallization layer.

[0022] A conductive channel structure is formed between the P+ gate region and the P-base region. The channel is turned on and off by controlling the voltage on the P+ gate region.

[0023] Preferably, the current extension region is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 0.7μm to 3μm.

[0024] Preferably, the N+ source region is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3 The thickness is 0.2μm to 1μm.

[0025] Preferably, the P+ gate region is made of P-type SiC, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.05μm to 0.5μm.

[0026] Preferably, the P-base region is made of P-type SiC, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 17 ~5×10 18 cm -3 The thickness is 0.5μm to 2μm.

[0027] Preferably, the P-pillar region is made of P-type SiC, doped by P-type ion implantation, and the doping element is aluminum or boron with a doping concentration of 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 5μm to 60μm.

[0028] Preferably, the N-pillar region is made of N-type SiC, with N-type epitaxial doping, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 5μm to 60μm.

[0029] Preferably, the N-buffer layer is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 17 ~1×10 19 cm -3 The thickness is 2μm to 20μm.

[0030] Preferably, the N+ substrate is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3The thickness ranges from 50μm to 300μm.

[0031] Secondly, a method for fabricating a radiation-hardened SiC superjunction JFET structure is provided, the method including but not limited to the following steps:

[0032] ① An N-type buffer layer is epitaxially grown on a heavily doped SiC N+ substrate;

[0033] ② By repeatedly growing N-type doped regions on the epitaxial layer and then performing high-energy ion implantation on the grown epitaxial layer to generate P-type doped regions, P-pillar regions and N-pillar regions are formed, and the thickness of the P / N pillar regions is kept consistent.

[0034] ③ An N-type epitaxial layer is grown on the upper surface of the P-pillar region and the N-pillar region. A mask is prepared to block part of the upper surface of the N-type epitaxial layer and ion implantation is performed to form the P-base region.

[0035] ④ Based on the previous step, another N-type epitaxial layer with the same doping concentration is grown epitaxially to form a complete current spread region. A mask is prepared, and the N+ source region and P+ gate region are formed by photolithography and high-energy ion implantation.

[0036] ⑤ Prepare a mask and use photolithography and etching processes to etch source trenches from the upper surface of the N+ source region. The trenches penetrate the N+ source region and the P-base region, and the bottom contacts the upper surface of the P-pillar region.

[0037] ⑥ Deposit gate metal above the P+ gate region to form a gate metallization layer. Grow passivation protection medium outside the gate metallization layer to form an isolation protection layer. Deposit source metal in the source trench. Reverse etch the metal to form a source metallization layer. Thin, metallize and laser anneal the SiC N+ substrate from the back side to form a drain metallization layer.

[0038] Preferably, in step ②, the number of epitaxial cycles required to form the P / N pillar region and the thickness of the N-type epitaxial layer grown in each epitaxial growth are determined according to the voltage rating of the designed device. The thickness of each epitaxial growth is within 1μm to 5μm, ensuring device performance while improving process feasibility.

[0039] In summary, this application includes at least the following beneficial technical effects:

[0040] 1. When high-energy charged particles pass through a device in a blocked state, a large number of holes generated by collision ionization in the depletion region can quickly move to the source through the P-pillar region and P-base region, reducing the number of holes accumulated on the gate, alleviating the strong electric field on the gate side, and effectively reducing the local high temperature on the gate side.

[0041] 2. The N buffer layer suppresses the avalanche of the high-low junction between the N+ substrate and the N pillar region caused by the bombardment of high-energy charged particles, alleviates the strong electric field on the drain side, and effectively reduces the local high temperature on the drain side.

[0042] 3. The P-pillar and N-pillar regions form a superjunction structure, which further reduces the on-resistance and improves the electrical performance of the device without changing the withstand voltage and leakage current.

[0043] In other words, without affecting the device's withstand voltage and leakage current, this invention effectively solves the problem of electric field concentration inside the device caused by high-energy charged particle radiation, reduces local high temperature, and greatly improves the single-event radiation resistance of SiC JFET. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of a unit cell of a traditional planar SiC JFET structure.

[0045] Figure 2 This is a schematic diagram of the unit cell of the radiation-hardened SiC superjunction JFET structure of the present invention.

[0046] Figure 3 This is a schematic diagram of the multi-cell structure of the radiation-hardened SiC superjunction JFET of the present invention.

[0047] Figures 4 to 9 This is a schematic diagram of the fabrication process of the radiation-hardened SiC superjunction JFET structure of the present invention. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments disclosed in the present invention will be described in further detail below with reference to the accompanying drawings.

[0049] This application discloses a radiation-hardened SiC superjunction JFET structure, such as... Figure 2 and Figure 3 As shown, it includes multiple parallel cells, each cell including: drain metallization layer 9, N+ substrate layer 8, N buffer layer 7, P pillar region 5, N pillar region 6, P-base region 4, current spread region 3, N+ source region 2, P+ gate region 1, gate metallization layer 10, source metallization layer 11, and isolation dielectric layer 12.

[0050] The N+ substrate layer 8 is located on the upper surface of the drain metallization layer 9; the N buffer layer 7 is located on the upper surface of the N+ substrate layer 8; P-pillar regions 5 and N-pillar regions 6 are alternately arranged on the upper surface of the N buffer layer 7, with the P-pillar regions 5 arranged symmetrically on the left and right sides, and the N-pillar regions 6 are located between the two P-pillar regions 5. The direction in which the P-pillar regions 5 and N-pillar regions 6 are alternately arranged is their width direction. The width of the P-pillar region 5 is 1 / 2 of the width of the N-pillar region 6, so that in the state of multiple cells connected in parallel, the entire P-pillar region formed by the P-pillar regions 5 of two cells has the same width as the N-pillar region 6; the P-base region 4 is located at the junction of the upper surfaces of the P-pillar regions 5 and N-pillar regions 6, and there is a gap between two adjacent P-base regions 4.

[0051] The current extension region 3 is located above the middle of the N-pillar region 6. The two sides of the current extension region 3 are in contact with the P-base region 4. The thickness of the current extension region 3 is greater than that of the P-base region 4, and the current extension region 3 covers part of the upper surface of the P-base region 4. The N+ source region 2 is located on the upper surface of the P-base region 4, and the N+ source region 2 is located on both sides of the current extension region 3. The N+ source region 2 and the current extension region 3 together cover the entire upper surface of the P-base region 4. The upper surface of the N+ source region 2 is flush with the upper surface of the current extension region 3. The P+ gate region 1 is located in the recessed position in the middle of the current extension region 3. The top of the P+ gate region 1 is flush with the top of the N+ source region 2 and the top of the current extension region 3.

[0052] The gate metallization layer 10 is located in the middle of the upper surface of the P+ gate region 1. The direction along which the P-pillar region 5 and the N-pillar region 6 are alternately arranged is the width direction of the P+ gate region 1 and the gate metallization layer 10. The width of the gate metallization layer 10 is smaller than the width of the P+ gate region 1. The isolation dielectric layer 12 is located in the current extension region 3, a part of the P+ gate region 1 and the upper surface of the gate metallization layer 10.

[0053] A source trench is provided on the side of N+ source region 2 and P-base region 4 away from current extension region 3. The source trench extends through the thickness direction of N+ source region 2 and P-base region 4, and the bottom of the source trench contacts the surface of P-pillar region 5. A source metallization layer 11 is disposed inside the source trench. The thickness of the source metallization layer 11 is greater than the depth of the source trench, so that the source metallization layer 11 covers the upper surface of N+ source region 2. The source metallization layer 11 contacts N+ source region 2, P-base region 4, P-pillar region 5 and isolation dielectric layer 12. The isolation dielectric layer 12 isolates the gate metallization layer 10 and the source metallization layer 11.

[0054] The P-pillar region 5 and the P-base region 4 together form a P-type doped region and are connected to the source metallization layer 11. A conductive channel structure is formed between the P+ gate region 1 and the P-base region 4. The channel is turned on and off by controlling the voltage on the P+ gate region 1.

[0055] Preferably, the current extension region 3 is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 0.7μm to 3μm.

[0056] Preferably, the N+ source region 2 is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3 The thickness is 0.2μm to 1μm.

[0057] Preferably, the P+ gate region 1 is made of P-type SiC, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.05μm to 0.5μm.

[0058] Preferably, the material of P-base region 4 is P-type SiC, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 17 ~5×10 18 cm -3 The thickness is 0.5μm to 2μm.

[0059] Preferably, the P-pillar region 5 is made of P-type SiC, doped by P-type ion implantation, and the doping element is aluminum or boron with a doping concentration of 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 5μm to 60μm.

[0060] Preferably, the N-pillar region 6 is made of N-type SiC, with N-type epitaxial doping, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 5μm to 60μm.

[0061] Preferably, the N-buffer layer 7 is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 17 ~1×10 19 cm -3 The thickness is 2μm to 20μm.

[0062] Preferably, the N+ substrate layer 8 is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3The thickness ranges from 50μm to 300μm.

[0063] Figures 4 to 8 This is a schematic diagram of the fabrication process of a radiation-hardened SiC superjunction JFET structure according to the present invention. The specific fabrication process includes:

[0064] Step 1: Epitaxially grow an N-type buffer layer 7 on a heavily doped SiC N+ substrate layer 8, with a doping concentration of 1×10⁻⁶. 17 ~1×10 19 cm -3 The thickness is 2μm to 20μm, such as Figure 4 As shown;

[0065] Step 2: A method of multiple epitaxial growth of N-type doped regions and high-energy particle implantation on the grown epitaxial layer to generate P-type doped regions is used to form P-pillar region 5 and N-pillar region 6. The thickness of the P / N pillar regions is the same, ranging from 5 μm to 60 μm. The doping concentration of P-pillar region 6 is 1 × 10⁻⁶. 16 ~1×10 18 cm -3 The doping concentration of N-pillar region 5 is 1×10⁵. 16 ~1×10 18 cm -3 ,like Figure 5 As shown;

[0066] Step 3: An N-type epitaxial layer is grown on the upper surfaces of P-pillar region 6 and N-pillar region 5, with a doping concentration of 1×10⁻⁶. 16 ~1×10 18 cm -3 A mask with a thickness of 0.5 μm to 2 μm was prepared to partially block the upper surface of the N-type epitaxial layer. Ion implantation was then performed to form a P-base region 4 with a doping concentration of 1 × 10⁻⁶. 17 ~5×10 18 cm -3 ,like Figure 6 As shown;

[0067] Step 4: Based on Step 3, another N-type epitaxial layer with the same doping concentration is grown, with a thickness of 0.2 μm to 1 μm, forming a complete current spreading region 3. A mask is prepared, and the N+ source region 2 and P+ gate region 3 are formed by photolithography and high-energy ion implantation, as shown below. Figure 7 As shown;

[0068] ⑤ Prepare a photomask. Using photolithography and etching processes, etch source trenches from the upper surface of the N+ source region 2. The trenches penetrate the N+ source region 2 and the P-base region 4, with their bottoms contacting the upper surface of the P-pillar region 5. The thickness of the etched trenches is 0.7 μm to 3 μm. Figure 8 As shown;

[0069] ⑥ Deposit gate metal above P+ gate region 1 to form gate metallization layer 10. Grow passivation protection dielectric outside gate metallization layer 10 to form isolation dielectric layer 12. Deposit source metal in source trench. Reverse etch the metal to form source metallization layer 11. Thinning, metallizing, and laser annealing the SiC N+ substrate from the back side to form drain metallization layer, as shown below. Figure 9 As shown.

[0070] Preferably, in step 2, the number of epitaxial cycles required to form the P / N pillar region and the thickness of the N-type epitaxial layer grown in each epitaxial cycle are determined according to the voltage rating of the designed device. The thickness of each epitaxial cycle is within 1 μm to 5 μm, ensuring device performance while improving process feasibility.

[0071] In the SiC superjunction JFET structure of the present invention, when the gate metallization layer 10 (i.e., the gate) is in the on state, a zero voltage is applied to the gate metallization layer 10 (i.e., the gate), and a positive voltage is applied to the drain metallization layer 9 (i.e., the drain). At this time, the formed conduction path is sequentially the drain metallization layer 9, the N+ substrate layer 8, the N buffer layer 7, the N pillar region 6, the current extension region 3, the N+ source region 2, and the source metallization layer 11. When the gate is in the off state, a negative voltage is applied to the gate, and there is no conduction path.

[0072] In the SiC superjunction JFET structure obtained by the above method, in the blocking state, the P-pillar region 5 and the P-base region 4 together form a P-type doped region connected to the source metallization layer 10. A large number of holes generated by the collision and ionization of high-energy charged particles can quickly move to the source (i.e., the source metallization layer 11) through the P-pillar region 5 and the P-base region 4, reducing the number of holes accumulated on the gate, alleviating the strong electric field on the gate side, and effectively reducing the local high temperature on the gate side. The buffer layer 7 is disposed above the N+ substrate layer 8, suppressing the avalanche of the high-low junction between the N+ substrate layer 8 and the N-pillar region 6 caused by the bombardment of high-energy charged particles, alleviating the strong electric field on the drain side, and effectively reducing the local high temperature on the drain side. The P-pillar region 5 and the N-pillar region 6 form a superjunction structure, which further reduces the on-resistance and improves the electrical performance of the device without changing the breakdown voltage and leakage current. In other words, without affecting the device's withstand voltage and leakage current, this invention effectively solves the problem of electric field concentration inside the device caused by high-energy charged particle radiation, reduces local high temperature, and greatly improves the single-event radiation resistance of SiC JFET.

[0073] The contents not described in detail in this application specification are common knowledge to those skilled in the art.

[0074] The present application has been described in detail above with reference to specific embodiments and exemplary examples; however, these descriptions should not be construed as limiting the present application. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and implementation methods of the present application without departing from the spirit and scope of the present application, and all such modifications and improvements fall within the scope of the present application. The scope of protection of the present application is determined by the appended claims.

Claims

1. A radiation-hardened SiC superjunction JFET structure, characterized in that, It includes multiple parallel cells, each cell comprising: Drain metallization layer (9), N+ substrate layer (8) and N buffer layer (7) are arranged in sequence; P-pillar regions (5) and N-pillar regions (6) are alternately arranged on the side of the N buffer layer (7) away from the N+ substrate layer (8). The P-pillar region (5) consists of two parts, and the N-pillar region (6) is located between the two parts of the P-pillar region (5). The P-base region (4) is located at the junction of the P-pillar region (5) and the N-pillar region (6) on the side away from the N buffer layer (7), and there is a gap between two adjacent P-base regions (4). The current extension region (3) is located on the side of the N-pillar region (6) away from the N-buffer layer (7). The current extension region (3) is located between the two P-base regions (4) and covers the surface of the P-base region (4) away from the N-pillar region (6). The N+ source region (2) is located on the side of the P-base region (4) away from the P-pillar region (5), and the N+ source region (2) is located on both sides of the current extension region (3); The P+ gate region (1) is located in the recessed position in the middle of the surface of the current extension region (3) on the side away from the N pillar region (6); The gate metallization layer (10) is located in the middle of the P+ gate region (1) away from the surface of the P-base region (4); An isolation dielectric layer (12) is located on the surface of the current extension region (3) and the P+ gate region (1) away from the N pillar region (6), and the isolation dielectric layer (12) covers the gate metallization layer (10); The source trench is located on the side of the N+ source region (2) and the P-base region (4) away from the current extension region (3). The source trench extends through the thickness direction of the N+ source region (2) and the P-base region (4). The bottom of the source trench is in contact with the surface of the P-pillar region (5). The source metallization layer (11) is located in the source trench. The thickness of the source metallization layer (11) is greater than the depth of the source trench so that the source metallization layer (11) covers the upper surface of the N+ source region (2). The source metallization layer (11) is in contact with the N+ source region (2), the P-base region (4), the P-pillar region (5) and the isolation dielectric layer (12). The isolation dielectric layer (12) isolates the gate metallization layer (10) and the source metallization layer (11).

2. The radiation-hardened SiC superjunction JFET structure according to claim 1, characterized in that: The width of the P-pillar area (5) is half the width of the N-pillar area (6), and the widths of the P-pillar area (5) and the N-pillar area (6) are the same.

3. The radiation-hardened SiC superjunction JFET structure according to claim 1, characterized in that: The P-pillar region (5) and the P-base region (4) together form a P-type doped region, which is connected to the source metallization layer (11).

4. The radiation-hardened SiC superjunction JFET structure according to claim 1, characterized in that: A conductive channel structure is formed between the P+ gate region (1) and the P-base region (4), and the channel is turned on and off by controlling the voltage on the P+ gate region (1).

5. The radiation-hardened SiC superjunction JFET structure according to claim 1, characterized in that: The P-pillar region (5) is made of P-type SiC, doped by P-type ion implantation, and the doping element is aluminum or boron with a doping concentration of 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 5μm to 60μm; The N-pillar region (6) is made of N-type SiC, doped using N-type epitaxial doping, with nitrogen or phosphorus as the doping element and a doping concentration of 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 5μm to 60μm.

6. The radiation-hardened SiC superjunction JFET structure according to claim 1, characterized in that: The N-buffer layer (7) is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 17 ~1×10 19 cm -3 The thickness is 2μm to 20μm.

7. The radiation-hardened SiC superjunction JFET structure according to claim 1, characterized in that: The current extension region (3) is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 16 ~1×10 18 cm -3 The thickness is 0.7μm to 3μm.

8. The radiation-hardened SiC superjunction JFET structure according to claim 1, characterized in that: The N+ source region (2) is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3 The thickness is 0.2μm to 1μm; The P+ gate region (1) is made of P-type SiC, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 18 ~1×10 20 cm -3 The thickness is 0.05μm to 0.5μm; The P-base region (4) is made of P-type SiC, and the doping element is aluminum or boron, with a doping concentration of 1×10⁻⁶. 17 ~5×10 18 cm -3 The thickness is 0.5μm to 2μm; The N+ substrate (8) is made of N-type SiC, and the doping element is nitrogen or phosphorus, with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3 The thickness ranges from 50μm to 300μm.

9. A method for fabricating a radiation-hardened SiC superjunction JFET structure according to any one of claims 1-8, characterized in that, include: S1: An N buffer layer (7) is epitaxially grown on a heavily doped SiC N+ substrate (8); S2: On the surface of the N buffer layer (7) away from the N+ substrate layer (8), N-type doped regions are grown by multiple epitaxial growths, and P-type doped regions are generated by high-energy ion implantation on the grown epitaxial layer to form P-pillar regions (5) and N-pillar regions (6). S3: An N-type epitaxial layer is grown on the surface of the N-buffer layer (7) away from the P-pillar region (5) and the N-pillar region (6), with a doping concentration of 1×10⁻⁶. 16 ~1×10 18 cm -3 A mask with a thickness of 0.5μm to 2μm is prepared to block the middle part of the surface of the N-type epitaxial layer. Aluminum or boron ion implantation is performed to form a P-base region (4). A partial current extension region is formed at the mask blocking position (3). S4: Based on S3, another N-type epitaxial layer with the same doping concentration as in the previous step is grown, with a thickness of 0.2μm to 1μm, forming a complete current extension region (3). Then, a mask is prepared, and N+ source region (2) and P+ gate region (1) are formed by photolithography and high-energy ion implantation. S5: Prepare a mask and etch source trenches from the surface of the N+ source region (2) away from the P-base region (4) through photolithography and etching processes. The source trenches penetrate the N+ source region (2) and the P-base region (4), and the bottom of the source trenches contacts the upper surface of the P-pillar region (5). S6: Deposit gate metal on the surface of P+ gate region (1) away from P-base region (4) to form gate metallization layer (10), grow passivation protection medium on the outside of gate metallization layer (10) to form isolation medium layer (12), deposit source metal in source trench, reverse etch metal to form source metallization layer (11), thin, metallize and laser anneal the SiC N+ substrate from the back side to form drain metallization layer (9).

10. The preparation method according to claim 9, characterized in that: In step S2, the number of epitaxial growths required to form the P-pillar region (5) and the N-pillar region (6) and the thickness of the N-type epitaxial layer grown each time are both 1 μm to 5 μm.

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