Bandgap reference circuit, chip and electronic device

Abstract

The present invention discloses a bandgap reference circuit, chip and electronic device, and relates to the field of analog circuit technology; the circuit includes: an undervoltage startup module and a bandgap module, the undervoltage startup module includes a clamping module, an undervoltage module and an output drive module, and the bandgap module includes an output module, a bandgap core module, a feedback startup module and a power supply module; the clamping module is used to provide a protection voltage; the undervoltage module is used to output an undervoltage signal when the protection voltage increases to a first preset voltage under the action of a bias voltage; the output drive module is used to provide a bias voltage, and output a driving current and a logic control signal according to the undervoltage signal; the feedback startup module is used to output a first voltage according to the driving current and the logic control signal; the bandgap core module is used to output a second voltage according to the first voltage and the reference voltage under the action of a current source; the output module is used to output a stable reference voltage according to a stable first voltage. The circuit has a high startup speed and stability.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuits, and in particular to a bandgap reference circuit, a chip and an electronic device. Background Art

[0002] The bandgap reference circuit is an important basic module in the chip, providing accurate current and voltage references for other modules. The bandgap reference circuit has a very high demand for reliable startup methods and power supply suppression.

[0003] In the related art, the starting mode of the bandgap reference circuit is voltage drive, which is slow and unstable, and has no dual threshold protection. In the face of interference, the circuit is easily put into a repeated operation state of opening and closing, making the output unstable and generating signal noise, and the circuit is not reliable enough. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art to at least some extent. To this end, the purpose of the present invention is to provide a bandgap reference circuit, chip and electronic device to ensure that the startup speed and stability of the circuit meet the requirements.

[0005] To achieve the above-mentioned purpose, the first aspect of the present invention proposes a bandgap reference circuit, including: an undervoltage startup module and a bandgap module, the undervoltage startup module includes a voltage clamping module, an undervoltage module and an output driving module, and the bandgap module includes an output module, a bandgap core module, a feedback startup module and a power supply module; wherein the voltage clamping module is used to provide a protection voltage; the undervoltage module is used to output an undervoltage signal when the protection voltage increases to a first preset voltage under the action of a bias voltage; the output driving module is used to provide the bias voltage, and output a driving current and a logic control signal according to the undervoltage signal; the feedback startup module is used to output a first voltage according to the driving current and the logic control signal, and stabilize the first voltage according to a second voltage; the power supply module is used to provide a stable current source for the bandgap core module under the action of the first voltage; the bandgap core module is used to output the second voltage according to the first voltage and the reference voltage under the action of the current source; the output module is used to output a stable reference voltage according to the stable first voltage.

[0006] In addition, the bandgap reference circuit of the above embodiment of the present invention may also have the following additional technical features:

[0007] According to one embodiment of the present invention, the voltage clamping module includes a first diode, a second diode, a third diode and a fourth diode connected in series in sequence, the anode of the first diode is connected to the undervoltage module to provide the protection voltage, and the cathode of the fourth diode is grounded.

[0008] According to an embodiment of the present invention, the undervoltage module includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth diode and a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor; wherein the drain of the first PMOS tube is respectively connected to the drain of the second PMOS tube, one end of the first resistor, the drain of the third PMOS tube and a preset power supply; the gate of the first PMOS tube is respectively connected to the gate of the second PMOS tube, the other end of the first resistor and the gate of the third PMOS tube; the source of the first PMOS tube is connected to one end of the second resistor; the other end of the second resistor is connected to the anode of the fifth diode; the cathode of the fifth diode is connected to one end of the third resistor, the other end of the third resistor is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to one end of the sixth resistor, and the other end of the sixth resistor is grounded; The source of the second PMOS tube is connected to the drain of the fourth PMOS tube, the source of the third PMOS tube is connected to the drain of the fifth PMOS tube, the gate of the fourth PMOS tube is connected to the gate of the fifth PMOS tube, the source of the fourth PMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is grounded, the gate of the first NMOS tube is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the anode of the first diode; the source of the fifth PMOS tube is connected to the drain of the sixth PMOS tube, and the The gate of the sixth PMOS tube is respectively connected to the drain of the first NMOS tube and the gate of the second NMOS tube, the source of the sixth PMOS tube is connected to the drain of the second NMOS tube, and serves as the output end of the undervoltage signal; the source of the second NMOS tube is grounded, the gate of the second NMOS tube is connected to the gate of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to one end of the fifth resistor, the source of the fourth NMOS tube is grounded, the drain of the third NMOS tube is connected to one end of the sixth resistor, and the source of the third NMOS tube is grounded.

[0009] According to an embodiment of the present invention, the output driving module includes: a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a fifth NMOS tube, a sixth NMOS tube and an eighth resistor and a ninth resistor; wherein the drain of the seventh PMOS tube is connected to a preset power supply, the gate of the seventh PMOS tube is connected to the gate of the third PMOS tube, and the source of the seventh PMOS tube is used to output the driving current; one end of the eighth resistor is connected to the preset power supply, the other end of the eighth resistor is connected to the drain of the eighth PMOS tube, one end of the ninth resistor is connected to the preset power supply, and the other end of the ninth resistor is connected to the gate of the ninth PMOS tube respectively. The drain and gate are connected, the source of the ninth PMOS tube is grounded, and the gate of the eighth PMOS tube is respectively connected to the gate of the fourth PMOS tube and the gate of the ninth PMOS tube to provide the bias voltage; the source of the eighth PMOS tube is connected to the drain of the tenth PMOS tube, the gate of the tenth PMOS tube is connected to the gate of the fifth NMOS tube and is used to input the undervoltage signal, the source of the tenth PMOS tube is respectively connected to the gate of the sixth NMOS tube, the gate of the third NMOS tube and the drain of the fifth NMOS tube and is used to output the logic control signal, the source of the fifth NMOS tube is grounded, and the source of the sixth NMOS tube is grounded.

[0010] According to an embodiment of the present invention, the power supply module includes: an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, and a seventh and an eighth NMOS tube; wherein the drain of the eleventh PMOS tube is connected to a preset power supply, the source and the gate of the eleventh PMOS tube are connected to the drain of the seventh NMOS tube, the source of the seventh NMOS tube is grounded, the gate of the seventh NMOS tube is respectively connected to the drain, the gate of the eighth NMOS tube and the source of the thirteenth PMOS tube, the source of the eighth NMOS tube is grounded, the drain of the thirteenth PMOS tube is connected to the source of the twelfth PMOS tube, the drain of the twelfth PMOS tube is used to input the first voltage, and the gates of the eleventh PMOS tube, the twelfth PMOS tube and the thirteenth PMOS tube are used to provide the current source.

[0011] According to one embodiment of the present invention, the feedback startup module includes: a fourteenth PMOS tube, a fifteenth PMOS tube and a ninth NMOS tube; wherein the drain of the fourteenth PMOS tube is connected to the preset power supply, the gate of the fourteenth PMOS tube is respectively connected to the gate and source of the eleventh PMOS tube, the source of the fourteenth PMOS tube is connected to the drain and gate of the fifteenth PMOS tube, and is used to output the first voltage, the source of the fifteenth PMOS tube is connected to the drain of the ninth NMOS tube, the source of the ninth NMOS tube is grounded, and the gate of the ninth NMOS tube is used to input the second voltage.

[0012] According to one embodiment of the present invention, the bandgap core module includes: a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a first triode, a second triode, a tenth resistor, and an eleventh resistor; wherein the drain of the sixteenth PMOS tube is connected to the drain of the twelfth PMOS tube and the seventeenth PMOS tube, and is used to input the first voltage, the gate of the sixteenth PMOS tube is respectively connected to the gate of the seventeenth PMOS tube and the gate of the twelfth PMOS tube, the source of the sixteenth PMOS tube is connected to the drain of the eighteenth PMOS tube, the source of the seventeenth PMOS tube is connected to the nineteenth PMOS tube, and the The drain of the eighteenth PMOS tube is connected to the drain of the S tube, the source of the eighteenth PMOS tube is connected to the collector of the first triode, the gate of the eighteenth PMOS tube is respectively connected to the gate of the nineteenth PMOS tube and the gate of the thirteenth PMOS tube, the source of the nineteenth PMOS tube is respectively connected to the collector of the second triode and the gate of the ninth NMOS tube, the base of the first triode is connected to the base of the second triode and is used to input the reference voltage, the emitter of the first triode is connected to one end of the tenth resistor, the other end of the tenth resistor is respectively connected to the emitter of the second triode and one end of the eleventh resistor, and the other end of the eleventh resistor is grounded.

[0013] According to one embodiment of the present invention, the output module includes: a tenth NMOS tube, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor; wherein, one end of the twelfth resistor is connected to a preset power supply, the other end of the twelfth resistor is connected to the drain of the tenth NMOS tube, the gate of the tenth NMOS tube is used to input the first voltage, the source of the tenth NMOS tube is connected to one end of the thirteenth resistor, the other end of the thirteenth resistor is connected to one end of the fourteenth resistor and is used to output the reference voltage, and the other end of the fourteenth resistor is grounded.

[0014] To achieve the above object, a second embodiment of the present invention provides a chip, including: the above-mentioned bandgap reference circuit.

[0015] To achieve the above-mentioned purpose, a third aspect of the present invention provides an electronic device, including: the above-mentioned chip.

[0016] The bandgap reference circuit, chip and electronic device of the embodiments of the present invention have high startup speed and stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a structural block diagram of a bandgap reference circuit according to an embodiment of the present invention;

[0018] Figure 2 is a circuit topology diagram of a bandgap reference circuit according to an embodiment of the present invention;

[0019] Figure 3 is a structural block diagram of a chip according to an embodiment of the present invention;

[0020] Figure 4 It is a structural block diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0022] The bandgap reference circuit, chip and electronic device according to the embodiments of the present invention are described below with reference to the accompanying drawings.

[0023] Figure 1 4 is a structural block diagram of a bandgap reference circuit according to an embodiment of the present invention.

[0024] like Figure 1 As shown, the bandgap reference circuit 100 includes: an undervoltage startup module 101 and a bandgap module 102, the undervoltage startup module 101 includes a clamping module 1011, an undervoltage module 1012 and an output driving module 1013, and the bandgap module 102 includes an output module 1021, a bandgap core module 1022, a feedback startup module 1023 and a power supply module 1024.

[0025] Among them, the clamping module 1011 is used to provide a protection voltage; the undervoltage module 1012 is used to output an undervoltage signal when the protection voltage increases to a first preset voltage under the action of the bias voltage Vbias; the output drive module 1013 is used to provide the bias voltage Vbias, and output the drive current Istart and the logic control signal VE according to the undervoltage signal.

[0026] The feedback start module 1023 is used to output a first voltage VF according to the driving current Istart and the logic control signal VE, and stabilize the first voltage VF according to the second voltage; the power supply module 1024 is used to provide a stable current source for the bandgap core module 1022 under the action of the first voltage VF; the bandgap core module 1022 is used to output a second voltage according to the first voltage VF and the reference voltage Voutput under the action of the current source; the output module 1021 is used to output a stable reference voltage Voutput according to the stable first voltage VF.

[0027] The bandgap reference circuit of the embodiment of the present invention has higher startup speed and stability.

[0028] In some embodiments, Figure 2 As shown, the clamping module 1011 includes a first diode D1, a second diode D2, a third diode D3 and a fourth diode D4 connected in series in sequence. The anode of the first diode D1 is connected to the undervoltage module 1012 to provide a protection voltage, and the cathode of the fourth diode D4 is grounded VSS.

[0029] In some embodiments, Figure 2 As shown, the undervoltage module 1012 includes: a first PMOS transistor MP1 to a sixth PMOS transistor MP6, a first NMOS transistor MN1 to a fourth NMOS transistor MN4, a fifth diode D5, and a first resistor R1 to a seventh resistor R7.

[0030] The drain of the first PMOS tube MP1 is respectively connected to the drain of the second PMOS tube MP2, one end of the first resistor R1, the drain of the third PMOS tube MP3 and the preset power supply VCC; the gate of the first PMOS tube MP1 is respectively connected to the gate of the second PMOS tube MP2, the other end of the first resistor R1 and the gate of the third PMOS tube MP3; the source of the first PMOS tube MP1 is connected to one end of the second resistor R2; the other end of the second resistor R2 is connected to the anode of the fifth diode D5; the cathode of the fifth diode D5 is connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to one end of the fifth resistor R5, the other end of the fifth resistor R5 is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is grounded to VSS; the source of the second PMOS tube MP2 is connected to the drain of the fourth PMOS tube MP4, the source of the third PMOS tube MP3 is connected to the drain of the fifth PMOS tube MP5, the gate of the fourth PMOS tube MP4 and the gate of the fifth PMOS tube MP5 are connected to the gate of the fifth PMOS tube MP6, and the gate of the fifth PMOS tube MP5 is connected to the gate of the fifth PMOS tube MP6. The gate of the fourth PMOS transistor MP4 is connected to the drain of the first NMOS transistor MN1, the source of the first NMOS transistor MN1 is connected to the ground VSS, the gate of the first NMOS transistor MN1 is connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is connected to the anode of the first diode D1; the source of the fifth PMOS transistor MP5 is connected to the drain of the sixth PMOS transistor MP6, the gate of the sixth PMOS transistor MP6 is respectively connected to the drain of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2, the source of the sixth PMOS transistor MP6 is connected to the drain of the second NMOS transistor MN2, and serves as the output end of the undervoltage signal; the source of the second NMOS transistor MN2 is connected to the ground VSS, the gate of the second NMOS transistor MN2 is connected to the gate of the fourth NMOS transistor MN4, the drain of the fourth NMOS transistor MN4 is connected to one end of the fifth resistor R5, the source of the fourth NMOS transistor MN4 is connected to the ground VSS, the drain of the third NMOS transistor MN3 is connected to one end of the sixth resistor R6, and the source of the third NMOS transistor MN3 is connected to the ground VSS.

[0031] In some embodiments, Figure 2 As shown, the output driving module 1013 includes: a seventh PMOS transistor MP7 to a tenth PMOS transistor MP10, a fifth NMOS transistor MN5 to a sixth NMOS transistor MN6, and an eighth resistor R8 to a ninth resistor R9.

[0032] Among them, the drain of the seventh PMOS tube MP7 is connected to the preset power supply VCC, the gate of the seventh PMOS tube MP7 is connected to the gate of the third PMOS tube MP3, and the source of the seventh PMOS tube MP7 is used to output the driving current Istart; one end of the eighth resistor R8 is connected to the preset power supply VCC, the other end of the eighth resistor R8 is connected to the drain of the eighth PMOS tube MP8, one end of the ninth resistor R9 is connected to the preset power supply VCC, the other end of the ninth resistor R9 is respectively connected to the drain and gate of the ninth PMOS tube MP9, the source of the ninth PMOS tube MP9 is grounded VSS, and the gate of the eighth PMOS tube MP8 is respectively connected to the fourth PMOS The gate of the S transistor MP4 is connected to the gate of the ninth PMOS transistor MP9 to provide a bias voltage Vbias; the source of the eighth PMOS transistor MP8 is connected to the drain of the tenth PMOS transistor MP10, the gate of the tenth PMOS transistor MP10 is connected to the gate of the fifth NMOS transistor MN5 and is used to input an undervoltage signal, the source of the tenth PMOS transistor MP10 is respectively connected to the gate of the sixth NMOS transistor MN6, the gate of the third NMOS transistor MN3 and the drain of the fifth NMOS transistor MN5 and is used to output a logic control signal VE, the source of the fifth NMOS transistor MN5 is grounded to VSS, and the source of the sixth NMOS transistor MN6 is grounded to VSS.

[0033] Specifically, Figure 2 As shown, as the preset power supply VCC voltage increases, the voltage VA at point A increases, generating a bias voltage Vbias. The output driver module 1013 provides the bias voltage Vbias to the undervoltage module 1012, and outputs a drive current Istart and a logic control signal VE.

[0034] In some embodiments, the power supply module 1024 includes: an eleventh PMOS transistor MP11 to a thirteenth PMOS transistor MP13 and a seventh NMOS transistor MN7 to an eighth NMOS transistor MN8 .

[0035] Among them, the drain of the eleventh PMOS tube MP11 is connected to the preset power supply VCC, the source and the gate of the eleventh PMOS tube MP11 are connected to the drain of the seventh NMOS tube MN7, the source of the seventh NMOS tube MN7 is grounded to VSS, the gate of the seventh NMOS tube MN7 is respectively connected to the drain and the gate of the eighth NMOS tube MN8 and the source of the thirteenth PMOS tube MP13, the source of the eighth NMOS tube MN8 is grounded to VSS, the drain of the thirteenth PMOS tube MP13 is connected to the source of the twelfth PMOS tube MP12, the drain of the twelfth PMOS tube MP12 is used to input the first voltage VF, and the gates of the eleventh PMOS tube MP11, the twelfth PMOS tube MP12 and the thirteenth PMOS tube MP13 are used to provide a current source.

[0036] In some embodiments, the feedback start module 1023 includes: a fourteenth PMOS transistor MP14 to a fifteenth PMOS transistor MP15 and a ninth NMOS transistor MN9 .

[0037] Among them, the drain of the fourteenth PMOS tube MP14 is connected to the preset power supply VCC, the gate of the fourteenth PMOS tube MP14 is respectively connected to the gate and source of the eleventh PMOS tube MP11, the source of the fourteenth PMOS tube MP14 is connected to the drain and gate of the fifteenth PMOS tube MP15, and is used to output the first voltage VF, the source of the fifteenth PMOS tube MP15 is connected to the drain of the ninth NMOS tube MN9, the source of the ninth NMOS tube MN9 is grounded VSS, and the gate of the ninth NMOS tube MN9 is used to input the second voltage.

[0038] In some embodiments, the bandgap core module 1022 includes: a sixteenth PMOS transistor MP16 to a nineteenth PMOS transistor MP19, a first transistor Q1 to a second transistor Q2, and a tenth resistor R10 to an eleventh resistor R11. Among them, the drain of the sixteenth PMOS transistor MP16 is connected to the drain of the twelfth PMOS transistor MP12 and the seventeenth PMOS transistor MP17, and is used to input the first voltage VF, the gate of the sixteenth PMOS transistor MP12 is respectively connected to the gate of the seventeenth PMOS transistor MP17 and the gate of the twelfth PMOS transistor MP12, the source of the sixteenth PMOS transistor MP16 is connected to the drain of the eighteenth PMOS transistor MP18, the source of the seventeenth PMOS transistor MP17 is connected to the drain of the nineteenth PMOS transistor MP19, the source of the eighteenth PMOS transistor MP18 is connected to the collector of the first transistor Q1, and the eighteenth PMOS transistor MP18 is connected to the collector of the first transistor Q2. The gate of the OS transistor MP18 is connected to the gate of the nineteenth PMOS transistor MP19 and the gate of the thirteenth PMOS transistor MP13 respectively, the source of the nineteenth PMOS transistor MP19 is connected to the collector of the second transistor Q2 and the gate of the ninth NMOS transistor MN9 respectively, the base of the first transistor Q1 is connected to the base of the second transistor Q2 and is used to input the reference voltage Voutput, the emitter of the first transistor Q1 is connected to one end of the tenth resistor R10, the other end of the tenth resistor R10 is connected to the emitter of the second transistor Q2 and one end of the eleventh resistor R11 respectively, and the other end of the eleventh resistor R11 is grounded VSS.

[0039] Specifically, Figure 2As shown, when the preset power supply VCC voltage gradually increases to the first preset voltage, the voltage at point B gradually increases until the gate-source voltage of the first NMOS tube MN1 is greater than the threshold voltage, the first NMOS tube MN1 is turned on, the voltage at point C VC decreases, the voltage at point D VD is output as a high level, the voltage at point E VE is output as a low level, the sixth NMOS tube MN6 is a logic control device, when the voltage at point E VE is a low level, the sixth NMOS tube MN6 is turned off, and the bandgap core module 1022 can work normally. At the same time, the seventh PMOS tube MP7 copies the driving current Istart of the third PMOS tube MP3, and inputs the driving current Istart to the bandgap core module 1022. That is to say, the above-mentioned logic control signal VE is the voltage at point E.

[0040] In some embodiments, the output module 1021 includes: a tenth NMOS transistor MN10 and a twelfth resistor R12 to a fourteenth resistor R14.

[0041] Among them, one end of the twelfth resistor R12 is connected to the preset power supply VCC, the other end of the twelfth resistor R12 is connected to the drain of the tenth NMOS transistor MN10, the gate of the tenth NMOS transistor MN10 is used to input the first voltage VF, the source of the tenth NMOS transistor MN10 is connected to one end of the thirteenth resistor R13, the other end of the thirteenth resistor R13 is connected to one end of the fourteenth resistor R14 and is used to output the reference voltage Voutput, and the other end of the fourteenth resistor R14 is grounded VSS.

[0042] Specifically, Figure 2 As shown, the voltage VF at point F increases, the tenth NMOS transistor MN10 is turned on, the voltage VG at the control terminals of Q1 and Q2 increases, the first transistor Q1 and the second transistor Q2 are turned on, and the bandgap core module 1022 can work normally. In other words, the first voltage VF is the voltage at point F. The second voltage can be the voltage at the control terminal of MN9.

[0043] In addition, the ratio of Q2 to Q1 can be set to 1:N. Figure 2 Taking an example for explanation, the number of Q2 is set to 1, and the number of Q1 is set to N, and the collectors of the N Q1s are connected to the source of the eighteenth PMOS tube MP18 and the collector of the first transistor Q1, the bases of the N Q1s are connected to the base of the second transistor Q2 and are used to input the reference voltage Voutput, and the emitters of the N Q1s are connected to one end of the tenth resistor R10.

[0044] VG is the output voltage of the output module 1021, VG=Voutput, as shown in the following formula:

[0045] VG=2VT·lnN·R11 / R10+Vbe_Q1

[0046] Wherein, VT is the thermal voltage, N is the ratio of the number of Q1 and Q2, R11 is the resistance of the eleventh resistor R11, R10 is the resistance of the tenth resistor R10, and Vbe_Q1 is the voltage between the base and the emitter of the first transistor Q1.

[0047] The feedback start-up module 1023 can avoid the influence of the fluctuation of the voltage VF at the F point on VG and improve the stability of VG. The feedback loop is: the increase of the voltage VF at the F point leads to the increase of the second voltage, which leads to the increase of the gate-source voltage VGS of the ninth NMOS tube MN9, making the voltage VF at the F point lower, thus making the voltage VF at the F point tend to be stable and reducing the power supply rejection ratio.

[0048] The power supply module 1024 provides a stable current source for the bandgap core module 1022. The twelfth PMOS tube MP12 and the thirteenth PMOS tube MP13 mirror the currents of the sixteenth PMOS tube MP16 and the eighteenth PMOS tube MP18. The seventh NMOS tube MN7 mirrors the current of the eighth NMOS tube MN8. The fourteenth PMOS tube MP14 mirrors the current of the eleventh PMOS tube MP11.

[0049] When the entire bandgap core module 1022 is in normal operation, the first PMOS tube MP1 mirrors the current of the second PMOS tube MP2, and the voltage VB at point B increases. At the same time, the voltage VC at point C and the voltage VE at point E are at low potentials, the fourth NMOS tube MN4 and the third NMOS tube MN3 are turned off, and the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 are connected in series, and the resistance value increases, further increasing the voltage VB at point B. Therefore, the voltage of the preset power supply VCC needs to be reduced to a lower value, that is, the second preset voltage (the second preset voltage is less than the first preset voltage), in order to close the circuit. At this time, the voltage VE at point E is at a high potential, reducing the voltage VF at point F, and the bandgap core module 1022 stops working.

[0050] In summary, the bandgap reference circuit of the embodiment of the present invention adopts current start-up, can be started more quickly, and has the effect of dual threshold protection, that is, when the preset power supply VCC voltage increases from 0 to the first preset voltage, the bandgap reference circuit is turned on, and after being turned on, the preset power supply VCC voltage needs to be reduced to the second preset voltage to turn off the bandgap reference circuit.

[0051] Figure 3 It is a structural block diagram of a chip according to an embodiment of the present invention.

[0052] like Figure 3 As shown, the chip 300 includes: the above-mentioned bandgap reference circuit 100 .

[0053] Figure 4 It is a structural block diagram of an electronic device according to an embodiment of the present invention.

[0054] like Figure 4 As shown, the electronic device 400 includes: the above-mentioned chip 300.

[0055] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0056] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0057] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0058] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0059] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0061] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A bandgap reference circuit, characterized in that: include: An undervoltage startup module and a bandgap module, wherein the undervoltage startup module includes a clamping module, an undervoltage module and an output driving module, and the bandgap module includes an output module, a bandgap core module, a feedback startup module and a power supply module; wherein, The clamping module is used to provide a protection voltage; the undervoltage module is used to output an undervoltage signal when the protection voltage increases to a first preset voltage under the action of a bias voltage; the output drive module is used to provide the bias voltage and output a drive current and a logic control signal according to the undervoltage signal; The feedback startup module is used to output a first voltage according to the driving current and the logic control signal, and stabilize the first voltage according to a second voltage; the power supply module is used to provide a stable current source for the bandgap core module under the action of the first voltage; the bandgap core module is used to output the second voltage according to the first voltage and a reference voltage under the action of the current source; the output module is used to output a stable reference voltage according to the stable first voltage; The voltage clamping module comprises a first diode, a second diode, a third diode and a fourth diode connected in series in sequence, the anode of the first diode is connected to the undervoltage module to provide the protection voltage, and the cathode of the fourth diode is grounded; The undervoltage module includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth diode and a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor; wherein, The drain of the first PMOS tube is respectively connected to the drain of the second PMOS tube, one end of the first resistor, the drain of the third PMOS tube and a preset power supply; the gate of the first PMOS tube is respectively connected to the gate of the second PMOS tube, the other end of the first resistor and the gate of the third PMOS tube; the source of the first PMOS tube is connected to one end of the second resistor; the other end of the second resistor is connected to the anode of the fifth diode; the cathode of the fifth diode is connected to one end of the third resistor, the other end of the third resistor is connected to one end of the fourth resistor, the other end of the fourth resistor is connected to one end of the fifth resistor, the other end of the fifth resistor is connected to one end of the sixth resistor, and the other end of the sixth resistor is grounded; the source of the second PMOS tube is connected to the drain of the fourth PMOS tube, the source of the third PMOS tube is connected to the drain of the fifth PMOS tube, the gate of the fourth PMOS tube is connected to the gate of the fifth PMOS tube, and the The source of the fourth PMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is grounded, the gate of the first NMOS tube is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the anode of the first diode; the source of the fifth PMOS tube is connected to the drain of the sixth PMOS tube, the gate of the sixth PMOS tube is respectively connected to the drain of the first NMOS tube and the gate of the second NMOS tube, the source of the sixth PMOS tube is connected to the drain of the second NMOS tube, and serves as the output end of the undervoltage signal; the source of the second NMOS tube is grounded, the gate of the second NMOS tube is connected to the gate of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to one end of the fifth resistor, the source of the fourth NMOS tube is grounded, the drain of the third NMOS tube is connected to one end of the sixth resistor, the source of the third NMOS tube is grounded, and the gate of the third NMOS tube is connected to the output driving module.

2. The bandgap reference circuit according to claim 1, characterized in that: The output driving module includes: a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, an eighth resistor, and a ninth resistor; wherein, The drain of the seventh PMOS tube is connected to a preset power supply, the gate of the seventh PMOS tube is connected to the gate of the third PMOS tube, and the source of the seventh PMOS tube is used to output the driving current; one end of the eighth resistor is connected to the preset power supply, the other end of the eighth resistor is connected to the drain of the eighth PMOS tube, one end of the ninth resistor is connected to the preset power supply, the other end of the ninth resistor is respectively connected to the drain and gate of the ninth PMOS tube, the source of the ninth PMOS tube is grounded, and the gate of the eighth PMOS tube is respectively connected to the fourth PMOS tube. The gate of the OS tube is connected to the gate of the ninth PMOS tube to provide the bias voltage; the source of the eighth PMOS tube is connected to the drain of the tenth PMOS tube, the gate of the tenth PMOS tube is connected to the gate of the fifth NMOS tube and is used to input the undervoltage signal, the source of the tenth PMOS tube is respectively connected to the gate of the sixth NMOS tube, the gate of the third NMOS tube and the drain of the fifth NMOS tube, and is used to output the logic control signal, the source of the fifth NMOS tube is grounded, and the source of the sixth NMOS tube is grounded.

3. The bandgap reference circuit according to claim 1, characterized in that: The power supply module includes: an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a seventh NMOS tube, and an eighth NMOS tube; wherein, The drain of the eleventh PMOS tube is connected to a preset power supply, the source and the gate of the eleventh PMOS tube are connected to the drain of the seventh NMOS tube, the source of the seventh NMOS tube is grounded, the gate of the seventh NMOS tube is respectively connected to the drain and the gate of the eighth NMOS tube and the source of the thirteenth PMOS tube, the source of the eighth NMOS tube is grounded, the drain of the thirteenth PMOS tube is connected to the source of the twelfth PMOS tube, the drain of the twelfth PMOS tube is used to input the first voltage, and the gates of the eleventh PMOS tube, the twelfth PMOS tube and the thirteenth PMOS tube are used to provide the current source.

4. The bandgap reference circuit according to claim 3, characterized in that: The feedback startup module includes: a fourteenth PMOS tube, a fifteenth PMOS tube and a ninth NMOS tube; wherein, The drain of the fourteenth PMOS tube is connected to the preset power supply, the gate of the fourteenth PMOS tube is respectively connected to the gate and source of the eleventh PMOS tube, the source of the fourteenth PMOS tube is connected to the drain and gate of the fifteenth PMOS tube, and is used to output the first voltage, the source of the fifteenth PMOS tube is connected to the drain of the ninth NMOS tube, the source of the ninth NMOS tube is grounded, and the gate of the ninth NMOS tube is used to input the second voltage.

5. The bandgap reference circuit according to claim 4, characterized in that: The bandgap core module includes: a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a first triode, a second triode, a tenth resistor, and an eleventh resistor; wherein, The drain of the sixteenth PMOS tube is connected to the drain of the twelfth PMOS tube and the drain of the seventeenth PMOS tube, and is used to input the first voltage. The gate of the sixteenth PMOS tube is respectively connected to the gate of the seventeenth PMOS tube and the gate of the twelfth PMOS tube. The source of the sixteenth PMOS tube is connected to the drain of the eighteenth PMOS tube. The source of the seventeenth PMOS tube is connected to the drain of the nineteenth PMOS tube. The source of the eighteenth PMOS tube is connected to the collector of the first transistor. The gate of the PMOS tube is respectively connected to the gate of the nineteenth PMOS tube and the gate of the thirteenth PMOS tube, the source of the nineteenth PMOS tube is respectively connected to the collector of the second transistor and the gate of the ninth NMOS tube, the base of the first transistor is connected to the base of the second transistor and is used to input the reference voltage, the emitter of the first transistor is connected to one end of the tenth resistor, the other end of the tenth resistor is respectively connected to the emitter of the second transistor and one end of the eleventh resistor, and the other end of the eleventh resistor is grounded.

6. The bandgap reference circuit according to claim 1, characterized in that: The output module includes: a tenth NMOS tube, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor; wherein, One end of the twelfth resistor is connected to a preset power supply, the other end of the twelfth resistor is connected to the drain of the tenth NMOS tube, the gate of the tenth NMOS tube is used to input the first voltage, the source of the tenth NMOS tube is connected to one end of the thirteenth resistor, the other end of the thirteenth resistor is connected to one end of the fourteenth resistor and is used to output the reference voltage, and the other end of the fourteenth resistor is grounded.

7. A chip, characterized in that: include: The bandgap reference circuit according to any one of claims 1 to 6.

8. An electronic device, characterized in that: include: The chip according to claim 7.

Images