Array substrate and display panel

Abstract

The present application belongs to the field of display technology, specifically to an array substrate and a display panel. The array substrate includes a base substrate, pixel electrode blocks, common electrode blocks, scan lines, and touch signal lines. The orthographic projection of each common electrode block on the base substrate covers at least the orthographic projection of one pixel electrode block on the base substrate. A plurality of touch signal lines are provided and arranged at intervals from each other, and each touch signal line is connected to a common electrode block. When not touched, the touch signal line transmits a common signal to the common electrode block. The discontinuity formed between two adjacent common electrode blocks in the row direction is defined as a row discontinuity. The orthographic projection of the row discontinuity on the base substrate overlaps with the orthographic projection of the scan line on the base substrate, and the orthographic projection of the row discontinuity on the base substrate is at least partially covered by the orthographic projection of the touch signal line on the base substrate. The present application solution can reduce or eliminate the light leakage problem of the scan line, ensure the pixel aperture ratio, and improve the display effect.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to an array substrate and a display panel. Background Art

[0002] With the passage of time and technological advancements, people are increasingly demanding not only the functionality of electronic products but also their appearance. This has driven the continuous development of electronic products towards being lighter, thinner, narrower, and more power-efficient, such as the emergence of in-cell touch display products. However, in-cell touch display designs often suffer from light leakage along the scanning lines. Summary of the Invention

[0003] The purpose of the present application is to provide an array substrate and a display panel that can reduce or eliminate the light leakage problem of the scanning line and ensure the pixel aperture ratio.

[0004] In a first aspect, the present application provides an array substrate, comprising a base substrate and pixel electrode blocks, common electrode blocks, scan lines, and touch signal lines provided on the base substrate, wherein the touch signal lines, the pixel electrode blocks, and the common electrode blocks are all formed on a side of the scan lines away from the base substrate, characterized in that:

[0005] A plurality of pixel electrode blocks and common electrode blocks are provided, and are arranged in an array at intervals along the row direction and the column direction. The pixel electrode blocks and the common electrode blocks are arranged at intervals in the thickness direction of the base substrate, and the orthographic projection of each common electrode block on the base substrate covers at least the orthographic projection of one pixel electrode block on the base substrate.

[0006] The scanning line extends in the row direction and is located between two adjacent rows of pixel electrode blocks;

[0007] The touch signal lines are provided in plurality and arranged at intervals from each other, and each of the touch signal lines is connected to a common electrode block, and the touch signal lines transmit common signals to the common electrode blocks when no touch is performed;

[0008] In which, the discontinuity formed between two adjacent common electrode blocks in the row direction is defined as a row discontinuity, the orthographic projection of the row discontinuity on the base substrate overlaps with the orthographic projection of the scan line on the base substrate, and the orthographic projection of the row discontinuity on the base substrate is at least partially covered by the orthographic projection of the touch signal line on the base substrate.

[0009] In an exemplary embodiment of the present application, at least part of the touch signal lines include main touch lines and auxiliary touch lines connected to each other;

[0010] The main touch line extends in a column direction, and one end of the main touch line is used to connect to a driving chip;

[0011] The auxiliary touch line is provided on a side of the main touch line away from the driver chip and extends in a row direction. The orthographic projection of the row discontinuity on the base substrate is covered by the orthographic projection of the auxiliary touch line on the base substrate.

[0012] In an exemplary embodiment of the present application, the secondary touch line is provided on a side of the common electrode block close to the base substrate, and an insulating film layer is formed between the secondary touch line and the common electrode block;

[0013] In which, there is a first overlapping area between the first of the two adjacent common electrode blocks in the column direction and the orthographic projection of the auxiliary touch line on the base substrate, and they are connected at the first overlapping area through a conductive via penetrating the insulating film layer, and the second of the two adjacent common electrode blocks in the column direction and the auxiliary touch line are insulated from each other.

[0014] In an exemplary embodiment of the present application, orthographic projections of the secondary touch line and the second of the common electrode blocks on the base substrate have a second overlapping area.

[0015] In an exemplary embodiment of the present application, a size of the first overlapping region in the column direction is greater than a size of the second overlapping region in the column direction.

[0016] In an exemplary embodiment of the present application, the common electrode block close to the driving chip is defined as an end common electrode block, and the touch signal line corresponding to the end common electrode block is defined as an end touch signal line, and the end touch signal line includes a main touch line extending in the column direction, and the main touch line of the end touch signal line is connected to the end common electrode block.

[0017] In an exemplary embodiment of the present application, the array substrate further includes data lines extending in a column direction, the data lines being connected to pixel electrode blocks of corresponding columns via transistors, wherein:

[0018] The data lines and the touch signal lines are arranged in the same layer and are spaced apart from each other.

[0019] In an exemplary embodiment of the present application, the array substrate includes a plurality of pixel units arranged in an array along row and column directions, each of the pixel units includes a plurality of pixel electrode blocks arranged at intervals in the column direction, the color resistance colors corresponding to any adjacent pixel electrode blocks in the column direction are different, and each pixel electrode block in the same pixel unit is connected to the data line in the same column and is respectively connected to the scanning line of the corresponding row.

[0020] In an exemplary embodiment of the present application, the orthographic projection of the common electrode block on the base substrate covers the orthographic projections of at least two pixel electrode blocks on the base substrate; and / or

[0021] The pixel electrode block is provided on a side of the common electrode block away from the base substrate, and the pixel electrode block is a slit electrode comprising a plurality of electrode strips arranged at intervals, and the common electrode block is a planar electrode; and / or

[0022] The touch signal line and the data line are located in different layers.

[0023] A second aspect of the present application provides a display panel, comprising:

[0024] an opposing substrate;

[0025] a liquid crystal layer; and

[0026] In any of the above array substrates, the counter substrate and the array substrate are arranged in a cell-type arrangement, and the liquid crystal layer is arranged between the counter substrate and the array substrate.

[0027] The array substrate and display panel of the present application have at least the following beneficial effects:

[0028] The array substrate includes a substrate substrate and a scanning line, a pixel electrode block, a common electrode block and a plurality of touch signal lines arranged on the substrate substrate. The orthographic projection of the common electrode block on the substrate substrate covers the orthographic projection of at least one pixel electrode block on the substrate substrate. There is a row discontinuity between two adjacent common electrode blocks in the row direction. The orthographic projection of the row discontinuity on the substrate substrate overlaps with the orthographic projection of the scanning line on the substrate substrate. The orthographic projection of the row discontinuity on the substrate substrate is at least partially covered by the orthographic projection of the touch signal line on the substrate substrate. The touch signal line inputs a common signal when not touched. The touch signal line shields the high-level signal generated by the scanning line through the input common signal, thereby eliminating the signal generated by the scanning line that interferes with the deflection of the liquid crystal, ensuring normal deflection of the liquid crystal, reducing or eliminating the light leakage problem generated by the scanning line, and improving the display effect of the display panel. The touch signal line in the present application can act as a touch line to transmit touch signals and can also be used to shield the scanning line to reduce or eliminate the light leakage problem of the scanning line.

[0029] In addition, by utilizing the touch signal line to shield the light leakage generated by the scan line, it is not necessary to increase the size of the black matrix to shield the light leakage generated by the scan line, thereby ensuring the pixel aperture ratio.

[0030] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0031] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0033] Figure 1 It shows a schematic structural diagram of the auxiliary touch lines provided in the row breaks provided in the first or fifth embodiment of the present application;

[0034] Figure 2 A schematic diagram showing the arrangement structure of red sub-pixels, green sub-pixels, and blue sub-pixels provided in Example 1 or Example 5 of the present application is shown;

[0035] Figure 3 It shows a schematic structural diagram of the connection between the touch signal line and the common electrode block provided in the first or fifth embodiment of the present application;

[0036] Figure 4 A schematic structural diagram showing a common electrode block corresponding to two or more pixel electrodes provided in the first or fifth embodiment of the present application is shown;

[0037] Figure 5 It shows a schematic structural diagram of adjacent common electrode blocks with row discontinuities provided by the first or fifth embodiment of the present application;

[0038] Figure 6 Shown Figure 1 Schematic diagram of the cross-sectional structure along the middle line A-A';

[0039] Figure 7 A schematic diagram showing the structure of the auxiliary touch line provided in the first or fifth embodiment of the present application being connected to the common electrode block through the conductive via;

[0040] Figure 8 It shows a schematic structural diagram of the common electrode block provided in the first or fifth embodiment of the present application adopting a whole-surface design;

[0041] Figure 9 Shown Figure 8 Schematic diagram of the cross-sectional structure along the middle line B-B';

[0042] Figure 10 A schematic diagram showing a structure in which a secondary touch line provided by a second embodiment of the present application is connected to a primary touch line through a via-hole transfer structure;

[0043] Figure 11 Shown Figure 10 Schematic diagram of the cross-sectional structure along the C-C' line;

[0044] Figure 12 It shows a structural schematic diagram of a secondary touch line provided in the third embodiment of the present application, in which a first extension line is provided at one end thereof;

[0045] Figure 13 Shown Figure 12 Schematic diagram of the cross-sectional structure along the middle line D-D';

[0046] Figure 14 A schematic diagram of the structure of the support pillars and the array substrate abutting against each other provided in the third or fifth embodiment of the present application is shown;

[0047] Figure 15 It shows a structural schematic diagram of a secondary touch line provided in a fourth embodiment of the present application, in which a second extension line is provided at one end thereof;

[0048] Figure 16 Shown Figure 15 Schematic diagram of the cross-sectional structure along the E-E' line;

[0049] Figure 17 A schematic diagram showing the structure of the support pillars provided in the fourth or fifth embodiment of the present application correspondingly abutting against the side covering area of ​​the array substrate;

[0050] Figure 18 A schematic structural diagram of a display panel provided in Example 5 of the present application is shown.

[0051] Description of reference numerals:

[0052] 10. Display panel; 100. Array substrate; 110. Base substrate; 120. Scan line; 130. Data line; 140. Touch signal line; 140a. End touch signal line; 141. Main touch line; 142. Secondary touch line; 1420. First extension line; 1421. Second extension line; 150. Sub-pixel; 150a. Red sub-pixel; 150b. Green sub-pixel; 150c. Blue sub-pixel; 151. Transistor; 1510. Gate; 1511. Active layer; 1512. First electrode; 1513. Second electrode; 152. Pixel electrode block; 1520, first electrode strip; 1521, first edge electrode strip; 1522, second edge electrode strip; 1523, connecting portion; 160, common electrode block; 160a, end common electrode block; 170, row discontinuity; 180, gate insulating layer; 190, driver chip; 1100, first insulating layer; 1110, flat layer; 1120, conductive via; 1130, second insulating layer; 200, opposing substrate; 300, liquid crystal layer; H, covering area; L, via transfer structure; M1, first overlapping area; M2, second overlapping area. DETAILED DESCRIPTION

[0053] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0054] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically specified.

[0055] In this application, unless otherwise specified or limited, terms such as "assembly" and "connection" should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0056] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0057] Example 1

[0058] Embodiment 1 of the present application provides an array substrate 100, which is applied to an in-cell touch display panel 10. The display panel 10 may employ Fringe Field Switching (FFS) technology. The display panel 10 employing FFS technology has the advantages of fast response time, high light transmittance, and wide viewing angle.

[0059] See also Figure 1As shown, the array substrate 100 may include a base substrate 110 and scan lines 120 , data lines 130 , touch signal lines 140 , sub-pixels 150 and common electrode blocks 160 disposed on the base substrate 110 .

[0060] The base substrate 110 may be a glass substrate, but is not limited thereto, and may also be a substrate made of other materials, such as PI material.

[0061] A plurality of pixel units are disposed on the base substrate 110 . The plurality of pixel units may be arranged in an array along a row direction X and a column direction Y on the base substrate 110 .

[0062] Each pixel unit includes a plurality of sub-pixels 150 spaced apart in the column direction Y. The color resist colors corresponding to any two adjacent sub-pixels 150 in the column direction Y are different, that is, adjacent sub-pixels within the same pixel unit correspond to different colors. Furthermore, the sub-pixels 150 within the same pixel unit are all connected to the same column data line 130, and the sub-pixels 150 within the same pixel unit are each connected to the corresponding row scan line 120.

[0063] For example, see Figure 2 As shown, a pixel unit may include a red sub-pixel 150a, a green sub-pixel 150b, and a blue sub-pixel 150c. The red sub-pixels 150a, 150b, and 150c are arranged sequentially in the column direction Y. The red sub-pixels 150a, 150b, and 150c correspond to different color resists, namely, red, green, and blue resists, respectively. The red sub-pixels 150a, 150b, and 150c within the same pixel unit share the same data line 130. The red sub-pixels 150a, 150b, and 150c within the same pixel unit are each connected to three different scan lines 120. In other words, by using tri-gate transistors, the number of scan lines 120 is tripled compared to a solution in which three sub-pixels are arranged alternately in the row direction within the pixel unit. This increases the number of scan lines 120 and reduces the number of source driver chips by two-thirds, thereby achieving cost savings.

[0064] It should be noted that each pixel unit may include not only the three sub-pixels 150 mentioned above, but also four or more sub-pixels 150 . The specific design may be based on different embodiments and is not specifically limited here.

[0065] In addition, in the column direction Y, the scan line 120 is disposed between two adjacent rows of sub-pixels 150 .

[0066] See Figure 1As shown, each sub-pixel 150 may include a transistor 151, and the transistor 151 may include a gate 1510, an active layer 1511, and a first electrode 1512 and a second electrode 1513 arranged on the same layer. A gate insulating layer 180 may be set between the gate 1510 and the active layer 1511 to insulate the gate 1510 and the active layer 1511 from each other; and the first electrode 1512 and the second electrode 1513 may be overlapped with the source and drain doping regions of the active layer 1511 respectively. Specifically, the corresponding connection relationship between the first electrode 1512 and the second electrode 1513 and the source and drain doping regions of the active layer 1511 can be determined according to whether the transistor 151 is N-type or P-type, which will not be described in detail here.

[0067] For example, the transistor 151 of the embodiment of the present application may be a bottom-gate type, that is, the gate 1510 may be first formed on the substrate 110; then, a gate insulating layer 180 is formed on the substrate 110, and the gate insulating layer 180 covers the gate 1510; then, an active layer 1511 is formed on the side of the gate insulating layer 180 away from the substrate 110, that is, the active layer 1511 is located on the side of the gate 1510 away from the substrate 110, and the active layer 1511 and the gate 1510 are on the substrate substrate. There is overlap in the orthographic projections on the plate 110. For example, the orthographic projection of the active layer 1511 on the base substrate 110 may be located within the orthographic projection of the gate 1510 on the base substrate 110; the first pole 1512 and the second pole 1513 may be formed after the active layer 1511 is formed, and at least a portion of the first pole 1512 may overlap on one doped region of the source and drain doped regions of the active layer 1511; at least a portion of the second pole 1513 may overlap on another doped region of the source and drain doped regions of the active layer 1511.

[0068] It should be noted that the transistor 151 of the embodiment of the present application is not limited to the bottom-gate type mentioned above, but can also be a top-gate type. In addition, it should be noted that the gate 1510 of the transistor 151 can be understood as its control terminal, the first electrode 1512 can be understood as the first terminal, and the second electrode 1513 can be understood as the second terminal.

[0069] The scan line 120 may extend in the row direction X, wherein the scan line 120 may be connected to the control terminal of the transistor 151 to control the conduction or closure of the transistor 151. Optionally, the scan line 120 may be provided in the same layer as the gate 1510 of the transistor 151 and integrally connected.

[0070] In this application, "same-layer arrangement" refers to the use of the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to one mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. This simplifies the manufacturing process, saves manufacturing costs, and improves production efficiency.

[0071] For example, the scanning line 120 may be made of metal or alloy materials, such as molybdenum, aluminum, and titanium, to ensure good electrical conductivity, but is not limited thereto and may also be made of other materials with good electrical conductivity.

[0072] See Figure 1 and Figure 2 As shown, the data line 130 may extend in the column direction Y, wherein the data line 130 may be connected to the second end of the transistor 151 (i.e., the second electrode 1513 mentioned above) to write a data signal to the second end of the transistor 151. Optionally, the data line 130 may be provided in the same layer as the second electrode 1513 of the transistor 151 and integrally connected.

[0073] The data line 130 may be made of metal or alloy materials, such as molybdenum, aluminum, and titanium, to ensure good electrical conductivity, but is not limited thereto and may also be made of other materials with good electrical conductivity.

[0074] See Figure 1 As shown, each sub-pixel 150 includes a pixel electrode block 152, and within the same pixel unit, the color resist corresponding to any two adjacent pixel electrode blocks 152 is different. The pixel electrode block 152 can be connected to the first end of the transistor 151 (i.e., the first electrode 1512 mentioned above). When the transistor 151 is turned on in response to the scan signal provided by the scan line 120, the data signal provided by the data line 130 can flow into the first electrode 1512 of the transistor 151 through the second electrode 1513, thereby being written to the pixel electrode block 152, thereby forming a voltage difference with the common voltage on the opposite substrate 200 side of the display panel 10, thereby causing the liquid crystal molecules between the opposite substrate 200 and the array substrate 100 to deflect, thereby realizing the display function.

[0075] The pixel electrode block 152 of the embodiment of the present application may be a transparent electrode. For example, it may be made of ITO (indium tin oxide) material to improve light transmittance, but is not limited thereto and may also be made of other transparent conductive materials.

[0076] For example, the pixel electrode block 152 can be formed after the first electrode 1512 and the second electrode 1513 of the transistor 151 are formed, and an insulating layer can be provided between the pixel electrode block 152 and the metal layer where the first electrode 1512 and the second electrode 1513 of the transistor 151 are located, and the pixel electrode block 152 can be connected to the first electrode 1512 of the transistor 151 through a via structure passing through this insulating layer.

[0077] In the column direction Y, the scan line 120 is disposed between two adjacent rows of pixel electrode blocks 152 , that is, the scan line 120 is located between two adjacent pixel electrode blocks 152 in the column direction Y.

[0078] See also Figure 1 and Figure 3 As shown, the common electrode block 160 is reused as a touch electrode block, and multiple common electrode blocks 160 are arranged in an array in the row direction X and the column direction Y. The common electrode blocks 160 and the pixel electrode blocks 152 are arranged at intervals in the vertical direction. The common electrode blocks 160 can be arranged above the pixel electrode blocks 152, or the pixel electrode blocks 152 can be arranged above the common electrode blocks 160.

[0079] In the embodiment of the present application, the common electrode block 160 is disposed below the pixel electrode block 152. The pixel electrode block 152 of this embodiment is a slit electrode comprising a plurality of electrode strips arranged at intervals, ie, slits are provided at positions corresponding to the opening areas.

[0080] For example, this pixel electrode block 152 includes a first electrode strip 1520, a first edge electrode strip 1521, a second edge electrode strip 1522 and a connecting portion 1523. Multiple first electrode strips 1520 are arranged at intervals in the column direction Y, and slits are formed between adjacent first electrode strips 1520; the first edge electrode strip 1521 is arranged at one end of the multiple first electrode strips 1520 and is connected to the ends of the multiple first electrode strips 1520; the second edge electrode strip 1522 is arranged at the other end of the multiple first electrode strips 1520 and is connected to the ends of the multiple first electrode strips 1520; the connecting portion 1523 is connected to the side of the second edge electrode strip 1522 away from the first electrode strip 1520, and this connecting portion 1523 is connected to the first pole 1512 through a via structure.

[0081] It is worth mentioning that the common electrode block 160 is a planar electrode and its orthographic projection on the base substrate 110 covers at least one orthographic projection of a pixel electrode block 152 on the base substrate 110 , that is, the common electrode block 160 corresponds to at least one pixel electrode block 152 .

[0082] An optional embodiment, see Figure 1As shown, the orthographic projection of a common electrode block 160 on the base substrate 110 covers the orthographic projection of a pixel electrode block 152 on the base substrate 110 , that is, the common electrode block 160 corresponds to the pixel electrode block 152 one-to-one.

[0083] Another optional embodiment, see Figure 4 As shown, the orthographic projection of a common electrode block 160 on the base substrate 110 covers the orthographic projections of two or more pixel electrode blocks 152 on the base substrate 110 , that is, one common electrode block 160 corresponds to two or more pixel electrode blocks 152 .

[0084] To achieve touch control, the array substrate 100 is provided with a plurality of touch signal lines 140 . The plurality of touch signal lines 140 are arranged in sequence and spaced apart in the row direction X. The touch signal lines 140 are connected to the common electrode blocks 160 in a one-to-one correspondence to transmit touch signals to the common electrode blocks 160 .

[0085] It is worth mentioning that the touch signal line 140 and the common electrode block 160 are arranged in the thickness direction of the base substrate 110, that is, the touch signal line 140 and the common electrode block 160 are arranged in the vertical direction. An insulating layer is provided between the common electrode block 160 and the touch signal line 140. The touch signal line 140 is connected to the common electrode block 160 through a conductive via 1120 passing through the insulating layer to transmit the touch signal.

[0086] The touch signal line 140 and the first electrode 1512 may be provided in the same layer, and the two may be spaced apart from each other to avoid interference between the touch signal line 140 and the first electrode 1512 , thereby ensuring touch and display effects.

[0087] The touch signal line 140 can be made of the same material as the data line 130 , and can be made of metal or alloy materials, such as molybdenum, aluminum, and titanium, to ensure good conductivity, but is not limited thereto, and can also be made of other materials with good conductivity.

[0088] It is understandable that disposing the touch signal line 140 and the first electrode 1512 in the same layer can reduce the film layer designed for the touch signal line 140 , reduce the thickness of the array substrate 100 , and further reduce the thickness of the display panel 10 .

[0089] See also Figure 3 and Figure 5 As shown, in order to avoid short circuits between adjacent common electrode blocks 160, adjacent common electrode blocks 160 are interrupted, and the interruption formed between two adjacent common electrode blocks in the row direction X is defined as a row interruption 170. That is, there is a row interruption 170 between two adjacent common electrode blocks 160 in the column direction Y.

[0090] To increase the aperture ratio, the line break 170 is disposed on the scan line 120 , that is, the orthographic projection of the line break 170 on the base substrate 110 overlaps with the orthographic projection of the scan line 120 on the base substrate 110 . In other words, a portion of the scan line 120 is exposed at the line break 170 .

[0091] The signal inputted by the scan line 120 is a high-level signal, which may interfere with the voltage signal of the pixel electrode block 152 , thereby affecting the deflection angle of the liquid crystal, thereby causing light leakage.

[0092] In order to eliminate or reduce the light leakage problem caused by the scan line 120 , the present application utilizes the touch signal line 140 to shield the high-level signal of the scan line 120 .

[0093] When not in touch mode, the touch signal lines 140 transmit common signals to the common electrode blocks 160, and the orthographic projections of the line breaks 170 on the base substrate 110 are at least partially covered by the orthographic projections of the touch signal lines 140 on the base substrate 110. In other words, the touch signal lines 140 cover the line breaks 170, and the common signals are input to the touch signal lines 140, thereby shielding the high-level signals of the scan lines 120, reducing or eliminating the impact of the scan lines 120 on the liquid crystal, and further eliminating or minimizing light leakage from the scan lines 120.

[0094] It is understandable that during normal touch, the touch signal line 140 occupies less time than the normal display, and a responsive touch signal is also present on the touch signal line 140. That is, during normal touch, the touch signal line 140 can also shield the scan line 120 of the line break 170, reducing or eliminating the impact of the scan line 120 on the liquid crystal.

[0095] That is to say, the touch signal line 140 in the present application solution can not only transmit the touch signal when touching the common electrode block 160, but also shield the high-level signal of the scan line 120 during normal display and touch, so as to ensure the normal deflection of the liquid crystal and eliminate or reduce the light leakage problem caused by the scan line 120.

[0096] It is worth mentioning that the multiple touch signal lines 140 can also be arranged alternately in the column direction Y, with the touch signal lines 140 being located at the row breaks 170 and common signals being transmitted to the touch signal lines 140 to shield the scan lines 120. In other words, the touch signal lines 140 can be directly used to shield the scan lines 120.

[0097] In the embodiment of the present application, the touch signal lines 140 are sequentially spaced apart in the row direction X. At least part of the touch signal lines 140 include main touch lines 141 and auxiliary touch lines 142 that are connected to each other.

[0098] See also Figure 1 As shown, the main touch lines 141 extend in the same direction as the data lines 130 in the column direction Y, with adjacent main touch lines 141 spaced apart from each other. The main touch lines 141 include connecting ends and extension ends located at opposite ends of the main touch lines 141. The connecting ends of the main touch lines 141 are connected to the driver chip 190, either directly or through other devices. The extension ends extend toward the end away from the driver chip 190.

[0099] See also Figure 1 or Figure 4 As shown, the auxiliary touch line 142 is arranged on a side of the main touch line 141 away from the driving chip 190 and is connected to the main touch line 141. The auxiliary touch line 142 is extended in the same extension direction as the scan line 120, that is, the auxiliary touch line 142 is extended in the row direction X.

[0100] In the examples of this application, see Figure 1 As shown, to eliminate or reduce light leakage from the scan line 120, an auxiliary touch line 142 is provided at the row discontinuity 170 and is capable of completely covering the row discontinuity 170. That is, the orthographic projection of the auxiliary touch line 142 on the base substrate 110 covers the orthographic projection of the row discontinuity 170 on the base substrate 110, and the width of the auxiliary touch line 142 is greater than the width of the row discontinuity 170. Furthermore, when no touch is being performed, a common signal is passed to the auxiliary touch line 142 to shield the high-level signal from the scan line 120, thereby eliminating interfering liquid crystal deflection caused by the scan signal and improving the display effect.

[0101] It can be understood that by having the orthographic projection of the secondary touch line 142 on the base substrate 110 cover the orthographic projection of the row discontinuity 170 on the base substrate 110 , the shielding effect of the secondary touch line 142 can be ensured.

[0102] For example, see Figure 1 As shown, one end of the auxiliary touch line 142 is connected to the main touch line 141, and the other end extends along the same extension direction as the scan line 120. That is, the extension direction of the auxiliary touch line 142 is the same as the extension direction of the scan line 120, the extension path of the auxiliary touch line 142 is the same as the extension path of the scan line 120, and the orthographic projection of the auxiliary touch line 142 on the base substrate 110 is located within the orthographic projection of the scan line 120 on the base substrate 110. Because the main touch line 141 and the auxiliary touch line 142 are interconnected, when a common signal is input to the main touch line 141, the auxiliary touch line 142 also receives a common signal. The common signal in the auxiliary touch line 142 can shield the high-level signal generated by the scan line 120, thereby eliminating the signal generated by the scan line 120 that interferes with liquid crystal deflection, thereby eliminating or reducing the light leakage problem caused by the scan line 120.

[0103] In addition, the display panel 10 includes a black matrix (BM) that shields metal lines such as the scan lines 120, data lines 130, and touch signal lines 140. To further prevent light leakage from the scan lines 120, the black matrix (BM) is typically widened for shielding. However, increasing the size of the black matrix (BM) reduces the pixel aperture ratio. The present application utilizes secondary touch lines 142 to shield the scan lines 120, resolving the light leakage issue. This eliminates the need to widen the black matrix (BM), effectively maintaining the pixel aperture ratio and the display quality of the display panel 10, thereby enhancing the display quality.

[0104] It is worth mentioning that the secondary touch line 142 does not need to follow the same extension path as the scan line 120 , and only needs to block the scan line 120 that leaks out of the line break 170 , thereby shielding the high-level signal of the scan line 120 .

[0105] In addition, the auxiliary touch line 142 can input a common signal when the scan line 120 inputs a scan signal. Since the auxiliary touch line 142 is connected to the main touch line 141, that is, the main touch line 141 inputs a common signal when no touch signal is input, thereby shielding the high-level signal generated by the scan line 120, thereby eliminating or reducing the interfering liquid crystal deflection caused by the high-level signal of the scan line 120, and improving the display effect of the display panel 10.

[0106] By inputting the common signal and the touch signal in a staggered manner, the shielding effect of the secondary touch line 142 on the high-level signal of the scan line 120 can be ensured, thereby improving the light shielding effect and further enhancing the display quality.

[0107] In an embodiment of the present application, the common electrode block 160 and the touch signal line 140 are located in different layers, and an insulating film layer is provided between the common electrode block 160 and the touch signal line 140. The touch signal line 140 can be connected to the common electrode block 160 through a conductive via 1120 to detect the capacitance change on the common electrode block 160 to determine whether the common electrode block 160 here is touched.

[0108] That is, the touch signal line 140 in this application can transmit touch signals during touch to sense where the common electrode block 160 is touched, and can also transmit common signals during display and touch to shield the signal of the scan line 120 and solve the light leakage problem.

[0109] The common electrode block 160 may be connected to the main touch line 141 through the conductive via 1120 , or may be connected to the auxiliary touch line 142 through the conductive via 1120 .

[0110] In the embodiments of this application, Figure 3 As shown, part of the common electrode block 160 is connected to the auxiliary touch line 142 through the conductive via 1120. Since the orthographic projection of the auxiliary touch line 142 on the base substrate 110 is located within the orthographic projection of the scan line 120 on the base substrate 110, the conductive via 1120 can be set within the orthographic projection of the scan line 120 on the base substrate 110. In this way, it is possible to avoid providing the conductive via 1120 on the main touch line 141. The size of the main touch line 141 can be designed to be smaller, thereby reducing the excessive space occupied by the touch signal line 140 and ensuring the pixel aperture ratio.

[0111] For example, see Figure 6 and Figure 7 As shown, the secondary touch line 142 is disposed on a side of the common electrode block 160 close to the base substrate 110. A first insulating layer 1100 and a planar layer 1110 are disposed between the secondary touch line 142 and the common electrode block 160. Conductive vias 1120 are formed in the first insulating layer 1100 and the planar layer 1110. The conductive vias 1120 expose a portion of the secondary touch line 142, and the secondary touch line 142 is connected to the common electrode block 160 via the conductive vias 1120. In the column direction Y, the orthographic projections of the first of two adjacent common electrode blocks 160 on the base substrate 110 overlap in a first region M1, and the secondary touch line 142 are connected in the first overlapping region M1 via the conductive via 1120 that penetrates the first insulating layer 1100 and the planar layer 1110. Furthermore, the second of the two adjacent common electrode blocks 160 in the column direction Y is insulated from the secondary touch line 142. Specifically, the orthographic projection of the auxiliary touch line 142 on the base substrate 110 and the orthographic projection of the common electrode block 160 to which it is connected on the base substrate 110 form a first overlapping region M1. The conductive via 1120 is located within the first overlapping region M1. The auxiliary touch line 142 utilizes this first overlapping region M1 to shield the scan line 120 and also connect to the common electrode block 160.

[0112] It is understandable that arranging the conductive via 1120 at the overlapping area between the auxiliary touch line 142 and the common electrode block 160 can reduce the size of the main touch line 141, thereby reducing the space occupied by the touch signal line 140 on the base substrate 110 and ensuring the pixel aperture ratio.

[0113] Furthermore, the secondary touch line 142 may overlap only with the common electrode block 160 to be connected, as long as the secondary touch line 142 can completely cover the row discontinuity 170. The secondary touch line 142 may also overlap with two adjacent common electrode blocks 160 in the column direction Y.

[0114] For example, the orthographic projection of the secondary touch line 142 on the substrate 110 is located within the orthographic projection of the scan line 120 on the substrate 110. Furthermore, to prevent the portion of the scan line 120 not covered by the secondary touch line 142 from affecting the deflection of the liquid crystal, the orthographic projections of adjacent common electrode blocks 160 on the substrate 110 overlap with the orthographic projections of the scan line 120 on the substrate 110. That is, the orthographic projections of the adjacent common electrode blocks 160 on the substrate 110 and the orthographic projections of the secondary touch line 142 on the substrate 110 completely cover the orthographic projections of the scan line 120 on the substrate 110. The common electrode blocks 160 and the secondary touch line 142 shield the high-level signal of the scan line 120, thereby eliminating interfering liquid crystal deflection caused by the scan signal and improving display quality.

[0115] The sizes of the overlapping areas of the orthographic projection of the secondary touch line 142 on the base substrate 110 and the orthographic projections of two adjacent common electrode blocks 160 on the base substrate 110 in the column direction Y may be the same or different in the column direction Y.

[0116] An optional embodiment, see Figure 6 As shown, the orthographic projection of the secondary touch line 142 on the base substrate 110 overlaps with the orthographic projection of two adjacent common electrode blocks 160 in the column direction Y on the base substrate 110 , thereby ensuring the shielding effect of the row break 170 and the scan line 120 .

[0117] Another optional embodiment, see Figure 7 As shown, the overlapping areas of the orthographic projection of the auxiliary touch line 142 on the substrate 110 and the orthographic projections of two adjacent common electrode blocks 160 on the substrate 110 in the column direction Y are different. Specifically, the orthographic projection of the auxiliary touch line 142 on the substrate 110 and the orthographic projection of the first of the two adjacent common electrode blocks 160 on the substrate 110 in the column direction Y have a first overlapping area M1, and the orthographic projection of the auxiliary touch line 142 on the substrate 110 and the orthographic projection of the second of the two adjacent common electrode blocks 160 on the substrate 110 in the column direction Y have a second overlapping area M2. Because the touch signal line 140 is connected to the common electrode block 160 via the auxiliary touch line 142, the size of the first overlapping area M1 in the column direction Y should be larger than the size of the second overlapping area M2 in the column direction Y to ensure the design position of the conductive via 1120 and, therefore, the connection between the touch signal line 140 and the common electrode block 160.

[0118] It is worth mentioning that the axis of the auxiliary touch line 142 coincides with the axis of the scan line 120 , that is, the center of the auxiliary touch line 142 and the center of the scan line 120 are located on the same straight line.

[0119] In an embodiment of the present application, the auxiliary touch line 142, the main touch line 141 and the data line 130 are arranged on the same layer, that is, the auxiliary touch line 142, the main touch line 141 and the data line 130 are obtained by the same patterning process. By arranging the touch signal line 140 and the data line 130 on the same layer, the number of film layers occupied by the touch signal line 140 alone can be reduced, thereby reducing the film layer thickness of the array substrate 100 to make it adapt to a thinner display panel 10.

[0120] It can be understood that since the auxiliary touch line 142, the main touch line 141 and the data line 130 are arranged in the same layer, when the auxiliary touch line 142 is connected to the common electrode block 160, the size of the main touch line 141 can be reduced, and the pixel electrode block 152 can be arranged more reasonably, thereby increasing the layout area of ​​the pixel electrode block 152 and improving the pixel aperture ratio.

[0121] The touch signal line 140 can be made of the same material as the data line 130 , and can be made of metal or alloy materials, such as molybdenum, aluminum, and titanium, to ensure good conductivity, but is not limited thereto, and can also be made of other materials with good conductivity.

[0122] Among them, see Figure 1 As shown, the touch signal line 140 and the data line 130 are spaced apart from each other, and the auxiliary touch line 142 extends toward the side close to the transistor 151. The auxiliary touch line 142 is located between the touch signal line 140 and the data line 130. That is, the auxiliary touch line 142 avoids the channel region of the transistor 151 to shield the row break 170, thereby shielding the scan line 120.

[0123] It is understood that in the row direction X, the end of the secondary touch line 142 close to the transistor 151 extends beyond the edge of the second edge electrode strip 1522 to reduce light leakage from the scan line 120 at the diagonal portion of the common electrode block 160 and ensure shielding of the scan line 120. That is, the secondary touch line 142 is as close as possible to the first electrode 1512 of the transistor 151 to ensure shielding of the secondary touch line 142.

[0124] In the examples of this application, see Figure 8 and Figure 9 As shown, the common electrode block 160 within the same touch electrode block 160 adopts a full-surface design, and the common electrode block 160 is used to block the high-level signal of the scan line 120 to avoid the light leakage problem caused by the scan line 120. There is no need to design an auxiliary touch line 142 within the touch electrode block 160, which reduces the use of materials and reduces production costs.

[0125] In the examples of this application, see Figure 3As shown, the common electrode block near the driver chip 190 is defined as the end common electrode block 160a, and the touch signal line 140 connected to the end common electrode block 160a is defined as the end touch signal line 140a. The end touch signal line 140a includes a main touch line 141 extending in the column direction Y. The main touch line 141 of the end touch signal line 140a is connected to the end common electrode block 160a. In other words, in the column direction Y, the common electrode block 160 near the driver chip 190 is connected to the main touch line 141, and the auxiliary touch line 142 is not used to connect to the common electrode block 160. This ensures the connection with the common electrode block 160, reduces the use of the auxiliary touch line 142, and reduces production costs.

[0126] In an embodiment of the present application, the first insulating layer 1100 adopts a composite, single-layer or stacked structure of silicon nitride (SiOx) and silicon oxide (SiNx); the flattening layer 1110 adopts an organic acrylic material, which can play a flattening and insulating role, so that the common electrode block 160 has a flattened design on the entire surface.

[0127] See also Figure 9 As shown, in order to avoid short circuit between the common electrode block 160 and the pixel electrode block 152, a second insulating layer 1130 is provided between the common electrode block 160 and the pixel electrode block 152. The second insulating layer 1130 is made of silicon nitride (SiOx) or silicon oxide (SiNx).

[0128] In some optional embodiments, the touch signal line 140 may also be located in a different layer from the data line 130, so that the touch signal line 140 can be placed above the data line 130, that is, the touch signal line 140 and the data line 130 are overlapped, which can further improve the pixel aperture ratio.

[0129] The present application utilizes a secondary touch line 142 extending from the touch signal line 140 to shield the scan line 120 exposed by the row break 170 between two adjacent common electrode blocks 160 in the column direction Y. When the touch signal is not input to the touch signal line 140, a common signal is input. The common signal on the secondary touch line 142 shields the high-level signal on the scan line 120, thereby eliminating or reducing the interfering liquid crystal deflection caused by the scan signal, thereby improving the display effect and quality. Furthermore, the secondary touch line 142 can be used as both a touch line and a shielding line, eliminating the need to design a shielding line and saving production costs. Furthermore, by utilizing the secondary touch line 142 to shield the scan line 120, it is no longer necessary to widen the size of the black matrix (BM). The size of the pixel electrode block 152 can be designed to be larger, thereby increasing the pixel aperture ratio.

[0130] Example 2

[0131] See also Figure 10and Figure 11 As shown, the difference between the second embodiment of the present application and the first embodiment is that the main touch line 141 and the data line 130 are arranged in the same layer, the auxiliary touch line 142 and the main touch line 141 are arranged in sequence in the vertical direction, and the auxiliary touch line 142 and the main touch line 141 are insulated. The auxiliary touch line 142 is connected to the main touch line 141 through a via adapter structure L to transmit a common signal to the auxiliary touch line 142.

[0132] For example, the auxiliary touch line 142 is disposed on a side of the common electrode block 160 away from the base substrate 110 and on a side of the pixel electrode block 152 close to the base substrate 110 , and the auxiliary touch line 142 is insulated from the common electrode block 160 and the pixel electrode block 152 .

[0133] Among them, see Figure 11 As shown, the via-hole transfer structure L is in the same layer as the pixel electrode block 152 and is spaced apart.

[0134] Example 3

[0135] See also Figure 12 As shown, the difference between the third embodiment of the present application and the second embodiment is that a first extension line 1420 is extended from one end of the secondary touch line 142 near the main touch line 141. The orthographic projection of the first extension line 1420 on the base substrate 110 overlaps with the orthographic projection of the main touch line 141 on the base substrate 110. The first extension line 1420 extends in the same direction as the scan line 120, and the orthographic projection of the first extension line 1420 on the base substrate 110 is located within the orthographic projection of the scan line 120.

[0136] It is understood that the first extension line 1420 can compensate for the uncovered portion of the secondary touch line 142, thereby improving the shielding effect on the scan line 120 and further reducing or eliminating the light leakage problem caused by the scan line 120. In addition, the first extension line 1420 can also reduce or eliminate the light leakage problem at the connection between the first edge electrode strip 1521 and the first edge electrode strip 1520.

[0137] In addition, see Figure 13 As shown, the height of the array substrate 100 where the first extension line 1420 is provided is greater than the height of the array substrate 100 where the first extension line 1420 is not provided. That is, the position where the second insulating layer 1130 is provided with the first extension line 1420 is more protruding than the position where the second insulating layer 1130 is not provided with the first extension line 1420.

[0138] It is worth mentioning that in order to ensure the box space between the counter substrate 200 and the array substrate 100 in the display panel 10 , a support column 220 is provided on the base 210 of the counter substrate 200 . The support column 220 extends vertically toward the array substrate 100 .

[0139] In addition, an alignment film for aligning liquid crystal molecules is provided on the array substrate 100. The alignment film is provided on the side of the second insulating layer 1130 away from the base substrate 110. When the display panel 10 is transported or moved, the support pillars 220 are likely to come into contact with the array substrate 100, which can easily scratch the alignment film on the array substrate 100, resulting in poor alignment of the liquid crystal molecules at the scratched area, thereby affecting the display effect.

[0140] See also Figure 14 As shown, in order to prevent the support column 220 from scratching the alignment film of the array substrate 100, this support column 220 corresponds to the first extension line 1420, and the support column 220 is abutted against the position of the array substrate 100 where the first extension line 1420 is provided, that is, the support column 220 is abutted against the protruding position of the second insulating layer 1130, and the support column 220 does not directly contact the alignment film in the pixel opening area, thereby preventing the support column 220 from scratching the alignment film on the side of the array substrate 100, avoiding the problem of stars in the sky.

[0141] It can be understood that even if this support column 220 slides out from the protruding position of the first extension line 1420 provided on the second insulating layer 1130, the support of the liquid crystal molecules can prevent the support column 220 from scratching the alignment film on the side of the array substrate 100, thereby improving the quality of the display panel 10.

[0142] In some embodiments, see Figure 14 As shown, the support column 220 is aligned with the overlapping area between the first extension line 1420 on the array substrate 100 and the touch signal line 140. The height of the overlapping area between the first extension line 1420 and the main touch line 141 is higher, which can better achieve the alignment of the support column 220, prevent the support column 220 from sliding out, avoid scratching the alignment film on the array substrate 100 side, and avoid the problem of star-shaped spots.

[0143] Example 4

[0144] See also Figure 15 As shown, the difference between the fourth embodiment of the present application and the third embodiment is that the secondary touch line 142 further includes a second extension line 1421, and the second extension line 1421 is extended in the row direction X. The second extension line 1421 is arranged on the side of the secondary touch line 142 away from the first extension line 1420, and the orthographic projection of the second extension line 1421 on the base substrate 110 and the orthographic projection of the gate 1510 on the base substrate 110 have an overlapping area.

[0145] The second extension line 1421 can extend the shielding range of the auxiliary touch line 142 , thereby improving the shielding effect on the high-level signal of the scan line 120 and reducing or eliminating the light leakage problem caused by the scan line 120 .

[0146] In the examples of this application, see Figure 15 As shown, the second extension line 1421 includes a covering region H, and the orthographic projection of the covering region H on the base substrate 110 covers the orthographic projection of the active layer 1511 on the base substrate 110 .

[0147] This covering area H can completely cover and protect the channel area of ​​the transistor 151, thereby preventing the etching solution from penetrating into the active layer 1511 due to cracks or loose films in the flat layer 1110, the second insulating layer 1130 and the first insulating layer 1100 when preparing the pixel electrode block 152 and the common electrode block 160, thereby affecting the characteristics of the transistor 151.

[0148] In addition, see Figure 16 and Figure 17 As shown, this masking area H can also correspond to the support column 220 on the opposing substrate 200. The support column 220 can be aligned with the position where the masking area H is provided on the array substrate 100. This can prevent the support column 220 from directly contacting the alignment film in the pixel opening area, thereby avoiding scratching the alignment film in the pixel opening area and ensuring the alignment effect on the liquid crystal molecules. In addition, the height of the array substrate 100 with the masking area H is greater than the height of the array substrate 100 without the masking area H. This height difference can accommodate some liquid crystal molecules. Therefore, even if the support column 220 slides off the area corresponding to the masking area H, the liquid crystal molecules are still supported and the alignment film of the array substrate 100 will not be scratched, thus avoiding the problem of starry sky, and improving the quality of the display panel 10.

[0149] It can be understood that, the supporting column 220 on the opposite substrate 200 side can be aligned with the first extension line 1420 on the array substrate 100 side; the supporting column 220 on the opposite substrate 200 can also be aligned with the covering area H of the second extension line 1421 on the array substrate 100 side; or part of the supporting column 220 of the opposite substrate 200 is aligned with the first extension line 1420, and the other part is aligned with the second extension line 1421, that is, the first extension line 1420 and the second extension line 1421 can both be aligned with the supporting column 220, so as to avoid the supporting column 220 directly aligning with the alignment film in the pixel opening area, prevent the supporting column 220 from scratching the alignment film in the pixel opening area, ensure the alignment effect of the liquid crystal molecules, and avoid the problem of starry sky.

[0150] In some embodiments, the secondary touch line 142 may have only the first extension line 1420 or only the second extension line 1421 .

[0151] The present application solution can shield the scanning signal of the scanning line 120 while aligning the support column 220 through the covering area H on the first extension line 1420, the auxiliary touch line 142 and the second extension line 1421, thereby preventing the support column 220 from scratching the alignment film in the opening area, ensuring the alignment stability of the liquid crystal molecules, and preventing the etching solution from damaging the active layer 1511 when preparing the common electrode block 160 and the pixel electrode block 152, thereby improving the characteristics of the transistor 151.

[0152] Example 5

[0153] See also Figure 14 、 Figure 17 and Figure 18 As shown, the fifth embodiment of the present application provides a display panel 10, which may be a liquid crystal display panel 10. The display panel 10 may include the array substrate 100 described in the first to fourth embodiments, which will not be repeated here. Figure 17 As shown, in addition, the display panel 10 further includes an opposite substrate 200 arranged in a cell with the array substrate 100 and a liquid crystal layer 300 located between the array substrate 100 and the opposite substrate 200 .

[0154] The counter substrate 200 may include a glass substrate and a color resist layer, a BM layer, a common electrode plate, an alignment film, support posts 220, and the like formed thereon. These layers are not described in detail herein. The support posts 220 correspond to the first extension lines 1420 or the second extension lines 1421. This prevents the support posts 220 from directly contacting the alignment film in the opening area on the side of the array substrate 100, thereby preventing scratches on the alignment film in the pixel opening area. This ensures proper alignment of the liquid crystal molecules and prevents the appearance of "starry sky" (a phenomenon often referred to as "starry sky"), which is a common problem in the optical microscope.

[0155] Among them, this support column 220 can be aligned with one of the first extension line 1420 in Example 3 or the second extension line 1421 in Example 4 to avoid scratching the alignment film on the side of the array substrate 100, ensure the alignment effect on the liquid crystal molecules, and improve the display quality of the display panel 10.

[0156] In some embodiments, the first extension line 1420 and the second extension line 1421 on the array substrate 100 side correspond to different support pillars 220 , and the first extension line 1420 and the second extension line 1421 correspond to different support pillars 220 and abut against them.

[0157] It is worth mentioning that the color resist layer on the opposite substrate 200 side may also be provided on the array substrate 100 , depending on the specific situation.

[0158] The BM layer shields the scan lines 120 , the data lines 130 and the touch signal lines 140 to avoid affecting the image display.

[0159] The display panel 10 in this application can be applied to mobile devices such as liquid crystal displays, mobile phones, laptops, wearable devices such as watches, VR devices, etc. Those skilled in the art can make corresponding choices based on the specific purpose of the display device, which will not be repeated here.

[0160] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0161] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. An array substrate comprising a base substrate and pixel electrode blocks, common electrode blocks, scan lines, and touch signal lines disposed on the base substrate, wherein the touch signal lines, the pixel electrode blocks, and the common electrode blocks are all formed on a side of the scan lines away from the base substrate, characterized in that: A plurality of pixel electrode blocks and common electrode blocks are provided, and are arranged in an array at intervals along the row direction and the column direction. The pixel electrode blocks and the common electrode blocks are arranged at intervals in the thickness direction of the base substrate, and the orthographic projection of each common electrode block on the base substrate covers at least the orthographic projection of one pixel electrode block on the base substrate. The scanning line extends in the row direction and is located between two adjacent rows of pixel electrode blocks; The touch signal lines are provided in plurality and arranged at intervals from each other, and each of the touch signal lines is connected to a common electrode block, and the touch signal lines transmit common signals to the common electrode blocks when no touch is performed; Wherein, a discontinuity formed between two adjacent common electrode blocks in the row direction is defined as a row discontinuity, an orthographic projection of the row discontinuity on the base substrate overlaps with an orthographic projection of the scan line on the base substrate, and the orthographic projection of the row discontinuity on the base substrate is at least partially covered by an orthographic projection of the touch signal line on the base substrate; At least part of the touch signal lines include main touch lines and auxiliary touch lines connected to each other; The main touch line extends in a column direction, and one end of the main touch line is used to connect to a driving chip; The auxiliary touch line is provided on a side of the main touch line away from the driver chip, and the auxiliary touch line extends in a row direction, and an orthographic projection of the row discontinuity on the base substrate is covered by an orthographic projection of the auxiliary touch line on the base substrate; The auxiliary touch line is provided on a side of the common electrode block close to the base substrate, and an insulating film layer is formed between the auxiliary touch line and the common electrode block; In which, there is a first overlapping area between the first of the two adjacent common electrode blocks in the column direction and the orthographic projection of the auxiliary touch line on the base substrate, and they are connected at the first overlapping area through a conductive via penetrating the insulating film layer, and the second of the two adjacent common electrode blocks in the column direction and the auxiliary touch line are insulated from each other.

2. The array substrate according to claim 1, wherein: The orthographic projections of the secondary touch line and the second of the common electrode blocks on the base substrate have a second overlapping area.

3. The array substrate according to claim 2, wherein: A size of the first overlapping region in the column direction is greater than a size of the second overlapping region in the column direction.

4. The array substrate according to claim 1, wherein: The common electrode block close to the driving chip is defined as an end common electrode block, and the touch signal line corresponding to the end common electrode block is defined as an end touch signal line. The end touch signal line includes a main touch line extending in the column direction, and the main touch line of the end touch signal line is connected to the end common electrode block.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The array substrate further includes data lines extending in the column direction, wherein the data lines are connected to the pixel electrode blocks of the corresponding columns through transistors, wherein: The data lines and the touch signal lines are arranged in the same layer and are spaced apart from each other.

6. The array substrate according to claim 5, wherein: The array substrate includes a plurality of pixel units arranged in an array along row and column directions, each of the pixel units includes a plurality of pixel electrode blocks arranged at intervals in the column direction, the color resistance colors corresponding to any adjacent pixel electrode blocks in the column direction are different, and each pixel electrode block in the same pixel unit is connected to the data line in the same column and is respectively connected to the scan line in the corresponding row.

7. The array substrate according to claim 5, wherein: The orthographic projection of the common electrode block on the base substrate covers the orthographic projections of at least two pixel electrode blocks on the base substrate; and / or The pixel electrode block is provided on a side of the common electrode block away from the base substrate, and the pixel electrode block is a slit electrode comprising a plurality of electrode strips arranged at intervals, and the common electrode block is a planar electrode; and / or The touch signal line and the data line are located in different layers.

8. A display panel, characterized in that: include: a counter substrate; liquid crystal layer; as well as According to the array substrate according to any one of claims 1 to 7, the counter substrate and the array substrate are arranged in a box, and the liquid crystal layer is arranged between the counter substrate and the array substrate.

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