Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes a substrate, and a light shielding layer on the substrate. A projection of the light shielding layer on the substrate at least partially overlaps with a projection of an active layer of a driving transistor of a pixel driving circuit on the substrate. A portion of the light shielding layer in a second region includes a plurality of islands, a plurality of bridges, and an auxiliary line extending along a direction substantially parallel to a second direction. The auxiliary line is connected to one or more adjacent islands by the bridges. The auxiliary line includes a plurality of split segments spaced apart from each other. A projection of the plurality of split segments on the substrate substantially does not overlap with a projection of a transistor of the pixel driving circuit on the substrate.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] In a first aspect, this disclosure provides an array substrate, comprising: a substrate substrate, and a light-shielding layer located on the substrate substrate; wherein the orthographic projection of the light-shielding layer on the substrate substrate at least partially overlaps with the orthographic projection of the active layer of a driving transistor of a pixel driving circuit on the substrate substrate; wherein a portion of the light-shielding layer located in a second region includes a plurality of islands, a plurality of bridges, and an auxiliary line extending along a direction substantially parallel to a second direction; the auxiliary line is connected to one or more adjacent islands of the plurality of islands via one of the plurality of bridges; the auxiliary line includes a plurality of segmented segments spaced apart from each other; and the orthographic projections of the plurality of segmented segments on the substrate substrate do not substantially overlap with the orthographic projections of the transistors of the pixel driving circuit on the substrate substrate.

[0004] In some embodiments of this disclosure, in a column of segments, each segment is located in a row of pixel driving circuits and is located between two adjacent pixel driving circuits in a corresponding pair in each row, and there is no data line between the two adjacent pixel driving circuits.

[0005] In some embodiments of this disclosure, the array substrate further includes additional signal lines located in a first region outside the second region; the additional signal lines extend in a direction substantially parallel to the second direction; the additional signal lines are located between two adjacent pixel driving circuits in the same row, and there are no data lines between the two adjacent pixel driving circuits; and the additional signal lines extend continuously through multiple rows of pixel driving circuits.

[0006] In some embodiments of this disclosure, the additional signal line is located in a region adjacent to a window region of the array substrate, the window region having holes configured for mounting accessories; and the additional signal line is connected to an accessory mounted in the window region.

[0007] In some embodiments of this disclosure, the additional signal line and the auxiliary line are located within the light-shielding layer.

[0008] In some embodiments of this disclosure, the additional signal line is connected to a signal line connected to an accessory located in a window region; the signal line located in the window region is connected to the additional signal line via a connection pad; the additional signal line is located in a third signal line layer on the side of the light-shielding layer away from the substrate.

[0009] In some embodiments of this disclosure, the array substrate further includes: a plurality of first fan-out connection lines extending in a direction substantially parallel to a first direction; a plurality of second fan-out connection lines extending in a direction substantially parallel to a second direction; a plurality of second voltage supply lines extending in a direction substantially parallel to the second direction; and a plurality of data lines extending in a direction substantially parallel to the second direction; a corresponding second fan-out connection line of the plurality of second fan-out connection lines is located between a second voltage supply line and a data line; two adjacent second fan-out connection lines of the plurality of second fan-out connection lines are located between two adjacent data lines of the plurality of data lines; and one of the plurality of second voltage supply lines separates two adjacent second fan-out connection lines.

[0010] In some embodiments of this disclosure, each data line is connected to a corresponding first fan-out connection line; each second fan-out connection line is connected to the corresponding first fan-out connection line; each first fan-out connection line connects the corresponding data line to the corresponding second fan-out connection line; and the plurality of second fan-out connection lines are connected to a data driving circuit.

[0011] In some embodiments of this disclosure, the array substrate further includes a plurality of third voltage supply lines extending in a direction substantially parallel to the second direction; a corresponding third voltage supply line of the plurality of third voltage supply lines is located between a second voltage supply line and a data line; two adjacent third voltage supply lines of the plurality of third voltage supply lines are located between two adjacent data lines of the plurality of data lines; and one of the plurality of second voltage supply lines separates two adjacent third voltage supply lines.

[0012] In some embodiments of this disclosure, at least one of the plurality of third voltage supply lines and the second fan-out connection line of the plurality of second fan-out connection lines are disconnected from each other and located between the same second voltage supply line and the same data line configured to provide signals to the same column of pixel driving circuitry; the at least one third voltage supply line crosses a first portion of the array substrate; the second fan-out connection line crosses a second portion of the array substrate; and the first portion and the second portion do not overlap each other.

[0013] In some embodiments of this disclosure, the array substrate further includes: an anode layer including a plurality of anodes; a plurality of first fan-out connection lines extending in a direction substantially parallel to a first direction; and a plurality of first voltage supply lines extending in a direction substantially parallel to the first direction; wherein the orthographic projections of the plurality of anodes on the substrate do not substantially overlap with the orthographic projections of the plurality of first fan-out connection lines on the substrate, and do not substantially overlap with the orthographic projections of the plurality of first voltage supply lines on the substrate.

[0014] In some embodiments of this disclosure, the array substrate further includes a plurality of second voltage supply lines extending in a direction substantially parallel to the second direction; wherein the anode layer includes a first corresponding anode, a second corresponding anode, a third corresponding anode, and a fourth corresponding anode; and the orthogonal projections of the plurality of second voltage supply lines on the substrate substantially cover the orthogonal projections of the first corresponding anode on the substrate, and substantially cover the orthogonal projections of the second corresponding anode on the substrate.

[0015] In some embodiments of this disclosure, the array substrate further includes: a plurality of second fan-out connection lines extending in a direction substantially parallel to the second direction; and a plurality of data lines extending in a direction substantially parallel to the second direction; wherein the anode layer includes a first corresponding anode, a second corresponding anode, a third corresponding anode, and a fourth corresponding anode; the orthographic projection of the third corresponding anode on the substrate at least partially overlaps with the orthographic projections of two adjacent data lines and two adjacent second fan-out connection lines on the substrate; the third corresponding anode includes a third main anode portion and a third extension portion connecting the third main anode portion and the third corresponding anode connection pad; the two adjacent data lines and the two adjacent second fan-out connection lines respectively cross the third corresponding anode in the second direction; and the two adjacent data lines and the two adjacent second fan-out connection lines are substantially uniformly distributed in a first direction relative to the third main anode portion of the third corresponding anode.

[0016] In some embodiments of this disclosure, the array substrate further includes a voltage connection pad; wherein the voltage connection pad connects a corresponding first voltage supply line of a plurality of first voltage supply lines to a second capacitor electrode of a storage capacitor, and connects a corresponding first voltage supply line of a plurality of first voltage supply lines to a first electrode of a light-emitting control transistor; each of a plurality of second voltage supply lines is connected to a corresponding first voltage supply line of a plurality of first voltage supply lines through an eighth via; and the corresponding first voltage supply line is connected to the voltage connection pad through a ninth via, thereby providing a first reference voltage signal to the voltage connection pad and sequentially to the second capacitor electrode.

[0017] In some embodiments of this disclosure, the voltage connection pad is located in the region between two adjacent pixel driving circuits in the same row, and there is at least one data line between the two adjacent pixel driving circuits; the voltage connection pad is not present in the region between two adjacent pixel driving circuits in the same row, and there is no data line between the two adjacent pixel driving circuits; and the orthographic projection of the voltage connection pad on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate.

[0018] In some embodiments of this disclosure, the array substrate further includes an interconnect reset signal line network; wherein the interconnect reset signal line network includes a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together; the plurality of first reset signal lines extend along a direction substantially parallel to a first direction; the plurality of fourth reset signal lines extend along a direction substantially parallel to a second direction; and the plurality of first reset signal lines and the plurality of fourth reset signal lines are part of an integral structure and are located in the same layer.

[0019] In some embodiments of this disclosure, the ratio of the number of the plurality of first reset signal lines to the number of rows of the pixel driving circuits located in the display area of ​​the array substrate is in the range of 0.8:1.0 to 1.2:1.0; and the ratio of the number of the plurality of fourth reset signal lines to the number of columns of the pixel driving circuits located in the display area of ​​the array substrate is in the range of 0.8:2.0 to 1.2:2.0.

[0020] In some embodiments of this disclosure, the array substrate further includes an interconnect voltage supply network; wherein the interconnect voltage supply network includes a plurality of first voltage supply lines and a plurality of second voltage supply lines interconnected together; the plurality of first voltage supply lines extend in a direction substantially parallel to a first direction; the plurality of second voltage supply lines extend in a direction substantially parallel to a second direction; the plurality of first voltage supply lines and the plurality of second voltage supply lines are located in different layers; and each second voltage supply line is connected to a corresponding first voltage supply line through a via extending through a planarization layer.

[0021] In some embodiments of this disclosure, the ratio of the number of the plurality of second voltage supply lines to the number of columns of pixel driving circuits located in the display area of ​​the array substrate is in the range of 0.8:2.0 to 1.2:2.0.

[0022] In a second aspect, this disclosure provides a display device including the array substrate and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0026] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0027] Figure 3A This is a schematic diagram of the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0028] Figure 3B It is shown Figure 3A A schematic diagram of the arrangement of pixel driving circuits in the array substrate.

[0029] Figure 3C It is shown Figure 3A A diagram showing the structure of the light-shielding layer in the array substrate.

[0030] Figure 3D It is shown Figure 3A A diagram showing the structure of the first semiconductor material layer in the array substrate.

[0031] Figure 3E It is shown Figure 3A A diagram showing the structure of the first gate metal layer in the array substrate.

[0032] Figure 3F It is shown Figure 3A A diagram showing the structure of the second gate metal layer in the array substrate.

[0033] Figure 3G It is shown Figure 3A The diagram shows a via extending through the first interlayer dielectric layer in the array substrate.

[0034] Figure 3H It is shown Figure 3A A diagram showing the structure of the second semiconductor material layer in the array substrate.

[0035] Figure 3I It is shown Figure 3A The diagram shows a via extending through the second interlayer dielectric layer in the array substrate.

[0036] Figure 3J It is shown Figure 3A A diagram showing the structure of the third gate metal layer in the array substrate.

[0037] Figure 3K It is shown Figure 3A A diagram showing vias extending through the passivation layer in an array substrate.

[0038] Figure 3L It is shown Figure 3A A diagram showing the structure of the first signal line layer in the array substrate.

[0039] Figure 3M It is shown Figure 3A A diagram showing vias extending through the first planarization layer in the array substrate.

[0040] Figure 3N It is shown Figure 3A A diagram showing the structure of the second signal line layer in the array substrate.

[0041] Figure 3O It is shown Figure 3A A diagram showing vias extending through the second planarization layer in the array substrate.

[0042] Figure 3P It is shown Figure 3A A diagram showing the structure of the third signal line layer in the array substrate.

[0043] Figure 3Q It is shown Figure 3A The diagram shows a via extending through the third planarization layer in the array substrate.

[0044] Figure 3R It is shown Figure 3A A diagram showing vias extending through the anode layer in the array substrate.

[0045] Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0046] Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram.

[0047] Figure 4C It is along Figure 3A A cross-sectional view of line C-C' in the diagram.

[0048] Figure 4D It is along Figure 3A A cross-sectional view of the D-D' line in the diagram.

[0049] Figure 4E It is along Figure 3A A cross-sectional view of the E-E' line in the diagram.

[0050] Figure 4F It is along Figure 3A A cross-sectional view of line F-F' in the diagram.

[0051] Figure 4G It is along Figure 3A A cross-sectional view of the G-G' line in the diagram.

[0052] Figure 4H It is along Figure 3A A cross-sectional view of the H-H' line in the diagram.

[0053] Figure 5 This is a diagram illustrating the structure of a light-shielding layer in an array substrate according to some embodiments of the present disclosure.

[0054] Figure 6 This is a diagram illustrating the structure of the light-shielding layer and the third signal line layer in an array substrate according to some embodiments of the present disclosure.

[0055] Figure 7 This is a diagram illustrating the structure of a light-shielding layer in an array substrate according to some embodiments of the present disclosure.

[0056] Figure 8 This is a diagram illustrating the structure of the light-shielding layer and the first semiconductor material layer in an array substrate according to some embodiments of the present disclosure.

[0057] Figure 9 This is a diagram illustrating the structure of a light-shielding layer and a second semiconductor material layer in an array substrate according to some embodiments of the present disclosure.

[0058] Figure 10 This is a diagram illustrating the layout of certain signal lines in the second and third signal line layers of an array substrate according to some embodiments of the present disclosure.

[0059] Figure 11A The connection between the corresponding data line and the corresponding first fan-out connection line via the first connection via is shown.

[0060] Figure 11B The connection between the corresponding first fan-out connection line and the corresponding second fan-out connection line via the second connection via is shown.

[0061] Figure 12 The layout of window regions in an array substrate is shown in some embodiments of the present disclosure.

[0062] Figure 13 The layout of window regions in an array substrate is shown in some embodiments of the present disclosure.

[0063] Figure 14 This is a diagram illustrating the structure of a third signal line layer in an array substrate according to some embodiments of the present disclosure.

[0064] Figure 15 This is a schematic diagram illustrating the structure of the second signal line layer, the third signal line layer, and the anode layer in an array substrate according to some embodiments of the present disclosure.

[0065] Figure 16 This is a diagram illustrating the structure of the anode layer in an array substrate according to some embodiments of the present disclosure.

[0066] Figure 17 An interconnected reset signal line network is shown in some embodiments according to this disclosure.

[0067] Figure 18 An interconnected voltage supply network is shown in some embodiments according to this disclosure. Detailed Implementation

[0068] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0069] This disclosure provides, in particular, an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a substrate and a light-shielding layer located on the substrate. Optionally, the orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the active layer of a driving transistor of a pixel driving circuit on the substrate. Optionally, the light-shielding layer is located in a second region and includes a plurality of islands, a plurality of bridges, and an auxiliary line extending along a direction substantially parallel to a second direction. Optionally, the auxiliary line is connected to one or more adjacent islands of the plurality of islands via one of the plurality of bridges. Optionally, the auxiliary line includes a plurality of segmented segments spaced apart from each other. Optionally, the orthographic projections of the plurality of segmented segments on the substrate do not substantially overlap with the orthographic projections of the transistors of the pixel driving circuit on the substrate.

[0070] Various suitable pixel driving circuits can be used in the array substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0071] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1 The array substrate includes an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes multiple first gate lines GL1, multiple second gate lines GL2, multiple data lines DL, multiple voltage supply lines Vdd, and a corresponding second voltage supply line (e.g., a low voltage supply line Vss). Each subpixel Sp emits light driven by its corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via a corresponding high voltage supply line among the multiple voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via a low voltage supply line. The voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0072] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A In some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a corresponding second gate line among a plurality of second gate lines. The transistor GL2 has a gate, a first electrode connected to the storage capacitor Cst's first capacitor electrode Ce1 and the gate of the driving transistor Td, and a second electrode connected to the second electrode of the driving transistor Td; a third transistor T3 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines, a first electrode connected to the second electrode of the driving transistor Td and the second transistor T2, and a second electrode connected to the anode of the light-emitting element LE; and a first reset transistor Tr1 has a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light-emitting element LE. A second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0073] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, both of which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0074] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0075] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, and S3 represents a corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, and C3 represents a corresponding third sub-pixel of a third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0076] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td.

[0077] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figure 2A The second transistor T2 is an n-type transistor, such as a metal-oxide-semiconductor (MOS) transistor, while the other transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0078] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A and Figure 2B During one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light-emitting sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2 to turn off the second reset transistor Tr2. Cutoff reset control signals are provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. In the initial sub-stage t0, each of the first gate lines GL1 provides a cutoff signal, therefore the first transistor T1 is turned off.

[0079] In reset phase t1, a turn-on reset control signal is provided to the gate of the first reset transistor Tr1 via each of the first reset control signal lines rst1 to turn on the first reset transistor Tr1, allowing the initialization voltage signal from each of the first reset signal lines Vint1 to pass from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1, and then to node N4. The anode of the light-emitting element LE is initialized. A turn-on reset control signal is provided to the gate of the third reset transistor Tr3 via each of the first reset control signal lines rst1 to turn on the third reset transistor Tr3; thereby allowing the initialization voltage signal from each of the third reset signal lines Vint3 to pass from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3, and then to node N2. Node N2 is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding voltage supply line Vdd. Due to the increased voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset phase t1. During the reset phase t1, each of the first gate lines GL1 provides a cutoff signal, thus turning off the first transistor T1. Each light-emitting control signal line em provides a high-voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0080] In the data writing sub-stage t2, a turn-on reset control signal is provided to the gate of the second reset transistor Tr2 via the second reset control signal line rst2 to turn on the second reset transistor Tr2. This allows the initialization voltage signal from the corresponding second reset signal line Vint2 to be transmitted from the first electrode of the second reset transistor Tr2 to the second electrode of the second reset transistor Tr2, and then to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is then initialized.

[0081] In data writing sub-stage t2, a cutoff reset control signal is again provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1, thus cutting off the first reset transistor Tr1 and the third reset transistor Tr3. Each first gate line GL1 and each second gate line GL2 provides a conduction signal, therefore the first transistor T1 and the second transistor T2 are turned on. The second electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Since the second transistor T2 is turned on in data writing sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus making the driving transistor Td a diode connection mode. The first transistor T1 is turned on in data writing sub-stage t2. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and sequentially transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. Node N2, connected to the first electrode of the driving transistor Td, has a data voltage signal level. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, the voltage level at node N1 in the data write sub-stage t2 gradually rises to (Vdata + Vth), where Vdata is the data voltage signal level and Vth is the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. The corresponding light-emitting control signal line em provides a high voltage signal to cut off the third transistor T3 and the fourth transistor T4.

[0082] In the light-emitting stage t3, a cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2 to turn off the second reset transistor Tr2. A cutoff reset control signal is provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. Each first gate line GL1 and each second gate line GL2 is provided with a cutoff signal, and the first transistor T1 and the second transistor T2 are turned off. The corresponding light-emitting control signal line em is provided with a low voltage signal to turn on the third transistor T3 and the fourth transistor T4. In the light-emitting stage t3, the voltage level at node N1 is maintained at (Vdata+Vth), and the driving transistor Td is turned on by this voltage level and operates in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, the fourth transistor T4 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at node N3, which is connected to the second electrode of the driving transistor Td, is equal to the light-emitting voltage of the light-emitting element LE.

[0083] Figure 3A This is a schematic diagram of the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 3B It is shown Figure 3A A schematic diagram of the arrangement of pixel driving circuits in the array substrate.

[0084] Figure 3A and Figure 3B A portion of an array substrate with two adjacent pixel driving circuits (including PDC1 and PDC2) is shown.

[0085] Figure 3C It is shown Figure 3A A diagram showing the structure of the light-shielding layer in the array substrate. Figure 3D It is shown Figure 3A A diagram showing the structure of the first semiconductor material layer in the array substrate. Figure 3E It is shown Figure 3A A diagram showing the structure of the first gate metal layer in the array substrate. Figure 3F It is shown Figure 3A A diagram showing the structure of the second gate metal layer in the array substrate. Figure 3G It is shown Figure 3A The diagram shows a via extending through the first interlayer dielectric layer in the array substrate. Figure 3H It is shown Figure 3A A diagram showing the structure of the second semiconductor material layer in the array substrate. Figure 3I It is shown Figure 3AThe diagram shows a via extending through the second interlayer dielectric layer in the array substrate. Figure 3J It is shown Figure 3A A diagram showing the structure of the third gate metal layer in the array substrate. Figure 3K It is shown Figure 3A A diagram showing vias extending through the passivation layer in an array substrate. Figure 3L It is shown Figure 3A A diagram showing the structure of the first signal line layer in the array substrate. Figure 3M It is shown Figure 3A A diagram showing vias extending through the first planarization layer in the array substrate. Figure 3N It is shown Figure 3A A diagram showing the structure of the second signal line layer in the array substrate. Figure 3O It is shown Figure 3A A diagram showing vias extending through the second planarization layer in the array substrate. Figure 3P It is shown Figure 3A A diagram showing the structure of the third signal line layer in the array substrate. Figure 3Q It is shown Figure 3A The diagram shows a via extending through the third planarization layer in the array substrate. Figure 3R It is shown Figure 3A A diagram showing vias extending through the anode layer in the array substrate.

[0086] Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram. Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram. Figure 4C It is along Figure 3A A cross-sectional view of line C-C' in the diagram. Figure 4D It is along Figure 3A A cross-sectional view of the D-D' line in the diagram. Figure 4E It is along Figure 3A A cross-sectional view of the E-E' line in the diagram. Figure 4F It is along Figure 3A A cross-sectional view of line F-F' in the diagram. Figure 4G It is along Figure 3A A cross-sectional view of the G-G' line in the diagram. Figure 4H It is along Figure 3A A cross-sectional view of the H-H' line in the diagram.

[0087] Reference Figures 3A to 3R as well as Figures 4A to 4HIn some embodiments, the array substrate includes a substrate BS; a light-shielding layer LSL located on the substrate BS; a buffer layer BUF located on the side of the light-shielding layer LSL away from the substrate BS; a first semiconductor material layer SML1 located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI located on the side of the first semiconductor material layer SML1 away from the substrate BS; a first gate metal layer Gate1 located on the side of the gate insulating layer GI away from the first semiconductor material layer SML1; an insulating layer IN located on the side of the first gate metal layer Gate1 away from the gate insulating layer GI; a second gate metal layer Gate2 located on the side of the insulating layer IN away from the first gate metal layer Gate1; a first interlayer dielectric layer ILD1 located on the side of the second gate metal layer Gate2 away from the insulating layer IN; a second semiconductor material layer SML2 located on the side of the first interlayer dielectric layer ILD1 away from the second gate metal layer Gate2; and a second interlayer dielectric layer ILD2 located on the side of the second semiconductor material layer SML2 away from the second gate metal layer Gate2. The first interlayer dielectric layer (ILD1) is located on the side away from the second interlayer dielectric layer (ILD2); the third gate metal layer (Gate3) is located on the side of the second interlayer dielectric layer (ILD2) away from the second semiconductor material layer (SML2); the passivation layer (PVX) is located on the side of the third gate metal layer (Gate3) away from the second interlayer dielectric layer (ILD2); the first signal line layer (SD1) is located on the side of the passivation layer (PVX) away from the third gate metal layer (Gate3); the first planarization layer (PLN1) is located on the side of the first signal line layer (SD1) away from the passivation layer (PVX); and the second signal line layer (SD2) is located on the side away from the first signal line layer (SD1). The first planarization layer PLN1 is located on the side away from the first signal line layer SD1; the second planarization layer PLN2 is located on the side away from the first planarization layer PLN1; the third signal line layer SD3 is located on the side away from the second signal line layer SD2; the third planarization layer PLN3 is located on the side away from the second planarization layer PLN2; and the anode layer ADL is located on the side away from the third signal line layer SD3.

[0088] refer to Figure 2A , Figure 3A , Figure 3C , Figure 4A , Figure 4D and Figure 4E In some embodiments, the light-shielding layer LSL includes a light-shielding element LS. Various suitable materials and various suitable manufacturing methods can be used to manufacture the light-shielding layer LSL. For example, metallic materials can be deposited on a substrate using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable metallic materials for manufacturing the light-shielding layer LSL include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or stacks comprising them.

[0089] In some embodiments, the orthographic projection of the light-shielding element LS on the substrate BS substantially covers (e.g., covers at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of the active layer of the driving transistor of the pixel driving circuit on the substrate BS.

[0090] In some embodiments, the light-shielding element LS is configured to provide a first reference signal. Optionally, the light-shielding element LS is electrically connected to a voltage supply line. In one example, the light-shielding element LS is electrically connected to a voltage supply line located in the peripheral region of the array substrate.

[0091] In an alternative embodiment, the light-shielding element LS is configured to provide a second reference signal.

[0092] In an alternative embodiment, the light-shielding element LS is configured to provide a reset signal.

[0093] Reference Figure 2A , Figure 3A , Figure 3D , Figures 4A to 4H In some embodiments, the first semiconductor material layer SML1 includes at least the active layer of a plurality of transistors (including first transistor T1, third transistor T3, fourth transistor T4, first reset transistor Tr1, second reset transistor Tr2, third reset transistor Tr3, and driving transistor Td) of the pixel driving circuit. Optionally, the first semiconductor material layer SML1 further includes at least a corresponding portion of the first electrode of the plurality of transistors (including first transistor T1, third transistor T3, fourth transistor T4, first reset transistor Tr1, second reset transistor Tr2, third reset transistor Tr3, and driving transistor Td) of the pixel driving circuit. Optionally, the first semiconductor material layer SML1 further includes at least a corresponding portion of the second electrode of the plurality of transistors (including first transistor T1, third transistor T3, fourth transistor T4, first reset transistor Tr1, second reset transistor Tr2, third reset transistor Tr3, and driving transistor Td) of the pixel driving circuit. Optionally, the first semiconductor material layer SML1 includes an active layer, a first electrode, and a second electrode for a plurality of transistors (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td) of the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the first semiconductor material layer SML1. Examples of semiconductor materials used to fabricate the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0094] exist Figure 3D In, corresponding to Figure 3BThe pixel driving circuit of PDC1 is labeled with components indicating each of the multiple transistors (T1, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1, and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0095] Optionally, the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr2, ACT3, and ACTd), the first electrodes (S1, S3, S4, Sr1, Sr2, Sr3, and Sd), and the second electrodes (D1, D3, D4, Dr1, Dr2, Dr3, and Dd) of each transistor (T1, T3, T4, Tr1, Tr2, Tr3, and Td) are located on the same layer.

[0096] In some embodiments, at least portions of the active layers (ACT1, ACT3, ACT4, ACTr1, and ACTd) of the plurality of transistors (T1, T3, T4, Tr1, and Td), at least portions of the first electrodes (S1, S3, S4, Sr1, and Sd), and at least portions of the second electrodes (D1, D3, D4, Dr1, and Dd) of the plurality of transistors (T1, T3, T4, Dr1, and Dd) in the pixel driving circuit are part of the overall structure. Optionally, in the same pixel driving circuit, a portion (ACTr2, Sr2, Dr2) of the second reset transistor Tr2 in the first semiconductor material layer is spaced apart from the overall structure (T1, T3, T4, Tr1, and Td). Optionally, in the same pixel driving circuit, a portion (ACTr3, Sr3, Dr3) of the third reset transistor Tr3 in the first semiconductor material layer is spaced apart from the overall structure (T1, T3, T4, Tr1, and Td).

[0097] In some embodiments, at least a portion of the active layers (ACTr2 and ACTr2'), the first electrodes (Sr2 and Sr2'), and the second electrodes (Dr2 and Dr2') of the second reset transistors in two adjacent pixel driving circuits in a row are part of an integral structure. Optionally, the first electrodes (Sr2 and Sr2') of two adjacent pixel driving circuits in a row are directly connected to each other.

[0098] Reference Figure 2A, Figure 3A , Figure 3E as well as Figures 4A to 4H In some embodiments, the first gate metal layer Gate1 includes a plurality of first gate lines (e.g., corresponding first gate line GL1), a plurality of first reset control signal lines (e.g., corresponding first reset control signal line rst1), a plurality of second reset control signal lines (e.g., corresponding second reset control signal line rst2), a plurality of light emission control signal lines (e.g., corresponding light emission control signal line em), and a first capacitor electrode Ce1 of the storage capacitor Cst in the pixel driving circuit.

[0099] Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first gate metal layer Gate1. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, a plurality of first gate lines (e.g., corresponding first gate line GL1), a plurality of first reset control signal lines (e.g., corresponding first reset control signal line rst1), a plurality of second reset control signal lines (e.g., corresponding second reset control signal line rst2), a plurality of light emission control signal lines (e.g., corresponding light emission control signal line em), and the first capacitor electrode Ce1 of the storage capacitor Cst in the pixel driving circuit are located in the same layer.

[0100] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple light-emitting control signal lines and first capacitor electrodes Ce1 are located in the same layer when they are formed due to one or more steps of the same patterning process performed in the same material layer. In another example, multiple light-emitting control signal lines and first capacitor electrodes Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple light-emitting control signal lines and forming the first capacitor electrodes Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0101] Reference Figure 2A , Figure 3A , Figure 3F as well as Figures 4A to 4HIn some embodiments, the second gate metal layer Gate2 includes at least portions of a plurality of second gate lines (e.g., corresponding first branches of the second gate lines GL2-1), a plurality of second reset signal lines (e.g., corresponding second reset signal Vint2), and a second capacitor electrode Ce2 of the storage capacitor Cst in the pixel driving circuit. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second gate metal layer Gate2. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, at least portions of the plurality of second gate lines (e.g., corresponding first branches of the second gate lines GL2-1), the plurality of second reset signal lines (e.g., corresponding second reset signal Vint2), and the second capacitor electrode Ce2 of the storage capacitor Cst in the pixel driving circuit are located in the same layer.

[0102] Reference Figure 3F In this invention, multiple second capacitor electrodes in multiple pixel driving circuits are interconnected and are part of an integral structure. By interconnecting the second capacitor electrodes, since the second capacitor electrodes are electrically connected to the corresponding first voltage supply line Vddh, the resistance of the corresponding first voltage supply line Vddh can be reduced. The inventors of this disclosure have found that this structure improves the display uniformity in the array substrate.

[0103] In an alternative embodiment, the multiple second capacitor electrodes in the multiple pixel driving circuits are spaced apart from each other. By spaced the second capacitor electrodes apart from each other, the parasitic capacitance between the multiple second capacitor electrodes and the second electrode Dd (e.g., node N3) of the driving transistor Td can be reduced, preventing short-term residual images when the array substrate is in display mode.

[0104] Figure 3G A via extending through the first interlayer dielectric layer ILD1 is shown.

[0105] Reference Figure 2A , Figure 3A , Figure 3H as well as Figures 4A to 4HIn some embodiments, the second semiconductor material layer SML2 includes at least the active layer ACT2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the first electrode S2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of the second electrode D2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 includes the active layer ACT2 of the second transistor T2, the first electrode S2, and the second electrode D2. In this array substrate, at least the active layer ACT2 of the second transistor T2 is located in a different layer from the active layers of at least other transistors in the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the second semiconductor material layer SML2. Examples of semiconductor materials used to fabricate the second semiconductor material layer SML2 include metal oxide-based semiconductor materials (such as indium gallium zinc oxide) and metal oxynitride-based semiconductor materials (such as zinc oxynitride).

[0106] exist Figure 3G In, corresponding to Figure 3B The pixel driving circuit of PDC1 is labeled with a tag indicating the components of the second transistor in the pixel driving circuit. For example, the second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. Optionally, the active layer ACT2, the first electrode S2, and the second electrode D2 of the second transistor T2 are in the same layer.

[0107] Figure 3I The via extending through the second interlayer dielectric layer ILD2 is shown.

[0108] refer to Figure 2A , Figure 3A , Figure 3J , Figures 4A to 4H In some embodiments, the third gate metal layer Gate3 includes at least portions of a plurality of second gate lines (e.g., corresponding second branches of the second gate lines GL2-2) and a plurality of third reset signal lines (e.g., corresponding third reset signal line Vint3). Various suitable electrode materials and various suitable fabrication methods can be used to fabricate the third gate metal layer Gate3. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third gate metal layer Gate3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0109] Figure 3K The image shows a via extending through the passivation layer PVX.

[0110] refer to Figure 2A , Figure 3A , Figure 3L , Figures 4A to 4H In some embodiments, the first signal line layer SD1 includes a plurality of first reset signal lines (e.g., a corresponding first reset signal line Vint1); a plurality of fourth reset signal lines (e.g., a corresponding fourth reset signal line Vintv); a first data connection pad DCP1; a voltage connection pad VCP; a first node connection line Cln1; a second node connection line Cln2; a third node connection line Cln3; a relay electrode RE; a first reset signal connection line Cli1; and a second reset signal connection line Cli2.

[0111] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer SD1. For example, the conductive material can be deposited on the substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, a plurality of first reset signal lines (e.g., corresponding first reset signal lines Vint1); a plurality of fourth reset signal lines (e.g., corresponding fourth reset signal lines Vintv); a first data connection pad DCP1; a voltage connection pad VCP; a first node connection line Cln1; a second node connection line Cln2; a third node connection line Cln3; a relay electrode RE; a first reset signal connection line Cli1; and a second reset signal connection line Cli2 are located in the same layer.

[0112] In some embodiments, the first node connection line Cln1 connects multiple components of the pixel driving circuit to node N1. (See reference...) Figure 4A The first node connection line Cln1 is connected to the first capacitor electrode Ce1 through the first via v1, and to the second transistor T2 (e.g., connected to the first electrode S2 of the second transistor T2) through the second via v2. Optionally, the first node connection line Cln1 corresponds to Figure 2A The node N1 described in the text.

[0113] Reference Figure 2A , Figure 3A , Figure 3E , Figure 3F and Figure 4AIn some embodiments, a portion of the second capacitor electrode Ce2 is absent from the via region H. Optionally, except for the via region H in which a portion of the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 onto the substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and extends beyond the orthographic projection of the first capacitor electrode Ce1 onto the substrate BS. Optionally, the first via v1 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the via region H, and the insulating layer IN.

[0114] In some embodiments, the first node connection line Cln1 crosses a corresponding second gate line among a plurality of second gate lines. For example... Figure 3A and Figure 4A As shown, the first node connection line Cln1 crosses the first branch GL2-1 of the corresponding second gate line in the second gate metal layer Gate2 and the second branch GL2-2 of the corresponding second gate line in the third gate metal layer Gate3.

[0115] In some embodiments, reference Figure 4B The second node connection line Cln2 is connected to the second electrode D3 of the third transistor T3 through the third via v3, and to the second electrode Dr3 of the third reset transistor Tr3 through the fourth via v4. Optionally, the second node connection line Cln2 corresponds to Figure 2A Node N2 as described in the diagram. Optionally, the second node connection line Cln2 crosses the corresponding light emission control signal line em among the plurality of light emission control signal lines.

[0116] In some embodiments, reference Figure 4C The third node connection line Cln3 is connected to the second electrode Dr2 of the second reset transistor Tr2 through the fifth via v5, to the second electrode D2 of the second transistor T2 through the sixth via v6, and to the second electrode Dd of the driving transistor Td and the first electrode S4 of the fourth transistor T4 through the seventh via v7. Optionally, the third node connection line Cln3 corresponds to Figure 2A Node N3 as described in [the document]. Optionally, the third node connection line Cln3 crosses a corresponding second gate line among a plurality of second gate lines. [Example...] Figure 3A and Figure 4C As shown, the third node connection line Cln3 crosses the first branch GL2-1 of the corresponding second gate line in the second gate metal layer Gate2, and the second branch GL2-2 of the corresponding second gate line in the third gate metal layer Gate3.

[0117] In some embodiments, the orthographic projection of the third node connection line Cln3 on the substrate BS at least partially overlaps (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) with the orthographic projection of the active layer ACT2 of the second transistor T2 on the substrate BS. Optionally, the third node connection line Cln3 extends in a direction substantially parallel to the extension direction of the active layer ACT2 of the second transistor T2. Optionally, the orthographic projection of the third node connection line Cln3 on the substrate BS at least partially overlaps with the orthographic projection of the first electrode S2 of the second transistor T2 on the substrate. Optionally, the orthographic projection of the third node connection line Cln3 on the substrate BS at least partially overlaps with the orthographic projection of the second electrode D2 of the second transistor T2 on the substrate.

[0118] In some embodiments, reference Figure 4D The voltage connection pad VCP connects a corresponding first voltage supply line Vddh from a plurality of first voltage supply lines to the second capacitor electrode Ce2, and also connects a corresponding first voltage supply line Vddh from a plurality of first voltage supply lines to the first electrode S3 of the third transistor T3. The voltage connection pad VCP is connected to the second capacitor electrode Ce2 via a tenth via v10, and to the first electrode S3 of the third transistor T3 via an eleventh via v11. Optionally, a corresponding second voltage supply line Vddv from a plurality of second voltage supply lines is connected to a corresponding first voltage supply line Vddh from a plurality of first voltage supply lines via an eighth via v8, and a corresponding first voltage supply line Vddh from a plurality of first voltage supply lines is connected to the voltage connection pad VCP via a ninth via v9, thereby providing a first reference voltage signal to the voltage connection pad VCP, and subsequently to the second capacitor electrode Ce2.

[0119] In some embodiments, the voltage connection pad VCP is located in the region between two adjacent pixel driving circuits in the same row, where at least one data line exists between the two adjacent pixel driving circuits. Optionally, the voltage connection pad VCP is not present in the region between two adjacent pixel driving circuits in the same row, where no data line exists between the two adjacent pixel driving circuits. In some embodiments, the orthographic projection of the voltage connection pad VCP on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate. With this structure, the voltage connection pad VCP is spaced apart from the first node connection line Cln1. The inventors of this disclosure have discovered that by spaced apart the voltage connection pad VCP from the first node connection line Cln1, a short circuit between the voltage connection pad VCP and the first node connection line Cln1 can be avoided.

[0120] See Figure 3A , Figure 3N and Figure 3P In some embodiments, the corresponding first voltage supply line Vddh extends in a direction substantially parallel to the first direction DR1, and the corresponding second voltage supply line Vddv extends in a direction substantially parallel to the second direction DR2. Optionally, the plurality of first voltage supply lines and the plurality of second voltage supply lines form an interconnected voltage supply network. The first direction DR1 and the second direction DR2 are different from each other.

[0121] In some embodiments, see Figure 4E The first reset signal connection line Cli1 connects a corresponding second reset signal line Vint2 among a plurality of second reset signal lines to the first electrode Sr2 of the second reset transistor. Optionally, the first reset signal connection line Cli1 is connected via a thirteenth via v13 to the overall structure including the first electrodes (Sr2 and Sr2') of the second reset transistors in two adjacent pixel driving circuits in the same row, to a portion of the corresponding second reset signal line Vint2 in the first adjacent pixel driving circuit, and to a portion of the corresponding second reset signal line Vint2 in the second adjacent pixel driving circuit. Through the thirteenth via v13, the first reset signal connection line Cli1 is configured to transmit the reset signal from the corresponding second reset signal line Vint2 to the first electrode of the second reset transistor in the two adjacent pixel driving circuits in the same row.

[0122] In some embodiments, see Figure 4F The second reset signal connection line Cli2 connects the corresponding third reset signal line Vint3 among the plurality of third reset signal lines to the first electrode Sr3 of the third reset transistor. The second reset signal connection line Cli2 is connected to the first electrode Sr3 of the third reset transistor through the fifteenth via v15, and to the corresponding third reset signal line Vint3 among the plurality of third reset signal lines through the sixteenth via v16, thereby transmitting the reset signal from the corresponding third reset signal line Vint3 to the first electrode Sr3 of the third reset transistor.

[0123] In some embodiments, see Figure 4G The corresponding first reset signal line Vint1 among the multiple first reset signal lines is connected to the first electrode Sr1 of the first reset transistor through the seventeenth via v17.

[0124] In some embodiments, reference Figure 4H The first data connection pad DCP1 and the second data connection pad DCP2 connect the corresponding data line DL to the first electrode S1 of the first transistor. The first data connection pad DCP1 is connected to the first electrode S1 of the first transistor through the twentieth via v20. (Reference) Figure 3N and Figure 4HThe second data connection pad DCP2 in the second signal line layer SD2 is connected to the first data connection pad DCP1 through the nineteenth via v19. (Refer to...) Figure 3P and Figure 4H The corresponding data line DL of the multiple data lines is connected to the second data connection pad DCP2 through the eighteenth via v18. The first data connection pad DCP1 and the second data connection pad DCP2 are configured to transmit data signals from the corresponding data line DL to the first electrode S1 of the first transistor.

[0125] Figure 3M The vias extending through the first planarization layer PLN1 are shown.

[0126] refer to Figure 2A , Figure 3A , Figure 3N and Figures 4A to 4H In some embodiments, the second signal line layer SD2 includes a plurality of first voltage supply lines (e.g., corresponding first voltage supply lines Vddh), a second data connection pad DCP2, an anode contact pad ACP, and a plurality of first fan-out connections (e.g., corresponding first fan-out connections FIPh). Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer SD2. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer SD2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of first voltage supply lines (e.g., corresponding first voltage supply lines Vddh), the second data connection pad DCP2, the anode contact pad ACP, and the plurality of first fan-out connections (e.g., corresponding first fan-out connections FIPh) are located in the same layer.

[0127] Figure 3O The image shows a via extending through the second planarization layer PLN2.

[0128] refer to Figure 2A , Figure 3A , Figure 3P , Figures 4A to 4HIn some embodiments, the third signal line layer SD3 includes a plurality of second voltage supply lines (e.g., corresponding second voltage supply lines Vddv), a plurality of data lines (e.g., corresponding data lines DL), and a plurality of second fan-out connection lines (e.g., corresponding second fan-out connection lines FIPv). Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the third signal line layer SD3. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third signal line layer SD3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of second voltage supply lines (e.g., corresponding second voltage supply lines Vddv), the plurality of data lines (e.g., corresponding data lines DL), and the plurality of second fan-out connection lines (e.g., corresponding second fan-out connection lines FIPv) are located in the same layer.

[0129] Multiple first fan-out connectors and multiple second fan-out connectors are configured to connect multiple data lines to a data driving circuit. By positioning the fan-out connectors at least partially within the display area of ​​the array substrate, the array substrate can have a reduced peripheral area.

[0130] In some embodiments, the corresponding first fan-out connection line FIPh extends in a direction substantially parallel to the first direction DR1, while the corresponding second voltage supply line Vddv extends in a direction substantially parallel to the second direction DR2.

[0131] In some embodiments, the orthographic projection of the corresponding second voltage supply line Vddv on the substrate BS at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) covers the orthographic projection of the first node connection line Cln1 on the substrate BS. Optionally, the orthographic projection of the corresponding second voltage supply line Vddv on the substrate BS at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) covers the orthographic projection of the first electrode S2 of the second transistor T2 on the substrate BS. By having this particular structure, the inventors of this disclosure have found that node N1 can be shielded from interference from other signals in the array substrate.

[0132] In some embodiments, the orthogonal projection of the corresponding second voltage supply line Vddv onto the substrate BS at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) covers the orthogonal projection of the active layer ACT2 of the second transistor T2 onto the substrate BS. By having this particular structure, the inventors of this disclosure have found that the active layer ACT2 of the second transistor T2 can be shielded from radiation, thereby enhancing the performance of the second transistor T2 in a pixel driving circuit.

[0133] In some embodiments, the orthographic projection of the corresponding second voltage supply line Vddv on the substrate BS at least partially (e.g., at least 20%, at least 30%, at least 40%, at least 50%, or at least 60%) covers the orthographic projection of the third node connection line Cln3 on the substrate BS.

[0134] In some embodiments, reference Figure 2A , Figure 3A , Figure 3F , Figure 3J , Figure 4A and Figure 4C The corresponding second gate line includes a first branch GL2-1 and a second branch GL2-2 located in two different layers. Optionally, the first branch GL2-1 is located in the second gate metal layer Gate2, and the second branch GL2-2 is located in the third gate metal layer Gate3. Optionally, the orthographic projection of the first branch GL2-1 on the substrate BS overlaps at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) with the orthographic projection of the second branch GL2-2 on the substrate BS. Optionally, the first branch GL2-1 and the second branch GL2-2 are configured to provide the same gate scan signal.

[0135] Figure 3Q The image shows a via extending through the third planarization layer PLN3.

[0136] Reference Figure 2A , Figure 3A , Figure 3R , Figures 4A to 4H In some embodiments, the anode layer ADL includes multiple anodes AD.

[0137] Reference Figures 3A to 3R as well as Figures 4A to 4H In some embodiments, the first pixel driving circuits that are directly adjacent to each other and in the current level (e.g., in the same row) (e.g., Figure 3B The corresponding layer of PDC1 and the second pixel driving circuit (e.g., Figure 3B The corresponding layer of PDC2 in the array, for example, has a substantially mirror symmetric relationship with respect to the plane that is perpendicular to the main surface of the array substrate and substantially parallel to the multiple data lines.

[0138] As used herein, the term "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" is not intended to include layers that are not part of the pixel driving circuit. For example, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include an anode layer or a pixel defining layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a light-shielding layer or a first signal line layer. In one example, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" refers to at least one conductive layer of the first pixel driving circuit and a conductive layer of the second pixel driving circuit. In a specific example, "corresponding layer" includes at least one of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, a second signal line layer, or a third signal line layer. In another specific example, "corresponding layer" also includes at least one of a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, a second planarization layer, or a third planarization layer.

[0139] Figure 5 This is a diagram illustrating the structure of a light-shielding layer in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 3A , Figure 3C and Figure 5 In some embodiments, the light-shielding layer includes multiple islands Is, multiple first bridges Br1, multiple second bridges Br2, and multiple third bridges Br3.

[0140] Figure 6 This is a diagram illustrating the structure of the light-shielding layer and the third signal line layer in an array substrate according to some embodiments of the present disclosure. (See reference...) Figure 3A , Figure 3C , Figure 5 and Figure 6 In some embodiments, a plurality of first bridges Br1 extend in a direction substantially parallel to the first direction DR1; in some embodiments, a plurality of second bridges Br2 extend in a direction substantially parallel to the first direction DR1; and in some embodiments, a plurality of third bridges Br3 extend in a direction substantially parallel to the second direction DR2.

[0141] In some embodiments, each of the plurality of first bridges Br1 connects two adjacent islands of the plurality of islands Is located in the same row, where there is no data line between the two adjacent pixel driving circuits. Optionally, each of the first bridges does not cross any data line.

[0142] In some embodiments, each of the plurality of second bridges Br2 connects two adjacent islands of the plurality of islands Is located in the same row, with at least one data line between the two adjacent pixel driving circuits. Optionally, each second bridge spans at least one data line. In one example, each second bridge spans two data lines.

[0143] In some embodiments, each of the plurality of third bridges Br3 connects two adjacent islands in the plurality of islands Is, which are located in the same column of adjacent pixel driving circuits.

[0144] In some embodiments, the array substrate includes a first region R1 and a second region R2 outside the first region R1. In the first region R1, the light-shielding layer further includes an additional signal line PDSL. Optionally, the additional signal line PDSL extends along a direction substantially parallel to the second direction DR2. In one example, the additional signal line PDSL is a sensor signal line of a photodetector. For example, the additional signal line PDSL can be an input or output signal line of the photodetector. Optionally, the additional signal line PDSL is located between two adjacent pixel driving circuits in the same row, where there is no data line between the two adjacent pixel driving circuits. In one example, the photodetector is a photodetector configured to detect ambient light intensity.

[0145] In some embodiments, the additional signal line PDSL is electrically isolated from the light-shielding element LS. Optionally, at least partially, a plurality of first bridges Br1 are absent in the first region R1 to allow the additional signal line PDSL to pass between two adjacent pixel driving circuits located in the same row without being connected to the light-shielding element LS, wherein there is no data line between the two adjacent pixel driving circuits.

[0146] In the second region R2, the light-shielding layer also includes an auxiliary line AUL. The auxiliary line AUL is located in the second region R2 at a position corresponding to the additional signal line PDSL located in the first region R1. Optionally, the auxiliary line AUL extends in a direction substantially parallel to the second direction DR2. Optionally, the auxiliary line AUL is located between two adjacent pixel driving circuits in the same row, where no data lines exist between the two adjacent pixel driving circuits.

[0147] In some embodiments, the light-shielding layer includes a plurality of auxiliary lines located in the second region R2, each auxiliary line being located between two adjacent pixel driving circuits in the same row, and no data lines are present between the two adjacent pixel driving circuits. The inventors of this disclosure have discovered that by placing auxiliary lines in the second region R2 at positions corresponding to the additional signal lines PDSL in the first region R1, the display uniformity of the entire array substrate can be improved.

[0148] In some embodiments, the auxiliary line AUL is connected to a plurality of first bridges located in the same column among a plurality of first bridges Br1. Optionally, in at least a portion of the second region R2, the auxiliary line AUL is part of an overall structure comprising a plurality of islands Is, a plurality of first bridges Br1, a plurality of second bridges Br2, and a plurality of third bridges Br3.

[0149] Reference Figure 5 In some embodiments, the auxiliary line AUL is a continuous line extending through multiple rows of pixel driving circuits.

[0150] Figure 7 This is a diagram illustrating the structure of a light-shielding layer in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 3A , Figure 3C and Figure 7 In some embodiments, the auxiliary line AUL comprises a plurality of spaced-apart segments AUF. Optionally, each segment is located in a corresponding row of pixel driving circuits and between two adjacent pixel driving circuits in a corresponding pair within the corresponding row, where no data lines exist between the two adjacent pixel driving circuits. Optionally, each segment is connected to a corresponding first bridge, which connects two adjacent islands in a corresponding pair of adjacent pixel driving circuits located in a corresponding row, where no data lines exist between the two adjacent pixel driving circuits.

[0151] Figure 8 This is a diagram illustrating the structure of the light-shielding layer and the first semiconductor material layer in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 3A , Figure 3C , Figure 7 and Figure 8In some embodiments, the orthographic projections of the plurality of segmented AUFs on the substrate are substantially non-overlapping with the orthographic projections of the first semiconductor material layer on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap). Optionally, the orthographic projections of the plurality of segmented AUFs on the substrate are substantially non-overlapping with the orthographic projections of the semiconductor material layer of the second reset transistor on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap). Optionally, the orthographic projections of the plurality of segmented AUFs on the substrate are substantially non-overlapping with the orthographic projections of the first electrode Sr2 of the second reset transistor on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap). Optionally, the orthographic projections of the plurality of segmented AUFs on the substrate are substantially non-overlapping with the orthographic projections of the active layer ACTr2 of the second reset transistor on the substrate (e.g., at least 80% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or completely non-overlapping). Alternatively, the orthographic projections of the plurality of segmented AUFs on the substrate are substantially non-overlapping with the orthographic projections of the second electrode Dr2 of the second reset transistor on the substrate (e.g., at least 80% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 99% non-overlapping, or completely non-overlapping).

[0152] In one example, the orthographic projections of the plurality of segmented AUFs onto the substrate do not overlap with the orthographic projection of the first electrode Sr2 of the second reset transistor onto the substrate. In another example, the orthographic projections of the plurality of segmented AUFs onto the substrate do not overlap with the orthographic projection of the active layer ACTr2 of the second reset transistor onto the substrate. In yet another example, the orthographic projections of the plurality of segmented AUFs onto the substrate do not overlap with the orthographic projection of the second electrode Dr2 of the second reset transistor onto the substrate. The inventors of this disclosure have found that this structure can minimize any interference from the light-shielding layer to the transistor (e.g., the second reset transistor).

[0153] Figure 9 This is a diagram illustrating the structure of a light-shielding layer and a second semiconductor material layer in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 3A , Figure 3C , Figure 7 and Figure 9In some embodiments, the orthographic projections of the plurality of segmented AUFs on the substrate are substantially non-overlapping with the orthographic projections of the second semiconductor material layer on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap). Optionally, the orthographic projections of the plurality of segmented AUFs on the substrate are substantially non-overlapping with the orthographic projections of the semiconductor material layer of the second transistor on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap). Optionally, the orthographic projections of the plurality of segmented AUFs on the substrate are substantially non-overlapping with the orthographic projections of the first electrode S2 of the second transistor on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap). Optionally, the orthographic projections of the plurality of segmented AUFs on the substrate are substantially non-overlapping with the orthographic projections of the active layer ACT2 of the second transistor on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap). Alternatively, the orthographic projections of the plurality of segmented AUFs on the substrate are substantially non-overlapping with the orthographic projections of the second electrode D2 of the second transistor on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap).

[0154] In one example, the orthographic projections of the multiple segmented AUFs onto the substrate do not overlap with the orthographic projection of the first electrode S2 of the second transistor onto the substrate. In another example, the orthographic projections of the multiple segmented AUFs onto the substrate do not overlap with the orthographic projection of the active layer ACT2 of the second transistor onto the substrate. In yet another example, the orthographic projections of the multiple segmented AUFs onto the substrate do not overlap with the orthographic projection of the second electrode D2 of the second transistor onto the substrate. The inventors of this disclosure have found that this structure can minimize any interference from the light-shielding layer to the transistor (e.g., the second transistor).

[0155] Reference Figure 3A , Figure 3N and Figure 3P As described above, in some embodiments, the array substrate includes a plurality of first fan-out connections (e.g., corresponding first fan-out connections FIPh) and a plurality of second fan-out connections (e.g., corresponding second fan-out connections FIPv). Optionally, the plurality of first fan-out connections are located in the second signal line layer. Optionally, the plurality of second fan-out connections are located in the third signal line layer. Optionally, the plurality of first fan-out connections extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of second fan-out connections extend in a direction substantially parallel to the second direction DR2.

[0156] In some embodiments, each second fan-out connection (FIPv) is located between a second voltage supply line and a data line. Optionally, two adjacent second fan-out connections are located between two adjacent data lines. Optionally, the second voltage supply lines of the plurality of second voltage supply lines space adjacent second fan-out connections apart.

[0157] Figure 10 This is a diagram illustrating the layout of certain signal lines in the second and third signal line layers of an array substrate according to some embodiments of the present disclosure. (See reference...) Figure 10 In some embodiments, each data line DL is connected to a corresponding first fan-out connection line FIPh, for example, via a first connection via cv1 extending through the second planarization layer. Each second fan-out connection line FIPv is connected to a corresponding first fan-out connection line FIPh, for example, via a second connection via cv2 extending through the second planarization layer. Each first fan-out connection line FIPh connects the corresponding data line DL to the corresponding second fan-out connection line FIPv. A plurality of second fan-out connections are connected to a data drive circuit DDC. Optionally, a single first fan-out connection line among the plurality of first fan-out connections is connected to only one of the plurality of data lines, and a single data line among the plurality of data lines is connected to only one of the plurality of first fan-out connection lines. Optionally, a single second fan-out connection line among the plurality of second fan-out connections is connected to only one of the plurality of first fan-out connection lines, and a single first fan-out connection line among the plurality of first fan-out connection lines is connected to only one of the plurality of second fan-out connection lines.

[0158] In some embodiments, at least one of the plurality of first fan-out connection lines crosses a plurality of data lines, but except for one corresponding data line, at least one of the plurality of first fan-out connection lines is not connected to the plurality of data lines. Figure 11A The connection between the corresponding data line and the corresponding first fan-out connection line via the first connection via is shown. Figure 11B The connection between the corresponding first fan-out connection line and the corresponding second fan-out connection line via the second connection via is shown.

[0159] Reference Figure 10In some embodiments, the array substrate further includes a plurality of third voltage supply lines. In some embodiments, each of the first voltage supply lines Vddh and each of the second voltage supply lines Vddv is configured to provide a first reference voltage signal (e.g., a high reference voltage signal). Optionally, each of the third voltage supply lines Vss is configured to provide a second reference voltage signal (e.g., a low reference voltage signal). Optionally, the first reference voltage signal is a constant voltage signal, the second reference voltage signal is a constant voltage signal, and the voltage level of the first reference voltage signal is higher than the voltage level of the second reference voltage signal.

[0160] Optionally, the plurality of third voltage supply lines are located in the third signal line layer. Optionally, the plurality of third voltage supply lines extend in a direction substantially parallel to the second direction DR2.

[0161] In some embodiments, a corresponding third voltage supply line Vss among the plurality of third voltage supply lines is located between a second voltage supply line and a data line. Optionally, two adjacent third voltage supply lines among the plurality of third voltage supply lines are located between two adjacent data lines among the plurality of data lines. Optionally, the second voltage supply lines among the plurality of second voltage supply lines space apart two adjacent third voltage supply lines.

[0162] In some embodiments, at least one of the plurality of third voltage supply lines and the second fan-out connection line of the plurality of second fan-out connection lines are disconnected from each other and located between the same second voltage supply line and the same data line configured to provide signals to the same column of pixel driving circuitry. The at least one third voltage supply line crosses a first portion of the array substrate, the second fan-out connection line crosses a second portion of the array substrate, and the first and second portions do not overlap. For example, the at least one third voltage supply line crosses at least one row of pixel driving circuitry in the first portion of the array substrate, the second fan-out connection line crosses at least one row of pixel driving circuitry in the second portion of the array substrate, and the first and second portions do not overlap.

[0163] In some embodiments, the additional signal line is located in a region adjacent to the window region of the array substrate. Figure 12 The layout of window regions in an array substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figure 12The array substrate includes a window area WR with holes configured for mounting accessories such as camera lenses or fingerprint sensors. An additional signal line PDSL is connected to the accessory mounted in the window area WR. In one example, the additional signal line PDSL is a sensor signal line for a photoelectric sensor. For example, the additional signal line PDSL can be an input or output signal line of the photoelectric sensor. In one example, the photoelectric sensor is a photoelectric sensor configured to detect ambient light intensity.

[0164] Reference Figure 3A and Figure 3C In some embodiments, the additional signal line PDSL is disposed within the light-shielding layer.

[0165] In an alternative embodiment, the additional signal lines may be located in other suitable layers. Figure 13 The layout of window regions in an array substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figure 13 In some embodiments, the additional signal line PDSL is connected to the signal line connected to the attachment located in the window area WR. The signal line located in the window area WR is connected to the additional signal line PDSL via a connection pad PAD. In one example, the additional signal line PDSL is located in the third signal line layer.

[0166] Figure 14 This is a diagram illustrating the structure of a third signal line layer in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 14 The additional signal line PDSL is located in the third signal line layer in at least a portion of the array substrate.

[0167] In some embodiments, the additional signal line PDSL is located between the corresponding second voltage supply line Vddv and the corresponding data line DL. Optionally, two adjacent additional signal lines are located between two adjacent data lines. Optionally, one of the multiple second voltage supply lines spaces two adjacent additional signal lines apart.

[0168] Figure 15 This is a schematic diagram illustrating the structure of the second signal line layer, the third signal line layer, and the anode layer in an array substrate according to some embodiments of the present disclosure. (See reference...) Figure 3A , Figure 3N , Figure 3P , Figure 3R and Figure 15In some embodiments, the orthographic projections of the plurality of anode ADs on the substrate are substantially non-overlapping with the orthographic projections of the plurality of first fan-out connection lines (e.g., corresponding first fan-out connection lines FIPh) on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap). In some embodiments, the orthographic projections of the plurality of anode ADs on the substrate are substantially non-overlapping with the orthographic projections of the plurality of first voltage supply lines (e.g., corresponding first voltage supply lines Vddh) on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap).

[0169] Optionally, the orthographic projections of the plurality of anodes AD on the substrate are substantially non-overlapping with the orthographic projections of the plurality of first fan-out connection lines (e.g., corresponding first fan-out connection lines FIPh) on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap), and substantially non-overlapping with the orthographic projections of the plurality of first voltage supply lines (e.g., corresponding first voltage supply lines Vddh) on the substrate (e.g., at least 80% non-overlap, at least 90% non-overlap, at least 95% non-overlap, at least 99% non-overlap, or completely non-overlap).

[0170] The inventors of this disclosure have discovered that the degree of evenness of the anode in a display panel can adversely affect image display. For example, anode tilt can cause color shift. This disclosure reveals that signal lines beneath the anode can significantly influence the degree of anode tilt. In one example, signal lines are positioned on one side below the anode, while no signal lines are present on the other side. This results in an uneven surface of the planarization layer on top of the signal lines. This uneven surface of the planarization layer, in turn, causes the anode on top of the planarization layer to tilt. For example, the presence of signal lines beneath the left portion of the planarization layer causes an uneven surface of the planarization layer, which in turn causes the anode on top of the planarization layer to tilt to the right. The tilted anode reflects more light towards the right side of the display panel. In a display panel, anodes associated with sub-pixels of different colors have different tilt angles, so light reflected by the anodes in sub-pixels of different colors is reflected at different angles to different colors of light. The cumulative effect of this problem leads to color shift at large viewing angles.

[0171] In this disclosure, by ensuring that the orthographic projections of the plurality of anodes (ADs) on the substrate do not substantially overlap with the orthographic projections of the plurality of first fan-out connection lines on the substrate, and also do not substantially overlap with the orthographic projections of the plurality of first voltage supply lines on the substrate, the surface of the array substrate below the anodes is made flat. Therefore, color shift problems can be mitigated.

[0172] In some embodiments, the anode layer includes a first corresponding anode RAD1, a second corresponding anode RAD2, a third corresponding anode RAD3, and a fourth corresponding anode RAD4. In one example, the first corresponding anode RAD1 is an anode for a sub-pixel of a first color (e.g., a red sub-pixel), the second corresponding anode RAD2 is an anode for a sub-pixel of a second color (e.g., a blue sub-pixel), and the third corresponding anode RAD3 and the fourth corresponding anode RAD4 are anodes for two sub-pixels of a third color (e.g., two green sub-pixels). In some embodiments, the array of multiple sub-pixels in the array substrate includes a repeating array in the form of RGBG, where R represents a red sub-pixel, B represents a blue sub-pixel, and G represents a green sub-pixel.

[0173] Figure 16 This is a diagram illustrating the structure of an anode layer in an array substrate according to some embodiments of the present disclosure. In some embodiments, a first corresponding anode RAD1 includes a first main anode portion MAP1 and a first extension E1 extending in a direction away from the first main anode portion MAP1. The first extension E1 connects the first main anode portion MAP1 to a first corresponding anode connection pad. In some embodiments, a second corresponding anode RAD2 includes a second main anode portion MAP2 and a second extension E2 extending in a direction away from the second main anode portion MAP2. The second extension E2 connects the second main anode portion MAP2 to a second corresponding anode connection pad. In some embodiments, a third corresponding anode RAD3 includes a third main anode portion MAP3 and a third extension E3 extending in a direction away from the third main anode portion MAP3. The third extension E3 connects the third main anode portion MAP3 to a third corresponding anode connection pad. In some embodiments, a fourth corresponding anode RAD4 includes a fourth main anode portion MAP4 and a fourth extension E4 extending in a direction away from the fourth main anode portion MAP4. The fourth extension E4 connects the fourth main anode portion MAP4 to a fourth corresponding anode connection pad. Optionally, the first extension E1 extends in a direction substantially parallel to the second direction DR2, moving away from the first main anode portion MAP1. Optionally, the second extension E2 extends in a direction substantially parallel to the second direction DR2, moving away from the second main anode portion MAP2. Optionally, the third extension E3 extends in a direction substantially parallel to the first direction DR1, moving away from the third main anode portion MAP3. Optionally, the fourth extension E4 extends in a direction substantially parallel to the first direction DR1, moving away from the fourth main anode portion MAP4.

[0174] In some embodiments, the orthographic projection of the first main anode portion MAP1 on the substrate does not overlap with the orthographic projections of the plurality of first fan-out connection lines on the substrate, nor does it overlap with the orthographic projections of the plurality of first voltage supply lines on the substrate. In some embodiments, the orthographic projection of the second main anode portion MAP2 on the substrate does not overlap with the orthographic projections of the plurality of first fan-out connection lines on the substrate, nor does it overlap with the orthographic projections of the plurality of first voltage supply lines on the substrate. In some embodiments, the orthographic projection of the third main anode portion MAP3 on the substrate does not overlap with the orthographic projections of the plurality of first fan-out connection lines on the substrate, nor does it overlap with the orthographic projections of the plurality of first voltage supply lines on the substrate. In some embodiments, the orthographic projection of the fourth main anode portion MAP4 on the substrate does not overlap with the orthographic projections of the plurality of first fan-out connection lines on the substrate, nor does it overlap with the orthographic projections of the plurality of first voltage supply lines on the substrate.

[0175] In some embodiments, the orthographic projections of a plurality of second voltage supply lines (e.g., corresponding second voltage supply lines Vddv) on the substrate substantially cover (e.g., cover at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely cover) the orthographic projection of the first corresponding anode RAD1 on the substrate. In some embodiments, the orthographic projections of a plurality of second voltage supply lines (e.g., corresponding second voltage supply lines Vddv) on the substrate substantially cover (e.g., cover at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely cover) the orthographic projection of the second corresponding anode RAD2 on the substrate. The inventors of this disclosure have discovered that by making the orthographic projections of a plurality of second voltage supply lines on the substrate cover the orthographic projections of the first corresponding anode RAD1 and the second corresponding anode RAD2 on the substrate, a planarization layer can be made flat on the surface beneath the first corresponding anode RAD1 and the second corresponding anode RAD2. Therefore, color shift problems can be mitigated.

[0176] In some embodiments, the orthographic projections of the plurality of second voltage supply lines on the substrate completely cover the orthographic projection of the first main anode portion MAP1 on the substrate. In some embodiments, the orthographic projections of the plurality of second voltage supply lines on the substrate completely cover the orthographic projection of the second main anode portion MAP2 on the substrate.

[0177] In some embodiments, the orthographic projection of the third corresponding anode RAD3 on the substrate at least partially overlaps with the orthographic projections of the two adjacent data lines and the two adjacent second fan-out connection lines on the substrate, such as... Figure 15As shown. Two adjacent data lines and two adjacent second fan-out connection lines cross the third corresponding anode RAD3 along the second direction DR2, and the two adjacent data lines and two adjacent second fan-out connection lines are substantially uniformly distributed along the first direction DR1 relative to the third main anode portion MAP3 of the third corresponding anode RAD3. For example, the portions of two adjacent data lines and two adjacent second fan-out connection lines in the region crossing the third main anode portion MAP3 are equally spaced. In another example, the portions of two adjacent data lines and two adjacent second fan-out connection lines in the region crossing the third main anode portion MAP3 have mirror symmetry with respect to a plane intersecting the center point of the third main anode portion MAP3 and perpendicular to the third main anode portion MAP3. The inventors of this disclosure have discovered that by having a unique structure of anodes and signal lines according to this disclosure, a planarization layer can be made flat on the surface below the third corresponding anode RAD3. Therefore, color shift problems can be mitigated.

[0178] In some embodiments, the orthographic projection of the fourth corresponding anode RAD4 on the substrate at least partially overlaps with the orthographic projections of the two adjacent data lines and the two adjacent second fan-out connection lines on the substrate, such as Figure 15 As shown in the diagram, two adjacent data lines and two adjacent second fan-out connection lines cross the fourth corresponding anode RAD4 along the second direction DR2, and the two adjacent data lines and two adjacent second fan-out connection lines are substantially uniformly distributed relative to the fourth main anode portion MAP4 of the fourth corresponding anode RAD4 along the first direction DR1. For example, the portions of two adjacent data lines and two adjacent second fan-out connection lines in the region crossing the fourth main anode portion MAP4 are equally spaced. In another example, the portions of two adjacent data lines and two adjacent second fan-out connection lines in the region crossing the fourth main anode portion MAP4 have mirror symmetry with respect to a plane intersecting the center point of the fourth main anode portion MAP4 and perpendicular to the fourth main anode portion MAP4. The inventors of this disclosure have discovered that by having a unique structure of anodes and signal lines according to this disclosure, a planarization layer can be made flat on the surface below the fourth corresponding anode RAD4. Therefore, color shift problems can be mitigated.

[0179] Reference Figure 3A and Figure 3LIn some embodiments, the array substrate includes an interconnect reset signal line network. In some embodiments, the interconnect reset signal line network includes a plurality of first reset signal lines (e.g., corresponding first reset signal lines Vint1) and a plurality of fourth reset signal lines (e.g., corresponding fourth reset signal lines Vintv) interconnected together. Optionally, the plurality of first reset signal lines extend in a direction substantially parallel to a first direction DR1. Optionally, the plurality of fourth reset signal lines extend in a direction substantially parallel to a second direction DR2. Optionally, the plurality of first reset signal lines and the plurality of fourth reset signal lines are part of an integral structure. Optionally, the plurality of first reset signal lines and the plurality of fourth reset signal lines are located in the same layer (e.g., in a first signal line layer).

[0180] In some embodiments, the ratio of the number of the plurality of first reset signal lines to the number of rows of pixel driving circuits located in the display area of ​​the array substrate is in the range of 0.8:1.0 to 1.2:1.0. In one embodiment, the ratio of the number of the plurality of first reset signal lines to the number of rows of pixel driving circuits located in the display area of ​​the array substrate is 1:1.

[0181] In some embodiments, the ratio of the number of the plurality of fourth reset signal lines to the number of columns of pixel driving circuits located in the display area of ​​the array substrate is in the range of 0.8:2.0 to 1.2:2.0. In one example, the ratio of the number of the plurality of fourth reset signal lines to the number of columns of pixel driving circuits located in the display area of ​​the array substrate is 1:2.

[0182] Figure 17 An interconnected reset signal line network according to some embodiments of the present disclosure is shown. (Refer to...) Figure 17 Multiple pixel driving circuits are arranged in multiple columns, including the (2k-1)th column C(2k-1) and the (2k)th column C(2k) of a total of K columns, where K and k are positive integers, 1 ≤ k ≤ (K / 2). (See reference) Figure 17 In some embodiments, multiple fourth reset signal lines exist in column (2k-1) C(2k-1) but not in column (2k) C(2k).

[0183] As used herein, the terms “(2k-1)th column” and “(2k)th column” are used in the context of column K. The array substrate may or may not include additional columns preceding the first column of column K and / or additional columns following the last column of column K. In the context of the array substrate, the term “(2k-1)th column” does not necessarily mean an odd-numbered column, and the term “(2k)th column” does not necessarily mean an even-numbered column. In one example, column (2k-1)th column is an odd-numbered column in the context of column K, but may be an even-numbered column in the context of the array substrate. In another example, column (2k-1)th column is an odd-numbered column in both the context of column K and the context of the array substrate. In one example, column (2k)th column is an even-numbered column in the context of column K, but may be an odd-numbered column in the context of the array substrate. In another example, column (2k)th column is an even-numbered column in both the context of column K and the context of the array substrate.

[0184] Figure 18 An interconnect voltage supply network according to some embodiments of this disclosure is shown. See also Figure 18 In some embodiments, the interconnect voltage supply network includes a plurality of first voltage supply lines (e.g., corresponding first voltage supply lines Vddh) and a plurality of second voltage supply lines (e.g., corresponding second voltage supply lines Vddv) interconnected together. Optionally, the plurality of first voltage supply lines extend along a direction substantially parallel to a first direction DR1. Optionally, the plurality of second voltage supply lines extend along a direction substantially parallel to a second direction DR2. Optionally, the plurality of first voltage supply lines and the plurality of second voltage supply lines are located in different layers. In one example, the plurality of first voltage supply lines are located in a second signal line layer. In another example, the plurality of second voltage supply lines are located in a third signal line layer. Optionally, each second voltage supply line Vddv is connected to a corresponding first voltage supply line Vddh via an eighth via v8 (e.g., see...). Figure 4D In one example, the eighth via v8 extends through the second planarization layer PLN2.

[0185] In some embodiments, the ratio of the number of the plurality of second voltage supply lines to the number of columns of the pixel driving circuits located in the display area of ​​the array substrate is in the range of 0.8:2.0 to 1.2:2.0. In one example, the ratio of the number of the plurality of second voltage supply lines to the number of columns of the pixel driving circuits located in the display area of ​​the array substrate is 1:2. Each second voltage supply line Vddv is at least partially located in the (2k)th column and at least partially located in the (2k-1)th column.

[0186] In another aspect, the present invention provides a display device comprising an array substrate manufactured as described herein or by the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0187] In another aspect, this disclosure provides a method of manufacturing an array substrate. In some embodiments, the method includes forming a light-shielding layer on a substrate. Optionally, the orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the active layer of a driving transistor of a pixel driving circuit on the substrate. Optionally, forming the light-shielding layer located in a second region includes forming a plurality of islands, forming a plurality of bridges, and forming an auxiliary line extending along a direction substantially parallel to a second direction. Optionally, the auxiliary line is connected to one or more adjacent islands of the plurality of islands via one of the plurality of bridges. Optionally, forming the auxiliary line includes forming a plurality of spaced-apart segments. Optionally, the orthographic projections of the plurality of segments on the substrate do not substantially overlap with the orthographic projections of the transistors of the pixel driving circuit on the substrate.

[0188] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising: A substrate, and a light-shielding layer located on the substrate; Wherein, the orthographic projection of the light-shielding layer on the substrate overlaps at least partially with the orthographic projection of the active layer of the driving transistor of the pixel driving circuit on the substrate. The portion of the light-shielding layer located in the second region includes multiple islands, multiple bridges, and auxiliary lines extending along a direction substantially parallel to the second direction. The auxiliary line connects to one or more adjacent islands among the plurality of islands via one of the plurality of bridges; The auxiliary lines include multiple segments spaced apart from each other; and The orthographic projections of the plurality of segmented sections on the substrate do not substantially overlap with the orthographic projections of the transistors of the pixel driving circuit on the substrate.

2. The array substrate according to claim 1, wherein, In a column of segments, each segment is located in a row of pixel driving circuits, and is located between two adjacent pixel driving circuits in the corresponding pair in each row, with no data lines between the two adjacent pixel driving circuits.

3. The array substrate according to claim 1, further comprising additional signal lines located in a first region outside the second region; The additional signal line extends in a direction substantially parallel to the second direction; The additional signal line is located between two adjacent pixel driving circuits in the same row, and there is no data line between the two adjacent pixel driving circuits; and The additional signal lines extend continuously through multiple rows of pixel drive circuits.

4. The array substrate according to claim 3, wherein, The additional signal line is located in a region adjacent to a window region of the array substrate, the window region having holes configured for mounting accessories; as well as The additional signal line is connected to an accessory installed in the window area.

5. The array substrate according to claim 3, wherein, The additional signal line and the auxiliary line are located within the light-shielding layer.

6. The array substrate according to claim 3, wherein, The additional signal line is connected to the signal line connected to the accessory located in the window area; The signal line located in the window area is connected to the additional signal line via a connection pad; The additional signal line is located in the third signal line layer on the side of the light-shielding layer away from the substrate.

7. The array substrate according to any one of claims 1 to 6, further comprising: Multiple first fan-out connecting lines extend in a direction substantially parallel to the first direction; Multiple second fan-out connecting lines extend in a direction substantially parallel to the second direction; Multiple second voltage supply lines extend in a direction substantially parallel to the second direction; as well as Multiple data lines extending in a direction substantially parallel to the second direction; The corresponding second fan-out connection line among the plurality of second fan-out connection lines is located between the second voltage supply line and the data line; Two adjacent second fan-out connection lines are located between two adjacent data lines in the plurality of data lines; and One of the plurality of second voltage supply lines separates two adjacent second fan-out connection lines.

8. The array substrate according to claim 7, wherein, Each data cable is connected to the corresponding first fan-out connector; Each second fan-out connection line is connected to the corresponding first fan-out connection line; Each first fan-out connector connects the corresponding data line to the corresponding second fan-out connector; and The plurality of second fan-out connection lines are connected to the data drive circuit.

9. The array substrate of claim 7, further comprising a plurality of third voltage supply lines extending in a direction substantially parallel to the second direction; The corresponding third voltage supply line among the plurality of third voltage supply lines is located between the second voltage supply line and the data line; Two adjacent third voltage supply lines are located between two adjacent data lines in the plurality of data lines; and One of the plurality of second voltage supply lines separates two adjacent third voltage supply lines.

10. The array substrate according to claim 9, wherein, At least one of the plurality of third voltage supply lines and the second fan-out connection line of the plurality of second fan-out connection lines are disconnected from each other and are located between the same second voltage supply line and the same data line configured to provide signals to the same column of pixel driving circuits; The at least one third voltage supply line crosses the first portion of the array substrate; The second fan-out connection line crosses the second portion of the array substrate; as well as The first part and the second part do not overlap.

11. The array substrate according to any one of claims 1 to 6, further comprising: An anode layer comprising multiple anodes; Multiple first fan-out connecting lines extend in a direction substantially parallel to the first direction; as well as Multiple first voltage supply lines extend in a direction substantially parallel to the first direction; The orthographic projections of the plurality of anodes on the substrate do not substantially overlap with the orthographic projections of the plurality of first fan-out connection lines on the substrate, nor do they substantially overlap with the orthographic projections of the plurality of first voltage supply lines on the substrate.

12. The array substrate of claim 11, further comprising a plurality of second voltage supply lines extending in a direction substantially parallel to the second direction; in, The anode layer includes a first corresponding anode, a second corresponding anode, a third corresponding anode, and a fourth corresponding anode; and The orthogonal projections of the plurality of second voltage supply lines onto the substrate substantially cover the orthogonal projections of the first corresponding anode onto the substrate, and substantially cover the orthogonal projections of the second corresponding anode onto the substrate.

13. The array substrate according to claim 11, further comprising: Multiple second fan-out connecting lines extend in a direction substantially parallel to the second direction; as well as Multiple data lines extending in a direction substantially parallel to the second direction; The anode layer includes a first corresponding anode, a second corresponding anode, a third corresponding anode, and a fourth corresponding anode; The orthographic projection of the third corresponding anode on the substrate at least partially overlaps with the orthographic projections of the two adjacent data lines and the two adjacent second fan-out connection lines on the substrate. The third corresponding anode includes a third main anode portion and a third extension portion connecting the third main anode portion and the third corresponding anode connection pad; The two adjacent data lines and the two adjacent second fan-out connection lines respectively cross the third corresponding anode along the second direction; and The two adjacent data lines and the two adjacent second fan-out connecting lines are substantially uniformly distributed along the first direction relative to the third main anode portion of the third corresponding anode.

14. The array substrate according to any one of claims 1 to 6, further comprising voltage connection pads; in, The voltage connection pad connects a corresponding first voltage supply line of the plurality of first voltage supply lines to the second capacitor electrode of the storage capacitor, and connects a corresponding first voltage supply line of the plurality of first voltage supply lines to the first electrode of the light-emitting control transistor. Each of the plurality of second voltage supply lines is connected to a corresponding first voltage supply line of the plurality of first voltage supply lines through an eighth via; as well as The corresponding first voltage supply line is connected to the voltage connection pad through the ninth via, thereby providing the first reference voltage signal to the voltage connection pad and then to the second capacitor electrode in sequence.

15. The array substrate according to claim 14, wherein, The voltage connection pad is located in the area between two adjacent pixel driving circuits in the same row, and there is at least one data line between the two adjacent pixel driving circuits. There are no voltage connection pads in the area between two adjacent pixel driving circuits in the same row, and there are no data lines between the two adjacent pixel driving circuits; and The orthographic projection of the voltage connection pad on the substrate overlaps at least partially with the orthographic projection of the data line on the substrate.

16. The array substrate according to any one of claims 1 to 6, further comprising an interconnect reset signal line network; in, The interconnected reset signal line network includes a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together; The plurality of first reset signal lines extend in a direction substantially parallel to the first direction; The plurality of fourth reset signal lines extend in a direction substantially parallel to the second direction; as well as The plurality of first reset signal lines and the plurality of fourth reset signal lines are part of an overall structure and are located in the same layer.

17. The array substrate according to claim 16, wherein, The ratio of the number of the plurality of first reset signal lines to the number of rows of pixel driving circuits located in the display area of ​​the array substrate is in the range of 0.8:1.0 to 1.2:1.0; as well as The ratio of the number of the plurality of fourth reset signal lines to the number of columns of pixel driving circuits located in the display area of ​​the array substrate is in the range of 0.8:2.0 to 1.2:2.

0.

18. The array substrate according to any one of claims 1 to 6, further comprising an interconnect voltage supply network; in, The interconnected voltage supply network includes a plurality of first voltage supply lines and a plurality of second voltage supply lines interconnected together; The plurality of first voltage supply lines extend in a direction substantially parallel to the first direction; The plurality of second voltage supply lines extend in a direction substantially parallel to the second direction; The plurality of first voltage supply lines and the plurality of second voltage supply lines are located in different layers; as well as Each second voltage supply line is connected to the corresponding first voltage supply line via a via extending through the planarization layer.

19. The array substrate according to claim 18, wherein, The ratio of the number of the plurality of second voltage supply lines to the number of columns of pixel driving circuits located in the display area of ​​the array substrate is in the range of 0.8:2.0 to 1.2:2.

0.

20. A display device comprising an array substrate according to any one of claims 1 to 19 and one or more integrated circuits connected to the array substrate.

Images