Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes pixels arranged in a plurality of repeating units. The array substrate includes a plurality of source interconnects and a plurality of data connection pads in the repeating units, as well as a plurality of data lines. Each of the plurality of source interconnects connects a first electrode of a first transistor and a first electrode of a second transistor in a corresponding pixel driving circuit together. Each of the source interconnects is also connected to a corresponding data connection pad in the plurality of data connection pads. Each data connection pad is connected to a corresponding data line in the plurality of data lines. The maximum width of each source interconnect is at least 75% greater than the maximum width of each anode.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] With the development of virtual reality imaging technology, the requirements for display panel resolution are becoming increasingly stringent. Organic light-emitting diode (OLED) display panels are commonly used for image display. Summary of the Invention

[0003] On one hand, this disclosure provides an array substrate including pixels arranged in a plurality of repeating units; wherein each repeating unit includes a plurality of pixels, and each pixel includes one or more sub-pixels; wherein the array substrate includes a plurality of source interconnects and a plurality of data interconnects pads in the repeating units, and a plurality of data lines; each source interconnect connects a first electrode of a first transistor and a first electrode of a second transistor in a corresponding pixel driving circuit together; each source interconnect also connects to a corresponding data interconnect in the plurality of data interconnects pads; and the corresponding data interconnects pads connect to a corresponding data line in the plurality of data lines; wherein the array substrate further includes a plurality of anodes; each anode has a first maximum width; and each source interconnect has a second maximum width; the second maximum width is at least 75% greater than the first maximum width.

[0004] Optionally, in the repeating unit, the number of pixel driving circuits is N, where N is an integer greater than or equal to 1; the number of data lines configured to provide data signals to the repeating unit is (N / 2); the number of data connection pads in the repeating unit is (N / 2); and the number of source connection lines in the repeating unit is (N / 2).

[0005] Optionally, in the repeating unit, the first electrodes of four transistors in two pixel driving circuits of two adjacent pixels in the same column are connected to the same source connection line; and wherein the four transistors include a first transistor and a second transistor in a first pixel driving circuit of a first adjacent pixel in the same column, and a first transistor and a second transistor in a second pixel driving circuit of a second adjacent pixel in the same column.

[0006] Optionally, the array substrate further includes a plurality of drain connection lines in the repeating unit; and each of the plurality of drain connection lines connects the second electrode of the first transistor and the second electrode of the second transistor in the corresponding pixel driving circuit together.

[0007] Optionally, the array substrate further includes a plurality of first node connection lines in the repeating unit; each drain connection line is connected to a corresponding first node connection line among the plurality of first node connection lines; and the corresponding first node connection line is electrically connected to the gate of the driving transistor in the corresponding pixel driving circuit.

[0008] Optionally, in the repeating unit, the number of transistors whose second electrode is connected to the first node in the repeating unit is 2N; the number of drain connection lines in the repeating unit is N; and the number of first node connection lines in the repeating unit is N.

[0009] Optionally, the array substrate further includes a plurality of first connection pads in the repeating unit and a plurality of first capacitor electrodes; each first node connection line is connected to a corresponding first connection pad in the plurality of first connection pads; and each first connection pad in the plurality of first connection pads is connected to a corresponding first capacitor electrode in the plurality of first capacitor electrodes.

[0010] Optionally, the array substrate further includes a plurality of second node connection lines, a plurality of second connection pads, and a plurality of anode connection pads in the repeating unit; each of the plurality of second node connection lines is connected to the second electrode of the driving transistor in the corresponding pixel driving circuit; each of the second node connection lines is connected to a corresponding second connection pad in the plurality of second connection pads; the corresponding second connection pad is connected to a corresponding anode connection pad in the plurality of anode connection pads; and the corresponding anode connection pad is connected to the anode of the corresponding sub-pixel.

[0011] Optionally, the array substrate further includes a low-voltage signal network configured to be provided with a low-voltage signal; wherein the low-voltage signal network includes a first anti-interference block, the first anti-interference block being configured to shield at least a portion of the active layer of the first transistor and at least a portion of the active layer of the driving transistor from electromagnetic interference; wherein the first anti-interference block is located on the same layer as the active layer of the first transistor and the active layer of the driving transistor.

[0012] Optionally, the low-voltage signal network further includes a third anti-interference block configured to shield at least a portion of the active layer of the first transistor and at least a portion of the active layer of the driving transistor from electromagnetic interference; wherein the third anti-interference block is connected to the first anti-interference block and is located on a different layer than the first anti-interference block; and the orthographic projection of the third anti-interference block on the substrate at least partially overlaps with the orthographic projection of the active layers of the plurality of driving transistors in the repeating unit on the substrate.

[0013] Optionally, the low-voltage signal network further includes a ground plane connected to the third anti-interference block and located on a different layer than the first anti-interference block or the third anti-interference block; wherein the ground plane in the repeating unit extends over at least 50% of the repeating unit; and the orthographic projection of the ground plane on the substrate at least partially overlaps with the orthographic projection of the third anti-interference block in the repeating unit on the substrate; and at least partially overlaps with the orthographic projection of the first anti-interference block in the repeating unit on the substrate.

[0014] Optionally, the low-voltage signal network further includes a plurality of grounding wires connected to the ground plane and located in a different layer from the ground plane, the first anti-interference block, or the third anti-interference block; wherein the plurality of grounding wires are located in the same layer as the plurality of data lines; and the plurality of grounding wires and the plurality of data lines extend in a direction substantially parallel to the second direction.

[0015] Optionally, the low-voltage signal network further includes a second capacitor electrode connected to the plurality of ground wires and located on a different layer than the plurality of ground wires, the ground plane, the first anti-interference block, or the third anti-interference block.

[0016] Optionally, the array substrate further includes an interconnected voltage supply network; wherein the interconnected voltage supply network includes a plurality of first voltage supply lines and a plurality of voltage supply connection lines; the plurality of first voltage supply lines extend in a direction substantially parallel to a first direction; the plurality of voltage supply connection lines extend in a direction substantially parallel to a second direction; the plurality of first voltage supply lines are located on a different layer than the plurality of voltage supply connection lines; each of the plurality of voltage supply connection lines is connected to a corresponding first voltage supply line among the plurality of first voltage supply lines through one or more vias; and two adjacent voltage supply connection lines and two adjacent first voltage supply connection lines substantially surround the pixel driving circuitry of the repeating unit.

[0017] Optionally, the array substrate further includes a plurality of second voltage supply lines and a plurality of anode connection pads located on the same layer, and a cathode located on the side of the plurality of second voltage supply lines away from the substrate; wherein each of the plurality of second voltage supply lines is connected to the cathode through one or more vias.

[0018] Optionally, the array substrate further includes a peripheral second voltage supply line located in a peripheral region of the array substrate; the plurality of second voltage supply lines are connected to the peripheral second voltage supply line; and the peripheral second voltage supply line substantially surrounds the display area of ​​the array substrate.

[0019] Optionally, the repeating unit comprises four pixels; and each of the four pixels in the repeating unit comprises at least three sub-pixels.

[0020] Optionally, the corresponding layers of the pixel driving circuits in adjacent pixels of the repeating unit are substantially mirror-symmetric with respect to each other about a plane that is perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines.

[0021] Optionally, each pixel driving circuit includes: a driving transistor, a first transistor, and a second transistor; and a storage capacitor having a first capacitor electrode and a second capacitor electrode; wherein the gate of the driving transistor is connected to the second electrode of the first transistor and the second electrode of the second transistor, and is also connected to the first capacitor electrode; the first electrode of the driving transistor is connected to a corresponding first voltage supply line among a plurality of first voltage supply lines; the second electrode of the driving transistor is connected to the anode of the light-emitting element; the gate of the first transistor is connected to a corresponding first gate line among a plurality of first gate lines; the gate of the second transistor is connected to a corresponding second gate line among a plurality of second gate lines; the first electrode of the first transistor and the first electrode of the second transistor are connected to corresponding data lines among the plurality of data lines; and the second capacitor electrode is configured to be provided with a low voltage signal.

[0022] Optionally, the array substrate further includes a plurality of first gate lines and a plurality of second gate lines; wherein a first corresponding first gate line, a first corresponding second gate line, a second corresponding second gate line, and a second corresponding first gate line among the plurality of first gate lines extend through a corresponding repeating unit; the source connection line in the corresponding repeating unit is located between a first group of gate lines and a second group of gate lines, the first group of gate lines including the first corresponding first gate line and the first corresponding second gate line, and the second group of gate lines including the second corresponding second gate line and the second corresponding first gate line; the drain connection line of the first group of sub-pixels in the corresponding repeating unit is located on the side of the first group of gate lines away from the source connection line in the corresponding repeating unit; the drain connection line of the second group of sub-pixels in the corresponding repeating unit is located on the side of the second group of gate lines away from the source connection line in the corresponding repeating unit; and there are no drain connection lines between the first group of gate lines and the second group of gate lines in the array substrate.

[0023] Optionally, the source interconnects in the corresponding repeating unit are arranged in one or more columns along the second direction; each column of the one or more columns of source interconnects includes a first source interconnect, a second source interconnect, and a third source interconnect; the second source interconnect is located between the first source interconnect and the third source interconnect; the first source interconnect and the third source interconnect have a U-shape; the opening of the U-shape of the first source interconnect and the opening of the U-shape of the third source interconnect are opposite to each other; and the second source interconnect is located between the opening of the U-shape of the first source interconnect and the opening of the U-shape of the third source interconnect.

[0024] Optionally, the drain connection lines of the first group of sub-pixels in the corresponding repeating unit are arranged in one or more columns along the second direction; each column of the one or more columns of drain connection lines of the first group of sub-pixels in the corresponding repeating unit includes a first drain connection line, a second drain connection line, and a third drain connection line; the second drain connection line is located between the first drain connection line and the third drain connection line; the first drain connection line and the second drain connection line have a U-shape; and the opening of the U-shape of the first drain connection line and the opening of the U-shape of the second drain connection line face the same direction.

[0025] Optionally, the drain connection lines of the second group of sub-pixels in the corresponding repeating unit are arranged in one or more columns along the second direction; each column of the one or more columns of drain connection lines of the second group of sub-pixels in the corresponding repeating unit includes a fourth drain connection line, a fifth drain connection line, and a sixth drain connection line; the fifth drain connection line is located between the fourth drain connection line and the sixth drain connection line; the fifth drain connection line and the sixth drain connection line have a U-shape; and the opening of the U-shape of the fifth drain connection line and the opening of the U-shape of the sixth drain connection line face the same direction.

[0026] Optionally, the orthographic projection of the second source connection line on the substrate does not overlap with the orthographic projections of the gates of the first transistor and the second transistor on the substrate; the orthographic projection of the first electrode connection line on the substrate partially overlaps with the orthographic projections of the gates of at least one first transistor and at least one second transistor on the substrate; and the orthographic projection of the third source connection line on the substrate partially overlaps with the orthographic projections of the gates of at least one first transistor and at least one second transistor on the substrate.

[0027] Optionally, the orthographic projection of any drain connection line on the substrate does not overlap with the orthographic projections of the gates of the first transistor, the second transistor, and the third transistor on the substrate.

[0028] Optionally, the array substrate further includes a plurality of N-well regions and a plurality of first anti-interference blocks; wherein, along a first direction, the plurality of first anti-interference blocks and the plurality of N-well regions are arranged alternately; and each of the plurality of N-well regions separates two adjacent first anti-interference blocks among the plurality of first anti-interference blocks.

[0029] Optionally, the array substrate further includes a plurality of second anti-interference blocks; wherein, along the first direction, the plurality of first anti-interference blocks and the plurality of second anti-interference blocks are arranged alternately; each of the plurality of second anti-interference blocks separates two adjacent first anti-interference blocks from the plurality of first anti-interference blocks; each of the plurality of first anti-interference blocks separates two adjacent second anti-interference blocks from the plurality of second anti-interference blocks; and in a row of repeating units, the first anti-interference blocks and the second anti-interference blocks are located on two opposite sides of a row of N-well regions.

[0030] Optionally, the array substrate further includes a plurality of first node connection lines; wherein each of the plurality of first node connection lines has a T-shape or an L-shape; each first node connection line includes a first segment and a second segment, the first segment and the second segment forming two strokes of the T-shape or the L-shape; the first segment is the location where each first node connection line is connected to the first capacitor electrode; and the second segment is the location where each first node connection line is connected to the gate of the third transistor.

[0031] Optionally, the array substrate further includes a plurality of first node connection lines and a plurality of second node connection lines; wherein, the orthographic projection of at least one of the plurality of second node connection lines on the substrate partially overlaps with the orthographic projection of the gate of the second transistor on the substrate; and the orthographic projection of each of the plurality of first node connection lines on the substrate partially overlaps with the orthographic projection of the gate of the third transistor on the substrate.

[0032] On the other hand, this disclosure provides a display device including an array substrate manufactured as described herein or by the methods described herein, and one or more integrated circuits connected to the array substrate; wherein the array substrate includes a plurality of light-emitting elements; each of the plurality of light-emitting elements includes an anode among the plurality of anodes; and the plurality of anodes are connected to the one or more integrated circuits. Attached Figure Description

[0033] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0034] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0035] Figure 2 This is a circuit diagram of a portion of an array substrate according to some embodiments of the present disclosure.

[0036] Figure 3 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0037] Figure 4A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0038] Figure 4B It is shown Figure 4A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate.

[0039] Figure 4C It is shown Figure 4A The diagram shows a schematic of the structure of the gate metal layer in the array substrate.

[0040] Figure 4D It is shown Figure 4A A schematic diagram of a via extending through the gate insulating layer in an array substrate shown.

[0041] Figure 4E It is shown Figure 4A A schematic diagram of a via extending through an insulating layer in an array substrate shown.

[0042] Figure 4F It is shown Figure 4A The diagram shows a schematic of the structure of the first signal line layer in the array substrate.

[0043] Figure 4G It is shown Figure 4A A schematic diagram of a via extending through the first interlayer dielectric layer in an array substrate shown.

[0044] Figure 4H It is shown Figure 4A A schematic diagram of the structure of the second signal line layer in the array substrate shown.

[0045] Figure 4I It is shown Figure 4A The diagram shows a schematic of the structure of the third signal line layer in the array substrate.

[0046] Figure 4JIt is shown Figure 4A A schematic diagram of a via extending through a third interlayer dielectric layer in an array substrate.

[0047] Figure 4K It is shown Figure 4A A schematic diagram of the structure of the fourth signal line layer in the array substrate shown.

[0048] Figure 4L It is shown Figure 4A A schematic diagram of the structure of the first conductive layer in the array substrate shown.

[0049] Figure 4M It is shown Figure 4A A schematic diagram of the structure of the second conductive layer in the array substrate shown.

[0050] Figure 4N It is shown Figure 4A A schematic diagram of a via extending through a third passivation layer in an array substrate shown.

[0051] Figure 4O It is shown Figure 4A A schematic diagram of the structure of the first interconnect layer in the array substrate shown.

[0052] Figure 4P It is shown Figure 4A A schematic diagram of a via extending through the first planarization layer in an array substrate shown.

[0053] Figure 4Q It is shown Figure 4A A schematic diagram of the structure of the second interconnect layer in the array substrate shown.

[0054] Figure 4R It is shown Figure 4A A schematic diagram of a via extending through the second planarization layer in the array substrate shown.

[0055] Figure 4S It is shown Figure 4A A schematic diagram of the structure of the anode layer in the array substrate shown.

[0056] Figure 5 It is shown Figure 4A The diagram shows the arrangement of the pixel driving circuit and the dummy circuit in the array substrate.

[0057] Figure 6 This is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0058] Figure 7AThe circuit connection layout of the first pixel driving circuit of the first sub-pixel of the first pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown.

[0059] Figure 7B The circuit connection layout of the second pixel driving circuit of the second sub-pixel of the first pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown.

[0060] Figure 7C The circuit connection layout of the third pixel driving circuit of the third sub-pixel of the first pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown.

[0061] Figure 7D The circuit connection layout of the first pixel driving circuit in the first sub-pixel of the second pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown.

[0062] Figure 7E The circuit connection layout of the second pixel driving circuit of the second sub-pixel of the second pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown.

[0063] Figure 7F The circuit connection layout of the third pixel driving circuit of the third sub-pixel of the second pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown.

[0064] Figure 7G The circuit connection layout of the first pixel driving circuit in the first sub-pixel of the third pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown.

[0065] Figure 7H The circuit connection layout of the second pixel driving circuit of the second sub-pixel of the third pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown.

[0066] Figure 7I The circuit connection layout of the third pixel driving circuit of the third sub-pixel of the third pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown.

[0067] Figure 7J The circuit connection layout of the first pixel driving circuit in the first sub-pixel of the fourth pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown.

[0068] Figure 7KThe circuit connection layout of the second pixel driving circuit of the second sub-pixel of the fourth pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown.

[0069] Figure 7L The circuit connection layout of the third pixel driving circuit of the third sub-pixel of the fourth pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown.

[0070] Figure 8 A data signal network in an array substrate according to some embodiments of the present disclosure is shown.

[0071] Figure 9 The layout of first node connection lines in an array substrate according to some embodiments of the present disclosure is shown.

[0072] Figure 10 The arrangement of first capacitor electrodes in an array substrate according to some embodiments of the present disclosure is shown.

[0073] Figure 11 An anode connection layout in an array substrate according to some embodiments of the present disclosure is shown.

[0074] Figure 12A This is a schematic diagram illustrating the structure of a second interconnect layer in an array substrate according to some embodiments of the present disclosure.

[0075] Figure 12B This is a schematic diagram illustrating the structure of the anode layer in an array substrate according to some embodiments of the present disclosure.

[0076] Figure 12C This is a schematic diagram illustrating the structure of the cathode layer in an array substrate according to some embodiments of the present disclosure.

[0077] Figure 12D The structure of the second interconnect layer and cathode layer in an array substrate according to some embodiments of the present disclosure is shown.

[0078] Figure 13 This is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0079] Figure 14 A second voltage supply network in an array substrate according to some embodiments of the present disclosure is shown.

[0080] Figure 15A The IR voltage drop on an array substrate without a second voltage supply network is shown.

[0081] Figure 15B The IR voltage drop on the array substrate with a second voltage supply network is shown.

[0082] Figure 16 It is shown Figure 4A The diagram shows the structure of the first signal line layer and the anode layer in the array substrate.

[0083] Figure 17 It is shown Figure 4A The diagram shows a schematic of the structure of the first signal line layer in the array substrate.

[0084] Figure 18 It is shown Figure 4A The diagram shows a schematic of the structure of the gate metal layer and the first signal line layer in the array substrate.

[0085] Figure 19 It is shown Figure 4A The diagram shows a schematic of the structure of the semiconductor material layer in the array substrate.

[0086] Figure 20 It is shown Figure 4A The diagram shows a schematic of the structure of the gate metal layer and the second signal line layer in the array substrate. Specific Implementation

[0087] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0088] Virtual reality display technology has developed rapidly in recent years, allowing users to have a realistic experience in virtual reality environments. A hyper-simulation system enables seamless human-computer interaction. In virtual reality displays, when the display resolution exceeds 300 PPI (pixels per inch) (equivalent to 60 PPD (pixels per degree) in spatial display), the human eye can no longer distinguish individual pixels. Ideally, when the overlapping field of view of both eyes is 120 degrees, a resolution of 7200×7200 is required for a single eye. Therefore, virtual reality displays require ultra-high display resolution.

[0089] Therefore, this disclosure particularly provides an array substrate and a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes pixels arranged in a plurality of repeating units. Optionally, each repeating unit in the plurality of repeating units includes a plurality of pixels, and each pixel includes one or more sub-pixels. Optionally, the array substrate includes a plurality of source interconnects and a plurality of data interconnect pads in the repeating units, as well as a plurality of data lines. Optionally, each source interconnect in the plurality of source interconnects connects a first electrode of a first transistor and a first electrode of a second transistor in a corresponding pixel driving circuit together. Optionally, each source interconnect also connects to a corresponding data interconnect pad in the plurality of data interconnect pads. Optionally, each data interconnect pad connects to a corresponding data line in the plurality of data lines. Optionally, the array substrate also includes a plurality of anodes. Optionally, each anode in the plurality of anodes has a first maximum width. Optionally, each source interconnect has a second maximum width. Optionally, the second maximum width is greater than at least 75% of the first maximum width.

[0090] Various suitable pixel driving circuits can be used in this array substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in the plurality of pixel driving circuits is a 3T1C driving circuit. Various suitable light-emitting elements can be used in this array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot LEDs, and micro LEDs. Optionally, the light-emitting element is a micro LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer. In one example, the light-emitting element is an organic light-emitting diode on silicon.

[0091] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1In some embodiments, the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a respective pixel driving circuit PDC. The array substrate includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of data lines DL, a plurality of first voltage supply lines Vdd, and a plurality of second voltage supply lines (e.g., low voltage supply lines Vss). Each sub-pixel Sp is driven to emit light by the respective pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via a high voltage supply line among the plurality of first voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via a low voltage supply line. The voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is the driving voltage ΔV that drives the light-emitting element to emit light.

[0092] Figure 2 This is a circuit diagram of a portion of an array substrate according to some embodiments of this disclosure. (Refer to...) Figure 2 Multiple data lines DL are connected to the data driving circuit DDC, and multiple gate lines (including multiple first gate lines GL1 and multiple second gate lines GL2) are connected to the gate driving circuit GDC. Optionally, the data driving circuit DDC and the gate driving circuit GDC are circuits formed in the array substrate.

[0093] Figure 3 This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 3In some embodiments, the pixel driving circuit includes: a driving transistor T3; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 and a second transistor T2. Optionally, the gate of the driving transistor T3 is connected to the second electrode of the first transistor T1 and the second electrode of the second transistor T2, and is also connected to the first capacitor electrode Ce1. The first electrode of the driving transistor T3 is connected to a corresponding first voltage supply line among a plurality of first voltage supply lines Vdd. The second electrode of the driving transistor T3 is connected to the anode of the light-emitting element LE. The gate of the first transistor T1 is connected to a corresponding first gate line among a plurality of first gate lines GL1. The gate of the second transistor T2 is connected to a corresponding second gate line among a plurality of second gate lines GL2. The first electrode of the first transistor T1 and the first electrode of the second transistor T2 are connected to corresponding data lines among a plurality of data lines DL. Optionally, the second capacitor electrode Ce2 is configured to be provided with a low voltage signal (e.g., a ground voltage signal). In some embodiments, the pixel driving circuit further includes a first anti-interference block IPB1, which is configured to shield at least a portion of the active layer of the first transistor T1 and at least a portion of the active layer of the driving transistor T3 from electromagnetic interference. In some embodiments, the pixel driving circuit further includes a second anti-interference block IPB2, which is configured to shield at least a portion of the active layer of the second transistor T2 from electromagnetic interference. Optionally, the first anti-interference block IPB1 is configured to be provided with a low voltage signal (e.g., a ground voltage signal). Optionally, the second anti-interference block IPB2 is configured to be provided with a first reference voltage signal (e.g., a high voltage signal). Optionally, the cathode of the light-emitting diode is configured to be provided with a second reference voltage signal (e.g., a low voltage signal VSS).

[0094] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, wherein the first terminal and the second terminal are connected to the active layer of the transistor. The direction of current flow through the transistor can be configured from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flow through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0095] In some embodiments, the pixel driving circuit further includes a first node N1 and a second node N2. The first node N1 is connected to the gate of the driving transistor T3, the first capacitor electrode Ce1, and the second electrode of the first transistor T1 and the second electrode of the second transistor T2. The second node N2 is connected to the second electrode of the driving transistor T3 and the anode of the light-emitting element LE.

[0096] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes each first sub-pixel, each second sub-pixel, and each third sub-pixel. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3, wherein S1 represents each first sub-pixel, S2 represents each second sub-pixel, and S3 represents each third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, and C3 represents each third sub-pixel of a third color. In another example, the C1-C2-C3 format is an RGB format, wherein each first sub-pixel is a red sub-pixel, each second sub-pixel is a green sub-pixel, and each third sub-pixel is a blue sub-pixel.

[0097] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes a first transistor T1, a second transistor T2, a driving transistor T3, and a storage capacitor Cst. Optionally, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel further includes a first anti-interference block IPB1 and a second anti-interference block IPB2.

[0098] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figure 3 In some embodiments, the first transistor T1 and the driving transistor T3 are n-type transistors, such as metal-oxide-semiconductor transistors, while the second transistor T2 is a p-type transistor, such as a polysilicon transistor. For p-type transistors, the active control signal (e.g., a turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., a turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a low-voltage signal.

[0099] Figure 4A This is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 4B It is shown Figure 4AThe diagram shows a schematic of the structure of the semiconductor material layer in the array substrate. Figure 4C It is shown Figure 4A The diagram shows a schematic of the structure of the gate metal layer of the array substrate.

[0100] Figure 4D It is shown Figure 4A A schematic diagram of a via extending through the gate insulating layer in an array substrate shown.

[0101] Figure 4E It is shown Figure 4A A schematic diagram of a via extending through an insulating layer in an array substrate shown. Figure 4F It is shown Figure 4A The diagram shows a schematic of the structure of the first signal line layer in the array substrate. Figure 4G It is shown Figure 4A A schematic diagram of a via extending through the first interlayer dielectric layer in an array substrate shown. Figure 4H It is shown Figure 4A A schematic diagram of the structure of the second signal line layer in the array substrate shown. Figure 4I It is shown Figure 4A The diagram shows a schematic of the structure of the third signal line layer in the array substrate. Figure 4J It is shown Figure 4A A schematic diagram of a via extending through a third interlayer dielectric layer in an array substrate. Figure 4K It is shown Figure 4A A schematic diagram of the structure of the fourth signal line layer in the array substrate shown. Figure 4L It is shown Figure 4A A schematic diagram of the structure of the first conductive layer in the array substrate shown. Figure 4M It is shown Figure 4A A schematic diagram of the structure of the second conductive layer in the array substrate shown. Figure 4N It is shown Figure 4A A schematic diagram of a via extending through a third passivation layer in an array substrate shown. Figure 4O It is shown Figure 4A A schematic diagram of the structure of the first interconnect layer in the array substrate shown. Figure 4P It is shown Figure 4A A schematic diagram of a via extending through the first planarization layer in an array substrate shown. Figure 4Q It is shown Figure 4A A schematic diagram of the structure of the second interconnect layer in the array substrate shown. Figure 4R It is shown Figure 4A A schematic diagram of a via extending through the second planarization layer in the array substrate shown. Figure 4S It is shown Figure 4A A schematic diagram of the structure of the anode layer in the array substrate shown. Figure 5 It is shown Figure 4A The diagram shows the arrangement of the pixel driving circuit and the dummy circuit in the array substrate. Figure 6 This is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0102] Figures 4A to 4S , Figure 5 and Figure 6 A portion of an array substrate having multiple sub-pixels is shown. In some embodiments, Figures 4A to 4S , Figure 5 and Figure 6 This illustrates repeating units (e.g., minimum repeating units) of multiple sub-pixels on an array substrate. In, for example... Figure 5 In one example shown, a repeating unit (e.g., a minimum repeating unit) of multiple subpixels of the array substrate includes four pixels px1, px2, px3, and px4. In some embodiments, each pixel in the repeating unit includes multiple subpixels. In one example, each pixel includes at least three subpixels, such as a first subpixel sp1 (e.g., a red subpixel), a second subpixel sp2 (e.g., a green subpixel), and a third subpixel sp3 (e.g., a blue subpixel).

[0103] In some embodiments, the corresponding layers of pixel driving circuits in adjacent pixels (e.g., adjacent px1 and px2, or adjacent px3 and px4, or adjacent px1 / px3 and px2 / px4) in a repeating unit are substantially mirror-symmetric relative to each other, for example, with respect to a plane perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL. Optionally, the corresponding layers of pixel driving circuits in adjacent pixels located in the same row in a repeating unit (e.g., adjacent px1 and px2 in a first row, or adjacent px3 and px4 in a second row) are substantially mirror-symmetric relative to each other, for example, with respect to a plane perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL. Optionally, the corresponding layers of pixel driving circuits in the array substrate are substantially mirror-symmetric relative to each other, for example, with respect to a plane perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines DL.

[0104] As used herein, the term "corresponding layer of the pixel driving circuit" is not intended to include layers that are not part of the pixel driving circuit. For example, "corresponding layer of the pixel driving circuit" does not include an anode layer or a pixel defining layer. In some embodiments, "corresponding layer of the pixel driving circuit" does not include a light-shielding layer or a first signal line layer or a second signal line layer or a third signal line layer or a second connection layer. In one example, "corresponding layer of the pixel driving circuit" refers to at least one conductive layer of the pixel driving circuit. In a specific example, "corresponding layer" includes at least one of a semiconductor material layer, a gate metal layer, a first conductive layer, a second conductive layer, or a first connection layer.

[0105] Reference Figures 4A to 4S , Figure 5 and Figure 6 In some embodiments, the array substrate includes a substrate BS, a semiconductor material layer SEM on the substrate BS, a gate insulating layer GI on the side of the semiconductor material layer SEM away from the substrate BS, a gate metal layer GT on the side of the gate insulating layer GI away from the substrate BS, an insulating layer IN on the side of the gate metal layer GT away from the substrate BS, a first signal line layer SD1 on the side of the insulating layer IN away from the substrate BS, a first interlayer dielectric layer ILD1 on the side of the first signal line layer SD1 away from the substrate BS, a second signal line layer SD2 on the side of the first interlayer dielectric layer ILD1 away from the substrate BS, a second interlayer dielectric layer ILD2 on the side of the second signal line layer SD2 away from the substrate BS, a third signal line layer SD3 on the side of the second interlayer dielectric layer ILD2 away from the substrate BS, a third interlayer dielectric layer ILD3 on the side of the third signal line layer SD3 away from the substrate BS, and a third interlayer dielectric layer ILD3 on the side of the third interlayer dielectric layer ILD3 away from the substrate BS. The fourth signal line layer SD4 on one side of the substrate BS, the first passivation layer PVX1 on the side of the fourth signal line layer SD4 away from the substrate BS, the first conductive layer CT1 on the side of the first passivation layer PVX1 away from the substrate BS, the second passivation layer PVX2 on the side of the first conductive layer CT1 away from the substrate BS, the second conductive layer CT2 on the side of the second passivation layer PVX2 away from the substrate BS, the third passivation layer PVX3 on the side of the second conductive layer CT2 away from the substrate BS, the first connection layer TM1 on the side of the third passivation layer PVX3 away from the substrate BS, the first planarization layer PLN1 on the side of the first connection layer TM1 away from the substrate BS, the second connection layer TM2 on the side of the first planarization layer PLN1 away from the substrate BS, the second planarization layer PLN2 on the side of the second connection layer TM2 away from the substrate BS, and the anode layer ADL on the side of the second planarization layer PLN2 away from the substrate BS.

[0106] Reference Figure 3 , Figure 4A , Figure 4B , Figure 5 and Figure 6 In some embodiments, the semiconductor material layer SEM includes at least an active layer of a plurality of transistors of a pixel driving circuit, wherein the plurality of transistors includes a first transistor T1, a second transistor T2, and a driving transistor T3. Optionally, the semiconductor material layer SEM also includes at least corresponding portions of the first electrodes of the plurality of transistors of the pixel driving circuit, wherein the plurality of transistors includes the first transistor T1, a third transistor T2, and a driving transistor T3. Optionally, the semiconductor material layer SEM also includes at least corresponding portions of the second electrodes of the plurality of transistors of the pixel driving circuit, wherein the plurality of transistors includes the first transistor T1, the third transistor T2, and a driving transistor T3. Optionally, the semiconductor material layer SEM includes an active layer, a first electrode, and a second electrode of the plurality of transistors of the pixel driving circuit, wherein the plurality of transistors includes the first transistor T1, the third transistor T2, and the driving transistor T3. Various suitable semiconductor materials can be used to fabricate the semiconductor material layer SEM. Examples of semiconductor materials used to fabricate the semiconductor material layer SEM include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon; metal oxide-based semiconductor materials, such as indium gallium zinc oxide; and metal oxynitride-based semiconductor materials, such as zinc oxynitride. Optionally, the active layer of the second transistor T2 comprises a metal-oxide-semiconductor material. Optionally, the active layers of the first transistor T1 and the driving transistor T3 comprise silicon-based semiconductor materials.

[0107] In some embodiments, the semiconductor material layer SEM further includes a first anti-interference block IPB1 and a second anti-interference block IPB2. The first anti-interference block IPB1 is configured to shield at least a portion of the active layer of the first transistor T1 and the driving transistor T3 from electromagnetic interference. The second anti-interference block IPB2 is configured to shield at least a portion of the active layer of the second transistor T2 from electromagnetic interference. Optionally, the first anti-interference block IPB1 is configured to be provided with a low-voltage signal (e.g., a ground voltage signal). Optionally, the second anti-interference block IPB2 is configured to be provided with a first reference voltage signal (e.g., a high-voltage signal).

[0108] Figure 4B The components of several transistors (T1, T2, and T3) are labeled. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The driving transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3.

[0109] Optionally, the active layers (ACT1, ACT2, and ACT3), the first electrodes (S1, S2, and S3), and the second electrodes (D1, D2, and D3) of each transistor (T1, T2, and T3) are located on the same layer.

[0110] Reference Figure 3 , Figure 4A , Figure 4C , Figure 5 and Figure 6 In some embodiments, the gate metal layer GT includes the gate G1 of the first transistor T1, the gate G2 of the second transistor T2, and the gate G3 of the driving transistor T3. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the gate metal layer GT. For example, a conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the gate G1 of the first transistor T1, the gate G2 of the second transistor T2, and the gate G3 of the driving transistor T3 are located in the same layer.

[0111] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, when the gate G1 of a first transistor T1 and the gate G2 of a second transistor T2 are formed as a result of performing one or more steps of the same patterning process in the same material layer, the gate G1 of the first transistor T1 and the gate G2 of the second transistor T2 are located in the same layer. In another example, the gate G1 of the first transistor T1 and the gate G2 of the second transistor T2 can be formed in the same layer by simultaneously performing the steps of forming the gate G1 of the first transistor T1 and the steps of forming the gate G2 of the second transistor T2. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0112] Figure 4D The image shows a via extending through the gate insulation layer.

[0113] Figure 4E The image shows a via extending through the insulating layer.

[0114] Reference Figure 3 , Figure 4A , Figure 4F , Figure 5 and Figure 6In some embodiments, the first signal line layer SD1 includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of first voltage supply lines Vdd, a third anti-interference block IPB3, a fourth anti-interference block IPB4, a plurality of first intermediate pads IP1, a plurality of second intermediate pads IP2, a plurality of drain connection lines DCL and a plurality of source connection lines SCL.

[0115] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer SD1. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, multiple first gate lines GL1, multiple second gate lines GL2, multiple first voltage supply lines Vdd, a third anti-interference block IPB3, a fourth anti-interference block IPB4, multiple drain connection lines DCL, and multiple source connection lines SCL are located in the same layer.

[0116] Each drain connection in the multiple drain lines (DCL) connects the second electrode of the first transistor T1 and the second electrode of the second transistor T2 in the same sub-pixel. Each source connection in the multiple source lines (SCL) connects the first electrode of the first transistor T1 and the first electrode of the second transistor T2 in the same sub-pixel.

[0117] In some embodiments, the third anti-interference block IPB3 is configured to shield at least a portion of the active layer of the first transistor T1 and the driving transistor T3 from electromagnetic interference. Optionally, the third anti-interference block IPB3 is electrically connected to the first anti-interference block IPB1. In some embodiments, the fourth anti-interference block IPB4 is configured to shield at least a portion of the active layer of the second transistor T2 from electromagnetic interference. Optionally, the fourth anti-interference block IPB4 is electrically connected to the second anti-interference block IPB2. Optionally, the third anti-interference block IPB3 is configured to be provided with a low voltage signal (e.g., a ground voltage signal). Optionally, the fourth anti-interference block IPB4 is configured to be provided with a first reference voltage signal (e.g., a high voltage signal).

[0118] In some embodiments, the orthographic projection of the third anti-interference block IPB3 on the substrate at least partially overlaps with the orthographic projection of the active layers of the driving transistors in the repeating unit on the substrate. Optionally, the orthographic projection of the third anti-interference block IPB3 on the substrate at least partially overlaps with the orthographic projection of the active layers of the driving transistors in the first pixel and the second pixel of the repeating unit on the substrate. Optionally, the orthographic projection of the third anti-interference block IPB3 on the substrate does not overlap with the orthographic projection of the active layers of the driving transistors in the third pixel and the fourth pixel of the repeating unit on the substrate.

[0119] In some embodiments, each of the plurality of first gate lines GL1 is connected to the gate of a first transistor located in the same row in the repeating unit. Each first gate line is configured to provide a gate scan signal to the first transistor located in the same row in the repeating unit. In some embodiments, each of the plurality of second gate lines GL2 is connected to the gate of a second transistor located in the same row in the repeating unit. Each second gate line is configured to provide a gate scan signal to the second transistor located in the same row in the repeating unit.

[0120] In some embodiments, each of the plurality of first voltage supply lines Vdd is connected to a first electrode of a driving transistor located in the same row in the repeating unit. Each first voltage supply line is configured to provide a first reference voltage signal to the first electrode of the driving transistor located in the same row in the repeating unit.

[0121] Each of the multiple first intermediate pads IP1 connects the gate of the driving transistor T3 to a corresponding first node connection line among the multiple first node connection lines. Each of the multiple second intermediate pads IP2 connects the second electrode of the driving transistor T3 to a corresponding second node connection line among the multiple second node connection lines.

[0122] Figure 4G The image shows a via extending through the first interlayer dielectric layer.

[0123] Reference Figure 3 , Figure 4A , Figure 4H , Figure 5 and Figure 6In some embodiments, the second signal line layer SD2 includes a plurality of first node connection lines Cln1, a plurality of second node connection lines Cln2, a plurality of data connection pads DCP, a plurality of voltage supply connection lines VCL, and a ground plane GND. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer SD2. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second signal line layer SD2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of first node connection lines Cln1, the plurality of second node connection lines Cln2, the plurality of data connection pads DCP, the plurality of voltage supply connection lines VCL, and the ground plane GND are located in the same layer.

[0124] In some embodiments, each data connection pad in the plurality of data connection pads (DCPs) connects a corresponding data line in the plurality of data lines to a corresponding source connection line in the plurality of source connection lines. Each source connection line in the plurality of source connection lines connects the first electrode of the first transistor T1 and the first electrode of the second transistor T2 in the same sub-pixel together.

[0125] In some embodiments, the array substrate includes a ground plane GND located in each of a plurality of repeating cells. Each repeating cell includes a ground plane. Optionally, the ground plane GND in the repeating cell is spaced apart from each of a plurality of first node connection lines Cln1, a plurality of second node connection lines Cln2, a plurality of data connection pads DCP, and a plurality of voltage supply connection lines VCL, but extends substantially throughout the remaining area of ​​the repeating cell in the second signal line layer. Optionally, the ground plane GND in the repeating cell is integrally structured. Optionally, the ground plane GND in the repeating cell extends throughout at least 50% (at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, or at least 90%) of the repeating cell. Optionally, the ground plane GND in the repeating cell extends throughout less than 100% of the repeating cells (less than 95%, less than 90%, less than 85%, less than 80%, less than 75%, less than 70%, less than 65%, or less than 60%).

[0126] In some embodiments, the ground plane GND is configured to be provided with a low-voltage signal (e.g., a ground voltage signal). Optionally, the ground plane GND is connected to a third anti-interference block IPB3 in the first signal line layer via one or more vias extending through at least a first interlayer dielectric layer. Optionally, the third anti-interference block IPB3 is connected to a first anti-interference block IPB1 in the semiconductor material layer via one or more vias extending through at least one of an insulating layer and a gate insulating layer.

[0127] In some embodiments, each of the plurality of first node connection lines Cln1 connects the gate of the driving transistor T3 to a corresponding drain connection line among the plurality of drain connection lines. Each of the plurality of drain connection lines connects the second electrode of the first transistor T1 and the second electrode of the second transistor T2 in the same sub-pixel together. Each of the plurality of first node connection lines Cln1 is also connected to the first capacitor electrode of the storage capacitor (e.g., via...). Figure 4O CP1 in the middle is connected to Figure 4L (Ce1 in the middle).

[0128] In some embodiments, each of the multiple second node connection lines Cln2 connects the second electrode of the driving transistor T3 to the anode of the light-emitting element (e.g., via...). Figure 4O CP2 in Figure 4Q (ACP in the text).

[0129] In some embodiments, refer to Figure 4A and Figures 4F to 4H A plurality of voltage supply connection lines VCL and a plurality of first voltage supply lines Vdd form an interconnected voltage supply network. In some embodiments, the plurality of first voltage supply lines Vdd extend in a direction substantially parallel to a first direction DR1; the plurality of voltage supply connection lines VCL extend in a direction substantially parallel to a second direction DR2. As used herein, the term “substantially parallel” means an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, and 0 degrees to about 30 degrees.

[0130] In some embodiments, a plurality of first voltage supply lines Vdd are located on a different layer than a plurality of voltage supply connection lines VCL. In one example, the plurality of first voltage supply lines Vdd are located on a first signal line layer. In another example, the plurality of voltage supply connection lines VCL are located on a second signal line layer. Optionally, each voltage supply connection line in the plurality of voltage supply connection lines VCL is connected to a corresponding first voltage supply line in the plurality of first voltage supply lines Vdd via one or more vias extending through a first interlayer dielectric layer.

[0131] In some embodiments, two adjacent voltage supply connection lines in a plurality of voltage supply connection lines VCL and two adjacent first voltage supply lines in a plurality of first voltage supply lines Vdd substantially surround the repeating unit.

[0132] Reference Figure 3 , Figure 4A , Figure 4I , Figure 5 and Figure 6In some embodiments, the third signal line layer SD3 includes a plurality of first node connection pads Cpn1, a plurality of second node connection pads Cpn2, a plurality of data lines DL, and a plurality of ground lines GNL. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the third signal line layer SD3. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the third signal line layer SD3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of first node connection pads Cpn1, the plurality of second node connection pads Cpn2, the plurality of data lines DL, and the plurality of ground lines GNL are located in the same layer.

[0133] In some embodiments, each data line in the plurality of data lines DL is connected, for example, to a corresponding data connection pad in a plurality of data connection pads in the repeating unit via one or more vias extending through the second interlayer dielectric layer. Each data connection pad in the plurality of data connection pads connects a corresponding data line in the plurality of data lines DL to a corresponding source connection line in a plurality of source connection lines. Each source connection line in the plurality of source connection lines connects the first electrode of the first transistor T1 and the first electrode of the second transistor T2 in the same sub-pixel together.

[0134] In some embodiments, a plurality of ground lines GNLs are configured to be provided with a low-voltage signal (e.g., a ground voltage signal). In some embodiments, the plurality of ground lines GNLs are connected to a ground plane in a second signal line layer, for example, via one or more vias extending through a second interlayer dielectric layer. Optionally, the ground plane is connected to a third anti-interference block in a first signal line layer via one or more vias extending through at least a first interlayer dielectric layer. Optionally, the third anti-interference block is connected to a first anti-interference block in a semiconductor material layer via one or more vias extending through at least one of an insulating layer and a gate insulating layer.

[0135] In some embodiments, each of the plurality of first node connection pads Cpn1 is connected to a corresponding first node connection line among the plurality of first node connection lines, for example, via one or more vias extending through the second interlayer dielectric layer. Each of the plurality of first node connection lines connects the gate of the driving transistor T3 to a corresponding drain connection line among the plurality of drain connection lines. Each of the plurality of drain connection lines connects the second electrode of the first transistor T1 and the second electrode of the second transistor T2 in the same sub-pixel together. Each of the plurality of first node connection lines Cpn1 is also connected to the first capacitor electrode of the storage capacitor (e.g., via...). Figure 4O CP1 in the middle is connected to Figure 4L (Ce1 in the middle).

[0136] In some embodiments, each of the plurality of second node connection pads Cpn2 is connected to a corresponding second node connection line among the plurality of second node connection lines, for example, via one or more vias extending through the second interlayer dielectric layer. Each of the plurality of second node connection lines connects the second electrode of the driving transistor T3 to the anode of the light-emitting element (e.g., via...). Figure 4O CP2 in Figure 4Q (ACP in the text).

[0137] Figure 4J The image shows a via extending through the third interlayer dielectric layer.

[0138] Reference Figure 3 , Figure 4A , Figure 4K , Figure 5 and Figure 6 In some embodiments, the fourth signal line layer SD4 includes a plurality of first relay electrodes RE1 and a plurality of second relay electrodes RE2. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the fourth signal line layer SD4. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the fourth signal line layer SD4 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of first relay electrodes RE1 and the plurality of second relay electrodes RE2 are located in the same layer.

[0139] In some embodiments, each of the plurality of first relay electrodes RE1 is connected, for example, to a corresponding first node connection pad in a plurality of first node connection pads Cpn1 via one or more vias extending through a third interlayer dielectric layer. Each of the plurality of first node connection pads Cpn1 is connected, for example, to a corresponding first node connection line in a plurality of first node connection lines via one or more vias extending through a second interlayer dielectric layer. Each of the plurality of first node connection lines connects the gate of the driving transistor T3 to a corresponding drain connection line in a plurality of drain connection lines. Each of the plurality of drain connection lines connects the second electrode of the first transistor T1 and the second electrode of the second transistor T2 in the same sub-pixel together. Each of the plurality of first node connection lines Cpn1 is also connected to the first capacitor electrode of the storage capacitor (e.g., via...). Figure 4O CP1 in the middle is connected to Figure 4L (Ce1 in the middle).

[0140] In some embodiments, each of the plurality of second relay electrodes RE2 is connected, for example, to a corresponding second node connection pad in a plurality of second node connection pads Cpn2 via one or more vias extending through the third interlayer dielectric layer. Each of the plurality of second node connection pads Cpn2 is connected, for example, to a corresponding second node connection line in a plurality of second node connection lines via one or more vias extending through the second interlayer dielectric layer. Each of the plurality of second node connection lines connects the second electrode of the driving transistor T3 to the anode of the light-emitting element (e.g., via...). Figure 4O CP2 in Figure 4Q (ACP in the text).

[0141] Reference Figure 3 , Figure 4A , Figure 4L , Figure 5 and Figure 6 In some embodiments, the first conductive layer CT1 includes a plurality of first capacitor electrodes CE1. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first conductive layer CT1. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer CT1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0142] In some embodiments, each of the plurality of first capacitor electrodes CE1 is connected to a corresponding first node connection pad in a plurality of first node connection pads Cpn1, for example, through one or more vias extending through at least one of the first passivation layer PVX1, the fourth interlayer dielectric layer ILD4, or the third interlayer dielectric layer ILD3. Each of the plurality of first node connection pads Cpn1 is connected to a corresponding first node connection line in a plurality of first node connection lines Cln1, for example, through one or more vias extending through the second interlayer dielectric layer ILD2. Each of the plurality of first node connection lines connects the gate of the driving transistor T3 to a corresponding drain connection line in a plurality of drain connection lines. Each of the plurality of drain connection lines connects the second electrode of the first transistor T1 and the second electrode of the second transistor T2 in the same sub-pixel together.

[0143] Reference Figure 3 , Figure 4A , Figure 4M , Figure 5 and Figure 6In some embodiments, the second conductive layer CT2 includes a second capacitor electrode Ce2 for a storage capacitor. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second conductive layer CT2. For example, a conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second conductive layer CT2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0144] In some embodiments, the second capacitor electrode Ce2 is an integral structure configured as the second capacitor electrode of a plurality of storage capacitors in a plurality of pixel driving circuits within a repeating unit. Optionally, the second capacitor electrode Ce2 is an integral structure configured as the second capacitor electrode of all storage capacitors in all pixel driving circuits within a repeating unit.

[0145] In some embodiments, the second capacitor electrode Ce2 is configured to be provided with a low voltage signal (e.g., a ground voltage signal). In some embodiments, the second capacitor electrode Ce2 is connected to a plurality of ground lines, for example, through one or more vias extending through at least one of the second passivation layer PVX2, the first passivation layer PVX1, the fourth interlayer dielectric layer, or the third interlayer dielectric layer. Optionally, the plurality of ground lines are connected to a ground plane located on the second signal line layer, for example, through one or more vias extending through the second interlayer dielectric layer. Optionally, the ground plane is connected to a third anti-interference block located on the first signal line layer through one or more vias extending through at least one of the first interlayer dielectric layer. Optionally, the third anti-interference block is connected to a first anti-interference block located on the semiconductor material layer through one or more vias extending through at least one of the insulating layer and the gate insulating layer.

[0146] In some embodiments, the second capacitor electrode Ce2 includes a plurality of electrode blocks connected together by a plurality of bridges. The orthographic projection of each electrode block in the plurality of electrode blocks onto the substrate at least partially overlaps with the orthographic projection of at least one of the plurality of first capacitor electrodes onto the substrate (e.g., the orthographic projection of each electrode block in the plurality of electrode blocks onto the substrate covers the orthographic projection of at least one of the plurality of first capacitor electrodes onto the substrate). The storage capacitor is formed from a corresponding first capacitor electrode among the plurality of first capacitor electrodes, a corresponding electrode block among the plurality of electrode blocks of the second capacitor electrode Ce2, and a second passivation layer PVX2 that spaces the corresponding first capacitor electrode and the corresponding electrode block.

[0147] Figure 4N The image shows a via extending through the third passivation layer.

[0148] Reference Figure 3 , Figure 4A , Figure 4O , Figure 5 and Figure 6 In some embodiments, the first connection layer TM1 includes a plurality of first connection pads CP1 and a plurality of second connection pads CP2. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first connection layer TM1. For example, a conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first connection layer TM1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of first connection pads CP1 and the plurality of second connection pads CP2 are located in the same layer.

[0149] In some embodiments, each of the plurality of first connection pads CP1 is connected to a corresponding first capacitor electrode among the plurality of first capacitor electrodes, for example, through one or more vias extending through at least one of the second passivation layer PVX2 or the third passivation layer PVX3. Each of the plurality of first connection pads CP1 is connected to a corresponding first node connection line among the plurality of first node connection lines, for example, through one or more vias extending through at least one of the second passivation layer PVX2, the third passivation layer PVX3, the second interlayer dielectric layer ILD2, the third interlayer dielectric layer ILD3, or the fourth interlayer dielectric layer ILD4.

[0150] In some embodiments, each of the plurality of second connection pads CP2 is connected to a corresponding anode connection pad among the plurality of anode connection pads, for example, through one or more vias extending through the first planarization layer PLN1. Each of the plurality of anode connection pads is connected to the anode of a corresponding sub-pixel. Each of the plurality of second connection pads CP2 is connected to a corresponding second node connection line among the plurality of second node connection lines, for example, through one or more vias extending through at least one of the second passivation layer PVX2, the third passivation layer PVX3, the second interlayer dielectric layer ILD2, the third interlayer dielectric layer ILD3, or the fourth interlayer dielectric layer ILD4.

[0151] Figure 4P The image shows a via extending through the first planarization layer.

[0152] Reference Figure 3 , Figure 4A , Figure 4Q , Figure 5 and Figure 6In some embodiments, the second interconnect layer TM2 includes a plurality of anode interconnect pads (ACPs). Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second interconnect layer TM2. For example, a conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second interconnect layer TM2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0153] In some embodiments, each anode pad in the plurality of anode connection pads ACP is connected to a corresponding second connection pad in the plurality of second connection pads via one or more vias extending through the first planarization layer PLN1. Each second connection pad in the plurality of second connection pads is connected to a corresponding second node connection line in the plurality of second node connection lines, for example, via one or more vias extending through at least one of the second passivation layer PVX2, the third passivation layer PVX3, the second interlayer dielectric layer ILD2, the third interlayer dielectric layer ILD3, or the fourth interlayer dielectric layer ILD4.

[0154] Figure 4R The image shows a via extending through the second planarization layer.

[0155] Reference Figure 3 , Figure 4A , Figure 4S , Figure 5 and Figure 6 In some embodiments, the anode layer ADL includes a plurality of anodes AD. Each anode in the plurality of anodes AD is connected to a corresponding anode connection pad in a plurality of anode connection pads ACP, for example, through one or more vias extending through the second planarization layer PLN2.

[0156] Figure 7A The circuit connection layout of the first pixel driving circuit of the first sub-pixel of the first pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown. Figure 7B The circuit connection layout of the second pixel driving circuit of the second sub-pixel of the first pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown. Figure 7C The circuit connection layout of the third pixel driving circuit of the third sub-pixel of the first pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown. Figure 7D The circuit connection layout of the first pixel driving circuit in the first sub-pixel of the second pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown. Figure 7EThe circuit connection layout of the second pixel driving circuit of the second sub-pixel of the second pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown. Figure 7F The circuit connection layout of the third pixel driving circuit of the third sub-pixel of the second pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown. Figure 7G The circuit connection layout of the first pixel driving circuit in the first sub-pixel of the third pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown. Figure 7H The circuit connection layout of the second pixel driving circuit of the second sub-pixel of the third pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown. Figure 7I The circuit connection layout of the third pixel driving circuit of the third sub-pixel of the third pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown. Figure 7J The circuit connection layout of the first pixel driving circuit in the first sub-pixel of the fourth pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown. Figure 7K The circuit connection layout of the second pixel driving circuit of the second sub-pixel of the fourth pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown. Figure 7L The circuit connection layout of the third pixel driving circuit of the third sub-pixel of the fourth pixel in the repeating unit of the array substrate according to some embodiments of the present disclosure is shown.

[0157] Reference Figure 3 , Figures 7A to 7L In each pixel driving circuit, each of the plurality of first voltage supply lines is connected to the first electrode of the driving transistor T3. Each of the plurality of first gate lines GL1 is connected to the gate of the first transistor T1. Each of the plurality of second gate lines GL2 is connected to the gate of the second transistor T2.

[0158] Each source connection in the multiple source connection lines SCL connects the first electrode of the first transistor T1 and the first electrode of the second transistor T2 together. Each source connection in the multiple source connection lines SCL also connects to a corresponding data connection pad in the multiple data connection pads DCP. Each data connection pad in the multiple data connection pads DCP is in turn connected to a corresponding data line in the multiple data lines DL.

[0159] Each drain connection in the multiple drain connection lines DCL connects the second electrode of the first transistor T1 and the second electrode of the second transistor T2 together. Each drain connection in the multiple drain connection lines DCL is also connected to a corresponding first node connection in the multiple first node connection lines Cln1. Each first node connection in the multiple first node connection lines Cln1 is then connected to the gate of the driving transistor T3.

[0160] Each of the multiple first node connection lines Cln1 is connected to a corresponding first connection pad among the multiple first connection pads. Each of the multiple first connection pads is connected to a corresponding first capacitor electrode among the multiple first capacitor electrodes.

[0161] Each of the multiple second-node connection lines Cln2 is connected to the second electrode of the driving transistor T3. Each of the multiple second-node connection lines is then connected to a corresponding second-connection pad among the multiple second-connection pads. Each of the multiple second-connection pads is then connected to a corresponding anode-connection pad among the multiple anode-connection pads. Each of the multiple anode-connection pads is connected to the anode of the corresponding sub-pixel.

[0162] Figure 8 A data signal network in an array substrate according to some embodiments of the present disclosure is illustrated. In a repeating unit, the number of transistors configured to receive data signals is 2N, where N is an integer greater than or equal to 1, such as 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, or 20. In one example, N = 12. In another example, the repeating unit comprises four pixels, each pixel comprising three sub-pixels, each sub-pixel comprising pixel driving circuitry, and each pixel driving circuitry comprising two transistors configured to receive data signals.

[0163] In some embodiments, the number of data lines configured to provide data signals to the repeating unit is (N / 2). In some embodiments, the number of data connection pads in the repeating unit is (N / 2). In some embodiments, the number of source connection lines in the repeating unit is (N / 2). Optionally, the first electrodes of four transistors (including two first transistors and two second transistors) in two pixel driving circuits located in the same column are connected to the same source connection line. Optionally, the first electrodes of four transistors (including two first transistors and two second transistors) in two adjacent pixels located in the same column of two pixel driving circuits are connected to the same source connection line.

[0164] In some embodiments, the first electrodes of two first transistors connected to the same source connection line are part of the overall structure. In some embodiments, the first electrodes of two second transistors connected to the same source connection line are part of the overall structure.

[0165] Figure 9 The layout of first node interconnects in an array substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figure 3 and Figure 9 In the repeating cell, the number of transistors whose second electrode is connected to the first node N1 is 2N. In one example, N = 12. Optionally, the number of drain connections in the repeating cell is N. Optionally, the number of first node connections in the repeating cell is N. Optionally, the number of intermediate connection pads in the repeating cell is N. Optionally, the number of first node connection pads in the repeating cell is N.

[0166] Figure 10 The arrangement of first capacitor electrodes in an array substrate according to some embodiments of the present disclosure is shown. Figure 10 It is shown that each of the multiple first connection pads CP1 connects the corresponding first node connection pad in the multiple first node connection pads Cpn1 to the corresponding first capacitor electrode in the multiple first capacitor electrodes Ce1.

[0167] Figure 11 An anode connection layout in an array substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figure 11 Each second node connecting line in the multiple second node connecting lines Cln2 is connected to the corresponding second connecting pad in the multiple second connecting pads CP2. Each second connecting pad in the multiple second connecting pads CP2 is connected to the corresponding anode connecting pad in the multiple anode connecting pads ACP.

[0168] Reference Figure 4A , Figure 4B , Figure 4F , Figure 4H , Figure 4I and Figure 4M In some embodiments, the array substrate includes a low-voltage signal network configured to be provided with a low-voltage signal (e.g., a ground voltage signal). In some embodiments, the low-voltage signal network includes a first anti-interference block IPB1 configured to shield at least a portion of the active layer of the first transistor T1 and at least a portion of the active layer of the driving transistor T3 from electromagnetic interference. Optionally, the first anti-interference block IPB1 is located on the same layer as the active layers of the first transistor T1 and the driving transistor T3.

[0169] In some embodiments, the low-voltage signal network further includes a third anti-interference block IPB3, which is configured to shield at least a portion of the active layer of the first transistor T1 and at least a portion of the active layer of the driving transistor T3 from electromagnetic interference. The third anti-interference block IPB3 is connected to the first anti-interference block IPB1. The third anti-interference block IPB3 is located on a different layer than the first anti-interference block IPB1. Optionally, the third anti-interference block IPB3 is located on the first signal line layer and on the side of the first anti-interference block IPB1 away from the substrate.

[0170] In some embodiments, the third anti-interference block IPB3 exists in the first and second pixels of the repeating unit, but not in the third and fourth pixels of the repeating unit.

[0171] In some embodiments, the orthographic projection of the third anti-interference block IPB3 on the substrate at least partially overlaps with the orthographic projection of the active layers of the driving transistors in the repeating unit on the substrate. Optionally, the orthographic projection of the third anti-interference block IPB3 on the substrate at least partially overlaps with the orthographic projection of the active layers of the driving transistors in the first pixel and the second pixel of the repeating unit on the substrate. Optionally, the orthographic projection of the third anti-interference block IPB3 on the substrate does not overlap with the orthographic projection of the active layers of the driving transistors in the third pixel and the fourth pixel of the repeating unit on the substrate.

[0172] In some embodiments, the low-voltage signal network further includes a ground plane (GND). Optionally, the ground plane (GND) is connected to a third anti-interference block (IPB3). The ground plane (GND) is located on a different layer than either the first anti-interference block (IPB1) or the third anti-interference block (IPB3). Optionally, the ground plane (GND) is located on a second signal line layer and on the side of the third anti-interference block (IPB3) away from the first anti-interference block (IPB1).

[0173] In some embodiments, the ground plane GND in the repeating unit extends over at least 50% (at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, or at least 90%) of the repeating unit. Optionally, the ground plane GND in the repeating unit extends over less than 100% of the repeating units (less than 95%, less than 90%, less than 85%, less than 80%, less than 75%, less than 70%, less than 65%, or less than 60%).

[0174] In some embodiments, the orthographic projection of the ground plane GND on the substrate at least partially overlaps with the orthographic projection of the third anti-interference block IPB3 in the repeating unit on the substrate; and at least partially overlaps with the orthographic projection of the first anti-interference block IPB1 in the repeating unit on the substrate. Optionally, the orthographic projection of the third anti-interference block IPB3 in the repeating unit on the substrate at least partially overlaps with the orthographic projection of the first anti-interference block IPB1 in the repeating unit on the substrate.

[0175] In some embodiments, the low-voltage signal network further includes a plurality of ground lines GNL. Optionally, the plurality of ground lines GNL are connected to a ground plane GND. The plurality of ground lines GNL are located on a different layer than the ground plane GND, the first anti-interference block IPB1, or the third anti-interference block IPB3. Optionally, the plurality of ground lines GNL are located on a third signal line layer and on the side of the ground plane GND away from the third anti-interference block IPB3.

[0176] In some embodiments, a plurality of grounding wires GNL extend in a direction substantially parallel to the second direction DR2.

[0177] In some embodiments, the low-voltage signal network further includes a second capacitor electrode Ce2. Optionally, the second capacitor electrode Ce2 is connected to a plurality of ground lines GNL. Optionally, the second capacitor electrode Ce2 is located on a different layer than the plurality of ground lines GNL, the ground plane GND, the first anti-interference block IPB1, or the third anti-interference block IPB3. Optionally, the second capacitor electrode Ce2 is located on a second conductive layer and on the side of the plurality of ground lines GNL away from the ground plane GND.

[0178] The inventors of this disclosure have discovered that the low-voltage signal network according to this disclosure can effectively shield at least a portion of the active layer of the first transistor T1 and at least a portion of the active layer of the driving transistor T3 from electromagnetic interference; and achieve an increase in the storage capacitance of the storage capacitor.

[0179] In some embodiments, the array substrate further includes a plurality of second voltage supply lines. Figure 12A This is a schematic diagram illustrating the structure of a second interconnect layer in an array substrate according to some embodiments of the present disclosure. Figure 12B This is a schematic diagram illustrating the structure of the anode layer in an array substrate according to some embodiments of the present disclosure. Figure 12C This is a schematic diagram illustrating the structure of the cathode layer in an array substrate according to some embodiments of the present disclosure. Figure 12D The structure of the second interconnect layer and cathode layer in an array substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figures 12A to 12DIn some embodiments, the second connection layer includes a plurality of anode connection pads (ACPs) and a plurality of second voltage supply lines (Vss). In some embodiments, the plurality of first voltage supply lines are configured to provide a first reference voltage signal (e.g., a high reference voltage signal). Optionally, the plurality of second voltage supply lines (Vss) are configured to provide a second reference voltage signal (e.g., a low reference voltage signal). Optionally, the first reference voltage signal is a constant voltage signal, the second reference voltage signal is a constant voltage signal, and the voltage level of the first reference voltage signal is higher than the voltage level of the second reference voltage signal.

[0180] Reference Figures 12A to 12D In some embodiments, each of the plurality of second voltage supply lines Vss is connected to the cathode CD via, for example, one or more vias v extending through at least the pixel defining layer. Optionally, the cathode CD is a common layer extending throughout the display area of ​​the array substrate. The inventors of this disclosure have found that by connecting the plurality of second voltage supply lines Vss to the cathode CD, the voltage drop across the cathode CD can be effectively reduced. The inventors of this disclosure have found that by placing the plurality of second voltage supply lines Vss in the same layer as the plurality of anode connection pads ACP, the need for an additional layer for forming the auxiliary cathode is eliminated, thereby simplifying the manufacturing process and increasing the aperture ratio of the array substrate.

[0181] Figure 13 This is a cross-sectional view of an array substrate according to some embodiments of this disclosure. (Refer to...) Figure 13In some embodiments, the array substrate includes a substrate BS, a semiconductor material layer SEM on the substrate BS, a gate insulating layer GI on the side of the semiconductor material layer SEM away from the substrate BS, a gate metal layer GT on the side of the semiconductor material layer SEM away from the substrate BS, an insulating layer IN on the side of the gate metal layer GT away from the substrate BS, a first signal line layer SD1 on the side of the insulating layer IN away from the substrate BS, a first interlayer dielectric layer ILD1 on the side of the first signal line layer SD1 away from the substrate BS, and a first interlayer dielectric layer ILD1 on the side of the first signal line layer SD1 away from the substrate BS. The second signal line layer SD2 on the side of LD1 away from the substrate BS, the second interlayer dielectric layer ILD2 on the side of the second signal line layer SD2 away from the substrate BS, the third signal line layer SD3 on the side of the second interlayer dielectric layer ILD2 away from the substrate BS, the third interlayer dielectric layer ILD3 on the side of the third signal line layer SD3 away from the substrate BS, the fourth signal line layer SD4 on the side of the third interlayer dielectric layer ILD3 away from the substrate BS, the first passivation layer PVX1 on the side of the fourth signal line layer SD4 away from the substrate BS, and the position The components are: a first conductive layer CT1 on the side of the first passivation layer PVX1 away from the substrate BS; a second passivation layer PVX2 on the side of the first conductive layer CT1 away from the substrate BS; a second conductive layer CT2 on the side of the second passivation layer PVX2 away from the substrate BS; a third passivation layer PVX3 on the side of the second conductive layer CT2 away from the substrate BS; a first interconnect layer TM1 on the side of the third passivation layer PVX3 away from the substrate BS; a first planarization layer PLN1 on the side of the first interconnect layer TM1 away from the substrate BS; and a first planarization layer PLN1 on the side of the first planarization layer PVX2 away from the substrate BS. The system comprises a second interconnect layer TM2 on the side of layer PLN1 away from the substrate BS, a second planarization layer PLN2 on the side of layer PLN2 away from the substrate BS, an anode layer ADL on the side of layer PLN2 away from the substrate BS, a pixel defining layer PDL on the side of layer ADL away from the substrate BS, a light emitting layer EL on the side of layer ADL away from the substrate BS and at least partially located in a pixel opening defined by the pixel defining layer PDL, and a cathode layer CD on the side of layer EL away from the substrate BS. The second interconnect layer TM2 includes a plurality of second voltage supply lines Vss. The cathode layer CD is connected to the plurality of second voltage supply lines Vss via, for example, one or more vias v extending through at least the pixel defining layer PDL and the second planarization layer PLN2.

[0182] Figure 14 A second voltage supply network in an array substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figure 14In some embodiments, the array substrate includes a display area DA and a peripheral area PA. As used herein, the term "display area" refers to the area of ​​the display substrate that actually displays an image. Optionally, the display area may include subpixel areas and inter-subpixel areas. A subpixel area refers to the light-emitting area of ​​a subpixel, for example, the area corresponding to a pixel electrode in a liquid crystal display or the area corresponding to a light-emitting layer in an organic light-emitting display. An inter-subpixel area refers to the area between adjacent subpixel areas, for example, the area corresponding to a black matrix in a liquid crystal display or the area corresponding to a pixel defining layer in an organic light-emitting display. Optionally, the inter-subpixel area is the area between adjacent subpixel areas within the same pixel. Optionally, the inter-subpixel area is the area between two adjacent subpixel areas in two adjacent pixels. As used herein, the term "peripheral area" refers to the area of ​​the display substrate (e.g., a counter substrate or an array substrate) in a display panel where various circuits and wires are provided to transmit signals to the display substrate. To increase the transparency of the display device, opaque or light-blocking components of the display device (e.g., batteries, printed circuit boards, metal frames) may be arranged in the peripheral area instead of the display area.

[0183] In some embodiments, the second voltage supply network includes a plurality of second voltage supply lines Vss and peripheral second voltage supply lines PVss. Each of the plurality of second voltage supply lines Vss intersects at least partially with the display area DA. Optionally, the peripheral second voltage supply lines PVss are at least partially located in the peripheral area PA. Optionally, the plurality of second voltage supply lines Vss are connected to the peripheral second voltage supply lines PVss. Optionally, the plurality of second voltage supply lines Vss and the peripheral second voltage supply lines PVss are part of an integral structure. The second voltage supply network is connected to the cathode, as shown below. Figures 12A to 12D and Figure 13 As shown. Optionally, the second voltage supply network is connected to the cathode via one or more vias in the display area DA. Optionally, the peripheral second voltage supply lines PVss substantially surround the display area DA.

[0184] In an array substrate without a second voltage supply network, the inventors of this disclosure found that when the array substrate is configured to display an image with 255 gray levels, the IR voltage drop can be as large as 992 mV, and the current uniformity is 67%. In an array substrate with a second voltage supply network, the inventors of this disclosure found that the IR voltage drop can be significantly reduced to 284 mV, and the current uniformity increases to 85%.

[0185] Figure 15A The IR voltage drop on an array substrate without a second voltage supply network is shown. Figure 15B The IR voltage drop on an array substrate with a second voltage supply network is shown. (Refer to...) Figure 15A In array substrates without a second voltage supply network, the IR voltage drop is much higher in the central region of the array substrate. (Refer to...) Figure 15B In an array substrate with a second voltage supply network, the IR voltage drop is more uniformly distributed across the entire array substrate (especially in the row direction). Display uniformity is significantly improved in an array substrate with a second voltage supply network.

[0186] Figure 16 It is shown Figure 4A A schematic diagram of the structure of the first signal line layer and the anode layer in the array substrate shown. (Refer to...) Figure 16 Each of the plurality of anodes AD has a first width w1 along a direction substantially parallel to the first direction DR1. The shortest source connection line among the plurality of source connection lines SCL has a second width w2 along a direction substantially parallel to the first direction DR1. In some embodiments, the second width w2 is greater than at least 75% of the first width w1 (e.g., greater than at least 80%, greater than at least 85%, greater than at least 90%, greater than at least 95%, greater than at least 99%, or greater than at least 100%). In some embodiments, the width of any source connection line in the plurality of source connection lines SCL along a direction substantially parallel to the first direction DR1 is greater than at least 75% of the first width w1 (e.g., greater than at least 80%, greater than at least 85%, greater than at least 90%, greater than at least 95%, greater than at least 99%, or greater than at least 100%).

[0187] In some embodiments, each anode in the plurality of anodes AD has a first maximum width. The shortest source connection line in the plurality of source connection lines SCL has a second maximum width. In some embodiments, the second maximum width is greater than at least 75% of the first maximum width (e.g., greater than at least 80%, greater than at least 85%, greater than at least 90%, greater than at least 95%, greater than at least 99%, or greater than at least 100%). In some embodiments, the maximum width of any source connection line in the plurality of source connection lines SCL is greater than at least 75% of the first maximum width (e.g., greater than at least 80%, greater than at least 85%, greater than at least 90%, greater than at least 95%, greater than at least 99%, or greater than at least 100%).

[0188] Figure 17 It is shown Figure 4A A schematic diagram of the structure of the first signal line layer in the array substrate shown. (Refer to...) Figure 4F and Figure 17A first corresponding first gate line 1RGL1 in a plurality of first gate lines GL1, a first corresponding second gate line 1RGL2 in a plurality of second gate lines GL2, a second corresponding second gate line 2RGL2 in a plurality of second gate lines GL2, and a second corresponding first gate line 2RGL1 in a plurality of first gate lines GL1 extend through the corresponding repeating unit. In some embodiments, the first corresponding first gate line 1RGL1, the first corresponding second gate line 1RGL2, the second corresponding second gate line 2RGL2, and the second corresponding first gate line 2RGL1 are arranged sequentially along a second direction DR2. Optionally, the source connection lines in each repeating unit (e.g., all source connection lines in each repeating unit) are located between a first group of gate lines and a second group of gate lines, the first group of gate lines including the first corresponding first gate line 1RGL1 and the first corresponding second gate line 1RGL2, and the second group of gate lines including the second corresponding second gate line 2RGL2 and the second corresponding first gate line 2RGL1. Optionally, the drain connection lines of the first group of sub-pixels in each repeating unit are located on the side of the first group of gate lines away from the source connection lines in the corresponding repeating unit. Optionally, the drain connection lines of the second group of sub-pixels in each repeating unit are located on the side of the second group of gate lines away from the source connection lines in the corresponding repeating unit. Optionally, the array substrate does not include any drain connection lines between the first group of gate lines and the second group of gate lines.

[0189] In some embodiments, the source interconnects in each repeating unit are arranged in one or more columns along the second direction DR2. Each column of the one or more columns of source interconnects includes a first source interconnect SCL1, a second source interconnect SCL2, and a third source interconnect SCL3. The second source interconnect SCL2 is located between the first source interconnect SCL1 and the third source interconnect SCL3. The first source interconnect SCL1 and the third source interconnect SCL3 have a U-shape. The opening of the U-shape of the first source interconnect SCL1 and the opening of the U-shape of the third source interconnect SCL3 are opposite to each other. The second source interconnect SCL2 is located between the opening of the U-shape of the first source interconnect SCL1 and the opening of the U-shape of the third source interconnect SCL3.

[0190] In some embodiments, the drain connection lines of the first group of sub-pixels in each repeating unit are arranged in one or more columns along the second direction DR2. Each column of the one or more columns of drain connection lines of the first group of sub-pixels in each repeating unit includes a first drain connection line DCL1, a second drain connection line DCL2, and a third drain connection line DCL3. The second drain connection line DCL2 is located between the first drain connection line DCL1 and the third drain connection line DCL3.

[0191] In some embodiments, the first drain connection line DCL1 and the second drain connection line DCL2 have a U-shape. The opening of the U-shape of the first drain connection line DCL1 and the opening of the U-shape of the second drain connection line DCL2 face the same direction, for example, towards the third drain connection line DCL3.

[0192] In some embodiments, the drain connection lines of the second group of sub-pixels in each repeating unit are arranged in one or more columns along the second direction DR2. Each column of the drain connection lines of the second group of sub-pixels in each repeating unit includes a fourth drain connection line DCL4, a fifth drain connection line DCL5, and a sixth drain connection line DCL6. The fifth drain connection line DCL5 is located between the fourth drain connection line DCL4 and the sixth drain connection line DCL6.

[0193] In some embodiments, the fifth drain connection line DCL5 and the sixth drain connection line DCL6 have a U-shape. The openings of the U-shape of the fifth drain connection line DCL5 and the U-shape of the sixth drain connection line DCL6 face the same direction, for example, towards the fourth drain connection line DCL4.

[0194] Figure 18 It is shown Figure 4A This is a schematic diagram of the structure of the gate metal layer and the first signal line layer in the array substrate shown. (Refer to...) Figure 18 In some embodiments, the orthographic projection of the second source connection line SCL2 on the substrate does not overlap with the orthographic projections of the gates of the first transistor and the second transistor on the substrate. In some embodiments, the orthographic projection of the first electrode connection line SCL1 on the substrate partially overlaps with the orthographic projections of the gates of at least one first transistor and at least one second transistor on the substrate. In some embodiments, the orthographic projection of the third source connection line SCL3 on the substrate partially overlaps with the orthographic projections of the gates of at least one first transistor and at least one second transistor on the substrate.

[0195] In some embodiments, the orthographic projection of any drain connection line (including the first drain connection line DCL1, the second drain connection line DCL2, the third drain connection line DCL3, the fourth drain connection line DCL4, the fifth drain connection line DCL5, and the sixth drain connection line DCL6) on the substrate does not overlap with the orthographic projection of the gate of the first transistor, the gate of the second transistor, and the gate of the third transistor on the substrate.

[0196] The inventors of this disclosure discovered that, Figure 17 and Figure 18 The unique structure shown helps to maximize the use of layout area.

[0197] Figure 19 It is shown Figure 4A A schematic diagram of the structure of the semiconductor material layer in the array substrate shown. (Refer to...) Figure 19 In some embodiments, the array substrate includes a plurality of N-well regions (NWRs). As used herein, the term "N-well region" refers to a region subjected to N-type doping. In some embodiments, a plurality of first anti-interference blocks and a plurality of N-well regions (NWRs) are arranged alternately along a first direction DR1. Each N-well region in the plurality of NWRs spacees two adjacent first anti-interference blocks in the plurality of first anti-interference blocks.

[0198] In some embodiments, along a first direction DR1, a plurality of first anti-interference blocks and a plurality of second anti-interference blocks are arranged alternately. Each of the plurality of second anti-interference blocks separates two adjacent first anti-interference blocks from the plurality of first anti-interference blocks. Each of the plurality of first anti-interference blocks separates two adjacent second anti-interference blocks from the plurality of second anti-interference blocks. In a row of repeating units, the first anti-interference blocks and the second anti-interference blocks are located on two opposite sides of a row of N-well regions.

[0199] Reference Figures 7A to 7L , Figure 9 and Figure 10 In some embodiments, each of the plurality of first node connection lines Cln1 has a T-shape or an L-shape. Each first node connection line includes a first segment and a second segment, the first segment and the second segment forming two strokes of a T-shape or an L-shape. Optionally, the first segment is the location where each first node connection line (e.g., via Cpn1 and Cp1) connects to the first capacitor electrode Ce1, and the second segment is the location where each first node connection line (e.g., via IP1) connects to the gate of the third transistor.

[0200] Figure 20 yes Figure 4A A schematic diagram of the structure of the gate metal layer and the second signal line layer in the array substrate shown. (Refer to...) Figure 20 , Figure 4C and Figure 4H In some embodiments, the orthographic projection of at least one of the plurality of second node connection lines Cln2 onto the substrate partially overlaps with the orthographic projection of the gate G2 of the second transistor T2 onto the substrate. In some embodiments, the orthographic projection of each of the plurality of first node connection lines Cln1 onto the substrate partially overlaps with the orthographic projection of the gate G3 of the third transistor T3 onto the substrate.

[0201] On the other hand, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0202] In some embodiments, the array substrate includes a plurality of light-emitting elements. Optionally, each of the plurality of light-emitting elements includes an anode among a plurality of anodes. Optionally, the plurality of anodes are connected to one or more integrated circuits. Optionally, each light-emitting element is an organic light-emitting diode (OLED). Optionally, each light-emitting element is a micro LED. Optionally, each light-emitting element is a miniature LED. Optionally, each light-emitting element includes an anode, a light-emitting layer, and a cathode.

[0203] On the other hand, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming pixels arranged in a plurality of repeating units. Optionally, forming each repeating unit in the plurality of repeating units includes: forming a plurality of pixels. Optionally, forming each pixel includes: forming one or more sub-pixels. Optionally, the method includes: forming a plurality of source interconnects and forming a plurality of data connection pads in the repeating units, and forming a plurality of data lines. Optionally, each source interconnect in the plurality of source interconnects connects a first electrode of a first transistor and a first electrode of a second transistor in a corresponding pixel driving circuit together. Optionally, each source interconnect also connects to a corresponding data connection pad in the plurality of data connection pads. Optionally, each data connection pad connects to a corresponding data line in the plurality of data lines. Optionally, the method further includes: forming a plurality of anodes. Optionally, each anode in the plurality of anodes has a first maximum width. Optionally, each source interconnect has a second maximum width. Optionally, the second maximum width is greater than at least 75% of the first maximum width.

[0204] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate comprising pixels arranged in a plurality of repeating units; in, Each of the plurality of repeating units includes a plurality of pixels, and each pixel includes one or more sub-pixels; The array substrate includes multiple source connection lines and multiple data connection pads in the repeating unit, as well as multiple data lines; Each of the plurality of source connection lines connects the first electrode of the first transistor and the first electrode of the second transistor in the corresponding pixel driving circuit together. Each source connection line is also connected to a corresponding data connection pad in the plurality of data connection pads; and The corresponding data connection pad is connected to the corresponding data line among the plurality of data lines; The array substrate further includes multiple anodes; Each of the plurality of anodes has a first maximum width; and Each source connection line has a second maximum width; The second maximum width is at least 75% greater than the first maximum width.

2. The array substrate according to claim 1, wherein, In the repeating unit, the number of pixel driving circuits is N, where N is an integer greater than or equal to 1; The number of data lines configured to provide data signals to the repeating unit is (N / 2); The number of data connection pads in the repeating unit is (N / 2); and The number of source connection lines in the repeating unit is (N / 2).

3. The array substrate according to claim 1, wherein, In the repeating unit, the first electrodes of the four transistors in the two pixel driving circuits of two adjacent pixels located in the same column are connected to the same source connection line; as well as The four transistors include a first transistor and a second transistor in the first pixel driving circuit of a first adjacent pixel in the same column, and a first transistor and a second transistor in the second pixel driving circuit of a second adjacent pixel in the same column.

4. The array substrate according to claim 1, wherein, The array substrate further includes multiple drain connection lines in the repeating unit; and Each of the plurality of drain connection lines connects the second electrode of the first transistor and the second electrode of the second transistor in the corresponding pixel driving circuit together.

5. The array substrate according to claim 4, wherein, The array substrate also includes multiple first node connection lines in the repeating unit; Each drain connection line is connected to the corresponding first node connection line among the plurality of first node connection lines; as well as The corresponding first node connection line is electrically connected to the gate of the driving transistor in the corresponding pixel driving circuit.

6. The array substrate according to claim 5, wherein, In the repeating unit, the number of transistors whose second electrode is connected to the first node in the repeating unit is 2N; The number of drain connections in the repeating unit is N; and The number of connecting lines for the first node in the repeating unit is N.

7. The array substrate according to claim 5, wherein, The array substrate also includes a plurality of first connection pads and a plurality of first capacitor electrodes in the repeating unit; Each first node connection line is connected to the corresponding first connection pad among the plurality of first connection pads; as well as Each of the plurality of first connecting pads is connected to a corresponding first capacitor electrode among the plurality of first capacitor electrodes.

8. The array substrate according to any one of claims 1 to 7, wherein, The array substrate also includes a plurality of second node connection lines, a plurality of second connection pads, and a plurality of anode connection pads in the repeating unit; Each of the plurality of second node connection lines is connected to the second electrode of the driving transistor in the corresponding pixel driving circuit. Each of the second node connection lines is connected to the corresponding second connection pad among the plurality of second connection pads; The corresponding second connecting pad is connected to the corresponding anode connecting pad among the plurality of anode connecting pads; and The corresponding anode connecting pad is connected to the anode of the corresponding sub-pixel.

9. The array substrate according to any one of claims 1 to 7, further comprising a low-voltage signal network configured to be provided with a low-voltage signal; in, The low-voltage signal network includes a first anti-interference block, which is configured to shield at least a portion of the active layer of the first transistor and at least a portion of the active layer of the driving transistor from electromagnetic interference. The first anti-interference block is located on the same layer as the active layer of the first transistor and the active layer of the driving transistor.

10. The array substrate according to claim 9, wherein, The low-voltage signal network further includes a third anti-interference block, which is configured to shield at least a portion of the active layer of the first transistor and at least a portion of the active layer of the driving transistor from electromagnetic interference. The third anti-interference block is connected to the first anti-interference block and is located on a different layer than the first anti-interference block; and The orthographic projection of the third anti-interference block on the substrate at least partially overlaps with the orthographic projection of the active layer of the plurality of driving transistors in the repeating unit on the substrate.

11. The array substrate according to claim 10, wherein, The low-voltage signal network also includes a ground plane connected to the third anti-interference block and located on a different layer than the first anti-interference block or the third anti-interference block; Wherein, the ground plane in the repeating unit extends throughout at least 50% of the repeating unit; and The orthographic projection of the ground plane on the substrate at least partially overlaps with the orthographic projection of the third anti-interference block in the repeating unit on the substrate; and at least partially overlaps with the orthographic projection of the first anti-interference block in the repeating unit on the substrate.

12. The array substrate according to claim 11, wherein, The low-voltage signal network also includes multiple grounding wires connected to the ground plane and located in a different layer from the ground plane, the first anti-interference block, or the third anti-interference block; The plurality of grounding wires and the plurality of data lines are located on the same layer; and The plurality of grounding wires and the plurality of data lines extend in a direction substantially parallel to the second direction.

13. The array substrate according to claim 12, wherein, The low-voltage signal network further includes a second capacitor electrode connected to the plurality of grounding wires and located on a different layer than the plurality of grounding wires, the ground plane, the first anti-interference block, or the third anti-interference block.

14. The array substrate according to any one of claims 1 to 7, further comprising an interconnected voltage supply network; in, The interconnected voltage supply network includes multiple first voltage supply lines and multiple voltage supply connection lines; The plurality of first voltage supply lines extend in a direction substantially parallel to the first direction; The plurality of voltage supply connection lines extend in a direction substantially parallel to the second direction; The plurality of first voltage supply lines are located on a different layer than the plurality of voltage supply connection lines; Each of the plurality of voltage supply connection lines is connected to a corresponding first voltage supply line among the plurality of first voltage supply lines through one or more vias; as well as Two adjacent voltage supply connection lines among the plurality of voltage supply connection lines and two adjacent first voltage supply connection lines among the plurality of first voltage supply connection lines substantially surround the pixel driving circuit of the repeating unit.

15. The array substrate according to any one of claims 1 to 7, further comprising a plurality of second voltage supply lines and a plurality of anode connection pads located on the same layer, and a cathode located on the side of the plurality of second voltage supply lines away from the substrate; in, Each of the plurality of second voltage supply lines is connected to the cathode via one or more vias.

16. The array substrate according to claim 15, further comprising a peripheral second voltage supply line located in the peripheral region of the array substrate; The plurality of second voltage supply lines are connected to the surrounding second voltage supply lines; and The peripheral second voltage supply line essentially surrounds the display area of ​​the array substrate.

17. The array substrate according to any one of claims 1 to 7, wherein, The repeating unit comprises four pixels; and Each of the four pixels in the repeating unit includes at least three sub-pixels.

18. The array substrate according to any one of claims 1 to 7, wherein, The corresponding layers of the pixel driving circuits in adjacent pixels of the repeating unit are substantially mirror-symmetric with respect to each other about a plane that is perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines.

19. The array substrate according to any one of claims 1 to 7, wherein, Each pixel driving circuit includes: The driving transistor, the first transistor, and the second transistor; and A storage capacitor having a first capacitor electrode and a second capacitor electrode; The gate of the driving transistor is connected to the second electrode of the first transistor and the second electrode of the second transistor, and is also connected to the first capacitor electrode; The first electrode of the driving transistor is connected to a corresponding first voltage supply line among a plurality of first voltage supply lines; The second electrode of the driving transistor is connected to the anode of the light-emitting element; The gate of the first transistor is connected to a corresponding first gate line among a plurality of first gate lines; The gate of the second transistor is connected to a corresponding second gate line among a plurality of second gate lines; The first electrode of the first transistor and the first electrode of the second transistor are connected to corresponding data lines among the plurality of data lines; and The second capacitor electrode is configured to be supplied with a low voltage signal.

20. The array substrate according to any one of claims 1 to 7, further comprising a plurality of first gate lines and a plurality of second gate lines; in, The first corresponding first gate line of the plurality of first gate lines, the first corresponding second gate line of the plurality of second gate lines, the second corresponding second gate line of the plurality of second gate lines, and the second corresponding first gate line of the plurality of first gate lines extend through the corresponding repeating unit; The source connection line in the corresponding repeating unit is located between the first group of gate lines and the second group of gate lines. The first group of gate lines includes the first corresponding first gate line and the first corresponding second gate line, and the second group of gate lines includes the second corresponding second gate line and the second corresponding first gate line. The drain connection line of the first group of sub-pixels in the corresponding repeating unit is located on the side of the first group of gate lines away from the source connection line in the corresponding repeating unit. The drain connection line of the second group of sub-pixels in the corresponding repeating unit is located on the side of the second group of gate lines away from the source connection line in the corresponding repeating unit; and The array substrate has no drain connection lines between the first group of gate lines and the second group of gate lines.

21. The array substrate according to claim 20, wherein, The source connection lines in the corresponding repeating unit are arranged in one or more columns along the second direction; Each column of the one or more columns of source connection lines includes a first source connection line, a second source connection line, and a third source connection line; The second source connection line is located between the first source connection line and the third source connection line; The first source connection line and the third source connection line have a U-shape; The U-shaped opening of the first source connection line is opposite to the U-shaped opening of the third source connection line; as well as The second source connection line is located between the U-shaped opening of the first source connection line and the U-shaped opening of the third source connection line.

22. The array substrate according to claim 20, wherein, The drain connection lines of the first group of sub-pixels in the corresponding repeating unit are arranged in one or more columns along the second direction. Each column of the one or more columns of drain connection lines in the first group of sub-pixels in the corresponding repeating unit includes a first drain connection line, a second drain connection line, and a third drain connection line. The second drain connection line is located between the first drain connection line and the third drain connection line; The first drain connection line and the second drain connection line have a U-shape; as well as The U-shaped openings of the first drain connection and the U-shaped openings of the second drain connection face the same direction.

23. The array substrate according to claim 20, wherein, The drain connection lines of the second group of sub-pixels in the corresponding repeating unit are arranged in one or more columns along the second direction. Each column of the drain connection lines in the second group of sub-pixels in the corresponding repeating unit includes a fourth drain connection line, a fifth drain connection line, and a sixth drain connection line. The fifth drain connection line is located between the fourth drain connection line and the sixth drain connection line; The fifth drain connection line and the sixth drain connection line have a U-shape; as well as The U-shaped opening of the fifth drain connection line and the U-shaped opening of the sixth drain connection line face the same direction.

24. The array substrate according to claim 21, wherein, The orthographic projection of the second source connection line on the substrate does not overlap with the orthographic projections of the gate of the first transistor and the gate of the second transistor on the substrate. The orthographic projection of the first electrode connection line on the substrate partially overlaps with the orthographic projections of the gate of at least one first transistor and the gate of at least one second transistor on the substrate. as well as The orthographic projection of the third source connection line on the substrate partially overlaps with the orthographic projections of the gates of at least one first transistor and at least one second transistor on the substrate.

25. The array substrate according to claim 20, wherein, The orthographic projection of any drain connection line on the substrate does not overlap with the orthographic projections of the gates of the first transistor, the second transistor, and the third transistor on the substrate.

26. The array substrate according to any one of claims 1 to 7, further comprising a plurality of N-well regions and a plurality of first anti-interference blocks; in, Along a first direction, the plurality of first anti-interference blocks and the plurality of N-well regions are arranged alternately; and Each of the plurality of N-well regions separates two adjacent first anti-interference blocks among the plurality of first anti-interference blocks.

27. The array substrate according to claim 26, further comprising a plurality of second anti-interference blocks; in, Along the first direction, the plurality of first anti-interference blocks and the plurality of second anti-interference blocks are arranged alternately; Each of the plurality of second anti-interference blocks separates two adjacent first anti-interference blocks from the plurality of first anti-interference blocks; Each of the plurality of first anti-interference blocks separates two adjacent second anti-interference blocks among the plurality of second anti-interference blocks; as well as In a row of repeating cells, the first anti-interference block and the second anti-interference block are located on two opposite sides of the row of N-well regions.

28. The array substrate according to any one of claims 1 to 7, further comprising a plurality of first node connection lines; in, Each of the plurality of first node connecting lines has a T-shape or an L-shape; Each first node connecting line includes a first segment and a second segment, the first segment and the second segment forming two strokes of the T shape or the L shape; The first section is the location where each first node connection line connects to the first capacitor electrode; and The second section is where the connection lines of each first node are connected to the gate of the third transistor.

29. The array substrate according to any one of claims 1 to 7, further comprising a plurality of first node connection lines and a plurality of second node connection lines; in, The orthographic projection of at least one of the plurality of second node connection lines on the substrate partially overlaps with the orthographic projection of the gate of the second transistor on the substrate. as well as The orthographic projection of each of the plurality of first node connection lines on the substrate partially overlaps with the orthographic projection of the gate of the third transistor on the substrate.

30. A display device comprising an array substrate according to any one of claims 1 to 29 and one or more integrated circuits connected to the array substrate; in, The array substrate includes multiple light-emitting elements; Each of the plurality of light-emitting elements includes an anode among the plurality of anodes; and The plurality of anodes are connected to the one or more integrated circuits.

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