FPGA Implementation of ABAQ Compression in Doppler Domain for Spaceborne Multi-channel SAR

Abstract

The present application discloses an FPGA implementation method based on ABAQ compression in Doppler domain of spaceborne multi-channel SAR, including: data acquisition and preprocessing, storing data in DDR3SDRAM, performing 8-way parallel zero-filling FFT operation on the stored data; performing Krieger azimuth reconstruction operation; using window-shifted large-point FFT reconstruction processing to reduce the periodic error caused by splicing of reconstructed data; performing on-board variable bit compression ABAQ operation: based on BAQ with adaptive bit allocation, caching all block means or standard deviations within a spectrum range, obtaining the bit allocation number corresponding to the mean or standard deviation of input block data, updating the array of cached mean or standard deviation data of all block means or standard deviations, and realizing data compression with variable bit number; processing valid data with variable bit number and adding frame header, frame tail and auxiliary file.

Description

Technical Field

[0001] The present application relates to the technical field of digital signal processing, and more specifically, to an FPGA implementation method of satellite-borne multi-channel SAR Doppler domain ABAQ compression. Background Art

[0002] Spaceborne synthetic aperture radar (SAR) is widely used in military reconnaissance and civil remote sensing satellites because it is not affected by bad weather. As the system continues to move towards high resolution and wide mapping band, which are conflicting requirements for pulse repetition frequency (PRF), along-track multi-channel technology has emerged. At the same time, the development of multi-polarization and multi-mode methods has further increased the data volume of spaceborne SAR (≥100Mbit / s). In order to meet the requirements of transmission bandwidth and the need for real-time transmission of raw data, a SAR raw data compression method with high compression ratio and low distortion needs to be used on the satellite. There is an existing spaceborne multi-channel SAR Doppler domain ABAQ (Adaptive bitallocation Block Adaptive Quantization, adaptive bit allocation BAQ) compression method (Jiang, T.; Zhang, C.; Zhang, F.; Wan, Y.; Chen, L.A. Multichannel, Multipulse, Multiweight Block-Adaptive Quantization (3MBAQ) Algorithm Based on Space-Borne Multichannel SAR Doppler Domain A-BAQ. Remote Sens. 2024, 16, 477. https: / / doi.org / 10.3390 / rs16030477), which can utilize the PRF redundancy between multi-channel data to achieve data compression with higher signal-to-noise ratio. However, due to the complexity of implementing the Krieger azimuth signal reconstruction algorithm and the adaptive bit allocation BAQ (Block Adaptive Quantization) algorithm on FPGA (Field Programmable Gate Array), the implementation of the spaceborne multi-channel SAR Doppler domain ABAQ compression method on FPGA is challenging. Specifically, there are the following three deficiencies:

[0003] (1) The reconstruction between multi-channel data on board is difficult to achieve on FPGA and cannot be realized by simple logic. It is generally implemented by CPU or GPU.

[0004] (2) Adaptive bit allocation is difficult to implement on FPGA, and the number of multi-channel zero-padding FFT points does not match the IP core of the development software Vivado;

[0005] (3) There is no implementation solution for transferring data to the Doppler domain on FPGA, which requires the transposition of the stored data, which requires a lot of time and computational overhead. Summary of the invention

[0006] To solve the above problems, an embodiment of the present application provides an FPGA implementation method based on satellite-borne multi-channel SAR Doppler domain ABAQ compression, which can solve the implementation problems of reconstruction and adaptive bit allocation between satellite-borne multi-channel data on FPGA.

[0007] In a first aspect, an embodiment of the present application provides an FPGA implementation method based on satellite-borne multi-channel SAR Doppler domain ABAQ compression, the method comprising:

[0008] Data acquisition and preprocessing: Based on the format of the front-end storage body as a data frame, according to the requirements of serial input, the first and last parts of the data are used to cover the frame header and frame tail respectively;

[0009] The preprocessed data is stored in a DDR3 SDRAM, and an interface is developed for the DDR3 SDRAM so that the package form thereof is an interface structure with address unit reading and writing;

[0010] Based on the DDR3 clock frequency and the user-side FPGA, an 8-way parallel zero-padding FFT (Fast Fourier Transform) operation is performed on the data stored in the DDR3 SDRAM;

[0011] Perform Krieger azimuth reconstruction based on the data after FFT operation, and constrain the start interval II to achieve continuous input;

[0012] Based on the data reconstructed in Krieger azimuth, the reconstruction process of moving window large point FFT is adopted to reduce the periodic error caused by splicing of the reconstructed data.

[0013] Performing on-board variable bit compression ABAQ operations, including: caching all block means or standard deviations within a frequency spectrum based on BAQ with adaptive bit allocation; obtaining the number of bit allocation bits corresponding to the mean or standard deviation of input block data based on the cached block means or standard deviation processing; updating the array of cached mean or standard deviation data of all blocks based on the mean or standard deviation of each input block; and realizing data compression with variable bit numbers based on the bit allocation number of input block data;

[0014] Based on the frame-based processing of the backend storage, the valid data with variable bit numbers is processed and the frame header, frame footer and auxiliary files are added.

[0015] In one embodiment, developing an interface for the DDR3 SDRAM and packaging it in a form of an interface structure with address unit read and write includes:

[0016] Based on the storage of big data, the Memory Interface Generator core is used to develop DDR3 interfaces;

[0017] Based on the transposition of big data, the MIG core is encapsulated to form an IP core with a simple dual port (Simple Dual Port RAM) interface structure for address unit reading and writing.

[0018] In one embodiment, performing a Krieger azimuth reconstruction operation based on the data after the FFT operation and constraining the start interval II to be a continuous input includes:

[0019] Implement the Krieger azimuth reconstruction algorithm based on FPGA serial input;

[0020] Based on the Krieger azimuth reconstruction algorithm, point-to-point processing is implemented on the HLS (High Level Synthetic) software, and the optimization statement is used to realize the startup interval II as a continuous input.

[0021] In one embodiment, the method further includes: solving the point matching problem of NFFT (Number of Fast Fourier Transform points) of the FFT kernel on vivado based on the Krieger azimuth reconstruction algorithm;

[0022] Based on the NFFT point matching problem of the FFT core on Vivado, point-to-point acquisition of reconstructed filter coefficients is implemented in the HLS software.

[0023] In one embodiment, based on the data reconstructed in Krieger azimuth, a reconstruction process of a large-point FFT with a moving window is used to reduce the periodic error caused by splicing the reconstructed data, and also includes: determining a cutting plan for the final redundant data based on the front-end multi-channel input points and the algorithm output points.

[0024] In one embodiment, the method further comprises:

[0025] The window shifting method is used to perform large-point zero-filled FFT on multi-channel data, and then reconstruct the IFFT (Inverse Fast Fourier Transform).

[0026] The IFFT data with a large number of points is clipped at both ends, and the result with a small number of points in the middle is retained;

[0027] The middle section small point number result is subjected to FFT conversion to the Doppler domain, and adaptive bit data compression is performed in the Doppler domain.

[0028] In one embodiment, based on the processing of the backend storage body in the form of frames, processing the valid data of variable bit numbers and adding the frame header, frame footer and auxiliary files includes:

[0029] Based on the data compression result of variable bit number, the effective number of bits is stored to realize data splicing;

[0030] Based on the spliced ​​indefinite length valid data, the frame header and frame tail inputted from the front end are used to distinguish the pulse boundary;

[0031] Based on the output frame structure, a fixed-length auxiliary file is added to the end of the frame and is limited by the current pulse frame end and the next pulse frame head.

[0032] In a second aspect, an embodiment of the present application further provides a device equipped with an FPGA, wherein the device equipped with an FPGA adopts the aforementioned FPGA implementation method based on satellite-borne multi-channel SAR Doppler domain ABAQ compression to transmit data to the FPGA carried thereon, and then transmits the compressed data to a subsequent device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0034] Figure 1 It is a flowchart of an FPGA implementation method based on satellite-borne multi-channel SAR Doppler domain ABAQ compression provided in an embodiment of the present application.

[0035] Figure 2 It is a schematic diagram of data changes before and after frame processing of the front-end input in the FPGA implementation method provided in the embodiment of the present application.

[0036] Figure 3 This is a schematic diagram of interval zero padding in the FPGA implementation method provided in an embodiment of the present application.

[0037] Figure 4 It is a noisy 2D image of the image processed by a conventional 128-point FFT.

[0038] Figure 5 This is a graph showing the noise variation with orientation of an image after conventional 128-point FFT processing.

[0039] Figure 6 It is a two-dimensional image of image noise restored by taking 64-point FFT after 128-point FFT and IFFT in the FPGA implementation method provided in the embodiment of the present application.

[0040] Figure 7 This is a graph showing the variation of image noise with azimuth after 128-point FFT followed by IFFT and 64-point FFT restoration in the FPGA implementation method provided in the embodiment of the present application.

[0041] Figure 8 It is a schematic diagram of the FPGA frame output structure in the FPGA implementation method provided in the embodiment of the present application. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0043] It should be understood that the "first", "second" and "third" in the embodiments of the present application are only for distinction and should not constitute any limitation to the present application. It should also be understood that in various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0044] It should also be noted that terms such as "upper", "lower", "front", "back", "left", "right", "top", "bottom", "inside" and "outside" indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0045] This application proposes an FPGA implementation scheme of a satellite-borne multi-channel SAR Doppler domain ABAQ compression method, which can effectively implement the corresponding algorithm.

[0046] The present application is further described below in conjunction with the accompanying drawings and embodiments.

[0047] See also Figure 1 , this application provides the main implementation steps of the FPGA implementation method based on satellite-borne multi-channel SAR Doppler domain ABAQ compression.

[0048] Step 1, perform front-end frame processing. Referring to Table 1, it is known that the format of the front-end storage data is in the form of a data frame, and the basic parameters of the data frame are shown in the following table. The first 128 bytes are the frame header, the last 128 bytes are the frame tail, the total frame length is 16K points (including the frame header and frame tail, each point unit is 2 bytes), the middle part is the SAR raw data, and each 2 bytes of data is represented as 16-bit IQ data, that is, the format of the IQ data is int8; when processing the frame reading, the default is 128B as 1 unit.

[0049] Table 1 Several parameters of the front-end input frame

[0050] parameter value Frame Header 128B Frame end 128B Frame Bytes 32KB Data Format Int8 Number of samples 16K Sampling format I / Q

[0051] See also Figure 2 The bit width of the data read from the front end for each clock CLK is 16 bits. The counter is used to determine the position of the current read data in the frame header, valid data, and frame tail. Several FIFOs (First In First Out) are set to overwrite the first and last valid data units to cover the frame header and frame tail. If the entire data frame is divided into 128B, there are n blocks.

[0052] By duplicating the process, valid data and frame header and frame tail can be processed separately, and finally the data frame shown below is obtained, where 0 represents the frame header, n-1 represents the frame tail, and the difference between adjacent Arabic numerals is 128B.

[0053] Step 2, big data storage and transposition. The data after front-end frame processing is stored in DDR3SDRAM, the interface of the DDR3SDRAM is developed, and its packaging form is an interface structure with address unit reading and writing. Among them, based on the storage of big data, the memory interface management core is used to develop the DDR3 interface; based on the transposition of big data, the MIG core is encapsulated to form an IP core with a simple dual-port RAM interface structure for address unit reading and writing.

[0054] The development board parameters in this step are shown in Table 2. The user-side system clock ui_clk is 200MHz, and the device clocks ddr_clk_n and ddr_clk_p of ddr3 are differential clocks of 800MHz, so the data input ratio is 8:1.

[0055] Table 2 Development board parameters

[0056]

[0057] According to the onboard parameters, if the bandwidth rate needs to be matched, the frame input is 16bit / clk, which is cached in a FIFO. The IP (hereinafter referred to as IP_0) that reads and writes DDR3 through the MIG core packaged in RAM reads the FIFO once every 8 clk times, and the read bit width is 128bit, that is, 8 16bit points. IP_0 will quickly write 128bit into the sequential address unit of DDR3 in 8 times in the next idle time.

[0058] Step 3, perform 8-way parallel zero-filling FFT. Based on the DDR3 clock frequency and the user-side FPGA, perform 8-way parallel zero-filling FFT operation on the data stored in the DDR3 SDRAM. Referring to Table 3, taking a three-channel radar system as an example, the parameter settings are as follows.

[0059] Table 3 Radar system parameters

[0060] parameter value Number of channels 3 Antenna spacing 1.875m wavelength 0.0555m Closest slope distance 902270 PRF 2179.8 V 7563.6 Sampling frequency 133.33MHz

[0061] See also Figure 3 ,The data processed by the three-channel frame is input into DDR3_0, DDR3_1, and DDR3_2. When the amount of data stored in the SDRAM exceeds M azimuth pulses, the azimuth data points are output in sequence according to the order of data transposition. M is the number of single-channel pulses processed in the azimuth each time. The idea of ​​transposing the address is as follows.

[0062] ddr3_data_addr=ddr3_data_pulse*range_num+ddr3_data_range

[0063] Where ddr3_data_pulse is the serial number of the current azimuth pulse, range_num is the total number of points in the range direction, and ddr3_data_range is the serial number of the current range point position.

[0064] Each channel is transposed and outputs M-point azimuth data, each point is 128 bits, and is processed in 8 parallel paths, with 16 bits of data processed each time, that is, one I and one Q data.

[0065] The data output by the above transposition is stored in a RAM with a bit width of 128 bits at intervals of 3 points, and then the NFFT point zero-filled data of the corresponding RAM of the three channels is output.

[0066] like Figure 3 In the formula, M is the number of azimuth pulses. From the algorithmic point of view, each channel should be padded to 3M points. However, in Vivado, FFT conversion to Doppler domain is performed later. The NFFT supported by the FFT core used is only a power of 2. As a trade-off, the channel data is further padded to a power of 2 NFFT.

[0067] Perform FFT transformation of NFFT points on the above results. Actually, each of the above data is 128 bits, 8 parallel paths, and 3 channels in parallel.

[0068] Then, the Krieger azimuth reconstruction operation is performed based on the data after the FFT operation, and the start interval II is constrained to achieve continuous input. Among them, the Krieger azimuth reconstruction algorithm is implemented based on the serial input of the FPGA; based on the Krieger azimuth reconstruction algorithm, point-to-point processing is implemented on the HLS software, and the optimization statement is used to realize the start interval II as a continuous input.

[0069] In addition, it is also necessary to solve the NFFT point matching problem of the FFT core on vivado based on the Krieger azimuth reconstruction algorithm; based on the NFFT point matching problem of the FFT core on vivado, point-to-point acquisition of reconstruction filter coefficients is implemented in the HLS software.

[0070] The azimuth signal is reconstructed from the FFT result of the NFFT point. However, according to the classic Krieger algorithm, the data points need to be segmented, and the number of segments is the number of channels. Because the NFFT point cannot be divided by 3, and considering the complexity of the reconstruction algorithm to find the matrix inverse and other steps, High Level Synthetic software is selected to implement the reconstruction algorithm. HLS software can realize the conversion from C / C++ language to Verilog language. The azimuth signal reconstruction algorithm is implemented in HLS software, which realizes from segmented to point-to-point processing. For each input frequency point, the reconstruction filter coefficient is given by the algorithm, and the coefficient is multiplied by the input frequency point, and the three channel frequency points are added to obtain the reconstructed data. In order to ensure the processing of the Verilog program, the optimization constraint statement "%HLSPIPELINE II=1" is added to realize the input start interval II is 1, that is, continuous input, and continuous output after a certain delay.

[0071] Then, based on the data reconstructed in Krieger azimuth, a large-point FFT reconstruction process with a moving window is used to reduce the periodic error caused by splicing the reconstructed data. It also includes: determining the final redundant data cutting plan based on the front-end multi-channel input points and the algorithm output points.

[0072] Since the reconstructed result is NFFT points, and the actual input is M points in each of the three channels, the asymmetry of the data will lead to splicing problems, such as Figure 4-Figure 7As shown in the figure, the final image has obvious periodic errors after imaging. The reconstructed result is restored to the time domain by IFFT, the output data is cut to retain the middle section, and FFT is converted to the frequency domain for subsequent processing. When the front end obtains data from DDR3_0, DDR3_1, and DDR3_2, the input of overlapping data is processed by window shifting, each time the win_shift point is offset to the azimuth pulse, and the reading rate is increased to read three-channel DDR3 data once every 4 clks to ensure the balance of input and output rates.

[0073] Combine the 8-way parallel FFT results into 128-bit data, calculate the equivalent transposed address position, and write it into the new DDR3_3, writing 128 bits each time.

[0074] In addition, the implementation method also includes: using a window shifting method to perform a large-point zero-filled FFT on the multi-channel data and reconstructing the IFFT; trimming the IFFT data at both ends under the large point number and retaining the middle section with a small point number result; performing an FFT conversion on the middle section with a small point number result to the Doppler domain and performing adaptive bit data compression in the Doppler domain.

[0075] Then, the variable bit compression ABAQ operation is performed on the board, including: BAQ based on adaptive bit allocation, caching all block means or standard deviations within a spectrum range; based on the cached block mean or standard deviation processing, obtaining the bit allocation number corresponding to the mean or standard deviation of the input block data; based on the mean or standard deviation of each input block, updating the array of cached all block mean or standard deviation data; and based on the bit allocation number of the input block data, realizing data compression with variable bit numbers. Specifically, data is read from DDR3_3, and the reconstructed data is read in the order of address units, 8 channels are parallelized, and the absolute value is taken and the sign bit is separated in sequence. The mean is calculated once for each input block of IQ data, and the corresponding amplitude block standard deviation is obtained by searching. The corresponding relationship is shown in the following formula.

[0076]

[0077] Where σ is the standard deviation of the block data, and |I| and |Q| are the mean amplitudes of the real and imaginary parts of the block data, respectively.

[0078] The following formula obtains the optimal quantization bit allocation scheme under predetermined conditions through the Lagrange multiplier method and the rate-distortion function under Gaussian distribution. This formula is used to guide the implementation of adaptive bit allocation on FPGA.

[0079]

[0080] Among them, R j Indicates the number of quantization bits corresponding to a certain block k, is the preset quantization digit target; σ j Indicates the standard deviation of block k; K represents the number of all blocks within the entire frequency band. If the azimuth pulse processed each time is M, the range sampling point is range_num, and the number of points in each block is 1024, then K = M × range_num ÷ 1024; ΔR j It is the change in the number of bits obtained based on the standard deviation of each block, that is, log2σ k ; R avg is the mean value corresponding to the matrix block points.

[0081] During the input time of each block, the standard deviation σ needs to be calculated k ; It is also necessary to use the standard deviation σ of the block corresponding to the previous pulse k-1 Normalize the current input block data with vivado's divisor kernel; cache the current standard deviation σ k , calculate the mean R corresponding to the matrix block points avg ; Using the current standard deviation σ k Calculate ΔR k , pre-set It is known that the number of quantization bits R corresponding to the current block is obtained k The standard deviation matrix is ​​moved backwards to obtain the average value, ensuring adaptive bit allocation.

[0082] The above result is the normalized data result, and the corresponding block quantization bit number bit_R_n is also input. The normalized result is quantized by table lookup using bit_R_n. The bit number is used as the high address bit of the table lookup and the normalized data is used as the low address bit to achieve adaptive quantization results.

[0083] Based on the processing of the back-end storage data in the form of frames, the valid data with variable bit numbers are processed and the frame header, frame tail and auxiliary files are added, which includes: based on the data compression result of the variable bit number, the valid bit number is stored to realize data splicing; based on the splicing of the indefinite length valid data, the frame header and frame tail of the front-end input are used to distinguish the pulse boundary; based on the output frame structure, the fixed-length auxiliary file is added to the frame tail and limited by the current pulse frame tail and the next pulse frame head. Specifically, the final output result is the variable-length data quantization result, the adaptive bit number allocation result aligned with the data block, and the standard deviation result aligned with the data block. Because the output result becomes longer, the output result needs to be trimmed to remove the redundant bits. Considering that each output is 8-way parallel, that is, 8 groups of IQ outputs, and the bit number is quantized to 1 to 5 bits, the minimum output of valid data is 8*2*1=16 bits, and the maximum output of valid data is 8*2*5=80 bits. Therefore, in order to ensure the same input and output bandwidth, the data of several clks are cached for splicing and disassembly to meet the input and output bit numbers of each clk of 128 bits.

[0084] See also Figure 8 The output of the azimuth pulse compression output uses PRF_OUT as the flag bit. The frame header and frame tail retained from the front-end frame data input are placed at both ends of the valid data, and also include R with variable bit numbers. k After the std file required for decompression is packaged into auxiliary files and stored at the end of the frame, the output result of the frame is as follows. In addition, because the time-shift window win_shift point is input each time, that is, win_shift*3 pulses are input each time, and the final number of spectrum points must be a power of 2, the number of frames must be asymmetric, and the frame header and frame tail information must be padded with zeros every few frame outputs. The output frame header and frame tail information is filtered and cut during decompression.

[0085] On the other hand, the present application also provides a device equipped with an FPGA, which uses the above-mentioned FPGA implementation method based on satellite-borne multi-channel SAR Doppler domain ABAQ compression to transmit data to the FPGA carried, and then transmits the compressed data to the subsequent equipment.

[0086] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An FPGA implementation method based on satellite-borne multi-channel SAR Doppler domain ABAQ compression, characterized by: Data acquisition and front-end frame processing: Based on the storage format of the front-end storage data as a data frame, according to the requirements of serial input, the frame header and frame tail are covered with the data of the first unit and the last unit respectively; The data after the front-end frame processing is stored in DDR3 SDRAM, and the interface of the DDR3 SDRAM is developed and its packaging form is an interface structure with address unit reading and writing; Based on the DDR3 clock frequency and the user-side FPGA, an 8-way parallel zero-padding FFT operation is performed on the data stored in the DDR3 SDRAM; Perform Krieger azimuth reconstruction based on the data after FFT operation, and constrain the start interval II to achieve continuous input; Based on the data reconstructed in Krieger azimuth, the reconstruction process of moving window large point FFT is adopted to reduce the periodic error caused by splicing of the reconstructed data. Performing on-board variable bit compression ABAQ operations, including: caching all block means or standard deviations within a frequency spectrum based on BAQ with adaptive bit allocation; obtaining the number of bit allocation bits corresponding to the mean or standard deviation of input block data based on the cached block means or standard deviation processing; updating the array of cached mean or standard deviation data of all blocks based on the mean or standard deviation of each input block; and realizing data compression with variable bit numbers based on the bit allocation number of input block data; Based on the backend storage data in the form of frames, it processes the valid data with variable bit numbers and adds frame headers, frame tails and auxiliary files. Among them, performing a Krieger azimuth reconstruction operation based on the data after the FFT operation and constraining the start interval II to be a continuous input includes: Implement the Krieger azimuth reconstruction algorithm based on FPGA serial input; Based on the Krieger azimuth reconstruction algorithm, point-to-point processing is implemented on the high-level synthesis software, and the optimization statement is used to realize the startup interval II as a continuous input. The method further comprises: Solve the NFFT point matching problem of FFT core on Vivado based on Krieger azimuth reconstruction algorithm; Based on the NFFT point matching problem of the FFT core on vivado, point-to-point acquisition of reconstructed filter coefficients is implemented in high-level synthesis software.

2. The FPGA implementation method based on satellite-borne multi-channel SAR Doppler domain ABAQ compression according to claim 1 is characterized in that: Developing the interface of the DDR3 SDRAM and making it packaged in a form of an interface structure with address unit read and write includes: Based on the storage of big data, the memory interface management core is used to develop the DDR3 interface; Based on the transposition of big data, the MIG core is encapsulated to form an IP core with a simple dual-port RAM interface structure for address unit reading and writing.

3. The FPGA implementation method based on satellite-borne multi-channel SAR Doppler domain ABAQ compression according to claim 1 is characterized in that: Based on the data reconstructed in Krieger azimuth, the reconstruction processing of the moving window large point FFT is used to reduce the periodic error caused by the splicing of the reconstructed data, which also includes: Based on the front-end multi-channel input points and the algorithm output points, determine the final cutting plan for redundant data.

4. The FPGA implementation method based on satellite-borne multi-channel SAR Doppler domain ABAQ compression according to claim 3 is characterized in that: The method further comprises: Use the window shifting method to perform large-point zero-filled FFT on multi-channel data and reconstruct the IFFT; The reconstructed IFFT data with a large number of points is clipped at both ends, and the result with a small number of points in the middle is retained; The middle section small point number result is subjected to FFT conversion to the Doppler domain, and adaptive bit data compression is performed in the Doppler domain.

5. The FPGA implementation method based on satellite-borne multi-channel SAR Doppler domain ABAQ compression according to claim 1 is characterized in that: Based on the frame-based processing of the backend storage, process the valid data with variable bit numbers and add frame headers, frame trailers and auxiliary files, including: Based on the data compression result of variable bit number, the effective bit number is stored to realize data splicing to obtain effective data of indefinite length; Based on the indefinite length valid data obtained by the splicing, the pulse boundary is distinguished by using the frame header and frame tail input by the front end; The frame structure is output after adding the frame header and frame tail of the front-end input based on the indefinite-length valid data, adding the fixed-length auxiliary file to the frame tail and limiting it with the current pulse frame tail and the next pulse frame header.

6. A device equipped with FPGA, wherein the device equipped with FPGA adopts the FPGA implementation method based on satellite-borne multi-channel SAR Doppler domain ABAQ compression according to claim 1 to transmit data to the FPGA carried thereon, and then transmits the compressed data to a subsequent device.

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