A true random number generator using power supply noise amplification

Abstract

The present invention relates to the field of information security technology, in particular to a true random number generator using power supply noise amplification. The generator comprises a first oscillator, a second oscillator, a de-correlation module, a data stream register counting module, a data post-processing module, a synchronizer and a counting state generator. The second oscillator comprises a ring voltage-controlled oscillator, and the bias voltage of the ring voltage-controlled oscillator is generated by a noise source. The generator has a high random number generation rate and can meet the occasions requiring high data rates.

Description

Technical Field

[0001] The invention relates to the technical field of information security, in particular to a true random number generator using power supply noise amplification. Background Art

[0002] A True Random Number Generator (TRNG) is a device that can generate random numbers based on physical entropy sources (such as electronic noise, chaotic circuits, metastable states of circuits, etc.). These random numbers are unpredictable and cannot be inferred by algorithms. TRNG is a basic component in the field of information security.

[0003] A free oscillator type true random number generator is a type of true random number generator structure widely used in the field of integrated circuits. It has a simple structure and is easy to implement. This structure uses the randomness introduced by the random jitter of the output frequencies of multiple oscillators to generate true random numbers required by the cryptographic system. The disadvantage of the traditional free oscillator type true random number generator is that the random number generation rate is not high and cannot meet the application of high data rate requirements. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a true random number generator using power supply noise amplification, which has a high random number generation rate and can meet the occasions requiring high data rates.

[0005] In order to solve the above problems, the following technical solutions are provided:

[0006] The true random number generator using power supply noise amplification of the present invention comprises:

[0007] Used to generate high frequency signal F H The first oscillator is used to generate a low frequency signal F L The second oscillator.

[0008] A data sampling and de-correlation module adapted to be connected to the first oscillator and the second oscillator, the data sampling and de-correlation module is used to generate a low-frequency signal F L is the clock, high frequency signal F H Form valid code stream data for the data end.

[0009] The data stream register counting module is adaptively connected to the de-correlation module, and the data stream register counting module is used to store effective code stream data and count the number of effective code stream data bits stored in the data stream register counting module in each working cycle.

[0010] The data post-processing module is adapted to be connected to the data stream register counting module, and the data post-processing module is used to generate a low-frequency signal F L and high frequency signal FH To drive the effective code stream data REG V The preliminary random number is subjected to a shift operation and then an XOR operation to form the output data.

[0011] The synchronizer connected to the data post-processing module is used to synchronize the output data with the system clock domain F S Synchronously generate random numbers.

[0012] The counting state generator uses a low frequency signal F L It is a clock unit and is used to count working cycles.

[0013] The characteristic is that the second oscillator comprises a ring voltage-controlled oscillator, and the bias voltage of the ring voltage-controlled oscillator is generated by a noise source.

[0014] Among them, the first oscillator is 100MH Z High-speed ring oscillator.

[0015] The noise source includes an operational amplifier A, the non-inverting input terminal of the operational amplifier A is connected to one end of the resistor R4 and the resistor R5 respectively, the other end of the resistor R4 inputs the external audio signal, and the other end of the resistor R5 is grounded; the inverting input terminal of the operational amplifier A is grounded through the resistor R3. The output terminal of the operational amplifier A is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the inverting input terminal of the operational amplifier A, and the output terminal of the operational amplifier A forms the bias voltage.

[0016] The de-correlation module comprises a D-type trigger and a de-correlation circuit. The D-type trigger is connected to the first oscillator and the second oscillator. The D-type trigger is used to generate a low-frequency signal F L is the clock, high frequency signal F H The D-type trigger is connected to the de-correlation circuit, which is used to obtain the original data stream by sampling the low-frequency signal F L The clock is used to perform de-correlation processing on the original data stream to obtain the effective code stream data.

[0017] The decorrelation circuit is a von Neumann type decorrelation module.

[0018] The data post-processing module includes XOR operator 1, XOR operator 2, LFSR register, CASR register, data selection synchronizer 1, data selection synchronizer 2 and XOR operator 3. The LFSR register receives the high-frequency signal F HAs a driver to generate low 16-bit data, the XOR operator 1 is connected to the data stream register counting module and the LFSR register. The XOR operator 1 reads the high 16-bit data in the effective code stream data bit and receives the low 16-bit data generated by the LFSR register, performs XOR operation, and then sends it to the LFSR register to form low 32-bit data. The CASR register is connected to the data stream register counting module and the LFSR register through the low frequency signal F L As a driver to generate low 16-bit data, the XOR operator 2 is connected to the data stream register counting module and the CASR register. The XOR operator 2 reads the low 16-bit data in the effective code stream data bit and receives the low 16-bit data generated by the CASR register, performs XOR operation, and then sends it to the CASR register to form low 32-bit data. The data selection synchronizer 1 is connected to the LFSR register, and the data selection synchronizer 2 is connected to the CASR register. The data selection synchronizer 1 and the data selection synchronizer 2 receive the low frequency signal F L As a clock signal, it is used to synchronize the lower 32-bit data in the LFSR register and the CASR register. The XOR operator 3 is connected to the selection synchronizer 1 and the selection synchronizer 2 respectively. After 31 rounds of operation of the LFSR register and the CASR register, the data selection synchronizer 1 and the data selection synchronizer 2 respectively read the lower 32-bit data in the LFSR register and the CASR register and send them to the XOR operator 3 for XOR operation to form the output data.

[0019] The counting state generator generates an indication signal RNG_RDY when the valid data of the data stream register counting module is not 0 and the state value of the counting state generator is 31, which is used to indicate whether the true random number generator generates a valid random number in the calculation cycle.

[0020] The above solution has the following advantages:

[0021] Since the second oscillator of the true random number generator using power supply noise amplification of the present invention contains a ring voltage controlled oscillator, the bias voltage of the ring voltage controlled oscillator is generated by the noise source. The design of sampling and amplifying the power supply noise voltage and then using it as the bias voltage of the second oscillator to change the oscillation frequency is adopted. The noise source introduces more randomness into the circuit system, generates true random numbers with higher data rate and quality, and thus meets the occasions requiring high data rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a structural topological diagram of a true random number generator using power supply noise amplification of the present invention;

[0023] Figure 2 The true random number generator of the present invention uses power supply noise amplification to generate a high-frequency signal F H and the low frequency signal F LThe high frequency signal F generated by the true random number generator in the background technology H and the low frequency signal F L Frequency comparison chart of

[0024] Figure 3 It is a circuit diagram of a second oscillator in a true random number generator using power supply noise amplification of the present invention;

[0025] Figure 4 It is an input-output comparison diagram of the decorrelation circuit in the true random number generator using power supply noise amplification of the present invention;

[0026] Figure 5 It is a driving topology diagram of a data post-processing module in a true random number generator using power supply noise amplification of the present invention;

[0027] Figure 6 It is a working cycle waveform diagram of a data post-processing module in a true random number generator using power supply noise amplification of the present invention;

[0028] Figure 7 The present invention is a working topology diagram of a data post-processing module in a true random number generator using power supply noise amplification. DETAILED DESCRIPTION

[0029] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0030] like Figure 1 As shown, the true random number generator using power supply noise amplification of the present invention includes a first oscillator, a second oscillator, a de-correlation module, a data stream register counting module, a data post-processing module, a synchronizer and a counting state generator.

[0031] The first oscillator is a 100 MHz high speed ring oscillator. The second oscillator includes a ring voltage controlled oscillator. The first oscillator generates a high frequency signal F H , the second oscillator generates a low frequency signal F L The bias voltage of the ring voltage controlled oscillator is generated by the noise source. In this embodiment, a design is adopted in which the bias voltage of the ring voltage controlled oscillator (VCO) is controlled after sampling and amplifying the power supply noise voltage to change the oscillation frequency. The power supply noise introduces more randomness into the circuit system, thereby generating true random numbers with higher data rate and quality, such as Figure 2 shown.

[0032] like Figure 3As shown, in this embodiment, the noise source includes an operational amplifier A, the in-phase input terminal of the operational amplifier A is connected to one end of the resistor R4 and the resistor R5 respectively, the other end of the resistor R4 inputs the external audio signal (whether it is correct), and the other end of the resistor R5 is grounded. The inverting input terminal of the operational amplifier A is grounded through the resistor R3. The output terminal of the operational amplifier A is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the inverting input terminal of the operational amplifier A, and the output terminal of the operational amplifier A forms a bias voltage. The noise amplifier circuit composed of the operational amplifier A and the resistor provides a bias voltage to the ring voltage-controlled oscillator to control the oscillation frequency of the VCO. The amplification factor can be adjusted by adjusting the resistors R2 and R3, R2 / R3=100, which is 100 times amplification. The resistors R4 and R5 can adjust the output voltage of the operational amplifier. The resistors all use N-well resistors with the worst voltage characteristics and temperature characteristics in the process to enhance randomness.

[0033] like Figure 1 As shown, the data sampling and de-correlation module is adaptively connected to the first oscillator and the second oscillator, and the data sampling and de-correlation module is used to use the low-frequency signal F L is the clock, high frequency signal F H Form valid code stream data for the data end.

[0034] like Figure 1 As shown, the de-correlation module includes a D-type flip-flop and a de-correlation circuit. The D-type flip-flop is connected to the first oscillator and the second oscillator. The D-type flip-flop is used to sample the original data stream using the low-frequency signal FL as the clock and the high-frequency signal FH as the data terminal. The D-type flip-flop is connected to the de-correlation circuit. The correlation circuit is used to de-correlate the original data stream using the low-frequency signal FL as the clock to obtain valid code stream data. The de-correlation circuit is a von Neumann type de-correlation module.

[0035] In this embodiment, sampling is performed using a D-type trigger, with the low-frequency signal FL as the trigger clock and the high-frequency signal FH as the trigger data end. The sampled data stream is the original random number. Although more noise is introduced at the low-frequency oscillator end, there is still a certain correlation between the two frequencies, and the original code stream must be de-correlated.

[0036] The classic von Neumann decorrelation circuit is used: its principle is: two bits of data are sent to the decorrelation module each time; if the two bits of data are the same (both 1 or both 0), the two bits of data are discarded; if the two bits of data are [1, 0], a 0 is output; if the two bits of data are [0, 1], a 1 is output, such as Figure 4 As shown in the figure, the de-correlated bitstream has a good distribution balance of "1" and "0".

[0037] The data stream register counting module is adapted to be connected with the de-correlation module. The data stream register counting module is used to store valid code stream data and count the number of valid code stream data bits stored in the data stream register counting module in each working cycle. The data stream register counting module contains a register REGv and a counter CNTv

[0038] The data post-processing module is adapted to be connected with the data stream register counting module, and the data post-processing module is used to L and high frequency signal F H To drive the effective code stream data REG V The preliminary random number is subjected to a shift operation and then an XOR operation to form the output data.

[0039] like Figure 1 As shown, the data post-processing module includes an XOR operator 1, an XOR operator 2, an LFSR register, a CASR register, a data selection synchronizer 1, a data selection synchronizer 2 and an XOR operator 3. The LFSR register is connected to the LFSR register by a high-frequency signal F H As a driver to generate low 16-bit data, XOR operator 1 is connected to the data stream register counting module and LFSR register. XOR operator 1 reads the high 16-bit data in the effective code stream data bit and receives the low 16-bit data generated by the LFSR register, performs XOR operation, and then sends it to the LFSR register to form low 32-bit data. L As a driver to generate low 16-bit data, XOR operator 2 is connected to the data stream register counting module and the CASR register. XOR operator 2 reads the low 16-bit data in the effective code stream data bit and receives the low 16-bit data generated by the CASR register, and then sends it to the CASR register to form low 32-bit data. Data selection synchronizer 1 is connected to the LFSR register, data selection synchronizer 2 is connected to the CASR register, and data selection synchronizer 1 and data selection synchronizer 2 receive the low frequency signal F L As a clock signal, it is used to synchronize the lower 32-bit data in the LFSR register and the CASR register. The XOR operator 3 3 is connected to the selection synchronizer 1 and the selection synchronizer 2 respectively. After the LFSR register and the CASR register operate 31 rounds, the data selection synchronizer 1 and the data selection synchronizer 2 read the lower 32-bit data in the LFSR register and the CASR register respectively and send them to the XOR operator 3 3 for XOR operation to form output data.

[0040] like Figure 5 As shown, in this embodiment, the two groups of shift registers are a 43-bit LFSR register (linear feedback shift register) and a 37-bit CASR register (cellular automaton shift register).

[0041] Specifically, the primitive polynomial of the LFSR register is X43+X41+X20+X+1. The CASR register has a superior characteristic to the LFSR register. The next state of the CA cell is a combination of the states of the neighboring cells. This is different from the LFSR register in which the next state value is obtained by simply shifting the adjacent cells left or right. Therefore, the sequence generated by the CASR register has a smaller correlation than the LFSR register. The design uses a hybrid cellular automaton (HCA) composed of linear rules 90 and 150 with a period of 2 n -1, n is the length of the cellular automaton. The operation rule of CA90 is ai(t+1)=ai-1(t)⊕ai+1(t), and the operation rule of CA150 is ai(t+1)=ai-1(t)⊕ai(t)⊕ai+1(t). CA150 is tapped at the 28th bit.

[0042] Because the cycle periods of the two state machines of the CASR register and the LFSR register are relatively independent, the cycle period of the combined data generator is close to 2 80 (2 80 -2 37 -2 43 +1).

[0043] The synchronizer is connected to the data post-processing module and is used to synchronize the output data with the system clock domain F S Synchronously forms a random number that can be read out via the bus.

[0044] The counting state generator uses a low frequency signal F L The clock unit is used to count the working cycle. The counting state generator contains counter CNT1024 and counter CNT32

[0045] When the counter CNT1024 of the counting state generator counts to 1023, the generator enters the working state. In the working state, counters CNT32 and CNTv start working. In the working state, the FL clock is used as the unit, and every 32 clocks are a working cycle. Counter CNT32 is the working cycle count, and counter CNTv is used to count the number of valid random numbers stored in register REGv in each working cycle. From a theoretical analysis, in one working cycle, the valid random number that can be stored in REGv will not exceed 16 bits, so the width of counter CNTv is 4 bits. At the beginning of each working cycle, counter CNTv will be cleared to 0.

[0046] In each working cycle in the working state, when CNT32 is 0, the random number in register REGv will be loaded into the LFSR register and CASR register as the starting value as a seed. When CNT32 counts to 31, the lower 32-bit data in the LFSR register and CASR register will be synchronized and XORed to generate a set of valid 32-bit data, such as Figure 6 shown.

[0047] When the valid data of the data stream register counting module is not 0 and the state value of the counting state generator is 31, the counting state generator generates an indication signal RNG_RDY to indicate whether the true random number generator generates a valid random number in the calculation cycle. The valid data of the data stream register counting module is not 0, which means that the counter CNTv is not 0, that is, in one working cycle, there is at least one valid random number stored in the register REGv after the de-correlation process. If there is no valid random number stored in the register REGv after the de-correlation process in one working cycle, the RNG_RDY signal will not change to 1, indicating that no random number is generated in the current working cycle and the system must wait.

[0048] At the beginning of each working cycle, the valid random digital streams generated by the first oscillator and the second oscillator are loaded into the LFSR register and CASR register of the post-processing operation as seeds, which serve as a new starting point for the operation.

[0049] The 32-bit valid data of the de-associated sequential shift stored in register REGv is divided into two parts: the upper 16 bits and the lower 16 bits. They are XORed with the lower 16 bits of the LFSR and CASR registers respectively and then loaded into the lower 16 bits of the two registers. After 31 rounds of calculation, the LFSR and CASR registers take the lower 32 bits of data for XOR operation to generate the final output data.

[0050] According to the above analysis, in each working cycle, the true random number loaded into the LFSR and CASR registers is at most 16 bits and at least 1 bit, and finally 32 bits of random number output data will be generated.

[0051] The continuous loading of seeds also interrupts the linear operation process of the two shift registers LFSR and CASR, such as Figure 7 shown.

[0052] In actual tests, the true random number generator using power supply noise amplification outputs a continuous, stable and high-speed data stream.

[0053] When testing the quality of random numbers, there are two mainstream random number statistical analysis tools currently used internationally: DIEHARD and NIST STS. DIEHARD is a widely used software testing tool for analyzing the quality of random numbers developed by the University of Florida. The DIEHARD test includes 12 test items. NIST STS is a set of random number quality testing tools released by the National Institute of Standards and Technology (NIST). NIST STS includes 15 test items. The analysis results show that the random numbers generated by this TRNG module can pass the tests of both DIEHARD and NIST STS.

Claims

1. A true random number generator using power supply noise amplification, comprising: Used to generate high frequency signal F H The first oscillator is used to generate a low frequency signal F L A second oscillator; A data sampling and de-correlation module adapted to be connected to the first oscillator and the second oscillator, the data sampling and de-correlation module is used to generate a low-frequency signal F L is the clock, high frequency signal F H Form valid code stream data for the data end; A data stream register counting module adapted to be connected to the de-correlation module, the data stream register counting module being used to store valid code stream data and count the number of bits of valid code stream data stored in the data stream register counting module in each working cycle; The data post-processing module is adapted to be connected to the data stream register counting module, and the data post-processing module is used to generate a low-frequency signal F L and high frequency signal F H To drive the effective code stream data REG V The initial random number is subjected to a shift operation and then an XOR operation to form output data; The synchronizer connected to the data post-processing module is used to synchronize the output data with the system clock domain F S Synchronously generate random numbers; The counting state generator uses a low frequency signal F L It is a clock unit and counts the working cycle; The invention is characterized in that the second oscillator comprises a ring voltage controlled oscillator, and the bias voltage of the ring voltage controlled oscillator is generated by a noise source.

2. The true random number generator using power supply noise amplification as claimed in claim 1, characterized in that: The first oscillator is 100MH Z High-speed ring oscillator.

3. The true random number generator using power supply noise amplification as claimed in claim 1, characterized in that: The noise source includes an operational amplifier A, the non-inverting input terminal of the operational amplifier A is connected to one end of the resistor R4 and the resistor R5 respectively, the other end of the resistor R4 inputs the external audio signal, and the other end of the resistor R5 is grounded; the inverting input terminal of the operational amplifier A is grounded through the resistor R3; the output terminal of the operational amplifier A is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the inverting input terminal of the operational amplifier A, and the output terminal of the operational amplifier A forms the bias voltage.

4. The true random number generator using power supply noise amplification as claimed in claim 1, characterized in that: The de-correlation module comprises a D-type trigger and a de-correlation circuit. The D-type trigger is connected to the first oscillator and the second oscillator. The D-type trigger is used to generate a low-frequency signal F L is the clock, high frequency signal F H The D-type trigger is connected to the de-correlation circuit, and the correlation circuit is used to obtain the original data stream by sampling the low-frequency signal F L The clock is used to perform de-correlation processing on the original data stream to obtain the effective code stream data.

5. The true random number generator using power supply noise amplification as claimed in claim 4, characterized in that: The decorrelation circuit is a von Neumann type decorrelation module.

6. The true random number generator using power supply noise amplification as claimed in claim 1, characterized in that: The data post-processing module comprises an XOR operator 1, an XOR operator 2, an LFSR register, a CASR register, a data selection synchronizer 1, a data selection synchronizer 2 and an XOR operator 3; the LFSR register is connected to the LFSR register by a high-frequency signal F H As a driver to generate low 16-bit data, the XOR operator 1 is connected to the data stream register counting module and the LFSR register. The XOR operator 1 reads the high 16-bit data in the effective code stream data bit and receives the low 16-bit data generated by the LFSR register, performs XOR operation, and then sends it to the LFSR register to form low 32-bit data; the CASR register is connected to the data stream register counting module and the LFSR register through the low frequency signal F L As a driver to generate low 16-bit data, the XOR operator 2 is connected to the data stream register counting module and the CASR register, the XOR operator 2 reads the low 16-bit data in the effective code stream data bit number and receives the low 16-bit data generated by the CASR register, and then sends it to the CASR register to form low 32-bit data; the data selection synchronizer 1 is connected to the LFSR register, the data selection synchronizer 2 is connected to the CASR register, and the data selection synchronizer 1 and the data selection synchronizer 2 receive the low frequency signal F L As a clock signal, it is used to synchronize the lower 32-bit data in the LFSR register and the CASR register; the XOR operator three is respectively connected to the selection synchronizer one and the selection synchronizer two, and after 31 rounds of operation of the LFSR register and the CASR register, the data selection synchronizer one and the data selection synchronizer two respectively read the lower 32-bit data in the LFSR register and the CASR register and send them to the XOR operator three for XOR operation to form the output data.

7. The true random number generator using power supply noise amplification as claimed in claim 1, characterized in that: The counting state generator generates an indication signal RNG_RDY when the valid data of the data stream register counting module is not 0 and the state value of the counting state generator is 31, which is used to indicate whether the true random number generator generates a valid random number in the calculation cycle.

Images