A three-dimensional sonar beam data deconvolution method and device based on FPGA

Abstract

The application discloses a three-dimensional sonar beam data deconvolution device and method based on FPGA, which comprises the following steps: carrying out two-dimensional FFT processing on a point spread function PSF to transform the point spread function PSF into a function PSF_FFT in a frequency domain; carrying out deconvolution iterative calculation on multi-layer beam intensity data by using parallel RL iterative operators containing a plurality of parallel paths, and performing a plurality of rounds of RL algorithms by each RL iterative operator; storing the function PSF_FTT by using a single-port RAM, storing original three-dimensional sonar beam intensity data by using a double-port RAM through one port, and accessing the parallel RL iterative operators through the other port to realize the cache of deconvolution calculation result data and the cross-clock data transmission; and controlling the parallel deconvolution calculation of the deconvolution calculation module and the parallel access of the data cache module, so that the deconvolution calculation can be completed on the FPGA, the limitation of the array physical aperture can be broken through, the angle resolution of the system can be improved, and the imaging quality can be optimized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of measurement, and particularly relates to a three-dimensional sonar beam data deconvolution method and device based on FPGA. BACKGROUND

[0002] Sonar is a widely used underwater detection equipment. According to the imaging dimension, sonar can be divided into two-dimensional imaging sonar and three-dimensional imaging sonar. Three-dimensional sonar can obtain a three-dimensional image of an underwater detection target, but requires more transducers and has higher requirements for signal processing capability compared with two-dimensional imaging sonar.

[0003] The resolution of a sonar system is a key indicator for measuring the imaging performance of the sonar system and the application efficiency of a sonar image. In the case of not changing the hardware of the sonar system, the resolution of the sonar system can be improved through mathematical methods. In view of the problem of low resolution of conventional beamforming (CBF) results, a series of researches have been carried out at home and abroad, and various algorithms have been proposed to reduce the main lobe beam width and suppress the side lobe intensity, so as to improve the resolution of the beam results and improve the signal-to-noise ratio. In 1969, Capon proposed the MVDR (Minimum Variance Distortionless Response) method. The design principle of the MVDR beamforming is to minimize the output power of the array under the premise that the response in the expected direction is not distorted. The MVDR calculates the weighting vector of the array through the covariance matrix of the array received signal to realize adaptive beamforming. Since the MVDR was proposed, a batch of high-resolution spatial spectrum estimation methods have been proposed, such as the MUSIC (Multiple Signal Classsifacation) method, the ESPRIT (Estimating Signal Parameter via Rotational Invariance Techniques) method, etc. These high-resolution spectrum estimation methods are based on the covariance matrix of the base array received data, and perform feature decomposition or singular value decomposition, etc., to divide the data into signal subspace and noise subspace. However, these algorithms have serious performance decline in the case of low signal-to-noise ratio or mismatch of the base array model, and have less robustness than the CBF. In addition, a certain number of data shots are required to complete the estimation of the covariance matrix, and the problem of "shot failure" will occur when facing fast-moving targets.

[0004] High resolution imaging technology based on deconvolution is widely used in image processing and array signal processing. In a sonar system, the beam pattern calculated from echo signals can be regarded as the convolution of the spatial distribution function of the target and the beam directivity function. Deconvolution beam forming performs deconvolution operation on the CBF result to restore the original signal distribution, which can effectively improve the resolution of the sonar system, and has the advantages of CBF, such as high robustness and less snapshots required. By using the deconvolution beam forming technology, the sonar system can realize finer target imaging while maintaining good robustness and fast imaging characteristics, providing important technical support for marine exploration, target identification and other applications. SUMMARY

[0005] In view of the above, the purpose of the present application is to provide a three-dimensional sonar beam data deconvolution method and device based on FPGA, which combines a frequency domain beam forming algorithm and completes deconvolution calculation on FPGA, can break through the limitation of array physical aperture, improve the angular resolution of the system, and optimize the imaging quality.

[0006] To achieve the above-mentioned purpose of the application, the embodiment provides a three-dimensional sonar beam data deconvolution device based on FPGA, characterized in that it comprises a pre-processing module, a data cache module, a deconvolution calculation module and a control module designed based on FPGA.

[0007] The pre-processing module is used for performing two-dimensional FFT processing on the point spread function PSF to transform it into the frequency domain to obtain the function PSF_FFT.

[0008] The deconvolution calculation module comprises a plurality of parallel RL iteration operators in parallel for performing deconvolution iteration calculation on multi-layer beam intensity data, wherein each RL iteration operator performs a plurality of rounds of RL algorithm by iteration, and in each round of RL algorithm, deconvolution calculation based on input data and the function PSF_FFT is performed to obtain single-round deconvolution calculation result data, which is used as input data for the next round of RL algorithm.

[0009] The data cache module comprises a single-port RAM and a dual-port RAM, wherein the single-port RAM stores the function PSF_FFT, the dual-port RAM caches the original three-dimensional sonar beam intensity data through one port, and accesses the parallel RL iteration operators in parallel through the other port to realize the caching of deconvolution calculation result data and the cross-clock data transmission.

[0010] The control module is used for controlling the parallel deconvolution calculation of the deconvolution calculation module and the parallel access of the data cache module to the deconvolution calculation module.

[0011] Preferably, each RL iteration operator comprises an FFT calculation submodule, a complex multiplication submodule and a divider.

[0012] The FFT calculation submodule is configured to perform two-dimensional FFT on the input data Q and the matrix Q2 to obtain data Q_FFT and Q2_FFT, and to perform two-dimensional IFFT calculation on the matrix Q1 and Q3 to obtain data Q1_IFFT and Q3_IFFT.

[0013] The complex multiplication submodule is configured to perform complex multiplication on the PSF_FFT and the Q_FFT to obtain the matrix Q1, to perform complex multiplication on the PSF_FFT and the Q2_FFT to obtain the matrix Q3, and to perform complex multiplication on the input data Q and the data Q3_IFFT to obtain the matrix Q4 as the single-round deconvolution calculation result data.

[0014] The divider is configured to divide the original three-dimensional sonar beam intensity data R by the data Q1_IFFT to obtain the matrix Q2.

[0015] In the first round of iteration, the input data Q is the original three-dimensional sonar beam intensity data, and in other rounds, the input data Q is the deconvolution calculation result data of the previous round.

[0016] Preferably, the FFT calculation submodule is configured in an FFT mode or an IFFT mode.

[0017] When performing FFT calculation in the FFT mode, the method specifically includes: after zero-padding the data to be subjected to FFT to a fixed size, the padded data is directly subjected to horizontal-direction FFT calculation by using an AXI_Stream interface and a fast Fourier transform IP core provided by Xilinx, the obtained FFT calculation result data is subjected to data caching by using a dual-port RAM and transposition to obtain transposition result, and the transposition result is input again to the FFT calculation submodule to perform vertical-direction FFT calculation to obtain final FFT calculation result data.

[0018] When performing IFFT calculation in the IFFT mode, the method specifically includes: after zero-padding the data to be subjected to IFFT to a fixed size, the padded data is directly subjected to horizontal-direction IFFT calculation by using an AXI_Stream interface and a fast Fourier transform IP core provided by Xilinx, the obtained IFFT calculation result data is subjected to data caching by using a dual-port RAM and transposition to obtain transposition result, and the transposition result is input again to the FFT calculation submodule to perform vertical-direction IFFT calculation to obtain final IFFT calculation result data.

[0019] Preferably, in the divider, the division calculation of the input data Q and the data Q1_IFFT is implemented by using a Divider Genrator IP core provided by Xilinx.

[0020] Preferably, the FFT calculation sub-module in each RL iteration operator is controlled to utilize the idle clock cycle of the pipeline to calculate the data requiring FFT calculation in the iteration result of the other layer beam data corresponding to the other RL iteration operator, including:

[0021] The calculation delay of the FFT calculation sub-module for N-point FFT is T, and M is the maximum integer of T / N result. The FFT calculation sub-module waits to receive the other M layer data requiring FFT calculation before starting calculation, and the waiting period of the FFT calculation sub-module is filled by continuously inputting M layer data.

[0022] Preferably, the deconvolution calculation module further comprises a multiplexer and a demultiplexer.

[0023] The multiplexer is used to divide the input real-time original three-dimensional sonar beam intensity data into multiple layer beam intensity data and input into the parallel multi-path RL iteration operator for calculation.

[0024] The demultiplexer is used to output the deconvolution calculation result data output by the multi-path RL iteration operator after being aggregated.

[0025] To achieve the above-mentioned purposes, the embodiment of the application further provides a three-dimensional sonar beam data deconvolution method based on FPGA, comprising the following steps:

[0026] S1, using a pre-processing module to perform two-dimensional FFT processing on a point spread function PSF to transform it into a frequency domain to obtain a function PSF_FFT, and caching it in a single-port RAM included in a data cache module;

[0027] S2, controlled by a control module, using a multi-path parallel RL iteration operator included in a deconvolution calculation module to perform deconvolution iteration calculation on multiple layer beam intensity data based on input data and the function PSF_FFT, and caching the deconvolution calculation result data in a dual-port RAM included in a data cache module.

[0028] Preferably, in S2, the deconvolution calculation process performed by each RL iteration operator comprises:

[0029] S21, using an FFT calculation sub-module to perform two-dimensional FFT calculation on the input data Q to obtain data Q_FFT;

[0030] S22, using a complex multiplication sub-module to perform complex multiplication on the function PSF_FFT and the data Q_FFT to obtain a matrix Q1;

[0031] S23, using an FFT calculation sub-module to perform two-dimensional IFFT calculation on the matrix Q1 to obtain data Q1_IFFT;

[0032] S24, divide the original three-dimensional sonar beam intensity data R by the data Q1_IFFT using a divider to obtain a matrix Q2;

[0033] S25, perform two-dimensional FFT calculation on the matrix Q2 using an FFT calculation submodule to obtain data Q2_FFT;

[0034] S26, perform complex multiplication on the function PSF_FFT and the data Q2_FFT using a complex multiplication submodule to obtain a matrix Q3;

[0035] S27, perform two-dimensional IFFT calculation on the matrix Q3 using an FFT calculation submodule to obtain data Q3_IFFT;

[0036] S28, perform complex multiplication on the input data Q and the data Q3_FFT to obtain a matrix Q4 as the single-round deconvolution calculation result data;

[0037] In the first round of iteration, the input data Q is the original three-dimensional sonar beam intensity data, and the input data Q in other rounds is the deconvolution calculation result data of the previous round.

[0038] Preferably, in S2, S23 and S27 need to extract the IFFT result with a matrix size of half of the original size, and under the condition of ignoring the output delay of S24 and S28, perform the next FFT operation after zero padding; the IFFT result with a matrix size of half of the original size is the latter half of the IFFT output sequence, and the next FFT calculation starts from the latter half of the IFFT output sequence, and the input pipeline of the FFT calculation submodule will produce an idle clock period in the former half of the IFFT output sequence, and the matrix is zero-padded by using the former half of the IFFT output.

[0039] Compared with the prior art, the present application has at least the following beneficial effects:

[0040] The FPGA-based three-dimensional sonar beam data deconvolution method and device provided by the present application adapt to underwater operation environment, can efficiently complete deconvolution calculation on FPGA, can effectively improve beam main lobe width, suppress sidelobe level, suppress multi-direction echo interference, and break through the limitation of physical aperture of receiving array, under the premise of maintaining imaging robustness. Through the present application, narrower receiving beam can be obtained compared with conventional beam forming, the angle resolution of the system is improved, the imaging quality is optimized, which is helpful for realizing three-dimensional high-precision imaging of underwater targets and fine detection of underwater targets, and has good engineering application prospect and popularization value. The present application also uses Fourier transform and inverse transform to calculate convolution and cross-correlation process, replaces time domain multiplication and accumulation operation, reduces algorithm operation time, and further guarantees the operation real-time of the algorithm and the engineering application feasibility. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can be obtained from these drawings without any creative effort.

[0042] Figure 1 is a structural schematic diagram of the FPGA-based three-dimensional sonar beam data deconvolution device provided by the embodiment;

[0043] Figure 2 is a structural schematic diagram of the deconvolution calculation module provided by the embodiment;

[0044] Figure 3 is a comparison of the deconvolution iteration calculation of the parallel structure and the serial structure based on the RL iteration operator provided by the embodiment;

[0045] Figure 4 is a structure of the RL iteration operator and an iteration calculation flowchart provided by the embodiment;

[0046] Figure 5 is a control state machine schematic diagram of the FFT calculation submodule provided by the embodiment. DETAILED DESCRIPTION

[0047] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can be obtained from these drawings without any creative effort.

[0048] The inventive concept of the present application is to provide a FPGA-based three-dimensional sonar beam data deconvolution method and device, which uses Fourier transform and inverse transform to calculate convolution and cross-correlation process, replaces time domain multiplication and accumulation operation, and reduces algorithm operation time; uses the pipeline of FPGA to implement parallel data processing, effectively improves the efficiency of data processing, improves the system throughput, fully utilizes the advantages of FPGA in the field of high-performance computing and signal processing, improves the angle resolution of the three-dimensional sonar system, and helps to realize three-dimensional high-precision imaging of underwater targets.

[0049] As Figure 1As shown, the FPGA-based three-dimensional sonar beam data deconvolution device provided by the embodiment includes a pre-processing module, a deconvolution calculation module, a data cache module, and a control module designed based on FPGA, wherein the pre-processing module is configured to perform two-dimensional FFT processing on a point spread function PSF to transform the PSF into a frequency domain to obtain a function PSF_FFT. The deconvolution calculation module includes multiple parallel RL iteration operators in parallel for performing deconvolution iteration calculation on multi-layer beam intensity data in parallel, wherein each RL iteration operator performs multiple rounds of RL algorithm by iteration, and in each round of RL algorithm, deconvolution calculation based on input data and the function PSF_FFT is performed to obtain single-round deconvolution calculation result data, which is used as input data for the next round of RL algorithm. The data cache module includes a single-port RAM and a dual-port RAM, wherein the single-port RAM stores the function PSF_FFT, and the dual-port RAM caches original three-dimensional sonar beam intensity data through one port and accesses the parallel RL iteration operators in parallel through the other port to realize cache and cross-clock data transmission of the deconvolution calculation result data, thereby ensuring correctness and stability of data transmission. The control module is configured to control parallel deconvolution calculation of the deconvolution calculation module and parallel access of the data cache module to the deconvolution calculation module.

[0050] In the above device, the two-dimensional point spread function PSF is converted into a frequency domain to obtain a function PSF_FFT through two-dimensional FFT by the pre-processing module, which calculates and initializes the ROM in advance, reduces the occupation of DSP resources, and simplifies the calculation. In subsequent FFT calculation and IFFT calculation, FFT and IFFT are performed based on the function PSF_FFT to reduce the calculation time and enhance the real-time performance of the imaging algorithm.

[0051] FPGA, as a programmable hardware platform, has the characteristics of flexibility and strong customizability, and plays an important role in this parallel data processing scheme. Through reasonable design and optimization, the advantages of FPGA in hardware acceleration and parallel computing can be fully utilized to provide high-performance data processing capability for the system and meet the requirements of real-time performance and high throughput.

[0052] In the above device, the parallel deconvolution calculation is completed by using a parallel structure, which supports fine-grained iteration number adjustment. In addition, the beam result is required in each iteration calculation, and the parallel structure is easier to implement. Multiple iteration calculations can be performed simultaneously, each calculation unit can independently process the deconvolution operation, and the beam result can be used immediately in each iteration, thereby accelerating the overall calculation speed.

[0053] As shown in FIG. 6, the FPGA-based three-dimensional sonar beam data deconvolution device provided by the embodiment includes a pre-processing module, a deconvolution calculation module, a data cache module, and a control module designed based on FPGA, wherein the pre-processing module is configured to perform two-dimensional FFT processing on a point spread function PSF to transform the PSF into a frequency domain to obtain a function PSF_FFT. The deconvolution calculation module includes multiple parallel RL iteration operators in parallel for performing deconvolution iteration calculation on multi-layer beam intensity data in parallel, wherein each RL iteration operator performs multiple rounds of RL algorithm by iteration, and in each round of RL algorithm, deconvolution calculation based on input data and the function PSF_FFT is performed to obtain single-round deconvolution calculation result data, which is used as input data for the next round of RL algorithm. The data cache module includes a single-port RAM and a dual-port RAM, wherein the single-port RAM stores the function PSF_FFT, and the dual-port RAM caches original three-dimensional sonar beam intensity data through one port and accesses the parallel RL iteration operators in parallel through the other port to realize cache and cross-clock data transmission of the deconvolution calculation result data, thereby ensuring correctness and stability of data transmission. The control module is configured to control parallel deconvolution calculation of the deconvolution calculation module and parallel access of the data cache module to the deconvolution calculation module. Figure 2As shown, the deconvolution calculation module includes a plurality of parallel RL iteration operators in parallel, a multi-path distributor and a multi-path selector, wherein the multi-path distributor is used to divide the input real-time original three-dimensional sonar beam intensity data into a plurality of layers of beam intensity data and input into the parallel multi-path RL iteration operators for calculation. The multi-path selector (MUX) is used to output the deconvolution calculation result data after the multi-path RL iteration operator outputs are aggregated.

[0054] In the deconvolution calculation module, parallel deconvolution calculation is completed by using a parallel structure. The reasons are as follows: there are two implementation methods for parallel deconvolution iteration calculation: a serial structure and a parallel structure. As shown in Figure 3 As shown, the serial structure connects a plurality of RL iteration operators for deconvolution in series, connects the output of one RL iteration operator to the input of another RL iteration operator, and completes N iterations of one layer of beam data by N deconvolution operators; the parallel structure connects a plurality of RL iteration operators in parallel, connects the output of each RL iteration operator to its own input, and completes N iterations of one layer of beam data by one RL iteration operator.

[0055] According to the area for speed idea, a plurality of RL iteration operators in a parallel structure are used to perform parallel deconvolution iteration calculation on a plurality of layers of beam intensity data. After the parallel structure receives one layer of beam intensity data, the multi-path distributor divides the layer of beam intensity data into N iteration results calculated by one RL iteration operator. N iteration operators output N deconvolution calculation results. After the serial structure receives one layer of beam intensity data, it enters an iteration pipeline composed of N RL iteration operators. If the number of iterations N is configured to be greater than N, the iteration result of the last iteration operator is sent to the first iteration operator again. After N iterations are completed, the deconvolution calculation result is output by the last iteration operator. The granularity of iteration number adjustment is 1 for the parallel structure, and the granularity of iteration number adjustment is N for the serial structure. The parallel structure supports fine-grained iteration number adjustment. In addition, the beam result is used in each iteration calculation, and the parallel structure is easier to implement. k k k k

[0056] In the RL iteration operator, the specific implementation method of the RL algorithm is adjusted to be suitable for FPGA architecture implementation. The convolution and correlation operation is converted into frequency domain multiplication, the RL algorithm is implemented based on FFT, so as to speed up the iteration calculation and reduce the delay of calculation.

[0057] The three-dimensional acoustic beam forming process can be equivalent to a convolution process, as shown in equation (1):

[0058]

[0059] ​​​​Among them, y CBF For conventional beamforming output, x is the array element signal input, h is the point spread function, and n is the system noise. This is the convolution operator.

[0060] The classic RL algorithm is represented as shown in equation (2):

[0061]

[0062] in, represents the estimation result of the k-th deconvolution, · represents scalar multiplication, and * represents cross-correlation operation. Known as the iterative kernel, the main computational burden of classic RL algorithms lies in the convolution between the iterative kernel and the point spread function, which requires temporal convolution to complete the calculation. Furthermore, the algorithm has a slow convergence speed, requiring numerous iterations to achieve the desired deconvolution effect, thus limiting the real-time performance of imaging algorithms.

[0063] The proposed FPGA-based deconvolution method for three-dimensional sonar beam data accelerates iterative computation by converting convolution and correlation operations into frequency domain multiplication and implementing the RL algorithm based on FFT. Specifically, the formula can be expressed as:

[0064]

[0065] make The values ​​of k and j are in the range of 0 ≤ k ≤ N. b -1, 0≤j≤N b -1, there is -N b +1≤kj≤N b -1. Calculate R as follows: n [k]:

[0066] First, extract -N b +1≤k≤N b B between -1 p [k]:

[0067]

[0068] Here at B' p Add a 0 to the end of [k′] so that B′ p The length of [k′] is 2N. b This is to facilitate computation using FFT. For B′ p [k′] and S n Convolution is performed on [k′] to obtain R′ n [k′]:

[0069] R′ nl [k′]=B′ p[k′]*S n [k′], 0 ≤ k′ ≤ 3N b -2 (5)

[0070] R n [k] is R′ nl [k′] in the interval [N] b -1,2N b Values ​​on [-2]:

[0071] R n [k]=R′ nl [k+N b -1], 0≤k≤N b -1 (6)

[0072] Since only R needs to be calculated n [k], no need to calculate R′ nl The complete result for [k′]. For S n [k′] supplement N b A zero point, for B′ p [k′] and S n [k′] do 2N b Point convolution operation:

[0073]

[0074] When N b -1≤k′≤2N b When -2, we have R′ nc [k′]=R′ nl [k′]. This can be used with respect to B′. p [k′] and S n [k′] is 2N b Pointwise FFT and multiplication in the frequency domain, followed by IFFT to obtain R. n [k]. R n [k] Take the Nth IFFT result b -1 point to the 2Nth b -2 points. Meanwhile, due to B p [kj]=B p [jk], for the formula A similar calculation method can also be used.

[0075] As the above analysis shows, the main operations used in the RL iterative algorithm are FFT calculation, complex multiplication, and division. FFT and division can be directly implemented using IP cores provided by Xilinx. Specifically, an RL iterative operator is designed with an FFT IP core, a floating-point divider, and a floating-point complex multiplier as its core. Within one iteration cycle, the structure and iterative calculation process of the RL iterative operator are as follows: Figure 4As shown, each RL iteration operator includes an FFT computation submodule, a complex multiplication submodule, and a divider.

[0076] The FFT calculation submodule is used to process the input data Q(S) n-1 Performing a two-dimensional FFT on the matrix Q2(q) yields the data Q_FFT. and Q2_FFT(H q It is also used for matrix Q1 and Q3(H c The data Q1_IFFT(R) is obtained by performing a two-dimensional IFFT calculation. n The complex multiplication submodule is used to convert PSF_FFT to Q3_IFFT(c). and Q_FFT Complex multiplication yields matrix Q1 It is also used to convert PSF_FFT and Q2_FFT(H q Complex multiplication yields matrix Q3(H) c It is also used to process input data Q(S) n-1 The matrix Q4(S) is obtained by performing complex multiplication with the data Q3_IFFT(c). n The original three-dimensional sonar beam intensity data R(R) is used as the result of a single-round deconvolution calculation; the divider is used to combine the original three-dimensional sonar beam intensity data R(R) with the data Q1_IFFT(R). n The matrix Q2(q) is obtained by dividing the two; where Q is the original three-dimensional sonar beam intensity data in the first iteration, and Q is the deconvolution calculation result data in the previous iteration in other iterations, and n represents the iteration round.

[0077] Discrete Fourier Transform of the Directionality Function Required in RL Iterative Operators The beam intensity is a known fixed value and can be stored in ROM. During the first iteration, the output beam intensity result is stored in RAM for use in subsequent iterations. Simultaneously, the beam intensity result is used as the initial value for the iteration calculation and written into the iteration result cache RAM, at which point the FFT calculation begins.

[0078] The FFT calculation submodule can be configured to either FFT mode or IFFT mode as needed.

[0079] When in FFT mode, FFT calculation is performed, specifically including: padding the data to be FFTed with zeros to a fixed size, using the AXI_Stream interface to directly use the Fast Fourier Transform IP core provided by Xilinx to perform FFT calculation in the horizontal direction, caching the FFT calculation result data in dual-port RAM and transposing it to obtain the transposed result, and then inputting the transposed result back into the FFT calculation submodule to perform FFT calculation in the vertical direction to obtain the final FFT calculation result data;

[0080] When in IFFT mode, IFFT calculation is performed, specifically including: padding the data to be IFFTed with zeros to a fixed size, using the AXI_Stream interface to directly implement the horizontal IFFT calculation using the Fast Fourier Transform IP core provided by Xilinx, caching the obtained IFFT calculation result data in dual-port RAM and then transposing it to obtain the transposed result, which is then input into the FFT calculation submodule to perform the vertical IFFT calculation to obtain the final IFFT calculation result data.

[0081] Figure 4 The operations represented by each label are shown in the table as the calculation steps of the RL iteration operator:

[0082] Table 1

[0083]

[0084]

[0085] To improve the processing capability of RL iterative operators, it is necessary to reduce the output latency of each iteration. The FFT computation submodule has a relatively large output latency, and in RL iterative computation, there exists a data path where the output of the FFT computation submodule is processed and then used as its input. This feedback data path significantly increases the output latency of the RL iterative operator. Therefore, filling the idle clock cycles of the FFT computation submodule's input pipeline and improving its data throughput is a key focus in designing RL iterative operators. To address these issues, the following optimization methods are proposed:

[0086] Method 1: The FFT calculation submodule has a computation delay of T for completing an N-point FFT. If the FFT calculation submodule needs to use the output result of the previous calculation, a waiting period needs to be inserted. The FFT calculation submodule in each RL iteration operator can be controlled to utilize the pipeline's idle clock cycle to calculate the data that needs FFT calculation in the iteration results of other layers of beam data corresponding to other RL iteration operators. Let the largest integer of the T / N result be M. The FFT calculation submodule waits to receive the data that needs FFT calculation from other M layers before starting the calculation. The waiting period of the FFT calculation submodule is filled by continuously inputting M layers of data. Although this method increases latency, it can improve the throughput of the FFT calculation submodule. Since the RL iteration operator calculates M layers of beam data in one iteration cycle, M copies of RAM are also needed to cache beam strength and iteration results.

[0087] Method 2: Steps (3) and (7) in Table 1 require extracting the IFFT result with a matrix size half that of the original size (e.g., 32×32). Ignoring the output delay of steps (4) and (8), the next FFT operation is performed after zero padding. The IFFT result with a matrix size half that of the original size (e.g., 32×32) is the second half of the IFFT output sequence. The next FFT calculation begins in the second half of the IFFT output sequence. In the first half of the IFFT output sequence, the input pipeline of the FFT calculation submodule will generate an idle clock cycle. The matrix zero padding is achieved by using the first half of the IFFT output.

[0088] Specifically, the RL iterative operator controls the iterative computation process through a state machine. In different states, the algorithm flow is controlled by adjusting the input data and enabling functions of each module. The state transition diagram is as follows: Figure 5 As shown.

[0089] The meanings of each state in the FFT-calculated control state machine are as follows:

[0090] RL_IDLE state: The default state after reset, indicating that the device is currently idle. Upon receiving a start signal, it transitions to the RL_BEAM state to begin calculation.

[0091] RL_BEAM state: Used for data retrieval during the first iteration. The original beam data Q is stored in the dual-port RAM. After storage is complete, the system jumps to the RL_FFT state.

[0092] RL_FFT state: Used for calculation step (1), configuring the FFT calculation submodule to FFT working mode. The first time, the original beam data Q of size 32×32 is retrieved, padded with zeros to a size of 64×64, and then entered into the FFT calculation submodule. The calculation will output the transpose of the current matrix's one-dimensional FFT, and then the transpose of the one-dimensional FFT will be re-input into the FFT calculation submodule, outputting the current matrix's two-dimensional FFT result Q_FFT. After the FFT calculation submodule completes the two-dimensional FFT calculation of the current matrix, it jumps to the RL_MUL1 state.

[0093] RL_MUL1 state: used for calculation step (2), read the point spread function PSF_FFT calculated by two-dimensional FFT in ROM, and input it together with the two-dimensional FFT result Q_FFT of the original matrix into the complex multiplication module for calculation, call the Multipler IP core for calculation, obtain Q1, and jump to RL_IFFT1 state after the calculation is completed.

[0094] RL_IFFT1 state: Used for calculation step (3), configuring the FFT calculation submodule to IFFT mode. The input for each IFFT calculation is the output of the floating-point complex multiplier. The Q1 data is padded with zeros to a size of 64×64 and then entered into the FFT calculation submodule. The calculation will output the transpose of the one-dimensional IFFT of the current matrix, and then the transpose of the one-dimensional IFFT will be re-input into the FFT calculation submodule, which will output the two-dimensional FFT result Q1_IFFT of the current matrix. After the FFT calculation submodule completes the two-dimensional IFFT calculation of the current matrix, it jumps to the RL_DIV state.

[0095] RL_DIV state: Used for calculating step (4), the original beam result Q is used as the dividend, the output of the FFT calculation submodule is used as the divisor of the floating-point divider, the Divider Generator IP core is called, and the floating-point divider is used for calculation to obtain the result Q2. When the data is completed, it jumps to the RL_FFT2 state.

[0096] RL_FFT2 state: Used for calculation step (5), configuring the FFT calculation submodule to FFT working mode. The output Q2 of the floating-point divider is used as the input to the FFT calculation submodule. After padding with zeros to a size of 64×64, the module enters the FFT calculation submodule. The calculation outputs the transpose of the one-dimensional FFT of the current matrix. This transpose is then re-inputted into the FFT calculation submodule, which outputs the two-dimensional FFT result Q2_FFT of the current matrix. After the FFT calculation submodule completes the two-dimensional FFT calculation of the current matrix, it jumps to the RL_MUL3 state.

[0097] RL_MUL3 state: Used for calculation step (6), read the point spread function PSF_FFT calculated by two-dimensional FFT in ROM, and input it together with Q2_FFT into the complex multiplication module for calculation, call the Multipler IP core for calculation, and obtain Q3. After the calculation is completed, jump to RL_IFFT3 state.

[0098] RL_IFFT3 state: Used for calculation step (7), configuring the FFT calculation submodule to IFFT mode. The input for each IFFT calculation is the output of the floating-point complex multiplier. The Q3 data is padded with zeros to a size of 64×64 and then entered into the FFT calculation submodule. The calculation will output the transpose of the one-dimensional IFFT of the current matrix, and then the transpose of the one-dimensional IFFT will be re-input into the FFT calculation submodule, which will output the two-dimensional FFT result Q3_IFFT of the current matrix. After the FFT calculation submodule completes the two-dimensional IFFT calculation of the current matrix, it jumps to the RL_MUL4 state.

[0099] RL_MUL4 state: Used for calculating step (8). The initial beam data Q is read from RAM and input into the complex multiplication module along with Q3_IFFT for calculation. The Multipler IP core is called to calculate Q4. After the calculation is completed, if it is the last iteration, it jumps to the RL_IDLE state and outputs the deconvolution calculation result; otherwise, it jumps to RL_FFT to start the next iteration.

[0100] In the control module of the aforementioned device, the specific number of iterations can be dynamically adjusted according to parameter configuration. During the use of 3D sonar, the number of iterations can be configured in real time according to the characteristics of the actual target being detected, sacrificing frame rate for higher angular resolution and better imaging results, thus offering high flexibility.

[0101] In the aforementioned device, the raw beam data is divided into several N×N sub-regions Q for parallel processing. Parallel data processing is implemented using an FPGA-based pipeline, effectively improving data processing efficiency and system throughput, and fully leveraging the advantages of FPGAs in high-performance computing and signal processing. Based on the principle of balancing area and speed, the appropriate number and depth of pipelines are selected.

[0102] Based on the above-mentioned device, a method for deconvolution of three-dimensional sonar beam data based on FPGA is also provided, including the following steps:

[0103] Step 1: The point spread function PSF is transformed into the frequency domain by a two-dimensional FFT using the preprocessing module to obtain the function PSF_FFT. The function is then stored in advance using a single-port ROM to reduce the DSP resource consumption of the FPGA and improve the system performance.

[0104] Step 2: Under the control of the control module, the deconvolution calculation module utilizes multiple parallel parallel RL iterative operators to perform deconvolution iterative calculations on multi-layer beam intensity data based on the input data and the PSF_FFT function. The deconvolution calculation results are cached in the dual-port RAM included in the data cache module. Specifically, one round of calculation performed by each RL iterative operator includes:

[0105] Step 21: Divide the original beam data into N×N (e.g., 32×32) sub-regions Q for parallel processing. Use a dual-port RAM to buffer the data. One port is used to read the original beam data, and the other port is used to access the parallel processing unit, thereby performing data temporary storage and cross-clock data transmission to ensure the correctness and stability of data transmission.

[0106] Step 22: The input data Q is processed using a two-dimensional FFT calculation submodule to obtain the data Q_FFT. This fast Fourier transform reduces computation time and enhances the real-time performance of the imaging algorithm. Specifically, the FFT calculation submodule is configured in FFT mode, and during data padding, a 32×32 matrix is ​​padded with zeros to a size of 64×64.

[0107] Step 23: Use the complex multiplication submodule to perform complex multiplication on the function PSF_FFT and the data Q_FFT to obtain matrix Q1;

[0108] Step 24: Use the FFT calculation submodule to perform a two-dimensional IFFT calculation on matrix Q1 and extract the useful data part to obtain data Q1_IFFT. Specifically, configure the FFT calculation submodule to IFFT mode and perform a two-dimensional IFFT calculation.

[0109] Step 25: Use a divider to divide the original three-dimensional sonar beam intensity data R with the data Q1_IFFT to obtain matrix Q2. Specifically, the division is directly implemented using the Divider Generator IP core provided by Xilinx, simplifying the process.

[0110] Step 26: Perform a two-dimensional FFT calculation on matrix Q2 using the FFT calculation submodule to obtain data Q2_FFT. Specifically, configure the FFT calculation submodule to FFT mode to perform a two-dimensional FFT calculation.

[0111] Step 27: Read the function PSF_FFT from the ROM, and use the complex multiplication submodule to perform complex multiplication on the function PSF_FFT and the data Q2_FFT to obtain matrix Q3;

[0112] Step 28: Use the FFT calculation submodule to perform a two-dimensional IFFT calculation on matrix Q3 and extract the useful data part to obtain data Q3_IFFT. Specifically, configure the FFT calculation submodule to IFFT mode to perform a two-dimensional IFFT calculation.

[0113] Step 29: Perform complex multiplication on the input data Q and the data Q3_FFT to obtain matrix Q4 as the result of a single round of deconvolution calculation.

[0114] The specific embodiments described above illustrate the technical solution and beneficial effects of the present invention in detail. It should be understood that the above description is only the most preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, additions, and equivalent substitutions made within the scope of the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A FPGA-based three-dimensional sonar beam data deconvolution device, characterized in that, It includes a preprocessing module based on FPGA design, a data caching module, a deconvolution calculation module, and a control module; The preprocessing module is used to perform two-dimensional FFT processing on the point spread function PSF to transform it into the frequency domain to obtain the function PSF_FFT; The deconvolution calculation module includes multiple parallel RL iterative operators for performing deconvolution iterative calculations of multi-layer beam intensity data in parallel. Each RL iterative operator performs multiple rounds of RL algorithm. In each round of RL algorithm, deconvolution calculation based on input data and function PSF_FFT is performed to obtain single-round deconvolution calculation result data, which is used as input data for the next round of RL algorithm. The data caching module includes a single-port RAM and a dual-port RAM. The single-port RAM stores the function PSF_FFT, while the dual-port RAM caches the original three-dimensional sonar beam intensity data through one port and accesses the parallel RL iterative operator in parallel through the other port, thereby realizing the caching of deconvolution calculation results and cross-clock data transmission. The control module is used to control the parallel deconvolution calculation of the deconvolution calculation module and the parallel access of the data caching module to the deconvolution calculation module. Each RL iteration operator includes an FFT computation submodule, a complex multiplication submodule, and a divider; The FFT calculation submodule is used to perform a two-dimensional FFT on the input data Q and matrix Q2 to obtain data Q_FFT and Q2_FFT, and is also used to perform a two-dimensional IFFT on matrices Q1 and Q3 to obtain data Q1_IFFT and Q3_IFFT; The complex multiplication submodule is used to perform complex multiplication of PSF_FFT and Q_FFT to obtain matrix Q1, and also to perform complex multiplication of PSF_FFT and Q2_FFT to obtain matrix Q3, and to perform complex multiplication of input data Q and data Q3_IFFT to obtain matrix Q4 as the result data of a single round of deconvolution calculation. The divider is used to divide the original three-dimensional sonar beam intensity data R with the data Q1_IFFT to obtain matrix Q2; In the first iteration, the input data Q is the original three-dimensional sonar beam intensity data, while in other iterations, the input data Q is the deconvolution calculation result data from the previous iteration.

2. The FPGA-based three-dimensional sonar beam data deconvolution device according to claim 1, characterized in that, The FFT calculation submodule is configured to either FFT mode or IFFT mode; When in FFT mode, FFT calculation is performed, specifically including: padding the data to be FFTed with zeros to a fixed size, using the AXI_Stream interface to directly use the Fast Fourier Transform IP core provided by Xilinx to perform FFT calculation in the horizontal direction, caching the FFT calculation result data in dual-port RAM and transposing it to obtain the transposed result, and then inputting the transposed result back into the FFT calculation submodule to perform FFT calculation in the vertical direction to obtain the final FFT calculation result data; When in IFFT mode, IFFT calculation is performed, specifically including: padding the data to be IFFTed with zeros to a fixed size, using the AXI_Stream interface to directly implement the horizontal IFFT calculation using the Fast Fourier Transform IP core provided by Xilinx, caching the obtained IFFT calculation result data in dual-port RAM and then transposing it to obtain the transposed result, which is then input into the FFT calculation submodule to perform the vertical IFFT calculation to obtain the final IFFT calculation result data.

3. The FPGA-based three-dimensional sonar beam data deconvolution device according to claim 1, characterized in that, The divider uses the Divider Generator IP core provided by Xilinx to perform the division calculation between the input data Q and the data Q1_IFFT.

4. The FPGA-based three-dimensional sonar beam data deconvolution device according to claim 1, characterized in that, The FFT calculation submodule in each RL iterative operator is controlled to utilize the pipeline's idle clock cycles to calculate the data requiring FFT calculation in the iteration results of other layer beam data corresponding to other RL iterative operators, including: The delay for the FFT calculation submodule to complete the calculation of the N-point FFT is T. Let M be the maximum integer of the T / N result. The FFT calculation submodule waits to receive data from other M layers that need FFT calculation before starting the calculation. The waiting period of the FFT calculation submodule is filled by continuously inputting data from M layers.

5. The FPGA-based three-dimensional sonar beam data deconvolution device according to claim 1, characterized in that, The deconvolution calculation module also includes a multiplexer and a multiplexer; The multiplexer is used to divide the input real-time raw three-dimensional sonar beam intensity data into multiple layers of beam intensity data and input them into parallel multi-path RL iterative operators for calculation. The multiplexer is used to summarize and output the deconvolution calculation results from multiple RL iterative operators.

6. A method for deconvolution of three-dimensional sonar beam data based on FPGA, characterized in that, The method employs the three-dimensional sonar beam data deconvolution device according to any one of claims 1-5, and includes the following steps: S1, the point spread function PSF is transformed into the frequency domain by two-dimensional FFT using the preprocessing module to obtain the function PSF_FFT, and then cached in the single-port RAM contained in the data cache module; S2, controlled by the control module, uses the multi-parallel parallel RL iterative operator contained in the deconvolution calculation module to perform deconvolution iterative calculation of multi-layer beam intensity data based on input data and the function PSF_FFT, and caches the deconvolution calculation results in the dual-port RAM contained in the data cache module.

7. The FPGA-based three-dimensional sonar beam data deconvolution method according to claim 6, characterized in that, In S2, the deconvolution calculation process performed by each RL iteration operator includes: S21, Use the FFT calculation submodule to perform two-dimensional FFT calculation on the input data Q to obtain data Q_FFT; S22, using the complex multiplication submodule, perform complex multiplication on the function PSF_FFT and the data Q_FFT to obtain matrix Q1; S23, use the FFT calculation submodule to perform two-dimensional IFFT calculation on matrix Q1 to obtain data Q1_IFFT; S24, use a divider to divide the original three-dimensional sonar beam intensity data R with the data Q1_IFFT to obtain matrix Q2; S25, use the FFT calculation submodule to perform a two-dimensional FFT calculation on matrix Q2 to obtain data Q2_FFT; S26, using the complex multiplication submodule, perform complex multiplication on the function PSF_FFT and the data Q2_FFT to obtain matrix Q3; S27, Use the FFT calculation submodule to perform a two-dimensional IFFT calculation on matrix Q3 to obtain data Q3_IFFT; S28, Perform complex multiplication on the input data Q and the data Q3_FFT to obtain matrix Q4 as the result data of a single round of deconvolution calculation; In the first iteration, the input data Q is the original three-dimensional sonar beam intensity data, while in other iterations, the input data Q is the deconvolution calculation result data from the previous iteration.

8. The FPGA-based three-dimensional sonar beam data deconvolution method according to claim 7, characterized in that, In S2, S23 and S27 need to extract the IFFT result with a matrix size half that of the original size. Ignoring the output delays of S24 and S28, the next FFT operation is performed after zero padding. The IFFT result with a matrix size half that of the original size is the second half of the IFFT output sequence. The next FFT calculation starts from the second half of the IFFT output sequence. In the first half of the IFFT output sequence, the input pipeline of the FFT calculation submodule will generate idle clock cycles. The matrix zero padding is achieved by using the first half of the IFFT output.

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