Array substrate and display device

Abstract

The array substrate includes a first sub-pixel having a second conductive layer and an anode layer. The anode layer includes a first anode in the first sub-pixel. The second conductive layer includes a first signal line and a second signal line. The second signal line includes a body extending along a direction substantially parallel to a second direction and a branch connected to the body. The branch is located on the side of the body away from the first signal line along a first direction. The orthographic projection of the first anode onto the substrate at least partially overlaps with the orthographic projection of the first signal line onto the substrate, at least partially overlaps with the orthographic projection of the body onto the substrate, and at least partially overlaps with the orthographic projection of the branch onto the substrate.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor with a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the selected row of a pixel unit is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. The OLED device is then driven to emit light at a corresponding brightness. Summary of the Invention

[0003] On one hand, this disclosure provides an array substrate including a plurality of sub-pixels; wherein the plurality of sub-pixels includes a first sub-pixel; the array substrate further includes a substrate, a second conductive layer located on the substrate, and an anode layer located on a side of the second conductive layer away from the substrate; the anode layer includes a first anode in the first sub-pixel; the second conductive layer includes a first signal line and a second signal line extending in directions substantially parallel to a second direction; the second signal line includes a body extending in a direction substantially parallel to the second direction and a branch connected to the body, the branch being located on a side of the body away from the first signal line in a direction substantially parallel to a first direction, the first direction and the second direction intersecting each other; and the orthographic projection of the first anode on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate, at least partially overlaps with the orthographic projection of the body on the substrate, and at least partially overlaps with the orthographic projection of the branch on the substrate.

[0004] Optionally, the array substrate includes a plurality of first voltage supply lines and a plurality of data lines; wherein the first signal line is one of the plurality of data lines; and the second signal line is one of the plurality of first voltage supply lines; wherein a first adjacent first voltage supply line among the plurality of first voltage supply lines includes a first body and a first branch connected to the first body; the orthographic projection of the first anode on the substrate at least partially overlaps with the orthographic projection of the data line among the plurality of data lines on the substrate; at least partially overlaps with the orthographic projection of the first body on the substrate; and at least partially overlaps with the orthographic projection of the first branch on the substrate; and the portions of the data line, the first body, and the first branch located in the region intersecting with the first anode have a substantially mirror symmetry with respect to a plane perpendicular to and intersecting the first anode.

[0005] Optionally, the branch includes a support portion and one or more connecting portions; the support portion is spaced apart from the main body; the one or more connecting portions connect the support portion to the main body.

[0006] Optionally, the array substrate further includes a first reset signal network and a second reset signal network, and includes a first column pixel driving circuit, a second column pixel driving circuit, and a third column pixel driving circuit that are adjacent to each other; wherein, the first reset signal network includes a plurality of first reset signal lines and a plurality of third reset signal lines interconnected with each other; the second reset signal network includes a plurality of second reset signal lines and a plurality of fourth reset signal lines interconnected with each other; a third reset signal line among the plurality of third reset signal lines exists in the first column pixel driving circuit, and the plurality of third reset signal lines does not exist in the second column pixel driving circuit; a fourth reset signal line among the plurality of fourth reset signal lines exists in the second column pixel driving circuit, and the plurality of fourth reset signal lines does not exist in the first column pixel driving circuit; and the plurality of third reset signal lines and the plurality of fourth reset signal lines do not exist in the third column pixel driving circuit.

[0007] Optionally, the first column pixel driving circuit is configured to drive the first column of sub-pixels of the first color to emit light; the second column pixel driving circuit is configured to drive the second column of sub-pixels of the second color to emit light; the third column pixel driving circuit is configured to drive the third column of sub-pixels of the third color to emit light; and the first color, the second color, and the third color are different colors.

[0008] Optionally, the plurality of first reset signal lines and the plurality of second reset signal lines are located in the same conductive layer; the plurality of third reset signal lines and the plurality of fourth reset signal lines are located in the same layer and on the side of the same conductive layer away from the substrate.

[0009] Optionally, the pixel driving circuit of the array substrate is arranged in K columns including the (3k-2)th column, the (3k-1)th column, and the (3k)th column, where K and k are positive integers, 1≤k≤(K / 3); the third reset signal line of the plurality of third reset signal lines exists in the pixel driving circuit of the (3k-2)th column, and the plurality of third reset signal lines does not exist in the pixel driving circuit of the (3k)th column; the fourth reset signal line of the plurality of fourth reset signal lines exists in the pixel driving circuit of the (3k)th column, and the plurality of fourth reset signal lines does not exist in the pixel driving circuit of the (3k-2)th column; and the plurality of third reset signal lines and the plurality of fourth reset signal lines do not exist in the pixel driving circuit of the (3k-1)th column.

[0010] Optionally, the pixel driving circuit in the second column pixel driving circuit includes a first connecting line, which connects the first electrode of the first reset transistor to the first reset signal line among the plurality of first reset signal lines; the pixel driving circuit in the first column pixel driving circuit includes a second connecting line, which connects the first electrode of the second reset transistor to the second reset signal line among the plurality of second reset signal lines; the pixel driving circuit in the third column pixel driving circuit includes a first connecting line and a second connecting line, where the first connecting line connects the first electrode of the first reset transistor to the first reset signal line among the plurality of first reset signal lines, and the second connecting line connects the first electrode of the second reset transistor to the second reset signal line among the plurality of second reset signal lines; the first column pixel driving circuit does not include a first connecting line, and the third reset signal line connects the first electrode of the first reset transistor to the first reset signal line among the plurality of first reset signal lines; and the second column pixel driving circuit does not include a second connecting line, and the fourth reset signal line connects the first electrode of the second reset transistor to the second reset signal line among the plurality of second reset signal lines.

[0011] Optionally, each pixel driving circuit includes a first connection line and a second connection line. The first connection line connects the first electrode of the first reset transistor to the first reset signal line among the plurality of first reset signal lines, and the second connection line connects the first electrode of the second reset transistor to the second reset signal line among the plurality of second reset signal lines. In the first column pixel driving circuit, the third reset signal line is connected to the first reset signal line among the plurality of first reset signal lines through the first connection line in the pixel driving circuit of the first column pixel driving circuit. And in the second column pixel driving circuit, the fourth reset signal line is connected to the second reset signal line among the plurality of second reset signal lines through the second connection line in the pixel driving circuit of the second column pixel driving circuit.

[0012] Optionally, the orthographic projection of the first anode on the substrate at least partially overlaps with the orthographic projection of the fourth reset signal line among the plurality of fourth reset signal lines on the substrate; at least partially overlaps with the orthographic projection of the first voltage supply line among the plurality of first voltage supply lines on the substrate; and at least partially overlaps with the orthographic projection of the data line among the plurality of data lines on the substrate; and the portions of the fourth reset signal line, the first voltage supply line, and the data line located in the region intersecting with the first anode have a substantially mirror symmetry with respect to a plane perpendicular to and intersecting the first anode.

[0013] Optionally, in the region where a portion of the fourth reset signal line, the first voltage supply line, and the data line intersect with the first anode, the first voltage supply line separates the fourth reset signal line from the data line.

[0014] Optionally, in the region where portions of the fourth reset signal line, the first voltage supply line, and the data line intersect with the first anode, the fourth reset signal line and the data line have a substantially mirror-symmetric relationship with respect to the first voltage supply line.

[0015] Optionally, the array substrate further includes a second anode; wherein the orthographic projection of the second anode on the substrate at least partially overlaps with the orthographic projection of a first adjacent first voltage supply line among a plurality of first voltage supply lines on the substrate; at least partially overlaps with the orthographic projection of a third reset signal line among a plurality of third reset signal lines on the substrate; at least partially overlaps with the orthographic projection of a data line among a plurality of data lines on the substrate; and at least partially overlaps with the orthographic projection of a second adjacent first voltage supply line among a plurality of first voltage supply lines on the substrate; and the portions of the first adjacent first voltage supply line, the third reset signal line, the data line, and the second adjacent first voltage supply line located in the region intersecting with the second anode have a substantially mirror symmetry with respect to a plane perpendicular to and intersecting the second anode.

[0016] Optionally, in the region where the first adjacent first voltage supply line, the third reset signal line, the data line, and a portion of the second adjacent first voltage supply line intersect with the second anode, the third reset signal line and the data line space the first adjacent first voltage supply line and the second adjacent first voltage supply line apart.

[0017] Optionally, the array substrate further includes a second anode and a plurality of first voltage supply lines; wherein a second adjacent first voltage supply line among the plurality of first voltage supply lines includes a second body and a second branch connected to the second body; the orthographic projection of the second anode on the substrate at least partially overlaps with the orthographic projection of the second body on the substrate, at least partially overlaps with the orthographic projection of the second branch on the substrate, at least partially overlaps with the orthographic projection of the data line among the plurality of data lines on the substrate, and at least partially overlaps with the orthographic projection of the third adjacent first voltage supply line among the plurality of first voltage supply lines on the substrate; and the portions of the second body, the second branch, the data line, and the third adjacent first voltage supply line located in the region intersecting with the second anode have a substantially mirror symmetry with respect to a plane perpendicular to and intersecting the second anode.

[0018] Optionally, in the region where the second body, the second branch, the data line, and the portion of the third adjacent first voltage supply line intersect with the second anode, the second branch and the data line space the second body apart from the third adjacent first voltage supply line.

[0019] Optionally, the array substrate further includes a second anode and a third anode; wherein each pixel driving circuit includes a compensation transistor and a driving transistor; the compensation transistor includes a first channel portion and a second channel portion, the first channel portion being connected to a second electrode of the compensation transistor, and the second channel portion being connected to a first electrode of the compensation transistor; the second electrode of the compensation transistor is connected to the gate of the driving transistor; and the orthographic projection of the first anode on the substrate substantially covers the orthographic projection of the first channel portion of the compensation transistor in the first pixel driving circuit on the substrate.

[0020] Optionally, the orthographic projection of the second anode on the substrate substantially covers the orthographic projection of the first channel portion of the compensation transistor in the second pixel driving circuit on the substrate, and substantially covers the orthographic projection of the first channel portion of the compensation transistor in the third pixel driving circuit on the substrate; and the orthographic projection of the third anode on the substrate does not overlap with the orthographic projection of the active layer of the compensation transistor in any pixel driving circuit on the substrate.

[0021] Optionally, the first sub-pixel includes an anti-interference block; wherein the anti-interference block includes a main pad portion, a first extension portion, and a second extension portion; the first extension portion and the second extension portion extend away from the main pad portion along a direction substantially parallel to the second direction; the main pad portion connects the first extension portion and the second extension portion; the orthographic projection of the first extension portion on the substrate at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between the two channel portions of the compensation transistor on the substrate; and the orthographic projection of the second extension portion on the substrate does not overlap with the orthographic projection of the portion of the semiconductor material layer located between the two channel portions of the compensation transistor on the substrate.

[0022] Optionally, the first sub-pixel includes a node connection line; the node connection line connects the gate of the driving transistor and the second electrode of the compensation transistor; the second extension overlaps with the node connection line along the second direction; and the second extension spacees the node connection line from a data line, the data line being connected to a pixel driving circuit including the node connection line.

[0023] On the other hand, this disclosure provides a display device comprising an array substrate described herein or manufactured by the methods described herein, and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0024] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0025] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0026] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0027] Figure 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0028] Figure 2C This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0029] Figure 3A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0030] Figure 3B It is shown Figure 3A The diagram depicts the arrangement of multiple pixel driving circuits in an array substrate.

[0031] Figure 3C It is shown Figure 3A A schematic diagram depicting the structure of the semiconductor material layer in the array substrate.

[0032] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in the array substrate is depicted.

[0033] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in the array substrate is depicted.

[0034] Figure 3F It is shown Figure 3A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate is depicted.

[0035] Figure 3G It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0036] Figure 3H It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate is depicted.

[0037] Figure 3I It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0038] Figure 3J It is shown Figure 3A A schematic diagram of the structure of the second planarization layer in the array substrate is depicted.

[0039] Figure 3K It is shown Figure 3A A schematic diagram of the structure of the anode layer in the array substrate is depicted.

[0040] Figure 3L It is shown Figure 3A A schematic diagram of the structure of the pixel-defining layer in the array substrate is depicted.

[0041] Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0042] Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram.

[0043] Figure 4C It is along Figure 3A A cross-sectional view of the C-C' line in the diagram.

[0044] Figure 4D It is along Figure 3A A cross-sectional view of the D-D' line in the diagram.

[0045] Figure 4E It is along Figure 3A A cross-sectional view of the E-E' line in the diagram.

[0046] Figure 5A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0047] Figure 5B It is shown Figure 5A The diagram depicts the arrangement of multiple pixel driving circuits in an array substrate.

[0048] Figure 5C It is shown Figure 5A A schematic diagram depicting the structure of the semiconductor material layer in the array substrate.

[0049] Figure 5D It is shown Figure 5A A schematic diagram of the structure of the first conductive layer in the array substrate is depicted.

[0050] Figure 5E It is shown Figure 5A A schematic diagram of the structure of the second conductive layer in the array substrate is depicted.

[0051] Figure 5F It is shown Figure 5A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate is depicted.

[0052] Figure 5G It is shown Figure 5A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0053] Figure 5H It is shown Figure 5A A schematic diagram of the structure of the first planarization layer in the array substrate is depicted.

[0054] Figure 5I It is shown Figure 5A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0055] Figure 5J It is shown Figure 5A A schematic diagram of the structure of the second planarization layer in the array substrate is depicted.

[0056] Figure 5K It is shown Figure 5A A schematic diagram of the structure of the anode layer in the array substrate is depicted.

[0057] Figure 5L It is shown Figure 5A A schematic diagram of the structure of the pixel-defining layer in the array substrate is depicted.

[0058] Figure 6A It is along Figure 5A A cross-sectional view of line F-F' in the diagram.

[0059] Figure 6B It is along Figure 5A A cross-sectional view of the G-G' line in the diagram.

[0060] Figure 6C It is along Figure 5A A cross-sectional view of the H-H' line in the diagram.

[0061] Figure 6D It is along Figure 5A A cross-sectional view of line I-I' in the diagram.

[0062] Figure 6E It is along Figure 5A A cross-sectional view of line J-J' in the diagram.

[0063] Figure 7A This is a schematic diagram illustrating the structure of a first reset signal network in an array substrate according to some embodiments of the present disclosure.

[0064] Figure 7B This is a schematic diagram illustrating the structure of a second reset signal network in an array substrate according to some embodiments of the present disclosure.

[0065] Figure 7CThis is a schematic diagram illustrating the structure of a first reset signal network and a second reset signal network in an array substrate according to some embodiments of the present disclosure.

[0066] Figure 7D This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0067] Figure 8A This is a schematic diagram illustrating the structure of a first reset signal network in an array substrate according to some embodiments of the present disclosure.

[0068] Figure 8B This is a schematic diagram illustrating the structure of a second reset signal network in an array substrate according to some embodiments of the present disclosure.

[0069] Figure 8C This is a schematic diagram illustrating the structure of a first reset signal network and a second reset signal network in an array substrate according to some embodiments of the present disclosure.

[0070] Figure 8D This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0071] Figure 9 The layout of signal lines in a second signal line layer and an anode layer in a portion of an array substrate according to some embodiments of the present disclosure is shown.

[0072] Figure 10A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0073] Figure 10B It is shown Figure 10A The diagram depicts the arrangement of multiple pixel driving circuits in an array substrate.

[0074] Figure 10C It is shown Figure 10A A schematic diagram depicting the structure of the semiconductor material layer in the array substrate.

[0075] Figure 10D It is shown Figure 10A A schematic diagram of the structure of the first conductive layer in the array substrate is depicted.

[0076] Figure 10E It is shown Figure 10A A schematic diagram of the structure of the second conductive layer in the array substrate is depicted.

[0077] Figure 10F It is shown Figure 10A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate is depicted.

[0078] Figure 10G It is shown Figure 10A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure.

[0079] Figure 10H It is shown Figure 10A A schematic diagram of the structure of the first planarization layer in the array substrate is depicted.

[0080] Figure 10I It is shown Figure 10A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted.

[0081] Figure 10J It is shown Figure 10A A schematic diagram of the structure of the second planarization layer in the array substrate is depicted.

[0082] Figure 10K It is shown Figure 10A A schematic diagram of the structure of the anode layer in the array substrate is depicted.

[0083] Figure 10L It is shown Figure 10A A schematic diagram of the structure of the pixel-defining layer in the array substrate is depicted.

[0084] Figure 10M The layout of signal lines in a second signal line layer and an anode layer in a portion of an array substrate according to some embodiments of the present disclosure is shown.

[0085] Figure 10N The structure of each first voltage supply line according to some embodiments of the present disclosure is shown.

[0086] Figure 11A The layout of signal lines in a semiconductor material layer and a second conductive layer in a portion of an array substrate according to some embodiments of the present disclosure is shown.

[0087] Figure 11B The layout of signal lines in a second conductive layer, a first signal line layer, and a second signal line layer in a portion of an array substrate according to some embodiments of the present disclosure is shown.

[0088] Figure 11C The structure of an anti-interference block according to some embodiments of the present disclosure is shown.

[0089] Figure 12 The layout of signal lines in a semiconductor material layer and an anode layer in a portion of an array substrate according to some embodiments of the present disclosure is shown.

[0090] Figure 13 This is a schematic diagram illustrating the structure of a semiconductor material layer in an array substrate according to some embodiments of the present disclosure.

[0091] Figure 14 This is a schematic diagram illustrating the structure of a semiconductor material layer in an array substrate according to some embodiments of the present disclosure. Detailed Implementation

[0092] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0093] This disclosure provides, in particular, an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of sub-pixels. Optionally, the plurality of sub-pixels includes a first sub-pixel. Optionally, the array substrate includes a substrate, a second conductive layer on the substrate, and an anode layer located on a side of the second conductive layer away from the substrate. Optionally, the anode layer includes a first anode in the first sub-pixel. Optionally, the second conductive layer includes a first signal line and a second signal line extending in directions substantially parallel to a second direction. Optionally, the second signal line includes a body extending in a direction substantially parallel to the second direction and a branch connected to the body, the branch located on a side of the body away from the first signal line in a direction substantially parallel to a first direction, the first and second directions intersecting each other. Optionally, the branch is located on the side of the body away from the first signal line. Optionally, the orthographic projection of the first anode on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate, at least partially overlaps with the orthographic projection of the body on the substrate, and at least partially overlaps with the orthographic projection of the branch on the substrate.

[0094] Various suitable pixel driving circuits can be used in the array substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0095] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1The array substrate includes an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes multiple gate lines GL, multiple data lines DL, and multiple voltage supply lines Vdd (including multiple second voltage supply lines Vdd2 and various first voltage supply lines (e.g., high voltage supply lines)). Each subpixel Sp emits light driven by its corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via various second voltage supply lines of the multiple second voltage supply lines Vdd2; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via a low voltage supply line. The voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is the driving voltage DV, which drives the light-emitting element to emit light.

[0096] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2AIn some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line rstN of the current stage, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first electrode of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding gate line, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td, The transistor T4 has a second electrode connected to the second electrode of the driving transistor Td; a fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line among a plurality of light-emitting control signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the second transistor T2; a fifth transistor T5 has a gate connected to a corresponding light-emitting control signal line, a first electrode connected to the second electrode of the driving transistor Td and the third transistor T3, and a second electrode connected to the anode of the light-emitting element LE; and a sixth transistor T6 has a gate connected to the reset control signal line rst(N+1) of the next stage, a first electrode connected to the second reset signal line among a plurality of second reset signal lines Vint2, and a second electrode connected to the second electrode of the fifth transistor and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the fourth transistor T4.

[0097] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a second transistor T2), a compensation transistor (e.g., a third transistor T3), two light-emitting control transistors (e.g., a fourth transistor T4 and a fifth transistor T5), and two reset transistors (e.g., a first transistor T1 and a sixth transistor T6).

[0098] Figure 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2BIn some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (alternatively, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding first gate line of the plurality of first gate lines GL1 twice (alternatively, the corresponding gate line crosses the active layer of the third transistor T3 twice). The gate of the first transistor T1 is... Figure 3D and Figure 5D The designation is "G1", where the first transistor T1 is a "dual-gate" transistor. The gate of the third transistor T3 is... Figure 3D and Figure 5D The designation is "G3", where the third transistor, T3, is a "dual-gate" transistor.

[0099] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the third transistor T3. The second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6, and the anode of the light-emitting element LE.

[0100] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, both of which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0101] Figure 2C This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figures 2A to 2CDuring one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emission sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the first transistor T1 via the corresponding reset control signal line in the plurality of reset control signal lines rst, thus turning off the first transistor T1. In the initial sub-stage t0, the corresponding gate lines in the plurality of gate lines GL are provided with cutoff signals, therefore the second transistor T2 and the third transistor T3 are turned off.

[0102] In reset phase t1, a turn-on reset control signal is provided to the gate of the first transistor T1 through the corresponding reset control signal line in the plurality of reset control signal lines rst, to turn on the first transistor T1; this allows the initialization voltage signal from the corresponding first reset signal line in the plurality of first reset signal lines Vint1 to be transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1, and further to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding second voltage supply line in the plurality of second voltage supply lines Vdd2. Due to the increase in the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset phase t1. In reset phase t1, the corresponding gate line in the plurality of gate lines GL is provided with a cutoff signal, thus the second transistor T2 and the third transistor T3 are turned off. The corresponding light emission control signal line in the plurality of light emission control signal lines em is provided with a high voltage signal to turn off the fourth transistor T4 and the fifth transistor T5.

[0103] During the data write sub-stage t2, a cutoff reset control signal is again provided to the gate of the first transistor T1 via the corresponding reset control signal line in the multiple reset control signal lines rst, thus turning off the first transistor T1. The corresponding gate line in the multiple gate lines GL is provided with a conduction signal, therefore the second transistor T2 and the third transistor T3 are turned on. The second electrode of the driving transistor Td is connected to the second electrode of the third transistor T3. The gate of the driving transistor Td is electrically connected to the first electrode of the third transistor T3. Since the third transistor T3 is turned on during the data write sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus making the driving transistor Td a diode-connected mode. The second transistor T2 is turned on during the data write sub-stage t2. The data voltage signal transmitted via the corresponding data line in the multiple data lines DL is received by the first electrode of the second transistor T2 and then transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the second transistor T2. The node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, the voltage level at node N1 gradually rises to (Vdata + Vth) during the data write sub-stage t2, where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. The corresponding light-emitting control signal lines in the plurality of light-emitting control signal lines em are provided with high-voltage signals to cut off the fourth transistor T4 and the fifth transistor T5.

[0104] During the data writing sub-stage t2, a turn-on reset control signal is provided to the gate of the sixth transistor T6 via the corresponding reset control signal line of the next adjacent stage among multiple reset control signal lines rst, to turn on the sixth transistor T6; to allow the initialization voltage signal from the corresponding second reset signal line of the multiple second reset signal lines Vint2 to be transmitted from the first electrode of the sixth transistor T6 to the second electrode of the sixth transistor T6; and further to node N4. The anode of the light-emitting element LE is initialized.

[0105] In the light-emitting phase t3, a cutoff reset control signal is again provided to the gate of the first transistor T1 through the corresponding reset control signal line in the plurality of reset control signal lines rst, thus turning off the first transistor T1. The corresponding gate lines in the plurality of gate lines GL are provided with cutoff signals, turning off the second transistor T2 and the third transistor T3. The corresponding light-emitting control signal lines in the plurality of light-emitting control signal lines em are provided with low voltage signals to turn on the fourth transistor T4 and the fifth transistor T5. In the light-emitting phase t3, the voltage level at node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level, operating in the saturation region. A path is formed through the fourth transistor T4, the driving transistor Td, and the fifth transistor T5 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at node N3, connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0106] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, and S3 represents a corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, and C3 represents a corresponding third sub-pixel of a third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0107] In another example, the array of multiple subpixels includes a repeating array in the format S1-S2-S3-S4, where S1 represents the corresponding first subpixel, S2 represents the corresponding second subpixel, S3 represents the corresponding third subpixel, and S4 represents the corresponding fourth subpixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C4 represents the corresponding fourth subpixel of the fourth color. In yet another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C2' represents the corresponding fourth subpixel of the second color. In another example, the C1-C2-C3-C2' format is RGBG format, where the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0108] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0109] In an alternative embodiment, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0110] Figure 3A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 3B It is shown Figure 3A A schematic diagram of the arrangement of multiple pixel driving circuits in the array substrate. Figure 3A and Figure 3B A portion of an array substrate with three pixel driving circuits (including PDC1, PDC2, and PDC3) is depicted.

[0111] Figure 3C It is shown Figure 3AA schematic diagram of the structure of the semiconductor material layer in the array substrate. Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in the array substrate. Figure 3E It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in the array substrate. Figure 3F It is shown Figure 3A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate. Figure 3G It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate. Figure 3H It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate. Figure 3I It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate. Figure 3J It is shown Figure 3A A schematic diagram of the structure of the second planarization layer in the array substrate. Figure 3K It is shown Figure 3A A schematic diagram of the structure of the anode layer in the array substrate. Figure 3L It is shown Figure 3A A schematic diagram of the pixel-defining layer structure in the array substrate. Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram. Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram. Figure 4C It is along Figure 3A A cross-sectional view of the C-C' line in the diagram. Figure 4D It is along Figure 3A A cross-sectional view of the D-D' line in the diagram. Figure 4E It is along Figure 3A A cross-sectional view of the E-E' line in the diagram.

[0112] Reference Figures 3A to 3L and Figures 4A to 4BIn some embodiments, the display panel includes a substrate BS; a semiconductor material layer SML on the substrate BS; a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS; a first conductive layer CT1 located on the side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN located on the side of the first conductive layer CT1 away from the gate insulating layer GI; a second conductive layer CT2 located on the side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD located on the side of the second conductive layer CT2 away from the insulating layer IN; and a first signal line layer SL1. The first planarization layer PLN1 is located on the side of the first signal line layer SL1 away from the interlayer dielectric layer ILD; the second signal line layer SL2 is located on the side of the first planarization layer PLN1 away from the first signal line layer SL1; the second planarization layer PLN2 is located on the side of the second signal line layer SL2 away from the first planarization layer PLN1; the anode layer ADL is located on the side of the second planarization layer PLN2 away from the second signal line layer SL2; and the pixel defining layer PDL is located on the side of the anode layer ADL away from the substrate BS.

[0113] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3CEach pixel driving circuit is labeled with a number, which indicates the region corresponding to the multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also labeled with a number indicating the component of each of the multiple transistors in the pixel driving circuit. For example, first transistor T1 includes active layer ACT1, first electrode S1, and second electrode D1. Second transistor T2 includes active layer ACT2, first electrode S2, and second electrode D2. Third transistor T3 includes active layer ACT3, first electrode S3, and second electrode D3. Fourth transistor T4 includes active layer ACT4, first electrode S4, and second electrode D4. Fifth transistor T5 includes active layer ACT5, first electrode S5, and second electrode D5. Sixth transistor T6 includes active layer ACT6, first electrode T6, and second electrode D6. Driving transistor Td includes active layer ACTd, first electrode Sd, and second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrode (S1, S2, S3, S4, S5, S6, and Sd), and the second electrode (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In yet another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer.

[0114] As used herein, an active layer refers to a portion of a transistor comprising a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. A first electrode refers to a portion of the transistor connected to one side of the active layer, and a second electrode refers to a portion of the transistor connected to the other side of the active layer. In the context of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a portion of the transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first and second portions, wherein the orthographic projection of the first portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of the second portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the context of a dual-gate transistor, a first electrode refers to a portion of the transistor connected to the side of the first portion away from the third portion, and a second electrode refers to a portion of the transistor connected to the side of the second portion away from the third portion.

[0115] Reference Figures 2A to 2C , Figure 3A and Figure 3D In some embodiments, the first conductive layer includes a plurality of first reset control signal lines rst (including the reset signal line rstN of this stage and the reset signal line rst(N+1) of the next stage), a plurality of light emission control signal lines em, a plurality of gate lines GL, and a first capacitor electrode Ce1 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of reset control signal lines rst, the plurality of light emission control signal lines em, the plurality of gate lines GL, and the first capacitor electrode Ce1 of the storage capacitor Cst are located in the same layer.

[0116] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple gate lines GL and a first capacitor electrode Ce1 are located in the same layer when they are formed due to one or more steps of the same patterning process performed in the same material layer. In another example, multiple gate lines GL and a first capacitor electrode Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple gate lines GL and forming the first capacitor electrode Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0117] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3E In some embodiments, the second conductive layer includes an anti-interference block IPB, a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the anti-interference block IPB, the plurality of first reset signal lines Vint1, the plurality of second reset signal lines Vint2, and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0118] Figure 3F The image depicts vias extending through the interlayer dielectric layer (ILD).

[0119] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3G In some embodiments, the first signal line layer includes a node connection line Cln, a plurality of second voltage supply lines Vdd2, a first connection line Cl1, a second connection line Cl2, a relay electrode RE, and a data signal connection pad DCP. In some embodiments, the first signal line layer further includes a plurality of third reset signal lines Vint3 and a plurality of fourth reset signal lines Vint4.

[0120] Node connection line Cln connects the first capacitor electrode Ce1 and the second electrode of the third transistor T3 in each pixel driving circuit. Data signal connection pad DCP is configured to connect a corresponding data line among multiple data lines to the first electrode of the second transistor T2. Relay electrode RE connects the fourth node N4 to the anode contact pad. The relay electrode is connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6. The anode contact pad is located in the second signal line layer and is connected to the anode in the corresponding sub-pixel.

[0121] Multiple second voltage supply lines Vdd2 are connected to multiple first voltage supply lines in the second signal line layer and to the second capacitor electrode Ce2 of the storage capacitor in the second conductive layer. The second capacitor electrodes in the same row are partially interconnected as an integral structure. Multiple integral structures of multiple second capacitor electrodes in multiple rows, multiple second voltage supply lines Vdd2, and multiple first voltage supply lines form an interconnected voltage signal network. Each of the multiple second voltage supply lines Vdd2 is connected to the first electrode of the fourth transistor T4 and to the second capacitor electrode Ce2 of the storage capacitor Cst. Optionally, the multiple second voltage supply lines Vdd2 extend in a direction substantially parallel to the second direction DR2; the multiple first voltage supply lines extend in a direction substantially parallel to the second direction DR2. Optionally, the integral structure including the interconnected second capacitor electrodes in the same row extends in a direction substantially parallel to the first direction DR1. As used herein, the term "substantially parallel" means an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, and 0 degrees to about 30 degrees.

[0122] The first connection line Cl1 connects the first electrode of the first transistor T1 to a first reset signal line among a plurality of first reset signal lines Vint1. In a pixel driving circuit having a corresponding third reset signal line among a plurality of third reset signal lines Vint3, the first connection line Cl1 does not exist; and the corresponding third reset signal line among the plurality of third reset signal lines Vint3 connects the first electrode of the first transistor T1 to a first reset signal line among the plurality of first reset signal lines Vint1. In a pixel driving circuit having a corresponding third reset signal line among a plurality of third reset signal lines Vint3, a portion of the corresponding third reset signal line can be considered as a first connection line.

[0123] The second connection line Cl2 connects the first electrode of the sixth transistor T6 to a second reset signal line among the plurality of second reset signal lines Vint2. In a pixel driving circuit having a corresponding fourth reset signal line among the plurality of fourth reset signal lines Vint4, the second connection line Cl2 does not exist; and the corresponding fourth reset signal line among the plurality of fourth reset signal lines Vint4 connects the first electrode of the sixth transistor T6 to a second reset signal line among the plurality of second reset signal lines Vint2. In a pixel driving circuit having a corresponding fourth reset signal line among the plurality of fourth reset signal lines Vint4, a portion of the corresponding fourth reset signal line can be considered as a second connection line.

[0124] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the node connection line Cln, multiple second voltage supply lines Vdd2, first connection line Cl1, second connection line Cl2, relay electrode RE, data signal connection pad DCP, multiple third reset signal lines Vint3, and multiple fourth reset signal lines Vint4 are located in the same layer.

[0125] Figure 3H The vias extending through the first planarization layer PLN1 are shown.

[0126] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3I In some embodiments, the second signal line layer includes a plurality of first voltage supply lines Vdd1, a plurality of data lines DL, and an anode contact pad ACP. The anode contact pad ACP is electrically connected via relay electrodes to the second electrodes of the fifth transistor T5 and the sixth transistor T6 in the corresponding pixel driving circuit. The anode contact pad ACP is also electrically connected to the anode in the corresponding sub-pixel. As described above, the plurality of first voltage supply lines Vdd1 are connected to a plurality of second voltage supply lines in the first signal line layer. Each of the plurality of data lines is electrically connected via a data signal connection pad to the first electrode of the second transistor T2.

[0127] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, multiple first voltage supply lines Vdd1, multiple data lines DL, and anode contact pads ACP are located in the same layer.

[0128] Figure 3J The vias extending through the second planarization layer PLN2 are depicted.

[0129] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3K The array substrate also includes an anode layer (ADL). Figure 3K The label indicates the multiple sub-pixel openings (SA) that correspond to the multiple anodes. Figure 3J Vias extending through the second planarization layer PLN2 are depicted. Each anode is connected to its corresponding anode contact pad via a corresponding via extending through the second planarization layer PLN2.

[0130] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3L The array substrate also includes a pixel definition layer (PDL) that defines multiple sub-pixel openings (SA).

[0131] Figure 5A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 5B It is shown Figure 5A The diagram depicts the arrangement of multiple pixel driving circuits in an array substrate. Figure 5C It is shown Figure 5A A schematic diagram depicting the structure of the semiconductor material layer in the array substrate. Figure 5D It is shown Figure 5A A schematic diagram of the structure of the first conductive layer in the array substrate is depicted. Figure 5E It is shown Figure 5A A schematic diagram of the structure of the second conductive layer in the array substrate is depicted. Figure 5F It is shown Figure 5A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate is depicted. Figure 5G It is shown Figure 5A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure. Figure 5H It is shown Figure 5A A schematic diagram of the structure of the first planarization layer of the array substrate is depicted. Figure 5I It is shown Figure 5A A schematic diagram of the structure of the second signal line layer in the array substrate is depicted. Figure 5J It is shown Figure 5A A schematic diagram of the structure of the second planarization layer in the array substrate is depicted. Figure 5K It is shown Figure 5A A schematic diagram of the structure of the anode layer in the array substrate is depicted. Figure 5L It is shown Figure 5A A schematic diagram of the structure of the pixel-defining layer in the array substrate is depicted. Figure 6A It is along Figure 5A A cross-sectional view of line F-F' in the diagram. Figure 6B It is along Figure 5A A cross-sectional view of the G-G' line in the diagram. Figure 6C It is along Figure 5A A cross-sectional view of the H-H' line in the diagram. Figure 6D It is along Figure 5A A cross-sectional view of line I-I' in the diagram. Figure 6E It is along Figure 5A A cross-sectional view of line J-J' in the diagram.

[0132] Figure 5C , Figure 5D , Figure 5E and Figure 5K The structure of the semiconductor material layer, the first conductive layer, the second conductive layer, and the anode layer shown is similar to... Figure 3C , Figure 3D , Figure 3E and Figure 3K The corresponding structures shown are basically the same.

[0133] Reference Figure 2A , Figure 2B , Figure 5A and Figure 5G In some embodiments, the first signal line layer does not include a plurality of third reset signal lines Vint3 and a plurality of fourth reset signal lines Vint4. In some embodiments, the first signal line layer includes a node connection line Cln, a plurality of second voltage supply lines Vdd2, a first connection line Cl1, a second connection line Cl2, a relay electrode RE, and a data signal connection pad DCP.

[0134] Node connection line Cln connects the first capacitor electrode Ce1 in the corresponding pixel driving circuit to the second electrode of the third transistor T3. Data signal connection pad DCP is configured to connect a corresponding data line among multiple data lines to the first electrode of the second transistor T2. Relay electrode RE connects the fourth node N4 to the anode contact pad. The relay electrode is connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6. The anode contact pad is located in the second signal line layer and is connected to the anode in the corresponding sub-pixel.

[0135] Multiple second voltage supply lines Vdd2 are connected to multiple first voltage supply lines in the second signal line layer and to the second capacitor electrode Ce2 of the storage capacitor in the second conductive layer. The second capacitor electrodes in the same row are partially interconnected as an integral structure. Multiple integral structures of the second capacitor electrodes in multiple rows, the multiple second voltage supply lines Vdd2, and the multiple first voltage supply lines form an interconnected reset signal network. A corresponding second voltage supply line among the multiple second voltage supply lines Vdd2 is connected to the first electrode of the fourth transistor T4 and to the second capacitor electrode Ce2 of the storage capacitor Cst. Optionally, the multiple second voltage supply lines Vdd2 extend in a direction substantially parallel to the second direction DR2; the multiple first voltage supply lines extend in a direction substantially parallel to the second direction DR2. Optionally, the integral structure including the interconnected second capacitor electrodes in the same row extends in a direction substantially parallel to the first direction DR1.

[0136] The first connection line Cl1 connects the first electrode of the first transistor T1 to the first reset signal line among the plurality of first reset signal lines Vint1. The second connection line Cl2 connects the first electrode of the sixth transistor T6 to the second reset signal line among the plurality of second reset signal lines Vint2.

[0137] Reference Figure 2A , Figure 2B , Figure 5A and Figure 5I In some embodiments, the second signal line layer includes a plurality of first voltage supply lines Vdd1, a plurality of data lines DL, and an anode contact pad ACP. The anode contact pad ACP is electrically connected via relay electrodes to the second electrodes of the fifth transistor T5 and the sixth transistor T6 in the corresponding pixel driving circuit. The anode contact pad ACP is also electrically connected to the anode in the corresponding sub-pixel. As described above, the plurality of first voltage supply lines Vdd1 are connected to a plurality of second voltage supply lines in the first signal line layer. The corresponding data lines among the plurality of data lines are electrically connected via data signal connection pads to the first electrode of the second transistor T2. In some embodiments, the second signal line layer further includes a plurality of third reset signal lines Vint3 and a plurality of fourth reset signal lines Vint4.

[0138] Each of the multiple third reset signal lines Vint3 is connected to a first connection line in the first signal line layer, and the first connection line connects the first electrode of the first transistor T1 to the first reset signal line among the multiple first reset signal lines.

[0139] Each of the multiple fourth reset signal lines Vint4 is connected to a second connection line in the first signal line layer, and the second connection line connects the first electrode of the sixth transistor T6 to the second reset signal line among the multiple second reset signal lines.

[0140] Reference Figure 3A , Figure 3B , Figure 3G , Figure 5A , Figure 5B and Figure 5IThe array substrate includes three adjacent columns of pixel driving circuits. For example, the first column of pixel driving circuits includes PDC1, the second column includes PDC2, and the third column includes PDC3. In some embodiments, the third reset signal lines Vint3 are present in the first column of the three adjacent columns of pixel driving circuits, but not in the second and third columns. In some embodiments, the fourth reset signal lines Vint4 are present in the second column of the three adjacent columns of pixel driving circuits, but not in the first and third columns. In some embodiments, neither the third reset signal lines Vint3 nor the fourth reset signal lines Vint4 are present in the third column of the three adjacent columns of pixel driving circuits.

[0141] In some embodiments, the first column of the adjacent three-column pixel driving circuit is configured to drive the first column of sub-pixels of the first color to emit light, the second column of the adjacent three-column pixel driving circuit is configured to drive the second column of sub-pixels of the second color to emit light, and the third column of the adjacent three-column pixel driving circuit is configured to drive the third column of sub-pixels of the third color to emit light. Optionally, a plurality of third reset signal lines Vint3 and a plurality of fourth reset signal lines Vint4 are not present in the third column of the adjacent three-column pixel driving circuit. Optionally, the third color is red, and the third column of sub-pixels of the third color is a column of red sub-pixels. Optionally, the first color and the second color are two different colors selected from green and blue. In one example, the first color is green, the second color is blue, and the third color is red. In another example, the first color is blue, the second color is green, and the third color is red.

[0142] Figure 7A This is a schematic diagram illustrating the structure of a first reset signal network in an array substrate according to some embodiments of the present disclosure. Figure 7B This is a schematic diagram illustrating the structure of a second reset signal network in an array substrate according to some embodiments of the present disclosure. Figure 7C This is a schematic diagram illustrating the structure of a first reset signal network and a second reset signal network in an array substrate according to some embodiments of the present disclosure. Figure 8A This is a schematic diagram illustrating the structure of a first reset signal network in an array substrate according to some embodiments of the present disclosure. Figure 8B This is a schematic diagram illustrating the structure of a second reset signal network in an array substrate according to some embodiments of the present disclosure. Figure 8C This is a schematic diagram illustrating the structure of a first reset signal network and a second reset signal network in an array substrate according to some embodiments of the present disclosure. Figures 7A to 7C The first reset signal network and the second reset signal network depicted correspond to Figure 3A The first reset signal network and the second reset signal network are depicted in the figure. Figures 8A to 8C The first reset signal network and the second reset signal network depicted correspond to Figure 5A The first reset signal network and the second reset signal network are depicted in the figure.

[0143] Reference Figures 7A to 7C and Figures 8A to 8C In some embodiments, the first reset signal network includes a plurality of first reset signal lines Vint1 and a plurality of third reset signal lines Vint3 interconnected with each other. Optionally, the plurality of first reset signal lines Vint1 extend in a direction substantially parallel to a first direction DR1. Optionally, the plurality of third reset signal lines Vint3 extend in a direction substantially parallel to a second direction DR2. Optionally, each first reset signal line in the plurality of first reset signal lines Vint1 is connected to one or more third reset signal lines in the plurality of third reset signal lines Vint3. Optionally, each third reset signal line in the plurality of third reset signal lines Vint3 is connected to one or more first reset signal lines in the plurality of first reset signal lines Vint1.

[0144] Reference Figures 7A to 7C Optionally, a plurality of first reset signal lines Vint1 are located in the second conductive layer. Optionally, a plurality of third reset signal lines Vint3 are located in the first signal line layer.

[0145] Reference Figures 8A to 8C Optionally, a plurality of first reset signal lines Vint1 are located in the second conductive layer. Optionally, a plurality of third reset signal lines Vint3 are located in the second signal line layer.

[0146] Reference Figures 7A to 7C and Figures 8A to 8C In some embodiments, the second reset signal network includes a plurality of second reset signal lines Vint2 and a plurality of fourth reset signal lines Vint4 interconnected with each other. Optionally, the plurality of second reset signal lines Vint2 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of fourth reset signal lines Vint4 extend in a direction substantially parallel to the second direction DR2. Optionally, each second reset signal line in the plurality of second reset signal lines Vint2 is connected to one or more fourth reset signal lines in the plurality of fourth reset signal lines Vint4. Optionally, each fourth reset signal line in the plurality of fourth reset signal lines Vint4 is connected to one or more second reset signal lines in the plurality of second reset signal lines Vint2.

[0147] Reference Figures 7A to 7COptionally, a plurality of second reset signal lines Vint2 are located in the first signal line layer. Optionally, a plurality of fourth reset signal lines Vint4 are located in the first signal line layer.

[0148] Reference Figures 8A to 8C Optionally, a plurality of second reset signal lines Vint2 are located in the first signal line layer. Optionally, a plurality of fourth reset signal lines Vint4 are located in the second signal line layer.

[0149] Figure 7D This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 7D A portion of an array substrate with six pixel driving circuits is depicted, the six pixel driving circuits including PDC1, PDC2, PDC3, PDC4, PDC5 and PDC6. Figure 7D The portion of the array substrate depicted in the image corresponds to... Figures 7A to 7C The portion of the array substrate depicted in the image has a first reset signal network and a second reset signal network.

[0150] Figure 8D This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 8D A portion of an array substrate with six pixel driving circuits is depicted, the six pixel driving circuits including PDC1, PDC2, PDC3, PDC4, PDC5 and PDC6. Figure 8D The portion of the array substrate depicted in the image corresponds to... Figures 8A to 8C The portion of the array substrate depicted in the image has a first reset signal network and a second reset signal network.

[0151] Reference Figures 7A to 7D and Figures 8A to 8D In some embodiments, the pixel driving circuits of the array substrate are arranged in multiple columns, namely the (3k-2)th column C(3k-2), the (3k-1)th column C(3k-1), and the (3k)th column C(3k) in column K, where K and k are positive integers, and 1≤k≤(K / 3).

[0152] As used herein, the terms "column (3k-2)," "column (3k-1)," and "column (3k)" are used in the case of column K. The array substrate may or may not include additional columns preceding the first column of column K and / or additional columns following the last column of column K. In the case of the array substrate, the term "column (3k-1)" does not necessarily indicate an odd-numbered column, and the terms "column (3k-2)" or "column (3k)" do not necessarily indicate an even-numbered column. In one example, column (3k-2) is an even-numbered column in the case of column K, but may be an odd-numbered column in the case of the array substrate. In another example, column (3k-2) is an even-numbered column in the case of column K and is also an even-numbered column in the case of the array substrate. In one example, column (3k-1) is an odd-numbered column in the case of column K, but may be an even-numbered column in the case of the array substrate. In another example, column (3k-1) is an odd-numbered column in the case of column K and is also an odd-numbered column in the case of the array substrate. In one example, column (3k) is an even column in the case of column K, but can be an odd column in the case of an array substrate. In another example, column (3k) is an even column in the case of column K, and also an even column in the case of an array substrate.

[0153] In some embodiments, column (3k-2) C(3k-1) includes a driving circuit for the (3k-2)th pixel, column (3k-1) C(3k-1) includes a driving circuit for the (3k-1)th pixel, and column (3k) C(3k) includes a driving circuit for the (3k)th pixel. The driving circuits for the (3k-2)th pixel, the (3k-1)th pixel, and the (3k)th pixel are located in the same row.

[0154] In some embodiments, column (3k-2) C(3k-2) includes a third reset signal line among a plurality of third reset signal lines Vint3; column (3k) C(3k) includes a fourth reset signal line among a plurality of fourth reset signal lines Vint4.

[0155] Optionally, the multiple third reset signal lines Vint3 do not exist in column (3k) C(3k) or column (3k-1) C(3k-1).

[0156] Optionally, the multiple fourth reset signal lines Vint4 do not exist in column (3k-2) C(3k-2) or column (3k-1) C(3k-1).

[0157] Optionally, there are no multiple third reset signal lines Vint3 or multiple fourth reset signal lines Vint4 in column (3k-1) C(3k-1).

[0158] In some embodiments, the pixel driving circuit of column (3k-2) C(3k-2) is configured to drive the first color sub-pixels of column (3k-2) C(3k-2) to emit light, the pixel driving circuit of column (3k) C(3k) is configured to drive the second color sub-pixels of column (3k) C(3k) to emit light, and the pixel driving circuit of column (3k-1) C(3k-1) is configured to drive the third color sub-pixels of column (3k-1) C(3k-1) to emit light. Optionally, neither the plurality of third reset signal lines Vint3 nor the plurality of fourth reset signal lines Vint4 are present in the pixel driving circuit of column (3k-1) C(3k-1). Optionally, the third color is red, and the third color sub-pixels of column (3k-1) C(3k-1) are a column of red sub-pixels. Optionally, the first color and the second color are two different colors selected from green and blue. In one example, the first color is green, the second color is blue, and the third color is red. In another example, the first color is blue, the second color is green, and the third color is red.

[0159] In some embodiments, refer to Figure 3G and Figures 7A to 7D The first connecting line Cl1 does not exist in column (3k-2) C(3k-2). In some embodiments, refer to Figure 3G , Figures 7A to 7D The second connecting line Cl2 does not exist in column (3k) C(3k).

[0160] In some embodiments, refer to Figure 5G , Figure 5I and Figures 8A to 8D The first reset signal network also includes a first connection line Cl1 located in column (3k-2) C(3k-2). The third reset signal lines in the plurality of third reset signal lines Vint3 are connected to the first connection line Cl1 in column (3k-2) C(3k-2). The first connection line Cl1 in column (3k-2) C(3k-2) also connects the first electrode of the first transistor T1 in column (3k-2) C(3k-2) to the first reset signal line in the plurality of first reset signal lines Vint1.

[0161] In some embodiments, refer to Figure 5G , Figure 5I and Figures 8A to 8D The second reset signal network also includes a second connection line Cl2 located in column (3k) C(3k). The fourth reset signal line of the plurality of fourth reset signal lines is connected to the second connection line Cl2 in column (3k) C(3k). The second connection line Cl2 in column (3k) C(3k) also connects the first electrode of the sixth transistor T6 to the second reset signal line of the plurality of second reset signal lines Vint2.

[0162] Reference Figure 2A , Figure 2B , Figure 3A , Figure 3D , Figure 3E , Figure 3G , Figure 4A , Figure 5A , Figure 5D , Figure 5E , Figure 5G and Figure 6A In some embodiments, except for the hole region H in which a portion of the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 on the substrate BS completely covers the orthographic projection of the first capacitor electrode Ce1 on the substrate BS with a margin. In some embodiments, the first signal line layer includes a node connection line Cln located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is located on the same layer as at least one of a plurality of second voltage supply lines Vdd2, a first connection line Cl1, a second connection line Cl2, a relay electrode RE, a data signal connection pad DCP, a plurality of third reset signal lines Vint3, or a plurality of fourth reset signal lines Vint4.

[0163] In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer GI away from the substrate BS. Optionally, the array substrate further includes a first via v1 and a second via v2. The first via v1 is located in the via region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the second electrode D3 of the third transistor, such as... Figure 4A and Figure 6A As shown.

[0164] Reference Figure 2A , Figure 2B , Figures 3A to 3L and Figure 4B In some embodiments, the array substrate further includes a third via v3 and a fourth via v4. The third via v3 extends through the interlayer dielectric layer ILD. The fourth via v4 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, each of the plurality of third reset signal lines Vint3 is connected to a first reset signal line of the plurality of first reset signal lines Vint1 through the third via v3. Optionally, each of the plurality of third reset signal lines Vint3 is connected to the first electrode S1 of the first transistor T1 through the fourth via v4.

[0165] Reference Figure 2A , Figure 2B , Figures 3A to 3L and Figure 4C In some embodiments, the array substrate further includes a fifth via v5 and a sixth via v6. The fifth via v5 extends through the interlayer dielectric layer (ILD). The sixth via v6 extends through the interlayer dielectric layer (ILD), the insulating layer (IN), and the gate insulating layer (GI). Optionally, the first connection line Cl1 is connected to a first reset signal line among a plurality of first reset signal lines Vint1 via the fifth via v5. Optionally, the first connection line Cl1 is connected to the first electrode S1 of the first transistor T1 via the sixth via v6.

[0166] Reference Figure 2A , Figure 2B , Figures 3A to 3L and Figure 4D In some embodiments, the array substrate further includes a seventh via v7 and an eighth via v8. The seventh via v7 extends through the interlayer dielectric layer ILD. The eighth via v8 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, each of the plurality of fourth reset signal lines Vint4 is connected to a second reset signal line of the plurality of second reset signal lines Vint2 via the seventh via v7. Optionally, each of the plurality of fourth reset signal lines Vint4 is connected to the first electrode S6 of the sixth transistor T6 via the eighth via v8.

[0167] Reference Figure 2A , Figure 2B , Figures 3A to 3L and Figure 4E In some embodiments, the array substrate further includes a ninth via v9 and a tenth via v10. The ninth via v9 extends through the interlayer dielectric layer ILD. The tenth via v10 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the second connection line Cl2 is connected to a second reset signal line among a plurality of second reset signal lines Vint2 via the ninth via v9. Optionally, the second connection line Cl2 is connected to the first electrode S6 of the sixth transistor T6 via the tenth via v10.

[0168] Reference Figure 2A , Figure 2B , Figures 5A to 5L and Figure 6BIn some embodiments, the array substrate further includes an eleventh via v11, a twelfth via v12, and a thirteenth via v13. The eleventh via v11 extends through the first planarization layer PLN1. The twelfth via v12 extends through the interlayer dielectric layer ILD. The thirteenth via v13 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, each of the plurality of third reset signal lines Vint3 is connected to the first connection line Cl1 via the eleventh via v11. Optionally, the first connection line Cl1 is connected to the first reset signal line of the plurality of first reset signal lines Vint1 via the twelfth via v12. Optionally, the first connection line Cl1 is connected to the first electrode S1 of the first transistor T1 via the thirteenth via v13.

[0169] Reference Figure 2A , Figure 2B , Figures 5A to 5L and Figure 6C In some embodiments, the array substrate further includes a fourteenth via v14 and a fifteenth via v15. The fourteenth via v14 extends through the interlayer dielectric layer (ILD). The fifteenth via v15 extends through the interlayer dielectric layer (ILD), the insulating layer (IN), and the gate insulating layer (GI). Optionally, a first connection line Cl1 is connected to a first reset signal line among a plurality of first reset signal lines Vint1 via the fourteenth via v14. Optionally, the first connection line Cl1 is connected to the first electrode S1 of the first transistor T1 via the fifteenth via v15.

[0170] Reference Figure 2A , Figure 2B , Figures 5A to 5L and Figure 6D In some embodiments, the array substrate further includes a sixteenth via v16, a seventeenth via v17, and an eighteenth via v18. The sixteenth via v16 extends through the first planarization layer PLN1. The seventeenth via v17 extends through the interlayer dielectric layer ILD. The eighteenth via v18 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, each of the plurality of fourth reset signal lines Vint4 is connected to the second connection line Cl2 via the sixteenth via v16. Optionally, the second connection line Cl2 is connected to the second reset signal line of the plurality of second reset signal lines Vint2 via the seventeenth via v17. Optionally, the second connection line Cl2 is connected to the first electrode S6 of the sixth transistor T6 via the eighteenth via v18.

[0171] Reference Figure 2A , Figure 2B , Figures 5A to 5L and Figure 6EIn some embodiments, the array substrate further includes a nineteenth via v19 and a twentieth via v20. The nineteenth via v19 extends through the interlayer dielectric layer (ILD). The twentieth via v20 extends through the interlayer dielectric layer (ILD), the insulating layer (IN), and the gate insulating layer (GI). Optionally, the second connection line Cl2 is connected to a second reset signal line among a plurality of second reset signal lines Vint2 via the nineteenth via v19. Optionally, the second connection line Cl2 is connected to the first electrode S6 of the sixth transistor T6 via the twentieth via v20.

[0172] Figure 9 The layout of signal lines in a second signal line layer and an anode layer in a portion of an array substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figure 9 In some embodiments, the orthographic projection of the anode on the substrate at least partially overlaps with the orthographic projection of the reset signal line on the substrate; at least partially overlaps with the orthographic projection of the first voltage supply line in the plurality of first voltage supply lines Vdd1 on the substrate; and at least partially overlaps with the orthographic projection of the data line in the plurality of data lines DL on the substrate.

[0173] In some embodiments, the anode layer includes a first anode AD1, a second anode AD2, and a third anode AD3. In one example, the first anode AD1 is the anode of a first-color light-emitting element; the second anode AD2 is the anode of a second-color light-emitting element; and the third anode AD3 is the anode of a third-color light-emitting element. In another example, the first, second, and third colors are three different colors selected from red, green, and blue.

[0174] In some embodiments, the orthographic projection of the first anode AD1 on the substrate at least partially overlaps with the orthographic projection of the fourth reset signal line in the plurality of fourth reset signal lines Vint4 on the substrate; at least partially overlaps with the orthographic projection of the first voltage supply line in the plurality of first voltage supply lines Vdd1 on the substrate; and at least partially overlaps with the orthographic projection of the data line in the plurality of data lines DL on the substrate.

[0175] In some embodiments, the orthographic projection of the second anode AD2 on the substrate at least partially overlaps with the orthographic projection of the third reset signal line among the plurality of third reset signal lines Vint3 on the substrate; at least partially overlaps with the orthographic projection of the two first voltage supply lines among the plurality of first voltage supply lines Vdd1 on the substrate; and at least partially overlaps with the orthographic projection of the data lines among the plurality of data lines DL on the substrate.

[0176] In some embodiments, the orthographic projection of the third anode AD3 on the substrate at least partially overlaps with the orthographic projection of the third reset signal line among the plurality of third reset signal lines Vint3 on the substrate; at least partially overlaps with the orthographic projection of the two first voltage supply lines among the plurality of first voltage supply lines Vdd1 on the substrate; and at least partially overlaps with the orthographic projection of the data lines among the plurality of data lines DL on the substrate.

[0177] The inventors of this disclosure have discovered that the degree of evenness of the anode in a display panel can adversely affect image display. For example, anode tilt can cause color shift. This disclosure finds that the signal lines beneath the anode can significantly affect the degree of anode tilt. In one example, a signal line is positioned on one side beneath the anode, while no signal line is positioned on the other side. This results in an uneven surface of the planarization layer on top of the signal lines. This uneven surface of the planarization layer, in turn, causes the anode on top of the planarization layer to tilt. For example, the presence of a signal line beneath the left portion of the planarization layer causes an uneven surface of the planarization layer, which in turn causes the anode on top of the planarization layer to tilt to the right. The tilted anode reflects more light towards the right side of the display panel. In a display panel, anodes associated with sub-pixels of different colors have different tilt angles, so light reflected by the anodes in sub-pixels of different colors is reflected at different angles to different colors of light. The cumulative effect of this problem leads to color shift at large viewing angles.

[0178] In this disclosure, by at least partially overlapping the orthographic projection of the anode on the substrate with the orthographic projection of the reset signal line on the substrate; at least partially overlapping the orthographic projection of the first voltage supply line among the plurality of first voltage supply lines Vdd1 on the substrate; and at least partially overlapping the orthographic projection of the data line among the plurality of data lines DL on the substrate, a planarization layer beneath the anode is achieved on the array substrate. Therefore, color shift problems can be mitigated.

[0179] In some embodiments, the fourth reset signal line in the plurality of fourth reset signal lines Vint4, the first voltage supply line Vdd1 in the plurality of first voltage supply lines, and the data line in the plurality of data lines DL cross the first anode AD1, respectively.

[0180] In some embodiments, the fourth reset signal lines in the plurality of fourth reset signal lines Vint4, the first voltage supply lines in the plurality of first voltage supply lines Vdd1, and the data lines in the plurality of data lines DL are substantially uniformly distributed relative to the first anode AD1 along the first direction DR1.

[0181] For example, the portions of the fourth reset signal lines in the plurality of fourth reset signal lines Vint4, the first voltage supply lines in the plurality of first voltage supply lines Vdd1, and the data lines in the plurality of data lines DL located in the region intersecting with the first anode AD1 are equally spaced.

[0182] In another example, portions of the fourth reset signal lines in the plurality of fourth reset signal lines Vint4, the first voltage supply lines in the plurality of first voltage supply lines Vdd1, and the data lines in the plurality of data lines DL located in the region intersecting with the first anode AD1 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry about a plane perpendicular to and intersecting with the first anode AD1.

[0183] In another example, in the region where a portion of the fourth reset signal line in the plurality of fourth reset signal lines Vint4, the first voltage supply line in the plurality of first voltage supply lines Vdd1, and the data line in the plurality of data lines DL intersects with the first anode AD1, the first voltage supply line in the plurality of first voltage supply lines Vdd1 separates the fourth reset signal line in the plurality of fourth reset signal lines Vint4 from the data line in the plurality of data lines DL.

[0184] The inventors of this disclosure have discovered that by setting a fine structure for the anode and signal lines according to this disclosure, a flat surface of the planarization layer beneath the first anode AD1 can be achieved. Therefore, color shift problems can be mitigated.

[0185] In some embodiments, the array substrate includes a first sub-pixel opening SA1 that extends through the pixel defining layer and exposes a portion of the first anode AD1. In some embodiments, the fourth reset signal line in the plurality of fourth reset signal lines Vint4, the first voltage supply line in the plurality of first voltage supply lines Vdd1, and the data line in the plurality of data lines DL intersect the first sub-pixel opening SA1.

[0186] In some embodiments, the fourth reset signal lines in the plurality of fourth reset signal lines Vint4, the first voltage supply lines in the plurality of first voltage supply lines Vdd1, and the data lines in the plurality of data lines DL are substantially uniformly distributed relative to the first sub-pixel opening SA1 along the first direction DR1.

[0187] For example, the portions of the fourth reset signal lines in the plurality of fourth reset signal lines Vint4, the first voltage supply lines in the plurality of first voltage supply lines Vdd1, and the data lines in the plurality of data lines DL located in the region intersecting with the first sub-pixel opening SA1 are equally spaced.

[0188] In another example, portions of the fourth reset signal line in the plurality of fourth reset signal lines Vint4, the first voltage supply line Vdd1 in the plurality of first voltage supply lines, and the data lines in the plurality of data lines DL located in the region intersecting with the first sub-pixel opening SA1 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry with respect to a plane perpendicular to the first anode AD1 and intersecting with the first sub-pixel opening SA1.

[0189] In another example, in the region where portions of the fourth reset signal lines in the plurality of fourth reset signal lines Vint4, the first voltage supply lines in the plurality of first voltage supply lines Vdd1, and the data lines in the plurality of data lines DL intersect with the first sub-pixel opening SA1, the first voltage supply lines in the plurality of first voltage supply lines Vdd1 space the fourth reset signal lines in the plurality of fourth reset signal lines Vint4 from the data lines in the plurality of data lines DL.

[0190] The inventors of this disclosure have discovered that by setting a fine structure for the anode and signal lines according to this disclosure, a flat surface of the planarization layer beneath the first anode AD1 can be achieved. Therefore, color shift problems can be mitigated.

[0191] In some embodiments, the first adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1, the third reset signal line in the plurality of third reset signal lines Vint3, the data line in the plurality of data lines DL, and the second adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 respectively cross the second anode AD2.

[0192] In another example, portions of the first adjacent first voltage supply lines in the plurality of first voltage supply lines Vdd1, the third reset signal lines in the plurality of third reset signal lines Vint3, the data lines in the plurality of data lines DL, and the second adjacent first voltage supply lines in the plurality of first voltage supply lines Vdd1 located in the region intersecting with the second anode AD2 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry with respect to a plane perpendicular to and intersecting with the second anode AD2.

[0193] In another example, in the region where a portion of a first adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1, a third reset signal line in a plurality of third reset signal lines Vint3, a data line in a plurality of data lines DL, and a portion of a second adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1 intersects with the second anode AD2, the third reset signal line in a plurality of third reset signal lines Vint3 and the data line in a plurality of data lines DL space the first adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1 from the second adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1.

[0194] The inventors of this disclosure have discovered that by setting a fine structure for the anode and signal lines according to this disclosure, a flat surface of the planarization layer beneath the second anode AD2 can be achieved. Therefore, color shift problems can be mitigated.

[0195] In some embodiments, the array substrate includes a second sub-pixel opening SA2 that extends through the pixel defining layer and exposes a portion of the second anode AD2. In some embodiments, a first adjacent first voltage supply line among a plurality of first voltage supply lines Vdd1, a third reset signal line among a plurality of third reset signal lines Vint3, a data line among a plurality of data lines DL, and a second adjacent first voltage supply line among a plurality of first voltage supply lines Vdd1 intersect the second sub-pixel opening SA2.

[0196] In another example, portions of the first adjacent first voltage supply lines in the plurality of first voltage supply lines Vdd1, the third reset signal lines in the plurality of third reset signal lines Vint3, the data lines in the plurality of data lines DL, and the second adjacent first voltage supply lines in the plurality of first voltage supply lines Vdd1 located in the region intersecting with the second sub-pixel opening SA2 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry with respect to a plane perpendicular to the second anode AD2 and intersecting with the second sub-pixel opening SA2.

[0197] In another example, in the region where a portion of a first adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1, a third reset signal line in a plurality of third reset signal lines Vint3, a data line in a plurality of data lines DL, and a portion of a second adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1 intersects with a second sub-pixel opening SA2, the third reset signal line in a plurality of third reset signal lines Vint3 and the data line in a plurality of data lines DL space the first adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1 from the second adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1.

[0198] The inventors of this disclosure have discovered that by setting a fine structure for the anode and signal lines according to this disclosure, a flat surface of the planarization layer beneath the second anode AD2 can be achieved. Therefore, color shift problems can be mitigated.

[0199] In some embodiments, the first adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1, the third reset signal line in the plurality of third reset signal lines Vint3, the data line in the plurality of data lines DL, and the second adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 respectively cross the third anode AD3.

[0200] In another example, portions of the first adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1, the third reset signal line in the plurality of third reset signal lines Vint3, the data lines in the plurality of data lines DL, and the second adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 located in the region intersecting with the third anode AD3 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry about a plane perpendicular to and intersecting with the third anode AD3.

[0201] In another example, in the region where a portion of a first adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1, a third reset signal line in a plurality of third reset signal lines Vint3, a data line in a plurality of data lines DL, and a portion of a second adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1 intersects with a third anode AD3, the third reset signal line in a plurality of third reset signal lines Vint3 and the data line in a plurality of data lines DL space the first adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1 from the second adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1.

[0202] The inventors of this disclosure have discovered that by setting a fine structure for the anode and signal lines according to this disclosure, a flat surface of the planarization layer beneath the third anode AD3 can be achieved. Therefore, color shift problems can be mitigated.

[0203] In some embodiments, the array substrate includes a third sub-pixel opening SA3 that extends through the pixel defining layer and exposes a portion of a third anode AD3. In some embodiments, a first adjacent first voltage supply line among a plurality of first voltage supply lines Vdd1, a third reset signal line among a plurality of third reset signal lines Vint3, a data line among a plurality of data lines DL, and a second adjacent first voltage supply line among a plurality of first voltage supply lines Vdd1 intersect the third sub-pixel opening SA3.

[0204] In another example, portions of the first adjacent first voltage supply lines in the plurality of first voltage supply lines Vdd1, the third reset signal lines in the plurality of third reset signal lines Vint3, the data lines in the plurality of data lines DL, and the second adjacent first voltage supply lines in the plurality of first voltage supply lines Vdd1 located in the region intersecting with the third sub-pixel opening SA3 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry with respect to a plane perpendicular to the third anode AD3 and intersecting with the third sub-pixel opening SA3.

[0205] In another example, in the region where a portion of a first adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1, a third reset signal line in a plurality of third reset signal lines Vint3, a data line in a plurality of data lines DL, and a portion of a second adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1 intersects with a third sub-pixel opening SA3, the third reset signal line in a plurality of third reset signal lines Vint3 and the data line in a plurality of data lines DL space the first adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1 from the second adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1.

[0206] The inventors of this disclosure have discovered that by setting a fine structure for the anode and signal lines according to this disclosure, a flat surface of the planarization layer beneath the third anode AD3 can be achieved. Therefore, color shift problems can be mitigated.

[0207] Figure 10A This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 10B It is shown Figure 10A The diagram depicts the arrangement of multiple pixel driving circuits in an array substrate. Figure 10C It is shown Figure 10A A schematic diagram depicting the structure of the semiconductor material layer in the array substrate. Figure 10D It is shown Figure 10A A schematic diagram of the first conductive layer structure of the array substrate is depicted. Figure 10E It is shown Figure 10A A schematic diagram of the structure of the second conductive layer in the array substrate is depicted. Figure 10F It is shown Figure 10A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate is depicted. Figure 10G It is shown Figure 10A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in the figure. Figure 10H It is shown Figure 10A A schematic diagram of the structure of the first planarization layer of the array substrate is depicted. Figure 10I It is shown Figure 10AA schematic diagram of the structure of the second signal line layer in the array substrate is depicted. Figure 10J It is shown Figure 10A A schematic diagram of the structure of the second planarization layer of the array substrate is depicted. Figure 10K It is shown Figure 10A A schematic diagram of the structure of the anode layer in the array substrate is depicted. Figure 10L It is shown Figure 10A A schematic diagram depicting the structure of the pixel-defining layer in the array substrate. (Refer to...) Figures 10A to 10L In some embodiments, the first voltage supply lines among the plurality of first voltage supply lines Vdd1 include branches connected to the body of the first voltage supply line. In some embodiments, the second signal line layer does not include a plurality of third reset signal lines and a plurality of fourth reset signal lines. The inventors of this disclosure have discovered that by making the first voltage supply lines branched, a flat surface of the planarization layer below the anode can be achieved.

[0208] In some embodiments, a first adjacent first voltage supply line among a plurality of first voltage supply lines Vdd1 includes a first body MB1 and a first branch LB1 connected to the first body MB1; a second adjacent first voltage supply line among a plurality of first voltage supply lines Vdd1 includes a second body MB2 and a second branch LB2 connected to the second body MB2. Figure 10M The diagram illustrates the layout of signal lines in a second signal line layer and an anode layer in a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 10I and Figure 10M In some embodiments, the orthographic projection of the anode on the substrate at least partially overlaps with the orthographic projection of the main body of the first voltage supply line in the plurality of first voltage supply lines Vdd1 on the substrate; at least partially overlaps with the orthographic projection of the branch in the first voltage supply line on the substrate; and at least partially overlaps with the orthographic projection of the data line in the plurality of data lines DL on the substrate.

[0209] In some embodiments, the orthographic projection of the first anode AD1 on the substrate at least partially overlaps with the orthographic projection of the data lines in the plurality of data lines DL on the substrate; at least partially overlaps with the orthographic projection of the first body MB1 of the first adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 on the substrate; and at least partially overlaps with the orthographic projection of the first branch LB1 of the first adjacent first voltage supply line on the substrate.

[0210] In some embodiments, the orthographic projection of the second anode AD2 on the substrate at least partially overlaps with the orthographic projection of the second body MB2 of the second adjacent first voltage supply line among the plurality of first voltage supply lines Vdd1 on the substrate; at least partially overlaps with the orthographic projection of the second branch LB2 of the second adjacent first voltage supply line on the substrate; at least partially overlaps with the orthographic projection of the data line among the plurality of data lines DL on the substrate; and at least partially overlaps with the orthographic projection of the third adjacent first voltage supply line among the plurality of first voltage supply lines Vdd1 on the substrate.

[0211] In some embodiments, the orthographic projection of the third anode AD3 on the substrate at least partially overlaps with the orthographic projection of the second body MB2 of the second adjacent first voltage supply line among the plurality of first voltage supply lines Vdd1 on the substrate; at least partially overlaps with the orthographic projection of the second branch LB2 of the second adjacent first voltage supply line on the substrate; at least partially overlaps with the orthographic projection of the data line among the plurality of data lines DL on the substrate; and at least partially overlaps with the orthographic projection of the third adjacent first voltage supply line among the plurality of first voltage supply lines Vdd1 on the substrate.

[0212] In this disclosure, by at least partially overlapping the orthographic projection of the anode on the substrate with the orthographic projection of the branch on the substrate; at least partially overlapping the orthographic projection of the main body of the first voltage supply line in the plurality of first voltage supply lines Vdd1 on the substrate; and at least partially overlapping the orthographic projection of the data line in the plurality of data lines DL on the substrate, the array substrate achieves a flat surface of the planarization layer below the anode. Therefore, color shift problems can be mitigated.

[0213] In some embodiments, the data lines in the plurality of data lines DL, the first body MB1 of the first voltage supply line in the plurality of first voltage supply lines Vdd1, and the first branch LB1 of the first voltage supply line intersect the first anode AD1. In some embodiments, the data lines in the plurality of data lines DL, the first body MB1 of the first voltage supply line, and the first branch LB1 of the first voltage supply line are substantially uniformly distributed relative to the first anode AD1 along a first direction DR1. For example, the portions of the data lines in the plurality of data lines DL, the first body MB1 of the first voltage supply line, and the first branch LB1 of the first voltage supply line located in the region intersecting with the first anode AD1 are equally spaced. In another example, the portions of the data lines in the plurality of data lines DL, the first body MB1 of the first voltage supply line, and the first branch LB1 of the first voltage supply line located in the region intersecting with the first anode AD1 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry about a plane perpendicular to and intersecting with the first anode AD1. In another example, in the region where portions of the data lines in the plurality of data lines DL, the first body MB1 of the first voltage supply line, and the first branch LB1 of the first voltage supply line intersect with the first anode AD1, the first body MB1 of the first voltage supply line separates the data lines in the plurality of data lines DL from the first branch LB1 of the first voltage supply line. The inventors of this disclosure have discovered that by providing a unique structure for the anode and signal lines according to this disclosure, a flat surface of the planarization layer beneath the first anode AD1 can be achieved. Therefore, color shift problems can be mitigated.

[0214] In some embodiments, the array substrate includes a first sub-pixel opening SA1 that extends through the pixel defining layer and exposes a portion of the first anode AD1. In some embodiments, data lines in a plurality of data lines DL, a first body MB1 of a first voltage supply line in a plurality of first voltage supply lines Vdd1, and a first branch LB1 of a first voltage supply line intersect the first sub-pixel opening SA1. In some embodiments, the data lines in the plurality of data lines DL, the first body MB1 of the first voltage supply line, and the first branch LB1 of the first voltage supply line are substantially uniformly distributed relative to the first sub-pixel opening SA1 along a first direction DR1. For example, the portions of the data lines in the plurality of data lines DL, the first body MB1 of the first voltage supply line, and the first branch LB1 of the first voltage supply line located in the region intersecting the first sub-pixel opening SA1 are equally spaced. In another example, portions of the data lines in the plurality of data lines DL, the first body MB1 of the first voltage supply line, and the first branch LB1 of the first voltage supply line located in the region intersecting with the first sub-pixel opening SA1 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry relative to a plane perpendicular to the first anode AD1 and intersecting with the first sub-pixel opening SA1. In another example, in the region where portions of the data lines in the plurality of data lines DL, the first body MB1 of the first voltage supply line, and the first branch LB1 of the first voltage supply line intersect with the first sub-pixel opening SA1, the first body MB1 of the first voltage supply line spaces the data lines in the plurality of data lines DL from the first branch LB1 of the first voltage supply line. The inventors of this disclosure have discovered that by providing a fine structure of the anode and signal lines according to this disclosure, a flat surface of the planarization layer beneath the first anode AD1 can be achieved. Therefore, color shift problems can be mitigated.

[0215] In some embodiments, the second body MB2 of a second adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1, the second branch LB2 of a second adjacent first voltage supply line, the data lines in the plurality of data lines DL, and the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 intersect the second anode AD2. In another example, the portions of the second body MB2 of the second adjacent first voltage supply line, the second branch LB2 of the second adjacent first voltage supply line, the data lines in the plurality of data lines DL, and the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 located in the region intersecting the second anode AD2 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry with respect to a plane perpendicular to and intersecting the second anode AD2. In another example, in the region where the second body MB2 of the second adjacent first voltage supply line, the second branch LB2 of the second adjacent first voltage supply line, the data lines in the plurality of data lines DL, and a portion of the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 intersect with the second anode AD2, the second branch LB2 of the second adjacent first voltage supply line and the data lines in the plurality of data lines DL space the second body MB2 of the second adjacent first voltage supply line from the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1. The inventors of this disclosure have discovered that by providing a fine structure for the anode and signal lines according to this disclosure, a flat surface of the planarization layer beneath the second anode AD2 can be achieved. Therefore, color shift problems can be mitigated.

[0216] In some embodiments, the array substrate includes a second sub-pixel opening SA2 that extends through the pixel defining layer and exposes a portion of the second anode AD2. In some embodiments, a second body MB2 of a second adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1, a second branch LB2 of a second adjacent first voltage supply line, a data line in a plurality of data lines DL, and a third adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1 intersect the second sub-pixel opening SA2. In another example, portions of the second body MB2 of the second adjacent first voltage supply line, the second branch LB2 of the second adjacent first voltage supply line, the data line in the plurality of data lines DL, and the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 located in the region intersecting the second sub-pixel opening SA2 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry with respect to a plane perpendicular to the second anode AD2 and intersecting the second sub-pixel opening SA2. In another example, in the region where the second body MB2 of the second adjacent first voltage supply line, the second branch LB2 of the second adjacent first voltage supply line, the data lines in the plurality of data lines DL, and a portion of the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 intersect with the second sub-pixel opening SA2, the second branch LB2 of the second adjacent first voltage supply line and the data lines in the plurality of data lines DL space the second body MB2 of the second adjacent first voltage supply line from the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1. The inventors of this disclosure have discovered that by setting a fine structure for the anode and signal lines according to this disclosure, a flat surface of the planarization layer beneath the second anode AD2 can be achieved. Therefore, color shift problems can be mitigated.

[0217] In some embodiments, the second body MB2 of the second adjacent first voltage supply line, the second branch LB2 of the second adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1, the data lines in the plurality of data lines DL, and the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 respectively intersect with the third anode AD3. In another example, the portions of the second body MB2 of the second adjacent first voltage supply line, the second branch LB2 of the second adjacent first voltage supply line, the data lines in the plurality of data lines DL, and the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 located in the region intersecting with the third anode AD3 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry with respect to a plane perpendicular to and intersecting with the third anode AD3. In another example, in the region where the second body MB2 of the second adjacent first voltage supply line, the second branch LB2 of the second adjacent first voltage supply line, the data lines in the plurality of data lines DL, and a portion of the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 intersect with the third anode AD3, the second branch LB2 of the second adjacent first voltage supply line and the data lines in the plurality of data lines DL space the second body MB2 of the second adjacent first voltage supply line from the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1. The inventors of this disclosure have discovered that by providing a fine structure for the anode and signal lines according to this disclosure, a flat surface of the planarization layer beneath the third anode AD3 can be achieved. Therefore, color shift problems can be mitigated.

[0218] In some embodiments, the array substrate includes a third sub-pixel opening SA3 that extends through the pixel defining layer and exposes a portion of the third anode AD3. In some embodiments, the second body MB2 of a second adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1, the second branch LB2 of a second adjacent first voltage supply line, the data lines in a plurality of data lines DL, and the third adjacent first voltage supply line in a plurality of first voltage supply lines Vdd1 each intersect the third sub-pixel opening SA3. In another example, portions of the second body MB2 of the second adjacent first voltage supply line, the second branch LB2 of the second adjacent first voltage supply line, the data lines in the plurality of data lines DL, and the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 located in the region intersecting the third sub-pixel opening SA3 have a substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, or at least 99%) mirror symmetry with respect to a plane perpendicular to the third anode AD3 and intersecting the third sub-pixel opening SA3. In another example, in the region where the second body MB2 of the second adjacent first voltage supply line, the second branch LB2 of the second adjacent first voltage supply line, the data lines in the plurality of data lines DL, and a portion of the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1 intersect with the third sub-pixel opening SA3, the second branch LB2 of the second adjacent first voltage supply line and the data lines in the plurality of data lines DL space the second body MB2 of the second adjacent first voltage supply line from the third adjacent first voltage supply line in the plurality of first voltage supply lines Vdd1. The inventors of this disclosure have discovered that by setting a fine structure for the anode and signal lines according to this disclosure, a flat surface of the planarization layer beneath the third anode AD3 can be achieved. Therefore, color shift problems can be mitigated.

[0219] Figure 10N The structure of various first voltage supply lines according to some embodiments of the present disclosure is shown. (Refer to...) Figure 10N In some embodiments, each first voltage supply line includes a main body MB and a branch LB connected to the main body MB. The branch LB includes one or more connectors CP and a support portion SP. The support portion SP is spaced apart from the main body MB. The one or more connectors CP connect the support portion SP to the main body MB.

[0220] Reference Figure 5IIn some embodiments, each of the plurality of fourth reset signal lines Vint4 includes a first portion P1, a second portion P2, a third portion P3, and a fourth portion P4. The second portion P2 connects the first portion P1 and the third portion P3. The third portion P3 connects the second portion P2 and the fourth portion P4. The first portion P1 and the fourth portion P4 extend along a direction substantially parallel to the second direction DR2. The second portion P2 and the third portion P3 extend along a direction neither parallel to the first direction DR1 nor parallel to the second direction DR2. At least one of the second portion P2 or the third portion P3 is connected to a second connection line Cl2 in the first signal line layer. Optionally, each of the plurality of fourth reset signal lines Vint4 is located in a second signal line layer, which is located on the side of the first signal line layer away from the substrate.

[0221] Figure 11A The layout of signal lines in a semiconductor material layer and a second conductive layer in a portion of an array substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figure 11A , Figure 3A , Figure 3C , Figure 3E , Figure 3G , Figure 5C , Figure 5E , Figure 5G In some embodiments, the array substrate further includes an anti-interference block IPB. Optionally, the anti-interference block IPB is located in the second conductive layer. Optionally, the anti-interference block IPB and the second capacitor electrode Ce2 are located in the same layer. Optionally, the anti-interference block IPB is connected to a corresponding second voltage supply line among a plurality of second voltage supply lines Vdd2. Optionally, the anti-interference block IPB is configured to receive a first reference voltage signal. Optionally, the first reference voltage signal is a constant voltage signal, for example, a high reference voltage signal.

[0222] In some embodiments, the orthographic projection of the anti-interference block IPB onto the substrate at least partially overlaps with the orthographic projection of the portion of the semiconductor material layer located between the two active layer portions (e.g., the two channel portions) of the third transistor T3 onto the substrate. The inventors of this disclosure have found that this unique structure enhances the stability of the third transistor T3.

[0223] Figure 11B The layout of signal lines in a second conductive layer, a first signal line layer, and a second signal line layer in a portion of an array substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figure 11B , Figure 3A , Figure 3C , Figure 3E , Figure 3G and Figure 3IIn some embodiments, the orthographic projection of the anti-interference block IPB on the substrate spaced apart from the orthographic projection of the node connection line Cln on the substrate and the orthographic projection of the corresponding data line among the plurality of data lines DL on the substrate. The corresponding data lines are configured to provide data signals to a pixel driving circuit including the anti-interference block IPB and the node connection line Cln. Specifically, the orthographic projection of the anti-interference block IPB on the substrate spaced apart from the orthographic projection of a portion of the node connection line Cln on the substrate and the orthographic projection of the corresponding data line among the plurality of data lines DL, the portion extending through a via (e.g., Figure 4A The second via (v2) is connected to the first electrode of the third transistor. The node connection line Cln (including the portion extending through the via to connect to the first electrode of the third transistor) can be considered as the first node N1. The inventors of this disclosure have discovered that this unique structure can reduce interference from data signals from the corresponding data lines to the node connection line Cln (e.g., the first node N1).

[0224] Figure 11C The structure of an anti-interference block according to some embodiments of this disclosure is shown. (Refer to...) Figure 11C In some embodiments, the anti-interference block IPB includes a main body pad MPP, a first extension E1, and a second extension E2. The first extension E1 and the second extension E2 extend away from the main body pad MPP along a direction substantially parallel to the second direction DR2. The main body pad MPP connects the first extension E1 and the second extension E2. In some embodiments, reference is made to... Figure 11A and Figure 11C The orthographic projection of the first extension E1 on the substrate at least partially overlaps with the orthographic projection of the portion of the semiconductor material layer located between the two active layer portions (e.g., the two channel portions) of the third transistor T3 on the substrate. Optionally, the orthographic projection of the second extension E2 on the substrate does not overlap with the orthographic projection of the portion of the semiconductor material layer located between the two active layer portions (e.g., the two channel portions) of the third transistor T3 on the substrate.

[0225] Reference Figure 11B and Figure 11C In some embodiments, the second extension E2 overlaps with the node connection line Cln along the second direction DR2. The second extension E2 spaces the node connection line Cln from the data lines in the plurality of data lines DL. Optionally, the data lines in the plurality of data lines DL are data lines connected to a pixel driving circuit including the node connection line Cln. The inventors of this disclosure have discovered that this unique structure minimizes interference of the data lines to the node connection line Cln (corresponding to the first node N1).

[0226] Figure 12The layout of signal lines in the semiconductor material layer and the anode layer in a portion of an array substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figure 12 In some embodiments, the orthographic projection of the anode layer onto the substrate at least partially overlaps with the orthographic projection of at least one active layer portion (e.g., two channel portions) of the third transistor T3 onto the substrate. Optionally, the orthographic projection of the anode layer onto the substrate substantially covers (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely covers) the orthographic projection of at least one active layer portion of the third transistor T3 onto the substrate. The inventors of this disclosure have discovered that by providing this unique structure, at least one active layer portion of the third transistor T3 can be at least partially protected from (e.g., ambient light) illumination. This can enhance the stability of the third transistor.

[0227] In some embodiments, the two active layer portions of the third transistor T3 include a first active layer portion (e.g., a first channel portion) and a second active layer portion (e.g., a second channel portion). Optionally, the first active layer portion is connected to the second electrode D3 of the third transistor T3, and the second active layer portion is connected to the first electrode S3 of the third transistor T3. Optionally, the orthographic projection of the anode layer on the substrate substantially covers the orthographic projection of the first active layer portion of the third transistor T3 on the substrate.

[0228] In some embodiments, the anode layer includes a first anode AD1, a second anode AD2, and a third anode AD3. In one example, the first anode AD1 is the anode of a first-color light-emitting element; the second anode AD2 is the anode of a second-color light-emitting element; and the third anode AD3 is the anode of a third-color light-emitting element. In another example, the first, second, and third colors are three different colors selected from red, green, and blue.

[0229] In some embodiments, the orthographic projection of the first anode AD1 onto the substrate substantially covers the orthographic projection of the first active layer portion (e.g., the first channel portion) of the third transistor T3 in the first pixel driving circuit onto the substrate.

[0230] In some embodiments, the orthogonal projection of the second anode AD2 onto the substrate substantially covers the orthogonal projection of the first active layer portion (e.g., the first channel portion) of the third transistor T3 in the second pixel driving circuit onto the substrate; and substantially covers the orthogonal projection of the first active layer portion (e.g., the first channel portion) of the third transistor T3 in the third pixel driving circuit onto the substrate. Optionally, the second pixel driving circuit and the third pixel driving circuit are respectively located in two adjacent columns of pixel driving circuits. Optionally, the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit are respectively located in three adjacent columns of pixel driving circuits.

[0231] In some embodiments, the orthographic projection of the third anode AD3 onto the substrate does not overlap with the orthographic projection of the active layer of the third transistor T3 in any pixel driving circuit onto the substrate.

[0232] Reference Figure 3C In some embodiments, the active layer ACTd driving the transistor Td is inverted S-shaped. The inventors of this disclosure have discovered that this unique structure allows for longer channel lengths. Various suitable alternative implementations can be practiced. Figure 13 This is a schematic diagram illustrating the structure of a semiconductor material layer in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 13 The active layer ACTd of the driving transistor Td is P-shaped.

[0233] Figure 14 This is a schematic diagram illustrating the structure of a semiconductor material layer in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 14 In some embodiments, the active layer ACTd of the driving transistor Td is zig-zag. The inventors of this disclosure have discovered that this unique structure results in an increased channel length for the driving transistor and a reduced leakage current.

[0234] On the other hand, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0235] On the other hand, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a plurality of sub-pixels. Optionally, forming a plurality of sub-pixels includes: forming a first sub-pixel. Optionally, forming the first sub-pixel includes: forming a second conductive layer on a substrate, and forming an anode layer on a side of the second conductive layer away from the substrate. Optionally, forming the anode layer includes: forming a first anode in the first sub-pixel. Optionally, forming the second conductive layer includes: forming a first signal line and forming a second signal line, the first signal line and the second signal line extending along a direction substantially parallel to a second direction, respectively. Optionally, forming the second signal line includes: forming a body extending along a direction substantially parallel to the second direction, and forming a branch connected to the body, the branch being located on a side of the body away from the first signal line along a direction substantially parallel to the first direction, the first direction and the second direction intersecting each other. Optionally, the branch is located on the side of the body away from the first signal line. Optionally, the orthographic projection of the first anode on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate, at least partially overlaps with the orthographic projection of the body on the substrate, and at least partially overlaps with the orthographic projection of the branch on the substrate.

[0236] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate comprising a plurality of sub-pixels; in, The plurality of sub-pixels includes a first sub-pixel; The array substrate further includes a substrate, a second conductive layer on the substrate, and an anode layer on the side of the second conductive layer away from the substrate. The anode layer includes a first anode in the first sub-pixel; The second conductive layer includes a first signal line and a second signal line extending in a direction substantially parallel to the second direction; "substantially parallel" means the angle is between 0 and 15 degrees. The second signal line includes a body extending in a direction substantially parallel to the second direction and a branch connected to the body, the branch being located on a side of the body away from the first signal line in a direction substantially parallel to the first direction, the first direction and the second direction intersecting each other; as well as The orthographic projection of the first anode on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate, at least partially overlaps with the orthographic projection of the body on the substrate, and at least partially overlaps with the orthographic projection of the branch on the substrate; It also includes a first reset signal network and a second reset signal network, and includes a first column pixel driving circuit, a second column pixel driving circuit and a third column pixel driving circuit that are adjacent to each other; The first reset signal network includes a plurality of first reset signal lines and a plurality of third reset signal lines interconnected with each other; The second reset signal network includes a plurality of second reset signal lines and a plurality of fourth reset signal lines interconnected with each other; The third reset signal line of the plurality of third reset signal lines exists in the first column pixel driving circuit, and the plurality of third reset signal lines do not exist in the second column pixel driving circuit; The fourth reset signal line of the plurality of fourth reset signal lines exists in the second column pixel driving circuit, and the plurality of fourth reset signal lines do not exist in the first column pixel driving circuit; and The plurality of third reset signal lines and the plurality of fourth reset signal lines are not present in the third column pixel driving circuit; The first column pixel driving circuit is configured to drive the first column of sub-pixels of the first color to emit light; The second column pixel driving circuit is configured to drive the second column of sub-pixels of the second color to emit light; The third column pixel driving circuit is configured to drive the third column of sub-pixels of the third color to emit light; the first color, the second color, and the third color are different colors; The branch includes a support portion and one or more connecting portions; the support portion is spaced apart from the main body; the one or more connecting portions connect the support portion to the main body.

2. The array substrate according to claim 1, comprising a plurality of first voltage supply lines and a plurality of data lines; in, The first signal line is one of the plurality of data lines; and The second signal line is one of the plurality of first voltage supply lines; Wherein, the first adjacent first voltage supply line among the plurality of first voltage supply lines includes a first body and a first branch connected to the first body; The orthographic projection of the first anode on the substrate at least partially overlaps with the orthographic projection of the data line among the plurality of data lines on the substrate; at least partially overlaps with the orthographic projection of the first body on the substrate; and at least partially overlaps with the orthographic projection of the first branch on the substrate; and The portions of the data line, the first body, and the first branch located in the region intersecting with the first anode have a basic mirror symmetry with respect to a plane perpendicular to and intersecting the first anode, wherein the basic mirror symmetry means at least 90% mirror symmetry.

3. The array substrate according to claim 1, wherein, The plurality of first reset signal lines and the plurality of second reset signal lines are located in the same conductive layer; The plurality of third reset signal lines and the plurality of fourth reset signal lines are located on the same layer and on the side of the same conductive layer away from the substrate.

4. The array substrate according to any one of claims 1 to 3, wherein, The pixel driving circuit of the array substrate is arranged in K columns including the (3k-2)th column, the (3k-1)th column and the (3k)th column, where K and k are positive integers, 1≤k≤(K / 3); The third reset signal line of the plurality of third reset signal lines exists in the pixel driving circuit of the (3k-2)th column, and the plurality of third reset signal lines do not exist in the pixel driving circuit of the (3k)th column; The fourth reset signal line of the plurality of fourth reset signal lines exists in the pixel driving circuit of the (3k)th column, and the plurality of fourth reset signal lines do not exist in the pixel driving circuit of the (3k-2)th column; as well as The plurality of third reset signal lines and the plurality of fourth reset signal lines are not present in the pixel driving circuit of the (3k-1)th column.

5. The array substrate according to any one of claims 1 to 3, wherein, The pixel driving circuit in the second column pixel driving circuit includes a first connecting line, which connects the first electrode of the first reset transistor to the first reset signal line among the plurality of first reset signal lines; The pixel driving circuit in the first column of pixel driving circuits includes a second connecting line, which connects the first electrode of the second reset transistor to the second reset signal line among the plurality of second reset signal lines; The pixel driving circuit in the third column pixel driving circuit includes a first connecting line and a second connecting line. The first connecting line connects the first electrode of the first reset transistor to the first reset signal line among the plurality of first reset signal lines, and the second connecting line connects the first electrode of the second reset transistor to the second reset signal line among the plurality of second reset signal lines. The first column pixel driving circuit does not include a first connection line, and the third reset signal line connects the first electrode of the first reset transistor to the first reset signal line among the plurality of first reset signal lines; and The second column pixel driving circuit does not include a second connection line, and the fourth reset signal line connects the first electrode of the second reset transistor to the second reset signal line among the plurality of second reset signal lines.

6. The array substrate according to any one of claims 1 to 3, wherein, Each pixel driving circuit includes a first connection line and a second connection line. The first connection line connects the first electrode of the first reset transistor to the first reset signal line among the plurality of first reset signal lines, and the second connection line connects the first electrode of the second reset transistor to the second reset signal line among the plurality of second reset signal lines. In the first column pixel driving circuit, the third reset signal line is connected to the first reset signal line among the plurality of first reset signal lines through the first connection line in the pixel driving circuit of the first column pixel driving circuit; as well as In the second column pixel driving circuit, the fourth reset signal line is connected to the second reset signal line among the plurality of second reset signal lines through the second connection line in the pixel driving circuit of the second column pixel driving circuit.

7. The array substrate according to any one of claims 1 to 3, wherein, The orthographic projection of the first anode on the substrate at least partially overlaps with the orthographic projection of the fourth reset signal line among the plurality of fourth reset signal lines on the substrate; The first voltage supply line of the plurality of first voltage supply lines at least partially overlaps with the orthographic projection of the first voltage supply line on the substrate. And its orthogonal projection on the substrate at least partially overlaps with that of the data lines in the plurality of data lines; as well as The portions of the fourth reset signal line, the first voltage supply line, and the data line located in the region intersecting with the first anode have a basic mirror symmetry with respect to a plane perpendicular to and intersecting the first anode, wherein the basic mirror symmetry means at least 90% mirror symmetry.

8. The array substrate according to claim 7, wherein, In the region where the fourth reset signal line, the first voltage supply line, and a portion of the data line intersect with the first anode, the first voltage supply line separates the fourth reset signal line from the data line.

9. The array substrate according to claim 7, wherein, In the region where portions of the fourth reset signal line, the first voltage supply line, and the data line intersect with the first anode, the fourth reset signal line and the data line have a substantially mirror-symmetric relationship with respect to the first voltage supply line.

10. The array substrate according to any one of claims 1 to 3, further comprising a second anode; in, The orthographic projection of the second anode on the substrate at least partially overlaps with the orthographic projection of the first adjacent first voltage supply line among the plurality of first voltage supply lines on the substrate; The orthographic projection of the third reset signal line among the plurality of third reset signal lines on the substrate is at least partially overlapped; the orthographic projection of the data line among the plurality of data lines on the substrate is at least partially overlapped; and the orthographic projection of the second adjacent first voltage supply line among the plurality of first voltage supply lines on the substrate is at least partially overlapped. as well as The portions of the first adjacent first voltage supply line, the third reset signal line, the data line, and the second adjacent first voltage supply line located in the region intersecting with the second anode have a basic mirror symmetry with respect to a plane perpendicular to and intersecting with the second anode, wherein the basic mirror symmetry means at least 90% mirror symmetry.

11. The array substrate according to claim 10, wherein, In the region where the first adjacent first voltage supply line, the third reset signal line, the data line, and a portion of the second adjacent first voltage supply line intersect with the second anode, the third reset signal line and the data line space the first adjacent first voltage supply line and the second adjacent first voltage supply line apart.

12. The array substrate according to any one of claims 1 to 3, further comprising a second anode and a plurality of first voltage supply lines; in, The second adjacent first voltage supply line among the plurality of first voltage supply lines includes a second body and a second branch connected to the second body; The orthographic projection of the second anode on the substrate at least partially overlaps with the orthographic projection of the second body on the substrate, at least partially overlaps with the orthographic projection of the second branch on the substrate, at least partially overlaps with the orthographic projection of the data line among the plurality of data lines on the substrate, and at least partially overlaps with the orthographic projection of the third adjacent first voltage supply line among the plurality of first voltage supply lines on the substrate. as well as The portions of the second body, the second branch, the data line, and the third adjacent first voltage supply line located in the region intersecting with the second anode have a basic mirror symmetry with respect to a plane perpendicular to and intersecting the second anode, wherein the basic mirror symmetry means at least 90% mirror symmetry.

13. The array substrate according to claim 12, wherein, In the region where the second body, the second branch, the data line, and the third adjacent first voltage supply line intersect with the second anode, the second branch and the data line separate the second body from the third adjacent first voltage supply line.

14. The array substrate according to any one of claims 1 to 3, further comprising a second anode and a third anode; in, Each pixel driving circuit includes a compensation transistor and a driving transistor; The compensation transistor includes a first channel portion and a second channel portion, wherein the first channel portion is connected to a second electrode of the compensation transistor, and the second channel portion is connected to a first electrode of the compensation transistor. The second electrode of the compensation transistor is connected to the gate of the driving transistor; as well as The orthographic projection of the first anode onto the substrate substantially covers the orthographic projection of the first channel portion of the compensation transistor in the first pixel driving circuit onto the substrate, wherein "substantially covers" means at least 90% coverage.

15. The array substrate according to claim 14, wherein, The orthogonal projection of the second anode onto the substrate substantially covers the orthogonal projection of the first channel portion of the compensation transistor in the second pixel driving circuit onto the substrate, and substantially covers the orthogonal projection of the first channel portion of the compensation transistor in the third pixel driving circuit onto the substrate. as well as The orthographic projection of the third anode onto the substrate does not overlap with the orthographic projection of the active layer of the compensation transistor in any pixel driving circuit onto the substrate.

16. The array substrate according to any one of claims 1 to 3, wherein, The first sub-pixel includes an anti-interference block; The anti-interference block includes a main body pad, a first extension, and a second extension; The first extension and the second extension extend away from the main body pad in a direction substantially parallel to the second direction; The main body pad connects the first extension and the second extension; The orthographic projection of the first extension on the substrate at least partially overlaps with the orthographic projection of the portion of the semiconductor material layer located between the two channel portions of the compensation transistor on the substrate; and The orthographic projection of the second extension on the substrate does not overlap with the orthographic projection of the portion of the semiconductor material layer located between the two channel portions of the compensation transistor on the substrate.

17. The array substrate according to claim 16, wherein, The first sub-pixel includes node connection lines; The node connection line connects the gate of the driving transistor and the second electrode of the compensation transistor. The second extension overlaps with the node connection line along the second direction; as well as The second extension spaced the node connection line from the data line, the data line being connected to a pixel driving circuit including the node connection line.

18. A display device comprising an array substrate according to any one of claims 1 to 17 and one or more integrated circuits connected to the array substrate.

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