Calibration detection structure and memory

Abstract

The present disclosure relates to a calibration detection structure and a memory, the calibration detection structure comprising: an identification generating module, configured to generate a first identification signal, a second identification signal and a third identification signal, wherein the first identification signal is used to indicate whether a calibration master chip or a calibration slave chip is undergoing a calibration process, the second identification signal is used to indicate whether the calibration master chip or the calibration slave chip has completed calibration, if set in the calibration master chip, the third identification signal is used to indicate whether the calibration ring to which the calibration master chip belongs has completed calibration, if set in the calibration slave chip, the third identification signal is used to indicate whether the calibration slave chip has completed calibration; a timing module, configured to generate a first count value; a trigger module, configured to generate a first error identification signal based on the first count value and the first identification signal, wherein when the first count value is a valid value and the first identification signal is a valid level, the generated first error identification signal is a valid level.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a calibration detection structure and a memory. Background Art

[0002] ZQ calibration is a crucial function in dynamic random access memory (DRAM). It determines the accuracy of the output impedance of the output port and the termination resistance of the input port. Deviations in these parameters can cause severe signal distortion during transmission due to impedance mismatch. The higher the signal frequency, the greater the impact of distortion on the signal.

[0003] The calibration of some memory chips is based on a calibration ring, in which individual chips are calibrated in sequence. However, the ring calibration design relies on the Tx end sending a pulse signal to calibrate all chips in sequence. If the pulse signal from the Tx end fails to be successfully transmitted to the next chip due to some factors, the ring structure will be disconnected and cannot be restored. Summary of the Invention

[0004] The embodiments of the present disclosure provide a calibration detection structure and a memory to monitor the calibration time of each chip performing ZQ calibration, thereby monitoring the calibration timing of the ring ZQ calibration structure to ensure the accuracy of the memory performing ZQ calibration.

[0005] An embodiment of the present disclosure provides a calibration detection structure, which is arranged in a calibration master chip and a calibration slave chip, including: an identification generation module, configured to generate a first identification signal, a second identification signal and a third identification signal, wherein the first identification signal is used to indicate whether the calibration master chip or the calibration slave chip is undergoing a calibration process, and the second identification signal is used to indicate whether the calibration master chip or the calibration slave chip has completed calibration; if it is arranged in the calibration master chip, the third identification signal is used to indicate whether the calibration ring to which the calibration master chip belongs has completed calibration; if it is arranged in the calibration slave chip, the third identification signal is used to indicate whether the calibration slave chip has completed calibration; a timing module, configured to generate a first count value; a trigger module, configured to generate a first error identification signal based on the first count value and the first identification signal, wherein when the first count value is a valid value and the first identification signal is a valid level, the generated first error identification signal is a valid level.

[0006] Based on the setting method of the trigger module, the first error identification signal is generated by judging whether the first count value and the first identification signal are valid. If the first count value is a valid value, it indicates that the current calibration time has timed out. If the first identification signal is a valid level at this time, it indicates that the chip is still performing calibration, that is, the ZQ calibration time of the chip has timed out, and there is a problem in the ZQ calibration process of the current chip, and corresponding inspection is required; by detecting the calibration time of each chip performing ZQ calibration, the ZQ calibration of each chip is guaranteed to be executed smoothly, so as to ensure the accuracy of the ZQ calibration performed by the memory.

[0007] For example, the identification generating module includes: a first identification signal generating unit, configured to generate the first identification signal; wherein, if the first identification signal is a valid level, it indicates that the calibration master chip or the calibration slave chip is performing a calibration process; if the first identification signal is an invalid level, it indicates that the calibration master chip or the calibration slave chip has not performed a calibration process; a second identification signal generating unit, configured to generate the second identification signal; wherein, if the second identification signal is a valid level, it indicates that the calibration master chip or the calibration slave chip has completed calibration; if the second identification signal is an invalid level, it indicates that the calibration master chip or the calibration slave chip has not completed calibration; a third identification signal generating unit The generating unit is configured to generate the third identification signal; wherein, if it is set in the calibration master chip, if the third identification signal is an invalid level, it indicates that the calibration ring to which the calibration master chip belongs has started to perform calibration, and if the third identification signal is a valid level, it indicates that the calibration ring to which the calibration master chip belongs has completed calibration; if it is set in the calibration slave chip, if the third identification signal is an invalid level, it indicates that the calibration slave chip has started to perform calibration, and if the third identification signal is a valid level, it indicates that the calibration slave chip has completed calibration; wherein, if the third identification signal generated by the third identification signal generating unit is a valid level, the second identification signal generated by the second identification signal generating unit is set to an invalid level.

[0008] For example, the timing module includes: n cascaded stages of D flip-flops, wherein the input end of each stage of the D flip-flop is used to receive the inverted signal output by the output end, and the reset end is used to receive the inverted signal of the third identification signal, and n is an integer greater than 1; wherein the clock end of the first stage of the D flip-flop is used to receive the timing clock signal, the clock end of the next stage of the D flip-flop is used to receive the inverted signal output by the output end of the previous stage of the D flip-flop, and the output end of the last stage of the D flip-flop is also used to output the first count value.

[0009] For example, the timing module is further configured to generate a second count value; the trigger module is further configured to generate a second error identification signal based on the second count value and the third identification signal, wherein when the second count value is a valid value and the third identification signal is an invalid level, the generated second error identification signal is a valid level; the time when the second count value becomes a valid value is later than the time when the first count value becomes a valid value. Based on the setting method of the trigger module, by judging whether the second error identification signal is generated by the second count value and the third identification signal, if the second count value is a valid value, it indicates that the calibration time of the current calibration loop has timed out. If the third identification signal generated by the calibration master chip is a valid level at this time, it indicates that the calibration loop is still performing calibration, that is, the ZQ calibration time of the calibration loop has timed out, and there is a problem with the ZQ calibration process of the calibration loop, and corresponding inspection is required; by detecting the calibration time of the calibration ring performing ZQ calibration, the smooth execution of the ZQ calibration of the calibration loop is ensured, the accuracy of the ZQ calibration of the memory is further ensured, and the transmission of the identification signal between multiple chips is ensured.

[0010] For example, the timing module includes: n cascaded stages of D flip-flops, wherein the input end of each stage of the D flip-flop is used to receive the inverted signal output by the output end, and the reset end is used to receive the inverted signal of the third identification signal, where n is an integer greater than 1; wherein the clock end of the first stage of the D flip-flop is used to receive the timing clock signal, the clock end of the next stage of the D flip-flop is used to receive the inverted signal output by the output end of the previous stage of the D flip-flop, and the output end of the last stage of the D flip-flop is also used to output the first count value; and m cascaded stages of D flip-flops, wherein the input end of each stage of the D flip-flop is used to receive the inverted signal output by the output end, and the reset end is used to receive the inverted signal of the third identification signal, where m is an integer greater than n; wherein the clock end of the first stage of the D flip-flop is used to receive the timing clock signal, the clock end of the next stage of the D flip-flop is used to receive the inverted signal output by the output end of the previous stage of the D flip-flop, and the output end of the last stage of the D flip-flop is also used to output the second count value.

[0011] For example, the cascaded m-stage D flip-flops and the cascaded n-stage D flip-flops share some of the D flip-flops, so as to reduce the number of D flip-flops required to be set in the timing module 102 .

[0012] For example, the trigger module includes: a first AND logic circuit, one input end for receiving the first identification signal, another input end for receiving the first count value, and an output end for outputting the first error identification signal; a second AND logic circuit, one input end for receiving the third identification signal, another input end for receiving the second count value, and an output end for outputting the second error identification signal.

[0013] For example, the calibration detection structure also includes: a recovery module, which is configured to reset the third identification signal to a valid signal when the error identification signal is a valid signal, wherein, if set in the calibration master chip, the error identification signal is one of the first error identification signal and the second error identification signal, and if set in the calibration slave chip, the error identification signal is the first error identification signal.

[0014] For example, the recovery module includes: a first AND gate, one input end of which is used to receive the error identification signal, and the other input end is connected to the output end of the delay unit, the input end of the delay unit is connected to the output end of the inverter, and the input end of the inverter is used to receive the error identification signal; a second AND gate, one input end of which is connected to the output end of the first AND gate, and one input end is used to receive the first count value; an OR gate, one input end of which is connected to the output end of the second AND gate, and one input end is used to receive the third identification signal generated by the identification generation module.

[0015] For example, the calibration detection structure also includes: a first latch, configured to output a first flag signal based on the rising edge of the first error identification signal, and the first flag signal is used to characterize the calibration failure of the chip to which it belongs; a second latch, configured to output a second flag signal based on the rising edge of the second error identification signal, and the second flag signal is used to characterize the calibration failure of the calibration ring to which the calibration main chip belongs, so as to facilitate relevant staff to inquire about the monitoring status of the chip ZQ calibration.

[0016] For example, the calibration detection structure also includes: a third latch, configured to output a third flag signal based on the falling edge of the first error identification signal, and the third flag signal is used to indicate the recovery of the calibration fault of the chip to which it belongs; a fourth latch, configured to output a fourth flag signal based on the falling edge of the second error identification signal, and the fourth flag signal is used to indicate the recovery of the calibration fault of the calibration ring to which the calibration main chip belongs, so as to facilitate relevant staff to inquire about the monitoring status of the chip ZQ calibration.

[0017] For example, the calibration detection structure further includes: a signal generating module, which is used to generate the timing clock signal.

[0018] For example, the signal generating module includes: a signal generating unit, configured to generate an enable signal; wherein, if the first identification signal is a valid signal, the enable signal generated by the signal generating unit is a valid signal, and if the second identification signal is a valid signal, the enable signal generated by the signal generating unit in the calibration main chip is a valid signal; an oscillation generating unit, configured to be driven based on the enable signal to generate the timing clock signal.

[0019] For example, if it is set in the calibration master chip, the signal generating unit includes: an OR logic circuit, one input end is used to receive the inverted signal of the chip enable signal, and the other input end is used to receive the third identification signal, and the chip enable signal is used to drive the calibration master chip; an AND-NON logic circuit, one input end is used to receive the output end of the OR logic circuit, the other input end is used to receive the inverted signal of the first identification signal, and the output end is used to output the enable signal; if it is set in the calibration slave chip, the signal generating unit includes: an OR-NON logic circuit, one input end is used to receive the inverted signal of the chip enable signal, and the other input end is used to receive the third identification signal, and the chip enable signal is used to drive the current calibration slave chip.

[0020] Another embodiment of the present disclosure further provides a memory, including the calibration detection structure provided by the above embodiment, to monitor the calibration time of each chip performing ZQ calibration, thereby monitoring the calibration timing of the ring ZQ calibration structure to ensure the accuracy of the memory performing ZQ calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of the structure of a ZQ calibration ring provided in one embodiment of the present disclosure;

[0023] Figure 2 A schematic diagram of a calibration sequence for performing ZQ calibration in a ZQ calibration loop structure according to an embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of a calibration detection structure provided in one embodiment of the present disclosure;

[0025] Figure 4 A schematic diagram of the structure of an identification generation module provided in one embodiment of the present disclosure;

[0026] Figure 5 A schematic diagram of a calibration timing of a first identification signal, a second identification signal, and a third identification signal generated by an identification generation module according to an embodiment of the present disclosure;

[0027] Figure 6A schematic structural diagram of a timing module for generating a first count value provided in one embodiment of the present disclosure;

[0028] Figure 7 A schematic structural diagram of a calibration detection structure further configured to generate and detect a second count value, provided in accordance with an embodiment of the present disclosure;

[0029] Figure 8 A schematic structural diagram of a timing module for generating a first count value and a second count value provided in one embodiment of the present disclosure;

[0030] Figure 9 A schematic structural diagram of another timing module for generating a first count value and a second count value provided in an embodiment of the present disclosure;

[0031] Figure 10 A schematic diagram of the structure of a trigger module provided in one embodiment of the present disclosure;

[0032] Figure 11 A schematic diagram of the structure of a recovery module provided in one embodiment of the present disclosure;

[0033] Figure 12 A schematic structural diagram of a first latch provided in one embodiment of the present disclosure;

[0034] Figure 13 A schematic structural diagram of a third latch provided in one embodiment of the present disclosure;

[0035] Figure 14 A schematic structural diagram of a signal generating module provided in one embodiment of the present disclosure;

[0036] Figure 15 A schematic structural diagram of a signal generating unit provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] Based on the discussion of background technology, it can be seen that the calibration of some memory chips is set based on a calibration ring, and the calibration of each chip is performed in sequence. However, the ring calibration design relies on the Tx end to send a pulse signal to calibrate all chips in sequence. Once the pulse signal from the Tx end fails to be successfully transmitted to the next chip due to some factors, the ring structure will be disconnected and cannot be restored.

[0038] An embodiment of the present disclosure provides a calibration detection structure to monitor the calibration time of each chip performing ZQ calibration, thereby monitoring the calibration timing of the ring ZQ calibration structure to ensure the accuracy of ZQ calibration performed by the memory.

[0039] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0040] Figure 1 This is a schematic diagram of the structure of the ZQ calibration ring provided in this embodiment. Figure 2 A schematic diagram of the calibration timing for performing ZQ calibration in the ZQ calibration loop structure provided in this embodiment. Figure 3 This is a schematic diagram of the calibration detection structure provided in this embodiment. Figure 4 This is a schematic diagram of the structure of the identification generation module provided in this embodiment. Figure 5 A schematic diagram of the calibration timing of the first identification signal, the second identification signal, and the third identification signal generated by the identification generation module provided in this embodiment, Figure 6 This is a schematic structural diagram of a timing module for generating a first count value provided in this embodiment. Figure 7 A schematic structural diagram of a calibration detection structure provided in this embodiment for generating a second count value and performing detection, Figure 8 A schematic structural diagram of a timing module for generating a first count value and a second count value provided in this embodiment, Figure 9 This is a schematic structural diagram of another timing module for generating a first count value and a second count value provided in this embodiment. Figure 10 A schematic diagram of the structure of the trigger module provided in this embodiment, Figure 11 This is a schematic diagram of the structure of the recovery module provided in this embodiment. Figure 12 A schematic structural diagram of the first latch provided in this embodiment, Figure 13 A schematic structural diagram of the third latch provided in this embodiment, Figure 14 This is a schematic diagram of the structure of the signal generating module provided in this embodiment. Figure 15 This is a schematic diagram of the structure of the signal generating unit provided in this embodiment. The calibration detection structure provided in this embodiment is described in detail below in conjunction with the accompanying drawings, as follows: Figure 1, the ZQ calibration command is transmitted to the calibration master chip 10 and multiple calibration slave chips 20, the calibration master chip 10 starts to perform ZQ calibration based on the ZQ calibration resistor, and when the calibration master chip 10 completes the ZQ calibration, it sends an identification signal through its Tx end; the calibration slave chip 20 cascaded with the calibration master chip 10 receives the identification signal through its Rx end and performs ZQ calibration based on the ZQ calibration resistor. When the calibration slave chip 20 completes the ZQ calibration, it continues to send the identification signal through the Tx end; the calibration slave chip 20 of the next cascade receives the identification signal through the Rx end and continues to perform ZQ calibration based on the ZQ calibration resistor until the last level of calibration slave chip 20 completes the ZQ calibration. The identification signal sent by the last level of calibration slave chip 20 through the Tx end is received by the Rx end of the calibration master chip 10, indicating that all chips have been calibrated.

[0041] Specifically, the ZQ calibration of the chip includes performing pull-down (PD) calibration using a pull-down calibration resistor and performing pull-up (PU) calibration using a pull-up calibration resistor. Figure 2 Combined with Figure 1 , the calibration master chip 10 performs PD calibration based on the ZQ calibration command and the pull-down calibration resistor. When the calibration master chip 10 completes the PD calibration, it sends an identification signal through the Tx end; the calibration slave chip 20 cascaded with the calibration master chip 10 receives the identification signal through the Rx end, and performs PD calibration based on the pull-down calibration resistor. At the same time, the calibration master chip 10 performs PU calibration through the pull-up calibration resistor; when the calibration slave chip 20 completes the PD calibration, it continues to send the identification signal through the Tx end; the next cascaded calibration slave chip 20 receives the identification signal through the Rx end, and continues to perform PD calibration based on the pull-down calibration resistor. At the same time, the current calibration slave chip 20 performs PU calibration based on the pull-up calibration resistor; until the last-level calibration slave chip 20 completes the PD calibration, the identification signal sent by the last-level calibration slave chip 20 through the Tx end is received by the Rx end of the calibration master chip 10, indicating that all chips have been calibrated.

[0042] It should also be noted that the above description uses the chip's PD calibration process as an identifier, thereby sending an identification signal through the Tx end; in some examples, the chip's PU calibration process can also be used as an identifier (in this case, each chip first performs PU calibration and then performs PD calibration), thereby sending an identification signal through the Tx end; in addition, Figure 2 In the timing sequence, the consistency of the time consumption of the PU calibration process and the time consumption of the PD calibration process does not constitute a limitation of the calibration loop, but is only used to reflect the sequence of the PU calibration process and the PD calibration process.

[0043] It should be noted that Figure 1The calibration ring shown includes one standard master chip 10 and three calibration slave chips 20, which is only used to illustrate the ZQ calibration ring and does not constitute a limitation on the number of chips in the calibration ring; in specific applications, the number of calibration slave chips 20 can be an integer greater than or equal to 1, for example, 7, 15, etc.

[0044] Based on the above discussion, it can be seen that the calibration process of the ZQ calibration loop is carried out in a chain manner. When a problem occurs in the calibration process of a certain chip, it is easy to cause the next chip to be unable to perform ZQ calibration. How to ensure the accuracy of ZQ calibration in the ZQ calibration loop is a technical problem that needs to be solved urgently.

[0045] refer to Figure 3 The calibration detection structure is provided in the calibration master chip 10 and the calibration slave chip 20, and includes:

[0046] The flag generating module 101 is configured to generate a first flag signal BusyState, a second flag signal DoneState and a third flag signal IdleState.

[0047] For the first identification signal BusyState, the second identification signal DoneState and the third identification signal IdleState, the first identification signal BusyState is used to indicate whether the calibration master chip 10 or the calibration slave chip 20 is performing the calibration process, and the second identification signal DoneState is used to indicate whether the calibration master chip 10 or the calibration slave chip 20 has completed the calibration. If it is set in the calibration master chip 10, the third identification signal IdleState is used to indicate whether the calibration ring to which the calibration master chip 10 belongs has completed the calibration. If it is set in the calibration slave chip 20, the third identification signal IdleState is used to indicate whether the calibration slave chip 20 has completed the calibration.

[0048] The timing module 102 is configured to generate a first count value CalTimeOut.

[0049] The trigger module 104 is configured to generate a first error flag signal based on the first count value CalTimeOut and the first flag signal BusyState, wherein when the first count value CalTimeOut is a valid value and the first flag signal BusyState is a valid level, the generated first error flag signal is a valid level.

[0050] In the subsequent description of the present disclosure, for the first identification signal BusyState, the active level of the first identification signal BusyState is "1", and the inactive level is "0", that is, when the first identification signal BusyState is "1", the calibration master chip 10 or the calibration slave chip 20 is performing the calibration process; when the first identification signal BusyState is "0", the calibration master chip 10 or the calibration slave chip 20 is not performing the calibration process. For the second identification signal DoneState, the active level of the second identification signal DoneState is "1", and the inactive level is "0", that is, when the second identification signal DoneState is "1", the calibration master chip 10 or the calibration slave chip 20 has completed the calibration; when the second identification signal DoneState is "0", the calibration master chip 10 or the calibration slave chip 20 has not completed the calibration. For the third identification signal IdleState, the valid level of the third identification signal IdleState is "1", and the invalid level is "0", that is, when the third identification signal IdleState is "1", the calibration ring to which the calibration master chip 10 belongs has completed calibration, or the calibration slave chip 20 has completed calibration; when the third identification signal IdleState is "0", the calibration ring to which the calibration master chip 10 belongs has not completed calibration, or the calibration slave chip 20 has not completed calibration. For the first count value CalTimeOut, the valid value of the first count value CalTimeOut is "1", and the invalid value is "0". It should be noted that the above-mentioned setting of the valid level and the valid value is only used to clearly introduce the calibration detection structure disclosed in the present disclosure, and does not limit the calibration detection. In specific applications, the specific setting method of the valid level or the valid value can be based on the specific circuit setting.

[0051] The first count value CalTimeOut generated by the timing module 102 is used to indicate whether the calibration time of the calibration master chip 10 or the calibration chip 20 exceeds the preset time, wherein the calibration time of the calibration master chip 10 or the calibration chip 20 is the interval time from the current time to the start of the ZQ calibration of the calibration master chip 10 or the calibration chip 20. The preset time can be set based on the maximum time required for the chip to perform ZQ calibration. If the calibration time of the calibration master chip 10 or the calibration chip 20 exceeds the preset time, the first count value CalTimeOut generated by the timing module 102 is a valid value; if the calibration time of the calibration master chip 10 or the calibration chip 20 does not exceed the preset time, the first count value CalTimeOut generated by the timing module 102 is an invalid value.

[0052] Based on the setting method of the trigger module 104, the first error identification signal is generated by judging whether the first count value CalTimeOut and the first identification signal BusyState are generated. If the first count value CalTimeOut is a valid value, it indicates that the current calibration time has timed out. If the first identification signal BusyState is a valid level at this time, it indicates that the chip is still performing calibration, that is, the ZQ calibration time of the chip has timed out, and there is a problem with the ZQ calibration process of the current chip, and corresponding inspection is required; by detecting the calibration time for each chip to perform ZQ calibration, the ZQ calibration of each chip is ensured to be performed smoothly, thereby ensuring the accuracy of the ZQ calibration performed by the memory.

[0053] In some embodiments, reference Figure 4 , the identification generating module 101 includes:

[0054] The first flag signal generating unit 201 is configured to generate a first flag signal BusyState. Specifically, if the first flag signal BusyState is at an active level, it indicates that the calibration master chip 10 or the calibration slave chip 20 is currently performing a calibration process. If the first flag signal BusyState is at an inactive level, it indicates that the calibration master chip 10 or the calibration slave chip 20 is not currently performing a calibration process.

[0055] The second flag signal generating unit 202 is configured to generate a second flag signal DoneState. Specifically, if the second flag signal DoneState is at an active level, it indicates that the calibration master chip 10 or the calibration slave chip has completed calibration; if the second flag signal DoneState is at an inactive level, it indicates that the calibration master chip 10 or the calibration slave chip has not completed calibration.

[0056] The third identification signal generating unit 203 is configured to generate a third identification signal, IdleState. Specifically, if provided in the calibration master chip 10, if the third identification signal, IdleState, is at an active level, it indicates that the calibration loop of the calibration master chip 10 has completed calibration; if the third identification signal, IdleState, is at an inactive level, it indicates that the calibration loop of the calibration master chip 10 has begun calibration. If provided in the calibration slave chip 20, if the third identification signal, IdleState, is at an active level, it indicates that the calibration slave chip 20 has completed calibration; if the third identification signal, IdleState, is at an inactive level, it indicates that the calibration slave chip 20 has begun calibration.

[0057] If the third flag signal IdleState generated by the third flag signal generating unit 203 is at a valid level, the second flag signal DoneState generated by the second flag signal generating unit 202 is set to an invalid level.

[0058] Combine Figure 2 and Figure 5 ,for Figure 2 The calibration timing shown in FIG. 1 is a timing diagram of the first identification signal BusyState, the second identification signal DoneState and the third identification signal IdleState corresponding to the calibration master chip 10 and the calibration slave chip 20. Figure 5 shown.

[0059] For the timing module 102, refer to Figure 6 In one example, the timing module 102 includes: n cascaded stages of D flip-flops, where the input terminal of each stage of the D flip-flop is used to receive an inverted signal output by the output terminal, and the reset terminal is used to receive an inverted signal of the third identification signal IdleState, where n is an integer greater than 1; wherein the clock terminal of the first stage of the D flip-flop is used to receive the timing clock signal Osc, the clock terminal of the next stage of the D flip-flop is used to receive the inverted signal output by the output terminal of the previous stage of the D flip-flop, and the output terminal of the last stage of the D flip-flop is further used to output a first count value CalTimeOut.

[0060] Specifically, Figure 6 Taking the timing module 102 composed of four cascaded D flip-flops as an example, when the third identification signal IdleState is at a valid level, the reset terminal of the D flip-flop always receives a low level and continuously performs the reset function. At this time, the timing module 102 cannot operate normally. When the third identification signal IdleState is at an invalid level, the reset terminal of the D flip-flop always receives a high level and cannot perform the reset function. At this time, the timing module 102 operates normally. In connection with the above, if it is set in the calibration master chip 10, when the calibration master chip 10 begins calibration, that is, when the calibration loop to which the calibration master chip 10 belongs begins calibration, the timing module 102 begins to operate normally. If it is set in the calibration slave chip 20, when the calibration slave chip 20 begins calibration, the timing module 102 begins to operate normally.

[0061] In the initial state, Q<3:0>=0000, the first-stage D flip-flop is driven based on the rising edge of the timing clock signal Osc. When the first rising edge of Osc comes, Q<3:0>=0001, the clock terminal Ck of the next-stage D flip-flop is used to connect the inverted signal of the output terminal of the previous-stage D flip-flop. When the next-stage D flip-flop is driven based on the falling edge of the previous-stage output signal, when the second rising edge of Osc comes, the first-stage D flip-flop is set to 0 by 1, and the second-stage D flip-flop is set to 1 by 0. At this time, Q<3:0>=0010, and so on. <3> =1, the first count value CalTimeOut outputted at this time is a valid value, and the time accumulated by the counting module 102 at this time is Q<3:0>*the period of the timing clock signal Osc.

[0062] Based on the above discussion, it can be seen that in a specific application, the preset time for the counting module 102 to perform determination can be adjusted by adjusting the period of the timing clock signal Osc or the number of stages of the D flip-flops that output the first count value CalTimeOut.

[0063] It should be noted that Figure 6 In the D flip-flop shown, the output terminal Q is connected to the input terminal D through an inverter, so that the input terminal of the D flip-flop is used to receive the inverted signal output by the output terminal; in a specific application, the inverting output terminal Q- of the D flip-flop can be connected to the input terminal D, so that the input terminal of the D flip-flop is used to receive the inverted signal output by the output terminal; accordingly, the data received by the clock terminal Ck of the subsequent D flip-flop can be directly connected to the inverting output terminal Q- of the previous D flip-flop, or can be connected to the inverter through the output terminal D of the previous D flip-flop.

[0064] It should also be noted that Figure 6 The timing module 102 shown is a timing implemented based on a counter and a timing clock signal Osc, and Figure 6 The counter shown is a synchronous counter. In specific applications, timing can also be achieved based on an asynchronous counter and a timing clock signal Osc, or timing can be achieved through other methods to achieve comparison with a preset time to generate a first count value CalTimeOut.

[0065] In some embodiments, reference Figure 7 The timing module 102 is further configured to generate a second count value RingTimeOut; the triggering module 104 is further configured to generate a second error flag signal based on the second count value RingTimeOut and the third flag signal IdleState, wherein, when the second count value RingTimeOut is a valid value and the third flag signal IdleState is an invalid level, the generated second error flag signal is a valid level, and the time when the second count value RingTimeOut is a valid value occurs later than the time when the first count value CalTimeOut is a valid value.

[0066] In the subsequent description of this disclosure, the valid value for the second count value RingTimeOut is "1" and the invalid value is "0." It should be noted that the setting of the valid value is only used to clarify the calibration detection structure disclosed in this disclosure and does not limit the calibration detection. In specific applications, the specific setting method of the valid value can be based on the specific circuit configuration.

[0067] The second count value RingTimeOut generated by the timing module 102 is used to indicate whether the calibration time of the calibration ring to which the calibration master chip 10 belongs exceeds the preset ring calibration time, wherein the calibration time of the calibration ring is the interval time from the current time to the start of ZQ calibration by the calibration master chip 10. The preset ring calibration time can be set based on the maximum time required for the calibration ring to perform ZQ calibration. If the calibration time of the calibration ring exceeds the preset ring time, the second count value RingTimeOut generated by the timing module 102 is a valid value; if the calibration time of the calibration ring does not exceed the preset time, the second count value RingTimeOut generated by the timing module 102 is an invalid value.

[0068] Based on the setting method of the trigger module 104, the second error identification signal is generated by judging whether the second count value RingTimeOut and the third identification signal IdleState are valid. If the second count value RingTimeOut is a valid value, it indicates that the calibration time of the current calibration ring has timed out. If the third identification signal IdleState generated by the calibration main chip 10 is an invalid level at this time, it indicates that the calibration ring is still performing calibration, that is, the ZQ calibration time of the calibration ring has timed out, and there is a problem in the ZQ calibration process of the calibration ring, and corresponding inspection is required; by detecting the calibration time of the calibration ring to perform ZQ calibration, the smooth execution of the ZQ calibration of the calibration ring is ensured, the accuracy of the memory performing ZQ calibration is further ensured, and the transmission of the identification signal between multiple chips is ensured.

[0069] It should be noted that since the timing of the calibration time of the calibration ring only involves the calibration main chip 10, the timing module 102 for generating the second count value RingTimeOut can be only set in the calibration main chip 10 to save the layout area of ​​the timing module 102. In some embodiments, the calibration main chip 10 and the calibration slave chip 20 both include a timing module 102 that can generate the second count value RingTimeOut to simplify the design difficulty of the chip.

[0070] refer to Figure 8 In one example, the timing module 102 includes:

[0071] A cascade of n stages of D flip-flops, wherein the input terminal of each stage of the D flip-flop is used to receive an inverted signal output by the output terminal, and the reset terminal is used to receive an inverted signal of a third identification signal IdleState, where n is an integer greater than 1; wherein the clock terminal of the first stage of the D flip-flop is used to receive a timing clock signal Osc, the clock terminal of the next stage of the D flip-flop is used to receive an inverted signal output by the output terminal of the previous stage of the D flip-flop, and the output terminal of the last stage of the D flip-flop is also used to output a first count value CalTimeOut.

[0072] m stages of cascaded D-type flip-flops, wherein the input terminal of each stage of the D-type flip-flop is used to receive the inverted signal of the output terminal, and the reset terminal is used to receive the inverted signal of the third identification signal IdleState, where m is an integer greater than n; wherein the clock terminal of the first-stage D-type flip-flop is used to receive the timing clock signal Osc, the clock terminal of the next-stage D-type flip-flop is used to receive the inverted signal output by the output terminal of the previous-stage D-type flip-flop, and the output terminal of the last-stage D-type flip-flop is also used to output the second count value RingTimeOut.

[0073] Specifically, refer to Figure 8 For the D flip-flop that generates the first count value CalTimeOut, the details are described above and will not be repeated in this embodiment; for the D flip-flop that generates the second count value RingTimeOut, Figure 7 Taking the timing module 102 composed of six cascaded D flip-flops as an example, when the third identification signal IdleState is at an active level, the reset terminal of the D flip-flop always receives a low level, continuously performing the reset function, and timing module 102 does not function normally. When the third identification signal IdleState is at an inactive level, the reset terminal of the D flip-flop always receives a high level, and the reset function cannot be performed. In this case, timing module 102 functions normally. In connection with the above, since it is provided in the calibration master chip 10, when the calibration master chip 10 begins calibration, that is, when the calibration loop to which the calibration master chip 10 belongs begins calibration, timing module 102 begins to function normally.

[0074] In the initial state, Q1<5:0>=00000, the first-stage D flip-flop is driven based on the rising edge of the timing clock signal Osc. When the first rising edge of Osc comes, Q1<5:0>=00001, the clock terminal Ck of the next-stage D flip-flop is used to connect the inverted signal of the output terminal of the previous-stage D flip-flop. When the next-stage D flip-flop is driven based on the falling edge of the previous-stage output signal, when the second rising edge of Osc comes, the first-stage D flip-flop is set to 0 by 1, and the second-stage D flip-flop is set to 1 by 0. At this time, Q1<5:0>=00010, and so on. When Q1 <5> =1, the second count value RingTimeOut outputted at this time is a valid value, and the time accumulated by the counting module 102 at this time is Q1<5:0>*the period of the timing clock signal Osc.

[0075] Based on the above discussion, it can be seen that in a specific application, the preset time for the counting module 102 to perform determination can be adjusted by adjusting the period of the timing clock signal Osc or the number of stages of the D flip-flops that output the second count value RingTimeOut.

[0076] It should be noted that Figure 8In the D flip-flop shown, the output terminal Q is connected to the input terminal D through an inverter, so that the input terminal of the D flip-flop is used to receive the inverted signal output by the output terminal; in a specific application, the inverting output terminal Q- of the D flip-flop can be connected to the input terminal D, so that the input terminal of the D flip-flop is used to receive the inverted signal output by the output terminal; accordingly, the data received by the clock terminal Ck of the subsequent D flip-flop can be directly connected to the inverting output terminal Q- of the previous D flip-flop, or can be connected to the inverter through the output terminal D of the previous D flip-flop.

[0077] It should also be noted that Figure 8 The timing module 102 shown is a timing implemented based on a counter and a timing clock signal Osc, and Figure 8 The counter shown is a synchronous counter. In specific applications, timing can also be achieved based on an asynchronous counter and a timing clock signal Osc, or timing can be achieved through other methods to achieve comparison with a preset time to generate a second count value RingTimeOut.

[0078] based on Figure 8 As can be seen from the structure, the difference between the structures used to generate the first count value CalTimeOut and the second count value RingTimeOut is only the number of D flip-flops, while the connection method of each level of D flip-flops is the same. In some embodiments, the cascaded m-level D flip-flops and the cascaded n-level D flip-flops share some D flip-flops. In some examples, refer to Figure 9 The D flip-flops generating the first count value CalTimeOut are set based on some D flip-flops generating the second count value RingTimeOut, so as to save the number of D flip-flops required to be set in the timing module 102.

[0079] Accordingly, reference Figure 10 The trigger module 104 includes a first AND logic circuit 401, one input terminal for receiving the first identification signal BusyState, another input terminal for receiving the first count value CalTimeOut, and an output terminal for outputting a first error identification signal. A second AND logic circuit 402, one input terminal for receiving the third identification signal IdleState, another input terminal for receiving the second count value RingTimeOut, and an output terminal for outputting a second error identification signal.

[0080] It should be noted that if the timing module 102 of the calibration master chip 10 or the calibration slave chip 20 does not need to generate the second count value RingTimeOut, the trigger module 104 does not include the second AND logic circuit 402 .

[0081] In some embodiments, the calibration detection structure further includes: a recovery module configured to reset the third flag signal IdleState to a valid signal when the error flag signal is a valid signal. If provided in the calibration master chip 10, the error flag signal is one of the first error flag signal and the second error flag signal; if provided in the calibration slave chip 20, the error flag signal is the first error flag signal.

[0082] The third identification signal IdleState is reset to a valid signal through the recovery module. Figure 6 or Figure 8 At this time, the third identification signal IdleState will reset the D flip-flop, thereby setting the first count value CalTimeOut and / or the second count value RingTimeOut to 0, that is, resetting the first error identification signal and / or the second error identification signal, so that the calibration master chip 10 or the calibration slave chip 20 re-executes the ZQ calibration, thereby determining whether the error in the ZQ calibration process of the chip is a single occasional error or a continuous error, so as to realize the monitoring of the chip ZQ calibration process, and reset and correct the occasional error, so that the ZQ calibration process of multiple chips can continue.

[0083] It should be noted that if the timing module 102 of the calibration main chip 10 does not need to generate the second count value RingTimeOut, then if the recovery module is provided in the calibration main chip 10 , the error flag signal is the first error flag signal.

[0084] In one example, refer to Figure 11 The recovery module includes: a first AND gate 501, one input end of which is used to receive the first error identification signal, and the other input end is connected to the output end of the delay unit Delay, the input end of the delay unit Delay is connected to the output end of the inverter, and the input end of the inverter is used to receive the first error identification signal; a second AND gate 502, one input end of which is connected to the output end of the first AND gate 501, and one input end for receiving the first count value CalTimeOut; an OR gate 503, one input end of which is connected to the output end of the second AND gate 502, and one input end for receiving the third identification signal IdleState generated by the identification generation module 101.

[0085] When the first error identification signal is at a valid level, the first AND gate 501 generates a high-level pulse based on the first error identification signal. In addition, when the first error identification signal is at a valid level, the first count value CalTimeOut is a valid value. The second AND gate 502 transmits the high-level pulse generated by the first AND gate 501 to the OR gate 503. The OR gate 503 resets the valid signal of the third identification signal IdleState generated by the identification generation module 101 based on this high-level pulse through the first error identification signal and the first count value CalTimeOut.

[0086] In some embodiments, the recovery module includes a first AND gate having one input terminal for receiving the second error flag signal and another input terminal connected to the output terminal of the delay unit, the input terminal of the delay unit being connected to the output terminal of the inverter, and the input terminal of the inverter being used to receive the second error flag signal; a second AND gate having one input terminal connected to the output terminal of the first AND gate and one input terminal for receiving the second count value RingTimeOut; and an OR gate having one input terminal connected to the output terminal of the second AND gate and one input terminal for receiving the third flag signal IdleState generated by the flag generation module. In this case, when the second error flag signal is at an active level, the first AND gate generates a high-level pulse based on the second error flag signal. Furthermore, when the second error flag signal is at an active level and the second count value RingTimeOut is a valid value, the second AND gate transmits the high-level pulse generated by the first AND gate to the OR gate. Based on this high-level pulse, the OR gate resets the validity of the third flag signal IdleState generated by the flag generation module using the second error flag signal and the second count value RingTimeOut.

[0087] In some embodiments, reference Figure 12 The calibration detection structure also includes: a first latch 601, which is configured to output a first flag signal based on the rising edge of the first error identification signal, and the first flag signal is used to characterize the chip calibration failure; a second latch, which is configured to output a second flag signal based on the rising edge of the second error identification signal, and the second flag signal is used to characterize the calibration failure of the calibration ring of the calibration main chip 10, so as to facilitate relevant staff to inquire about the monitoring status of the chip ZQ calibration.

[0088] In some embodiments, the first latch 601 and the second latch are latches of the mode register, and the first flag signal and the second flag signal are latched in the first latch 601 and the second latch respectively, that is, the first flag signal and the second flag signal are recorded in the mode register. Figure 12The first latch 601 is set based on a D flip-flop, which is triggered based on the rising edge of the first error identification signal, thereby outputting the Vcc received by the D terminal to the Q terminal, thereby generating a first flag signal; the structure of the second latch is consistent with that of the first latch 601, Figure 12 The corresponding signal in can be replaced, and this embodiment will not be described in detail.

[0089] In some embodiments, reference Figure 13 The calibration detection structure also includes: a third latch 602, which is configured to output a third flag signal based on the falling edge of the first error identification signal, and the third flag signal is used to indicate the recovery of the chip calibration fault; a fourth latch, which is configured to output a fourth flag signal based on the falling edge of the second error identification signal, and the fourth flag signal is used to indicate the recovery of the calibration fault of the calibration ring to which the calibration main chip 10 belongs, so as to facilitate relevant staff to inquire about the monitoring status of the chip ZQ calibration.

[0090] In some embodiments, the third latch 602 and the fourth latch are latches of the mode register, and the third flag signal and the fourth flag signal are latched in the third latch 602 and the fourth latch respectively, that is, the process of recording the third flag signal and the fourth flag signal in the mode register. Figure 13 The third latch 602 is set based on a D flip-flop, which is triggered based on the falling edge of the second error identification signal, thereby outputting the Vcc received by the D terminal to the Q terminal, thereby generating a third flag signal; the structure of the fourth latch is consistent with that of the third latch 602, Figure 13 The corresponding signal in can be replaced, and this embodiment will not be described in detail.

[0091] In some embodiments, the calibration detection structure further includes: a signal generating module 103 for generating a timing clock signal Osc. Figure 14 The signal generating module 103 includes: a signal generating unit 301, configured to generate an enable signal En; wherein, if the first identification signal BusyState is a valid signal, the enable signal En generated by the signal generating unit 301 is a valid signal; if the second identification signal DoneState is a valid signal, the enable signal En generated by the signal generating unit 301 in the calibration main chip 10 is a valid signal; the oscillation generating unit 302 is configured to be driven based on the enable signal En to generate the timing clock signal Osc.

[0092] For the signal generating unit, refer to Figure 15If provided in the calibration master chip 10, the signal generating unit 301 includes: an OR logic circuit 313, having one input terminal for receiving the inverted signal of the chip enable signal and another input terminal for receiving the third identification signal IdleState. The chip enable signal is used to drive the calibration master chip 10; a NAND logic circuit 312, having one input terminal for receiving the output terminal of the OR logic circuit 313, another input terminal for receiving the inverted signal of the first identification signal BusyState, and an output terminal for outputting the enable signal En. If provided in the calibration slave chip 20, the signal generating unit 301 includes: an NOR logic circuit 315, having one input terminal for receiving the inverted signal of the chip enable signal and another input terminal for receiving the third identification signal IdleState. The chip enable signal is used to drive the current calibration slave chip 20.

[0093] For the calibration detection structure provided in this embodiment, based on the setting method of the trigger module 104, a first error identification signal is generated by judging whether the first count value CalTimeOut and the first identification signal BusyState are generated. If the first count value CalTimeOut is a valid value, it indicates that the current calibration time has timed out. If the first identification signal BusyState is a valid level at this time, it indicates that the chip is still performing calibration, that is, the ZQ calibration time of the chip has timed out, and there is a problem with the ZQ calibration process of the current chip, and corresponding inspection is required; by detecting the calibration time for each chip to perform ZQ calibration, the ZQ calibration of each chip is ensured to be performed smoothly, thereby ensuring the accuracy of the ZQ calibration performed by the memory.

[0094] It should be noted that the features disclosed in the calibration detection structure provided in the above embodiments can be arbitrarily combined without conflict to obtain a new calibration detection structure embodiment.

[0095] Another embodiment of the present disclosure provides a memory, including the calibration detection structure provided by the above embodiment, to monitor the calibration time of each chip performing ZQ calibration, thereby monitoring the calibration timing of the ring ZQ calibration structure to ensure the accuracy of the memory performing ZQ calibration.

[0096] Specifically, refer to Figure 3Based on the setting method of the trigger module 104, a first error identification signal is generated by judging whether the first count value CalTimeOut and the first identification signal BusyState are generated. If the first count value CalTimeOut is a valid value, it indicates that the current calibration time has timed out. If the first identification signal BusyState is at a valid level at this time, it indicates that the chip is still performing calibration, that is, the ZQ calibration time of the chip has timed out, and a problem has occurred in the ZQ calibration process of the current chip, and corresponding inspection is required; by detecting the calibration time of each chip performing ZQ calibration, the smooth execution of ZQ calibration of each chip is ensured, thereby ensuring the accuracy of ZQ calibration performed by the memory.

[0097] Further, refer to Figure 6 Based on the setting method of the trigger module 104, the second error identification signal is generated by judging whether the second count value RingTimeOut and the third identification signal IdleState are generated. If the second count value RingTimeOut is a valid value, it indicates that the calibration time of the current calibration ring has timed out. If the third identification signal IdleState generated by the calibration main chip 10 is a valid level at this time, it indicates that the calibration ring is still performing calibration, that is, the ZQ calibration time of the calibration ring has timed out, and there is a problem in the ZQ calibration process of the calibration ring, and corresponding inspection is required; by detecting the calibration time of the calibration ring to perform ZQ calibration, the smooth execution of the ZQ calibration of the calibration ring is ensured, the accuracy of the memory performing ZQ calibration is further ensured, and the transmission of the identification signal between multiple chips is ensured.

[0098] It should be noted that the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphic double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0099] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A calibration detection structure, characterized in that: Set in the calibration master chip and calibration slave chip, including: an identification generation module configured to generate a first identification signal, a second identification signal, and a third identification signal, wherein the first identification signal is used to indicate whether the calibration master chip or the calibration slave chip is undergoing a calibration process, the second identification signal is used to indicate whether the calibration master chip or the calibration slave chip has completed calibration, and if provided in the calibration master chip, the third identification signal is used to indicate whether the calibration ring to which the calibration master chip belongs has completed calibration, and if provided in the calibration slave chip, the third identification signal is used to indicate whether the calibration slave chip has completed calibration; The timing module is configured to generate a first count value; the first count value is used to indicate whether the calibration time of the calibration master chip or the calibration slave chip exceeds a preset time; if the first count value is a valid value, it indicates that the current calibration time has exceeded the preset time; The trigger module is configured to generate a first error identification signal based on the first count value and the first identification signal, wherein when the first count value is a valid value and the first identification signal is at a valid level, the generated first error identification signal is at a valid level.

2. The calibration detection structure according to claim 1, characterized in that: The identification generating module includes: A first identification signal generating unit is configured to generate the first identification signal; wherein, if the first identification signal is at a valid level, it indicates that the calibration master chip or the calibration slave chip is performing a calibration process; if the first identification signal is at an invalid level, it indicates that the calibration master chip or the calibration slave chip is not performing a calibration process; A second identification signal generating unit is configured to generate the second identification signal; wherein, if the second identification signal is at a valid level, it indicates that the calibration master chip or the calibration slave chip has completed calibration; if the second identification signal is at an invalid level, it indicates that the calibration master chip or the calibration slave chip has not completed calibration; A third identification signal generating unit is configured to generate the third identification signal; wherein, if the third identification signal is set in the calibration master chip, if the third identification signal is at an invalid level, it indicates that the calibration loop to which the calibration master chip belongs has started to perform calibration; if the third identification signal is at a valid level, it indicates that the calibration loop to which the calibration master chip belongs has completed calibration; if the third identification signal is set in the calibration slave chip, if the third identification signal is at an invalid level, it indicates that the calibration slave chip has started to perform calibration; if the third identification signal is at a valid level, it indicates that the calibration slave chip has completed calibration; If the third identification signal generated by the third identification signal generating unit is at a valid level, the second identification signal generated by the second identification signal generating unit is set to an invalid level.

3. The calibration detection structure according to claim 1, characterized in that: The timing module includes: n-stage cascaded D flip-flops, wherein the input terminal of each stage of the D flip-flop is used to receive the inverted signal output by the output terminal, and the reset terminal is used to receive the inverted signal of the third identification signal, where n is an integer greater than 1; Among them, the clock end of the first-level D-type flip-flop is used to receive a timing clock signal, the clock end of the next-level D-type flip-flop is used to receive an inverted signal output by the output end of the previous-level D-type flip-flop, and the output end of the last-level D-type flip-flop is also used to output the first count value.

4. The calibration detection structure according to claim 1, characterized in that: include: The timing module is further configured to generate a second count value; The trigger module is further configured to generate a second error identification signal based on the second count value and the third identification signal, wherein when the second count value is a valid value and the third identification signal is an invalid level, the generated second error identification signal is a valid level; The time when the second count value becomes a valid value is later than the time when the first count value becomes a valid value.

5. The calibration detection structure according to claim 4, characterized in that: The timing module includes: n-stage cascaded D flip-flops, wherein the input terminal of each stage of the D flip-flop is used to receive the inverted signal output by the output terminal, and the reset terminal is used to receive the inverted signal of the third identification signal, where n is an integer greater than 1; The clock terminal of the first-stage D flip-flop is used to receive a timing clock signal, the clock terminal of the next-stage D flip-flop is used to receive an inverted signal output by the output terminal of the previous-stage D flip-flop, and the output terminal of the last-stage D flip-flop is also used to output the first count value. m-stage cascaded D flip-flops, wherein the input terminal of each stage of the D flip-flop is used to receive the inverted signal output by the output terminal, and the reset terminal is used to receive the inverted signal of the third flag signal, where m is an integer greater than n; Among them, the clock end of the first-level D-type flip-flop is used to receive the timing clock signal, the clock end of the next-level D-type flip-flop is used to receive the inverted signal output by the output end of the previous-level D-type flip-flop, and the output end of the last-level D-type flip-flop is also used to output the second count value.

6. The calibration detection structure according to claim 5, characterized in that: The cascaded m-stage D flip-flops and the cascaded n-stage D flip-flops share some of the D flip-flops.

7. The calibration detection structure according to claim 4, characterized in that: The trigger module includes: a first AND logic circuit, having one input terminal for receiving the first identification signal, another input terminal for receiving the first count value, and an output terminal for outputting the first error identification signal; The second AND logic circuit has one input terminal for receiving the third identification signal, another input terminal for receiving the second count value, and an output terminal for outputting the second error identification signal.

8. The calibration detection structure according to claim 4, characterized in that: Also includes: The recovery module is configured to reset the third identification signal to a valid signal when the error identification signal is a valid signal, wherein, if it is set in the calibration master chip, the error identification signal is one of the first error identification signal and the second error identification signal; if it is set in the calibration slave chip, the error identification signal is the first error identification signal.

9. The calibration detection structure according to claim 8, characterized in that: The recovery module includes: a first AND gate, having one input end for receiving the error identification signal and another input end connected to the output end of the delay unit, the input end of the delay unit being connected to the output end of the inverter, and the input end of the inverter being used to receive the error identification signal; a second AND gate, having an input terminal connected to the output terminal of the first AND gate and an input terminal for receiving the first count value; An OR gate has one input end connected to the output end of the second AND gate, and one input end for receiving the third identification signal generated by the identification generation module.

10. The calibration detection structure according to claim 4, characterized in that: Also includes: a first latch configured to output a first flag signal based on a rising edge of the first error identification signal, wherein the first flag signal is used to indicate a calibration failure of the corresponding chip; The second latch is configured to output a second flag signal based on a rising edge of the second error identification signal, where the second flag signal is used to indicate a calibration failure of the calibration ring to which the calibration master chip belongs.

11. The calibration detection structure according to claim 4, characterized in that: Also includes: a third latch configured to output a third flag signal based on a falling edge of the first error identification signal, wherein the third flag signal is used to indicate that a calibration fault of the chip to which it belongs has been recovered; The fourth latch is configured to output a fourth flag signal based on a falling edge of the second error identification signal, wherein the fourth flag signal is used to indicate that a calibration fault of the calibration ring to which the calibration master chip belongs has been recovered.

12. The calibration detection structure according to claim 1, characterized in that: Also includes: The signal generating module is used to generate a timing clock signal.

13. The calibration detection structure according to claim 12, characterized in that: The signal generating module comprises: The signal generating unit is configured to generate an enable signal; Wherein, if the first identification signal is a valid signal, the enable signal generated by the signal generating unit is a valid signal; if the second identification signal is a valid signal, the enable signal generated by the signal generating unit in the calibration main chip is a valid signal; The oscillation generating unit is configured to be driven based on the enable signal to generate the timing clock signal.

14. The calibration detection structure according to claim 13, characterized in that: include: If provided in the calibration main chip, the signal generating unit includes: an OR logic circuit, one input end of which is used to receive an inverted signal of a chip enable signal, and another input end of which is used to receive the third identification signal, wherein the chip enable signal is used to drive the calibration master chip; a NAND logic circuit, having one input terminal for receiving the output terminal of the OR logic circuit, another input terminal for receiving the inverted signal of the first identification signal, and an output terminal for outputting the enable signal; If provided in the calibration slave chip, the signal generating unit includes: The NOR logic circuit has one input terminal for receiving an inverted signal of a chip enable signal, and another input terminal for receiving the third identification signal, wherein the chip enable signal is used to drive the current calibration slave chip.

15. A memory, characterized in that: Comprising the calibration detection structure according to any one of claims 1 to 14.

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