Surrounding gate transistor with heavily doped substrate source region, electronic device and method of manufacturing

Abstract

The application provides a heavily doped substrate source region surrounding gate transistor, which comprises a substrate, a source region, a drain region, a surrounding gate channel control gate and a channel layer; the source region, the drain region and the channel layer are arranged along a first direction; the source region and the drain region are heavily doped with first ions; the first direction represents the direction of the channel of the surrounding gate MOSFET device; a substrate source region is formed in the substrate, the substrate source region is oppositely arranged with the source region, the width of the substrate source region in the first direction is greater than the width of the source region in the first direction, the substrate source region is heavily doped with second ions, and the type of the second ions is opposite to the type of the first ions. The technical scheme can effectively inhibit the off-state parasitic leakage current at the bottom of the surrounding gate transistor, and the implementation is more simple.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to a heavily doped substrate source region gate-around transistor, electronic device, and fabrication method. Background Technology

[0002] As device dimensions continue to shrink, power consumption has become a major challenge in advancing Moore's Law. A primary method for reducing power consumption is enhancing gate control. Due to their superior electrostatic control of the channel and higher placement efficiency at extremely small sizes, gate-all-around (GAA) nanowire (NW) / nanofash (NS) transistors are strong candidates for next-generation CMOS device structures, surpassing fin field-effect transistors. However, traditional GAA MOSFETs have a parasitic fin leakage channel at the bottom, introducing additional off-state leakage current. When source / drain etching depths are inaccurate or over-etching occurs, transistor performance degradation becomes more pronounced.

[0003] Currently, the method for suppressing substrate leakage in GAA MOSFETs employs bottom dielectric isolation (BDI) technology. This approach blocks parasitic channels by burying an insulating dielectric layer before source / drain epitaxy, thereby preventing parasitic leakage current from flowing out. This technique requires dielectric burying before source / drain epitaxy, which presents additional challenges for subsequent selective Si and SiGe epitaxy of the source / drain, including slower speeds, higher stacking fault density, and difficulties in channel stress engineering. Another approach is to use a punch-through stopping (PTS) layer, where the substrate is doped with ions of the opposite type to those used for the source / drain. However, this approach still generates a planar / finned parasitic transistor at the bottom, resulting in leakage.

[0004] Therefore, developing an easily implementable structure and process for suppressing bottom parasitic leakage gate-around transistors has become a key technical challenge for those skilled in the art. Summary of the Invention

[0005] This invention provides a gate-around transistor, an electronic device, and a fabrication method using a heavily doped substrate source region to suppress bottom parasitic leakage of the gate-around transistor.

[0006] According to a first aspect of the present invention, a heavily doped substrate source-region-gate transistor is provided, comprising:

[0007] A gate-all-around MOSFET device includes a substrate, a source region, a drain region, a gate-all-around channel control gate, and a channel layer; the source region, the drain region, and the channel layer are arranged along a first direction; wherein the source region and the drain region are heavily doped with a first ion; wherein the first direction is characterized as the direction of the channel of the gate-all-around MOSFET device.

[0008] The substrate has a substrate source region formed therein, which is disposed opposite to the source region. The width of the substrate source region in the first direction is greater than the width of the source region in the first direction. The substrate source region is heavily doped with a second ion, and the type of the second ion is opposite to the type of the first ion.

[0009] Optionally, the thickness of the substrate source region along the second direction is 3nm-220nm; the second direction is characterized as a direction perpendicular to the first direction.

[0010] Optionally, the doping concentration of the source region and the drain region is 1E18cm. -3 -1E22cm -3 .

[0011] Optionally, the doping concentration of the substrate source region is 1E18cm⁻¹. -3 -1E24cm -3 .

[0012] Optionally, the substrate material is Si, SiGe, Ge, or a binary or ternary compound of group II-VI, III-V, or IV-IV.

[0013] Optionally, the substrate and the channel are undoped or lightly doped, with the lightly doped concentration being 1E12cm⁻¹. -3 -1E16cm -3 .

[0014] Optionally, the channel layer is a nanowire structure or a nanosheet structure.

[0015] Optionally, the surrounding gate channel control gate includes an interface oxide layer, a high-k dielectric material layer, and a metal gate, wherein the interface oxide layer, the high-k dielectric material layer, and the metal gate sequentially surround the channel layer from the inside out and are located above the substrate.

[0016] Optionally, the gate-all-around transistor device further includes a sidewall, a source metal layer, a drain metal layer, a gate metal layer, and a passivation layer; the sidewall is located between the gate-all-around channel control gate and the source region and the drain region; the source metal layer and the drain metal layer are respectively formed on the surfaces of the source region and the drain region; the gate metal layer is formed at the top of the gate-all-around channel control gate; the passivation layer is located between the gate-all-around channel control gate, the sidewall, the source metal layer, the drain metal layer, and the gate metal layer.

[0017] According to a second aspect of the present invention, a method for fabricating a heavily doped substrate source-gate-around transistor is provided, comprising:

[0018] Provide one of the aforementioned substrates;

[0019] A sacrificial layer and a channel layer are formed; the sacrificial layer and the channel layer are stacked on the substrate at intervals;

[0020] The sacrificial layer and the channel layer are etched to form a fin structure;

[0021] A dummy gate structure and the sidewalls are formed, and the sacrificial layer is etched at both ends along the first direction to form an inner sidewall cavity;

[0022] An inner sidewall is formed; the inner sidewall is formed in the cavity of the inner sidewall;

[0023] Forming the heavily doped substrate source region;

[0024] The source region and the drain region are formed; wherein the source region and the drain region are arranged along the first direction; the source region is disposed opposite to the substrate source region;

[0025] Remove the dummy gate structure and the sacrificial layer to form a channel cavity;

[0026] Form the control fence for the surrounding trench;

[0027] The source metal layer, the drain metal layer, the gate metal layer, and the passivation layer are formed.

[0028] Optionally, in the method for fabricating a heavily doped substrate source region gate-around transistor, forming the substrate source region specifically includes:

[0029] A patterned photoresist layer is formed, which covers the substrate portion corresponding to the drain region and exposes the substrate portion corresponding to the source region;

[0030] The substrate portion corresponding to the source region is heavily doped to form the substrate source region;

[0031] Remove the photoresist;

[0032] Annealing to repair the crystal lattice.

[0033] According to a third aspect of the present invention, an electronic device is provided, comprising a heavily doped substrate source region gate-around transistor as described in any of the first aspects of the present invention.

[0034] According to a fourth aspect of the present invention, a method for manufacturing an electronic device is provided, comprising the method for fabricating a heavily doped substrate source region gate-around transistor as described in any of the second aspects of the present invention.

[0035] This invention designs a heavily doped substrate source region inside the substrate below the source region of the gate-all-around transistor (GABOT), utilizing the ultra-low reverse conduction characteristics of the PI / NI junction to suppress parasitic leakage at the bottom. Furthermore, since this invention only requires forming a heavily doped structure within the substrate below the GABOT source region, it only requires an additional doping step, which can be achieved through ion implantation, epitaxial in-situ doping, solid-phase source doping, etc., resulting in higher compatibility with standard processes. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a schematic diagram of a gate-around transistor using a heavily doped substrate source region according to an embodiment of the present invention;

[0038] Figure 2 This is a schematic flowchart of a method for fabricating a gate-around-the-source transistor using a heavily doped substrate source region, according to an embodiment of the present invention.

[0039] Figure 3 This is a schematic diagram of the device structure formed after the dummy gate and sidewall deposition is completed, according to a method for fabricating a gate-around transistor using a heavily doped substrate source region provided by an embodiment of the present invention.

[0040] Figure 4 This is a schematic diagram of the device structure after the formation of the substrate source region, according to a method for fabricating a gate-around transistor using a heavily doped substrate source region provided by an embodiment of the present invention.

[0041] Figure 5 This is a schematic diagram of the device structure after the formation of the source and drain regions in a method for fabricating a gate-around-the-field transistor using a heavily doped substrate source region according to an embodiment of the present invention.

[0042] Figure 6 This is a schematic diagram of the device structure after etching away the sacrificial layer to release the channel and growing the control gate, according to a method for fabricating a gate-around-the-field transistor using a heavily doped substrate source region provided by an embodiment of the present invention.

[0043] Explanation of reference numerals in the attached figures:

[0044] 101-Substrate;

[0045] 102-channel layer;

[0046] 103a - Interface oxide layer;

[0047] 103b-high-k dielectric material layer;

[0048] 103c - Metal grid;

[0049] 104-Source Region;

[0050] 105 - Leakage Zone;

[0051] 106 - Substrate source region;

[0052] 107-Side wall;

[0053] 108 - Inner wall;

[0054] 109 - Passivation layer;

[0055] 110 - Gate metal layer;

[0056] 111-Source metal layer;

[0057] 112 - Drain metal layer;

[0058] 113 - Sacrificial Layer;

[0059] 114 - Pseudo-gate structure;

[0060] 115 - Photoresist. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] In the description of this invention, it should be understood that the terms "upper part", "lower part", "upper end", "lower end", "lower surface", "upper surface", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0063] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0064] In the description of this invention, "a plurality of" means multiple, such as two, three, four, etc., unless otherwise explicitly specified.

[0065] In the description of this invention, unless otherwise explicitly specified and limited, the term "connection" and other such terms should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection, an electrical connection, or a connection that allows communication between the components; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0066] As described in the background section, existing gate-all-around (GAA) transistors suffer from bottom parasitic leakage. Effectively suppressing the off-state parasitic leakage current generated by the parasitic finned channel at the bottom of GAA nanowire (NW) / nanosheet (NS) transistors has become one of the key challenges in optimizing GAA devices.

[0067] In view of this, the inventors of this application have designed a heavily doped substrate source region-gate-around transistor device. The device structure forms a heavily doped substrate source region in the substrate region at the bottom of the source region. Since the bottom substrate is an intrinsic semiconductor or a lightly doped semiconductor, the heavily doped substrate source region and the substrate region outside the substrate source region form a reverse bias NI junction or PI junction to suppress the bottom parasitic leakage current.

[0068] As can be seen, the technical solution provided in this application can effectively suppress the off-state parasitic leakage current at the bottom of the gate-around transistor by utilizing the ultra-low reverse conduction characteristics of the reverse-biased NI junction or PI junction when the transistor is off.

[0069] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0070] Please refer to Figures 1-6 According to an embodiment of the present invention, a heavily doped substrate source-gate-surround transistor is provided, comprising:

[0071] Gate-around MOSFET devices, such as Figure 1 As shown, the device includes a substrate 101, a source region 104, a drain region 105, a gate-all-around (GAOO) control gate, and a channel layer 102. The GAOO control gate specifically includes an interface oxide layer 103a, a high-k dielectric material layer 103b, and a metal gate 103c. The source region 104, the drain region 105, and the channel layer 102 are arranged along a first direction. The source region 104 and the drain region 105 are heavily doped with first ions. The first direction represents the direction of the channel of the GAOO MOSFET device.

[0072] In this embodiment, a substrate source region 106 is formed in the substrate 101. The substrate source region 106 is disposed opposite to the source region 104, and the width of the substrate source region 106 in the first direction is greater than the width of the source region 104 in the first direction. The substrate source region 106 is heavily doped with a second ion, and the type of the second ion is opposite to the type of the first ion.

[0073] This application provides a heavily doped substrate source region-gate-around transistor, which creatively proposes that: by providing a heavily doped substrate source region 106 inside the substrate opposite to the source region 104 of a conventional gate-around (GAA) nanowire (NW) / nanofamber (NS) transistor, when the gate-around transistor is operating in the off state, the heavily doped substrate source region 106 and the intrinsically doped or lightly doped substrate region outside the source region 106 form a reverse-biased NI junction or PI junction, thereby effectively suppressing the off-state parasitic leakage current at the bottom of the gate-around transistor through the ultra-low directional conduction characteristics of the NI junction or PI junction.

[0074] As can be seen, the technical solution provided by this invention solves the problem of off-state parasitic leakage current caused by the parasitic fin channel at the bottom of conventional gate-all-around (GAA) nanowire (NW) / nanosheet (NS) transistors.

[0075] The width of the heavily doped substrate source region 106 in the first direction is an important parameter for device design and needs to be greater than the width of the source region 104 in the first direction. When the width of the heavily doped substrate source region 106 in the first direction is equal to or less than the width of the source region 104 in the first direction, the heavily doped substrate source region 106 will not be able to completely enclose the source region 104 in the first direction, thus failing to effectively suppress the off-state parasitic leakage current at the bottom of the gate-around crystal.

[0076] The thickness of the heavily doped substrate source region 106 extends in the substrate region along a second direction, which is defined as a direction perpendicular to the first direction. The thickness of the heavily doped substrate source region 106 is an important parameter for device design. If the thickness of the heavily doped substrate source region 106 is too small, it will not be able to effectively suppress the off-state parasitic leakage current in the parasitic channel at the bottom of the gate-around transistor. If the thickness of the heavily doped substrate source region 106 is too large, it will significantly increase the difficulty of the substrate source region 106 doping process, resulting in a decrease in device consistency and reliability.

[0077] Therefore, in a preferred embodiment, the thickness of the substrate source region 106 along the second direction is 3nm-220nm.

[0078] In one embodiment, the source region 104 and the drain region 105 are heavily doped with N-type ions or P-type ions, and the substrate source region 106 is heavily doped with ions of the opposite type to those in the source region 104 and the drain region 105.

[0079] Specifically, N-type ions are: hydrides and fluorides of phosphorus and arsenic, specifically one or a combination of the following materials: phosphine, arsine, phosphorus pentafluoride, phosphorus trifluoride, arsenic pentafluoride, or arsenic trifluoride; P-type ions are: hydrides, fluorides, or chlorides of boron, specifically one or a combination of the following materials: B2H6, B4H10, B6H10, B10H14, B18H22, BF3, or BCL3.

[0080] For N-type devices, the source region 104 and the drain region 106 are N-type doped with a doping concentration of approximately 1E18 cm⁻¹. -3 -1E22cm -3 The substrate source region is P-type doped with a doping concentration of approximately 1E18 cm⁻¹. -3 -1E24cm -3 .

[0081] For P-type devices, the source region 104 and the drain region 106 are P-type doped with a doping concentration of approximately 1E18cm⁻¹. -3 -1E22cm -3The substrate source region is N-type doped with a doping concentration of approximately 1E18 cm⁻¹. -3 -1E24cm -3 .

[0082] In the heavily doped substrate source region gate-all-around transistor, the doping concentration of the substrate source region 106 is an important parameter for device design. The doping concentration of the substrate source region 106 cannot be too low. If the doping concentration is too low, the junction depth of the NI junction or PI junction formed by the substrate source region 106 and the substrate region outside the substrate source region 106 will be too shallow, which will increase the reverse bias leakage current of the NI junction or PI junction, thus failing to effectively suppress the off-state parasitic leakage current in the parasitic channel at the bottom of the gate-all-around transistor. If the doping concentration is too high, the effective doping concentration at the bottom of the source region 104 will decrease, causing the transistor's on-state current to decrease.

[0083] Therefore, in a preferred embodiment, the doping concentration of the substrate source region 106 is approximately 1E18 cm⁻¹. -3 -1E22cm -3 .

[0084] In one embodiment, the substrate 101 is made of Si, SiGe, Ge, or a binary or ternary compound of group II-VI, III-V, or IV-IV.

[0085] In one embodiment, the substrate 101 and the channel layer 102 are undoped or lightly doped, wherein the lightly doped concentration is 1E12cm⁻¹. -3 -1E16cm -3 .

[0086] In one embodiment, the channel layer 102 is a nanowire structure or a nanosheet structure.

[0087] In one embodiment, the heavily doped substrate source-gate-around transistor further includes:

[0088] The surrounding gate channel control gate specifically includes an interface oxide layer 103a, a high-k dielectric material layer 103b, and a metal gate 103c. The interface oxide layer 103a, the high-k dielectric material layer 103b, and the metal gate 103c sequentially surround the channel layer 102 from the inside out and are located above the substrate 101.

[0089] The system comprises a sidewall 107, a source metal layer 111, a drain metal layer 112, a gate metal layer 110, and a passivation layer 109. The sidewall 107 is located between the gate-around-the-gate control gate and the source region 104 and the drain region 105. The source metal layer 111 and the drain metal layer 112 are formed on the surfaces of the source region 104 and the drain region 105, respectively. The gate metal layer 110 is formed at the top of the gate-around-the-gate control gate. The passivation layer 109 is located between the gate-around-the-gate control gate, the sidewall 107, the source metal layer 110, the drain metal layer 110, and the gate metal layer 110.

[0090] According to an embodiment of the present invention, a method for fabricating a heavily doped substrate source-gate-around transistor is also provided, for fabricating the heavily doped substrate source-gate-around transistor as described in any of the foregoing embodiments, comprising:

[0091] S111: Provide one of the substrates 101;

[0092] S112: Forming a sacrificial layer 113 and the channel layer 102; the sacrificial layer 113 and the channel layer 102 are stacked at intervals on the substrate 101;

[0093] S113: Etch the sacrificial layer 113 and the channel layer 102 to form a fin structure;

[0094] S114: Form a dummy grid structure 114 and the sidewall 107, and etch the two ends of the sacrificial layer 113 along the first direction to form an inner sidewall cavity;

[0095] S115: Forming an inner sidewall 108; the inner sidewall 108 is formed in the cavity of the inner sidewall, such as Figure 3 As shown;

[0096] S116: Form the heavily doped substrate source region 106, such as Figure 4 As shown;

[0097] S117: Form the source region 104 and the drain region 105, as follows Figure 5 As shown; wherein, the source region 104 and the drain region 105 are arranged along the first direction; the source region 104 is disposed opposite to the substrate source region 106;

[0098] S118: Remove the dummy gate structure 114 and the sacrificial layer 113 to form a channel cavity;

[0099] S119: Form the control fence for the surrounding trench, such as Figure 6As shown; wherein, the surrounding gate communication control gate specifically includes an interface oxide layer 103a, a high-k dielectric material layer 103b, and a metal gate 103c. The interface oxide layer 103a, the high-k dielectric material layer 103b, and the metal gate 103c sequentially surround the channel layer 102 from the inside to the outside and are located above the substrate 101.

[0100] S120: Forming the source metal layer 111, the drain metal layer 112, the gate metal layer 110, and the passivation layer 109, as follows: Figure 1 As shown, the passivation layer 109 is located between the gate surrounding channel control gate, the sidewall 107 and the source metal layer 111, the drain metal layer 112 and the gate metal layer 110, and provides passivation protection for the gate surrounding transistor.

[0101] In one embodiment, such as Figure 4 As shown, in step S116, forming the substrate source region 106 specifically includes:

[0102] A patterned photoresist layer 115 is formed, which covers the substrate portion corresponding to the drain region and exposes the substrate portion corresponding to the source region.

[0103] The substrate portion corresponding to the source region is heavily doped to form the substrate source region 106;

[0104] Remove the photoresist;

[0105] Annealing to repair the crystal lattice.

[0106] in, Figure 4 The method of heavily doping the substrate portion corresponding to the source region shown is ion implantation. However, it should be recognized that other doping methods are also within the scope of protection of this invention, such as epitaxial in-situ doping, solid-phase source doping, and other doping methods.

[0107] Secondly, according to an embodiment of the present invention, an electronic device is also provided, including a heavily doped substrate source region gate-around transistor as described in any of the foregoing embodiments of the present invention;

[0108] In addition, according to an embodiment of the present invention, a method for manufacturing an electronic device is also provided, including the method for fabricating a heavily doped substrate source region gate-around transistor as described in any of the foregoing embodiments of the present invention.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A heavily doped substrate source region surround gate transistor, characterized by, include: A gate-all-around MOSFET device includes a substrate, a source region, a drain region, a gate-all-around channel control gate, and a channel layer; the source region, the drain region, and the channel layer are arranged along a first direction; wherein the source region and the drain region are heavily doped with a first ion; wherein the first direction is characterized as the direction of the channel of the gate-all-around MOSFET device. The substrate has a substrate source region formed therein, which is disposed opposite to the source region. The width of the substrate source region in the first direction is greater than the width of the source region in the first direction. The substrate source region is heavily doped with a second ion, and the type of the second ion is opposite to that of the first ion. The doping concentration of the substrate and the channel layer is undoped or lightly doped. The substrate source region and the intrinsically doped or lightly doped substrate region outside the substrate source region form a reverse-biased NI junction or PI junction.

2. The heavily doped substrate source region surround gate transistor of claim 1, wherein, The thickness of the substrate source region along the second direction is 3nm-220nm; the second direction is characterized as a direction perpendicular to the first direction.

3. The heavily doped substrate source region surround gate transistor of claim 1, wherein, The source region and the drain region have a doping concentration of 1E18 cm -3 -1E22 cm -3 .

4. The heavily doped substrate source-gate-around transistor according to claim 1 or 3, characterized in that, The substrate source region has a doping concentration of 1E18 cm -3 -1E24 cm -3 .

5. The heavily doped substrate source region surround gate transistor of claim 1, wherein, The substrate is made of Si, SiGe, Ge, or binary or ternary compounds of groups II-VI, III-V, and IV-IV.

6. The heavily doped substrate source region surround gate transistor of claim 1, wherein, The lightly doped has a doping concentration of 1E12 cm -3 -1E16 cm -3 .

7. The heavily doped substrate source region surround gate transistor of claim 1 or 6, wherein, The channel layer is a nanowire structure or a nanosheet structure.

8. The heavily doped substrate source region surround gate transistor of claim 1, wherein, The surrounding channel control gate includes an interface oxide layer, a high-k dielectric material layer, and a metal gate. The interface oxide layer, the high-k dielectric material layer, and the metal gate sequentially surround the channel layer from the inside out and are located above the substrate.

9. The heavily doped substrate source region surround gate transistor of claim 1, wherein, It also includes sidewalls, a source metal layer, a drain metal layer, a gate metal layer, and a passivation layer; the sidewalls are located between the gate-around-the-gate control gate and the source region and the drain region; the source metal layer and the drain metal layer are respectively formed on the surfaces of the source region and the drain region; the gate metal layer is formed at the top of the gate-around-the-gate control gate; the passivation layer is located between the gate-around-the-gate control gate, the sidewalls, the source metal layer, the drain metal layer, and the gate metal layer.

10. A method for fabricating a heavily doped substrate source-gate-around transistor, used to fabricate the heavily doped substrate source-gate-around transistor of claim 9, characterized in that, include: Provide one of the aforementioned substrates; Forming a sacrificial layer and the channel layer; The sacrificial layer and the channel layer are stacked on the substrate at intervals, and the doping concentration of the substrate and the channel layer is undoped or lightly doped; The sacrificial layer and the channel layer are etched to form a fin structure; A dummy grid structure and the sidewalls are formed, and the sacrificial layer is etched at both ends along the first direction to form an inner sidewall cavity; An inner sidewall is formed; the inner sidewall is formed in the cavity of the inner sidewall; The substrate source region is formed, and the substrate source region and the intrinsically doped or lightly doped substrate region outside the substrate source region form a reverse-biased NI junction or PI junction; The source region and the drain region are formed; wherein the source region and the drain region are arranged along the first direction; the source region is disposed opposite to the substrate source region; Remove the dummy gate structure and the sacrificial layer to form a channel cavity; Form the control fence for the surrounding trench; The source metal layer, the drain metal layer, the gate metal layer, and the passivation layer are formed.

11. The method of claim 10, wherein the method further comprises: Forming the substrate source region specifically includes: A patterned photoresist layer is formed, which covers the substrate portion corresponding to the drain region and exposes the substrate portion corresponding to the source region; The substrate portion corresponding to the source region is heavily doped to form the substrate source region; Remove the photoresist; Annealing to repair the crystal lattice.

12. An electronic device, comprising: Includes the heavily doped substrate source region gate-surround transistor as described in any one of claims 1-9.

13. A method of manufacturing an electronic device, comprising: The method for fabricating a heavily doped substrate source region gate-around transistor as described in claim 10 or 11.

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