A microchip and method for preparing ultracold atoms

Abstract

The present invention discloses a microchip and method for preparing ultracold atoms. The microchip includes a chip substrate, an oxide isolation layer provided on the chip substrate, a wire etching layer provided by ion evaporation sputtering, and wires etched on the wire etching layer by photolithography. The wires are designed as double U-shaped wires and double H-shaped wires, with a groove size of 15 μm between the wires. The present invention uses the extremely high gradient potential well field generated by the double U-shaped and double H-shaped wires on the chip to trap and manipulate cold atoms on-chip. On the one hand, this method overcomes the limitations imposed by the large coils and complex optical paths of traditional magneto-optical traps on the optical system and magnetic field coils of miniaturized atomic vacuum physics units. On the other hand, the compact and steep potential well provides an effective way to further achieve on-chip rapid evaporative cooling to prepare ultracold atoms.

Description

Technical Field

[0001] The present invention relates to the field of cold atom chips, and in particular to a microchip and method for preparing ultracold atoms. Background Art

[0002] Since the advent of quantum theory in the last century, studying the properties of matter waves in the microscopic world has become increasingly important, driving the rapid development of modern physics over the past century. Laser cooling and trapping of atoms have quickly become a reality. Cooled atoms can be used for matter-wave interferometry, quantum computing, and precise measurement of physical quantities. Atomic cooling is achieved using three pairs of spatially oppositely directed red-detuned laser beams, based on the Doppler cooling mechanism. Atomic trapping can be categorized by optical trapping and magnetic trapping, respectively. The binding forces exerted on atoms by these two traps correspond to dipole forces and scattering forces, respectively. Later, the magneto-optical trap (MOT) was invented. It consists of a three-dimensional standing wave field formed by three pairs of mutually perpendicular, negatively detuned, opposing laser beams with specific polarization configurations, and a gradient field generated by an anti-Helmholtz coil. The zero point of the magnetic field coincides with the center of the optical field, and the negatively detuned laser beams exert a damping force on the atoms. The gradient magnetic field, combined with the laser polarization, generates the binding force.

[0003] On the one hand, the traditional magneto-optical trap consists of three pairs of lasers and a pair of anti-Helmholtz coils, but for cold atom experiments, simplicity and miniaturization are what we have always pursued. The traditional MOT device is too bulky. Therefore, being able to replace the magnetic trap generated by macroscopic coils with a magnetic trap generated by a chip is a key technology for miniaturizing atomic optical systems in the future.

[0004] On the other hand, miniaturization is a key concept behind the development of atom chips. Micrometer-sized structures can be formed on a chip by patterning permanent magnets or microfabricating wires, allowing the generation of very strong field gradients with relatively modest magnets or electric currents. This makes it very easy to form tightly trapped clouds of cold atoms, which are required for rapid evaporation to produce Bose-Einstein condensates (BECs) and subsequent rapid manipulation. In addition to generating strong trapping forces, miniaturization also opens up the possibility of controlling atomic motion on the micrometer length scale. This is important, for example, in realizing matter-wave interferometry, using de Broglie waves on a chip, or for controlled tunneling between traps, or for other more complex quantum circuits based on the flow and interaction of neutral atoms. Summary of the Invention

[0005] In view of the deficiencies of the prior art, the object of the present invention is to provide a microchip and method for preparing ultracold atoms.

[0006] The object of the present invention is achieved through the following technical solutions:

[0007] A microchip for preparing ultracold atoms, comprising a wire etching layer, an oxidation isolation layer, and a chip substrate;

[0008] The chip substrate is provided with an oxide isolation layer, the oxide isolation layer is provided with a wire etching layer by ion evaporation sputtering, the wire etching layer is etched with wires by photolithography, and the groove size between the wires is 15 μm;

[0009] The conductors include: a first Z-shaped conductor, a second Z-shaped conductor, a third Z-shaped conductor, a fourth Z-shaped conductor, a first U-shaped conductor, a second U-shaped conductor, and a transversely connected straight conductor;

[0010] The wire etching layer is provided with chip pins, and the number of the chip pins is 14, and the chip pins include: a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin, an eighth pin, a ninth pin, a tenth pin, an eleventh pin, a twelfth pin, a thirteenth pin, and a fourteenth pin; wherein the first pin and the twelfth pin are connected to the first Z-shaped wire, the second pin and the eleventh pin are connected to the second Z-shaped wire, the fifth pin and the eighth pin are connected to the third Z-shaped wire, the sixth pin and the seventh pin are connected to the fourth Z-shaped wire, the third pin and the fourth pin are connected to the first U-shaped wire, the ninth pin and the tenth pin are connected to the second U-shaped wire, and the thirteenth pin and the fourteenth pin are connected to the horizontal connecting straight wire;

[0011] The thirteenth and fourteenth pins, the first and twelfth pins, and the sixth and seventh pins are connected simultaneously to form a first H-shaped wire, and the thirteenth and fourteenth pins, the second and eleventh pins, and the fifth and eighth pins are connected simultaneously to form a second H-shaped wire.

[0012] The first U-shaped wire and the second U-shaped wire together constitute a double U-shaped wire, the middle straight wire size of the double U-shaped wire is L1=0.9mm, the middle straight wire L3 of the first H-shaped wire is 2mm, the middle straight wire L2 of the second H-shaped wire is 1.2mm, and the first H-shaped wire and the second H-shaped wire together constitute a double H-shaped wire; the double U-shaped wire is symmetrically distributed about the horizontal center line of the chip, the middle straight wire of the double H-shaped wire coincides with the horizontal center line of the chip, and the vertical wires on both sides are symmetrically distributed about the vertical center line of the chip.

[0013] Furthermore, the chip size is 36x36mm, and the wire drawing area size on the chip is 2x3mm.

[0014] Furthermore, the wire etching layer is a pure gold wire layer with a thickness of 5um; the oxidation isolation layer is a SiO2 oxidation isolation layer with a thickness of 20nm; and the chip substrate is a Si wafer substrate with a thickness of 0.5mm.

[0015] Furthermore, the double U-shaped wire has a line width of 300um, a thickness of 5um, and is made of pure gold; the double H-shaped wire has a line width of 100um, a thickness of 5um, and is made of pure gold.

[0016] A method for preparing ultracold atoms, using the above-mentioned microchip, comprises the following steps:

[0017] S1. Mount a microchip on a connecting plate to form a chip assembly and connect it to an external power supply through the connecting plate. Then connect the chip assembly to an all-quartz vacuum chamber. The chip assembly, the all-quartz vacuum chamber, and the glass tube together form a chip vacuum cavity. The chip vacuum cavity is locked together with a vacuum indium sealing flange and connected to a vacuum pump group to achieve an ultra-high vacuum experimental environment. Set a three-axial bias magnetic field outside the chip, wherein the three-axial bias magnetic field includes an x-axial bias magnetic field Bx, a y-axial bias magnetic field By, and a z-axial bias magnetic field Bz.

[0018] S2. Setting a cooling light field above the chip assembly, the cooling light field including horizontal incident light and two pairs of cooling lights at an oblique angle of 45° to the surface of the chip assembly, the oblique cooling light including left incident light, left reflected light, right incident light, and right reflected light; wherein the left incident light forms right reflected light after being reflected by the chip assembly mirror surface, and the right reflected light and the right incident light form a paired beam; the right incident light forms left reflected light after being reflected by the chip assembly mirror surface, and the left reflected light and the left incident light form a paired beam; the horizontal incident light and the return light form a paired beam, forming three pairs of cooling light beams in three-dimensional space to form a cooling light field;

[0019] S3. Connect the third or ninth pin to the positive pole of the power supply, and the corresponding fourth or tenth pin to the negative pole of the power supply, with a current of 1A-4A, and turn on the y-axial bias magnetic field By. At this time, a U-shaped trap is formed under the chip, and a U-shaped magneto-optical trap (U-MOT) is formed in combination with an external cooling light field. The U-MOT traps cold atoms from the background rubidium vapor; turn off the y-axial bias magnetic field By, and only use cooling light for polarization gradient cooling; connect the first or sixth pin to the positive pole of the power supply, and the corresponding twelfth or seventh pin to the negative pole of the power supply, with a current of 1A-4A, and turn on the y-axial bias magnetic field By, and a Z-shaped magneto-optical trap (Z-MOT) with L3=2mm is formed in combination with the external cooling light field. At the same time, turn on the x-axial bias magnetic field Bx and the z-axial bias magnetic field Bz, and adjust the three The axial bias magnetic field brings the center of the U-MOT close to the chip surface until it coincides with the center of the Z-MOT with L3=2mm; the power supply of the pin connected to the U-shaped wire is turned off, and the U-MOT is turned off, realizing the transfer of atoms from the loading MOT to the cooling MOT; finally, the second pin or the fifth pin is connected to the positive pole of the power supply, and the corresponding eleventh pin or the eighth pin is connected to the negative pole of the power supply. At this time, the y-axial external bias magnetic field By is formed into a Z-MOT with L2=1.2mm. By adjusting the three-axial bias magnetic field, the atoms are transferred to the Z-MOT with L2=1.2mm. The final evaporative cooling is performed in this MOT. The high-energy atoms are gradually expelled from the potential well, and the remaining low-energy atoms re-collide to reach thermal equilibrium. Finally, the atomic temperature reaches the nK level, realizing the preparation of ultracold atoms.

[0020] Furthermore, the connection board in step S1 includes a via pad, a surface square pad, a silk screen pattern, and a PCB substrate;

[0021] The microchip is connected to the connection board in the following way: the microchip is positioned by the silk-screen pattern and connected to the PCB substrate by glue. The pins on the surface of the microchip are connected to the square pads on the surface through thin metal wires. The square pads are connected to the via pads through wires. The via pads are finally connected to the power supply through an external pin header to power the chip.

[0022] Furthermore, the external bias magnetic field in step S3 is generated by a Helmholtz coil, and the Helmholtz coil is fixedly connected to the coil overall frame through a magnetic field coil frame.

[0023] The beneficial effects of the present invention are: the chip wire magnetic trap is fully designed, and the present invention designs two wire structures of different sizes and types, which can take into account the compact steep potential wells required for trapping atoms and generating evaporative cooling. The magnetic traps are complete in variety and compact in structure, and can realize on-chip magneto-optical trap multiple micro-MOT structures. The invention designs two H-type wire structures in order to take into account chip MOT transfer and evaporative cooling; it provides a basic design structure for miniaturized atomic optical systems, and the heat dissipation effect of the heat dissipation substrate selection is relatively good. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Design diagram for chip wires;

[0025] Figure 2 This is the exploded diagram of the chip;

[0026] Figure 3 This is the chip schematic;

[0027] Figure 4 It is a chip bias magnetic field unit;

[0028] Figure 5 This is a schematic diagram of the chip wire pin external connection board;

[0029] Figure 6 Schematic diagram of the main working structure of the chip. DETAILED DESCRIPTION

[0030] The present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the described embodiments are only for facilitating the understanding of the present invention and do not serve to limit the present invention in any way.

[0031] like Figure 1 , Figure 2 As shown, a microchip for preparing ultracold atoms includes a wire etching layer 17, an oxidation isolation layer 18, and a chip substrate 19.

[0032] The oxide isolation layer 18 is a silicon dioxide layer formed on the chip substrate 19 by a thermal oxidation process or chemical deposition method. Neither the resistivity of silicon nor the 2 nm natural oxide layer on the substrate is sufficient to isolate the DC current. Therefore, the chip substrate 19 is covered with a SiO2 insulating layer, providing a DC resistance greater than 40 MΩ between the wires. Since the thermal conductivity of silicon dioxide is only 1.5 W / (mK), the insulating layer should be as thin as possible. Therefore, the present invention uses a 20 nm oxide isolation layer to isolate the DC layer without affecting the heat dissipation effect of the base. The wire etching layer 17 is a layer of pure gold sputtered by ion evaporation on the oxide isolation layer 18, and then the wire pattern is engraved by photolithography.

[0033] like Figure 3As shown, the wire etching layer 17 is provided with wires and chip pins. The surface gold layer is etched by photolithography, and what remains is the wire body. Connecting different chip pin combinations can produce different wire magnetic traps; the groove size between the wires is 15um, and pure gold is used as the surface wire layer. Its high reflectivity surface has a great success rate for making a mirror magneto-optical trap, and the groove design at the micron level will not cause much loss in the later stage of mirror light reflection.

[0034] The conductors include: a first Z-shaped conductor, a second Z-shaped conductor, a third Z-shaped conductor, a fourth Z-shaped conductor, a first U-shaped conductor, a second U-shaped conductor, and a transversely connected straight conductor.

[0035] The number of chip pins is 14, and the chip pins include: a first pin 1, a second pin 2, a third pin 3, a fourth pin 4, a fifth pin 5, a sixth pin 6, a seventh pin 7, an eighth pin 8, a ninth pin 9, a tenth pin 10, an eleventh pin 11, a twelfth pin 12, a thirteenth pin 13, and a fourteenth pin 14; wherein, the first pin 1 and the twelfth pin 12 are connected to the first Z-shaped wire, the second pin 2 and the eleventh pin 11 are connected to the second Z-shaped wire, the fifth pin 5 and the eighth pin 8 are connected to the third Z-shaped wire, the sixth pin 6 and the seventh pin 7 are connected to the fourth Z-shaped wire, the third pin 3 and the fourth pin 4 are connected to the first U-shaped wire, the ninth pin 9 and the tenth pin 10 are connected to the second U-shaped wire, and the thirteenth pin 13 and the fourteenth pin 14 are connected to the horizontal connecting straight wire.

[0036] Among them, the thirteenth pin 13 and the fourteenth pin 14, the first pin 1 and the twelfth pin 12, the sixth pin 6 and the seventh pin 7 are connected at the same time to form a first H-type wire, and the thirteenth pin 13 and the fourteenth pin 14, the second pin 2 and the eleventh pin 11, the fifth pin 5 and the eighth pin 8 are connected at the same time to form a second H-type wire.

[0037] The first U-shaped wire and the second U-shaped wire together constitute a double U-shaped wire 15, the middle straight wire size of the double U-shaped wire 15 is L1=0.9mm, the middle straight wire L3=2mm of the first H-shaped wire, the middle straight wire L2=1.2mm of the second H-shaped wire, and the first H-shaped wire and the second H-shaped wire together constitute a double H-shaped wire 16; the double U-shaped wire 15 is symmetrically distributed about the horizontal center line of the chip, the middle straight wire of the double H-shaped wire 16 coincides with the horizontal center line of the chip, and the vertical wires on both sides are symmetrically distributed about the vertical center line of the chip. The purpose of designing a symmetrical double well is to ensure that the chip magnetic trap function will not be immediately terminated due to processing problems or wire burnout in the later stage. In addition, designing middle straight wires of different sizes can not only make the on-chip transfer of atomic clusters more convenient, but also solve the problem of insufficient compactness of the magnetic trap.

[0038] The chip size is 36x36mm, and the wire drawing area size on the chip is 2x3mm.

[0039] The wire etching layer 17 is a pure gold wire layer with a thickness of 5 μm; the oxidation isolation layer 18 is a SiO 2 oxidation isolation layer with a thickness of 20 nm; and the chip substrate 20 is a Si wafer substrate with a thickness of 0.5 mm.

[0040] The double U-shaped wire 15 has a wire width of 300um, a thickness of 5um, and is made of pure gold; the double H-shaped wire 16 has a wire width of 100um, a thickness of 5um, and is made of pure gold; the wires can pass a current of 4-5A for 3 minutes without being burned.

[0041] The magnetic field generated by the conductors on the chip surface of the present invention is combined with the external bias magnetic field to form a "quadrupole trap" above or below the chip space similar to that generated by a macroscopic anti-Helmholtz coil, such as Figure 4 The figure shows the design of the external magnetic field structure essential for chip operation, including a triaxial bias magnetic field. This triaxial bias magnetic field is relatively uniform across the chip's operating area. In addition to integrating with the chip's wires to achieve a micro-magnetic trap function, the bias magnetic field in one direction also serves an important function: regulating the position and depth of the MOT (magneto-optical trap) on the chip's surface. The bias magnetic field coils shown in the figure are secured to the coil frame 27 via a magnetic field coil frame 22 using M3 screws.

[0042] The principle of the chip magnetic trap described in the present invention is to add the magnetic field generated by the middle current-carrying straight wire and the external uniform bias magnetic field perpendicular to the strip line direction to generate a magnetic trap with a certain magnetic field gradient in three-dimensional space. The currents in the two bent wire arms of the "U"-shaped trap are in opposite directions, so a closed quadrupole trap with a magnetic field zero point is formed in three-dimensional space, which has a certain effect on the trapping of atoms. Majorana transition loss will occur at the point where the magnetic field in the center of the magnetic trap is zero, and the atoms will change from the bound state to the expelled state and escape from the trap. Therefore, in order to eliminate this hidden danger, a "Z"-shaped magnetic trap with the currents in the two bent arms in the same direction is designed to generate a potential well with a minimum magnetic field in three-dimensional space. The two magnetic traps are located at a distance of 1.5 meters from the surface of the chip. of which:

[0043] (1)

[0044] Among them, the magnetic field represents the bias magnetic field, is the magnetic permeability in vacuum, is the magnitude of the current flowing through the wire, and the magnitude of the magnetic field generated by the chip wire is:

[0045] (2)

[0046] in, represents the magnitude of the Z-direction component of the magnetic field, Indicates the distance from the wire spool;

[0047] The magnetic field gradient is:

[0048] (3)

[0049] in, Indicates the magnetic permeability of the medium;

[0050] The curvature of the magnetic field is:

[0051] (4)

[0052] Wherein, L represents the length of the middle straight wire;

[0053] The magnetic trap capture frequency is:

[0054] (5)

[0055] in, represents the Landau factor, represents the magnetic quantum number, represents the Bohr magneton, represents the static magnetic field gradient, represents the curvature of the magnetic field induction line of the magnetic trap, represents the magnetic trap capture frequency, and m represents the atomic mass.

[0056] Therefore, the depth and compactness of the magnetic trap are closely related to the bias magnetic field and current. When the current is constant, the greater the bias magnetic field, the greater the gradient of the magnetic trap generated by the chip, the closer the center of the magnetic trap is to the chip surface, the greater the curvature of the magnetic induction line, and the greater the potential trap capture frequency. Therefore, the deeper the magnetic trap, the steeper and more compact it is. As shown in formula (4), since Z0 is much smaller than L, the curvature of the magnetic trap mainly depends on the size of L. The larger L is, the lower the curvature. The smaller the L, the better. However, in order to simultaneously satisfy the requirements of transferring the internal magnetic trap from the external magnetic trap, the present invention designs two wires with different L lengths. In summary, for micro-nano fabricated wires with a width of a few microns or less, the maximum field gradient can reach about 10 7 G / cm, and leads to a potential trap frequency of up to 1 MHz. This is several orders of magnitude higher than that of conventional magnetic traps, so micro-sized atomic chip magnetic traps can achieve rapid evaporation and reach BEC in about seconds.

[0057] A method for preparing ultracold atoms, using the above-mentioned microchip, comprises the following steps:

[0058] S1, such as Figure 5 、 Figure 6As shown, the microchip is mounted on the connecting board to form a chip assembly 32 and connected to an external power supply through the connecting board. The connection method is as follows: the microchip is positioned by the silk screen pattern 30 and connected to the PCB substrate 31 through epoxy resin glue. The surface pins of the microchip are connected to the surface square pads 29 through thin metal wires. The square pads 29 are connected to the via pads 28 through wires. The via pads 28 are finally connected to the power supply through an external pin header to power the chip. After the connection is completed, the chip assembly 32 is connected to the all-quartz vacuum chamber 33. The chip assembly 32, the all-quartz vacuum chamber 33 and the glass tube 34 together form a chip vacuum cavity. The chip vacuum cavity is locked together with the vacuum indium sealing flange 36 and connected to the vacuum pump group to achieve an ultra-high vacuum experimental environment; a three-axial bias magnetic field is set outside the chip, and the three-axial bias magnetic field includes an x-axial bias magnetic field Bx25, a y-axial bias magnetic field By26, and a z-axial bias magnetic field Bz20; the bias magnetic field is generated by a Helmholtz coil, and the Helmholtz coil is fixedly connected to the coil overall frame 27 through the magnetic field coil frame 23.

[0059] S2. A cooling light field is set above the chip component 32, wherein the cooling light field includes horizontal incident light 37 and two pairs of cooling lights 42 with an oblique angle of 45° to the surface of the chip component 32. The oblique cooling light 42 includes left incident light 40, left reflected light 41, right incident light 38, and right reflected light 39; wherein the left incident light 40 is reflected by the chip component 32 to form the right reflected light 39, and the right reflected light 39 forms a paired beam with the right incident light 38. The right incident light 38 is reflected by the chip component 32 to form the left reflected light 41, and the left reflected light 41 forms a paired beam with the left incident light 40. The horizontal incident light 37 forms a paired beam with the return light, forming three pairs of cooling light beams in three-dimensional space to form a cooling light field.

[0060] S3. Connect the third pin 3 or the ninth pin 9 to the positive pole of the power supply, and the corresponding fourth pin 4 or the tenth pin 10 to the negative pole of the power supply, with a current of 1A-4A, and turn on the y-axial bias magnetic field By26 at the same time. At this time, a U-shaped trap is formed under the chip, and a U-shaped magneto-optical trap is formed in combination with the external cooling light field. The U-shaped magneto-optical trap traps cold atoms from the background rubidium vapor; turn off the y-axial bias magnetic field By26, and only use the cooling light for polarization gradient cooling; connect the first pin 1 or the sixth pin 6 to the positive pole of the power supply, and the corresponding twelfth pin 12 or the seventh pin 7 to the negative pole of the power supply, with a current of 1A-4A, and turn on the y-axial bias magnetic field By26 at the same time. Combined with the external cooling light field, a Z-shaped magneto-optical trap with L3=2mm is formed, and the x-axial bias magnetic field Bx25 and the z-axial bias magnetic field Bz20 are turned on at the same time to adjust the three axes. The bias magnetic field is used to bring the center of the U-shaped magneto-optical trap close to the chip surface until it coincides with the center of the Z-shaped magneto-optical trap of L3=2mm; the power supply of the pin connected to the U-shaped wire is turned off, and the U-shaped magneto-optical trap is turned off, thereby realizing the transfer of atoms from the loaded magneto-optical trap to the cooled magneto-optical trap; finally, the second pin 2 or the fifth pin 5 is connected to the positive pole of the power supply, and the corresponding eleventh pin 11 or the eighth pin 8 is connected to the negative pole of the power supply. At this time, a Z-shaped magneto-optical trap of L2=1.2mm is formed in conjunction with the y-axial external bias magnetic field By26. By adjusting the three-axial bias magnetic field, the atoms are transferred to the Z-shaped magneto-optical trap of L2=1.2mm, and the final evaporative cooling is performed in the Z-shaped magneto-optical trap. The high-energy atoms are gradually expelled from the potential well, and the remaining low-energy atoms collide again to reach thermal equilibrium. Finally, the atomic temperature reaches the nK level, realizing the preparation of ultracold atoms.

[0061] When the present invention is used in conjunction with an external vacuum chamber, the wire material and structure manufactured using micro-nano processing technology can be well bonded to the quartz vacuum chamber. For example, when epoxy resin glue is used for sealing, the vacuum degree can reach 5e-7Pa.

Claims

1. A microchip for preparing ultracold atoms, characterized in that: It includes a wire etching layer (17), an oxidation isolation layer (18), and a chip substrate (19); An oxide isolation layer (18) is provided on the chip substrate (19), a wire etching layer (17) is provided on the oxide isolation layer (18) by ion evaporation sputtering, wires are etched on the wire etching layer (17) by photolithography, and the groove size between the wires is 15 μm; The conductors include: a first Z-shaped conductor, a second Z-shaped conductor, a third Z-shaped conductor, a fourth Z-shaped conductor, a first U-shaped conductor, a second U-shaped conductor, and a transversely connected straight conductor; The wire etching layer (17) is provided with chip pins, and the number of the chip pins is 14. The chip pins include: a first pin (1), a second pin (2), a third pin (3), a fourth pin (4), a fifth pin (5), a sixth pin (6), a seventh pin (7), an eighth pin (8), a ninth pin (9), a tenth pin (10), an eleventh pin (11), a twelfth pin (12), a thirteenth pin (13), and a fourteenth pin (14); wherein the first pin (1) and the twelfth pin (12) are connected to the first Z-shaped wire, the second pin (2) and the eleventh pin (11) are connected to the second Z-shaped wire, the fifth pin (5) and the eighth pin (8) are connected to the third Z-shaped wire, the sixth pin (6) and the seventh pin (7) are connected to the fourth Z-shaped wire, the third pin (3) and the fourth pin (4) are connected to the first U-shaped wire, the ninth pin (9) and the tenth pin (10) are connected to the second U-shaped wire, and the thirteenth pin (13) and the fourteenth pin (14) are connected to the horizontal connecting straight wire; Wherein, the thirteenth pin (13) and the fourteenth pin (14), the first pin (1) and the twelfth pin (12), the sixth pin (6) and the seventh pin (7) are connected at the same time to form a first H-type wire, and the thirteenth pin (13) and the fourteenth pin (14), the second pin (2) and the eleventh pin (11), the fifth pin (5) and the eighth pin (8) are connected at the same time to form a second H-type wire; The first U-shaped wire and the second U-shaped wire together form a double U-shaped wire (15), the middle straight wire size of the double U-shaped wire (15) is L1=0.9mm, the middle straight wire size of the first H-shaped wire L3=2mm, the middle straight wire size of the second H-shaped wire L2=1.2mm, and the first H-shaped wire and the second H-shaped wire together form a double H-shaped wire (16); the double U-shaped wire (15) is symmetrically distributed about the horizontal center line of the chip, the middle straight wire of the double H-shaped wire (16) coincides with the horizontal center line of the chip, and the vertical wires on both sides are symmetrically distributed about the vertical center line of the chip.

2. A microchip for preparing ultracold atoms according to claim 1, characterized in that: The chip size is 36x36mm, and the wire drawing area size on the chip is 2x3mm.

3. A microchip for preparing ultracold atoms according to claim 1, characterized in that: The wire etching layer (17) is a pure gold wire layer with a thickness of 5 μm; the oxidation isolation layer (18) is a SiO2 oxidation isolation layer with a thickness of 20 nm; and the chip substrate (19) is a Si chip substrate with a thickness of 0.5 mm.

4. A microchip for preparing ultracold atoms according to claim 1, characterized in that: The double U-shaped wire (15) has a line width of 300 μm, a thickness of 5 μm, and is made of pure gold; the double H-shaped wire (16) has a line width of 100 μm, a thickness of 5 μm, and is made of pure gold.

5. A method for preparing ultracold atoms, characterized in that: Using the microchip according to any one of claims 1 to 4, comprising the following steps: (S1) The microchip is mounted on a connecting plate to form a chip assembly (32) and connected to an external power supply through the connecting plate, and then the chip assembly (32) is connected to an all-quartz vacuum chamber (33). The chip assembly (32), the all-quartz vacuum chamber (33) and the glass tube (34) together form a chip vacuum cavity. The chip vacuum cavity is locked together with a vacuum indium sealing flange (36) and connected to a vacuum pump group to achieve an ultra-high vacuum experimental environment; a three-axial bias magnetic field is set outside the chip, and the three-axial bias magnetic field includes an x-axial bias magnetic field Bx (25), a y-axial bias magnetic field By (26), and a z-axial bias magnetic field Bz (20); (S2) a cooling light field is provided above the chip assembly (32), wherein the cooling light field includes horizontal incident light (37), two pairs of cooling lights (42) with an oblique angle of 45° to the surface of the chip assembly (32), and the oblique angle cooling light (42) includes left incident light (40), left reflected light (41), right incident light (38), and right reflected light (39); wherein the left incident light (40) is reflected by the mirror surface of the chip assembly (32) to form the right reflected light (39), the right reflected light (39) and the right incident light (38) form a pair of light beams, the right incident light (38) is reflected by the mirror surface of the chip assembly (32) to form the left reflected light (41), the left reflected light (41) and the left incident light (40) form a pair of light beams, and the horizontal incident light (37) and the return light form a pair of light beams, thereby forming three pairs of cooling light beams in three-dimensional space to form a cooling light field; (S3) Connect the third pin (3) or the ninth pin (9) to the positive pole of the power supply, connect the fourth pin (4) or the tenth pin (10) to the negative pole of the power supply, and the current is 1A-4A. At the same time, turn on the y-axis bias magnetic field By (26). At this time, a U-shaped trap is formed under the chip, and a U-shaped magneto-optical trap is formed in combination with the external cooling light field. The U-shaped magneto-optical trap traps cold atoms from the background rubidium vapor; turn off the y-axis bias magnetic field By (26), and only use the cooling light for polarization gradient cooling; connect the first pin (1) or the sixth pin (6) to the positive pole of the power supply, connect the twelfth pin (12) or the seventh pin (7) to the negative pole of the power supply, and the current is 1A-4A. At the same time, turn on the y-axis bias magnetic field By (26), and form a Z-shaped magneto-optical trap with L3=2mm in combination with the external cooling light field. At the same time, turn on the x-axis bias magnetic field Bx (25) and the z-axis bias magnetic field Bz ( 20), adjust the three-axial bias magnetic field to bring the center of the U-shaped magneto-optical trap close to the chip surface until it coincides with the center of the Z-shaped magneto-optical trap of L3=2mm; turn off the power supply of the pin connected to the U-shaped wire, turn off the U-shaped magneto-optical trap, and realize the transfer of atoms from the loading magneto-optical trap to the cooling magneto-optical trap; finally, connect the second pin (2) and the fifth pin (5) or the positive pole of the power supply, and connect the eleventh pin (11) or the eighth pin (8) to the negative pole of the power supply. At this time, cooperate with the y-axial bias magnetic field By (26) to form a Z-shaped magneto-optical trap of L2=1.2mm. By adjusting the three-axial bias magnetic field, the atoms are transferred to the Z-shaped magneto-optical trap of L2=1.2mm, and the final evaporative cooling is performed in the Z-shaped magneto-optical trap. The high-energy atoms are gradually expelled from the potential well, and the remaining low-energy atoms collide again to reach thermal equilibrium. Finally, the atomic temperature reaches the nK level, and the preparation of ultracold atoms is realized.

6. A method for preparing ultracold atoms according to claim 5, characterized in that: The connecting plate in step (S1) includes a via pad (28), a surface square pad (29), a silk screen pattern (30), and a PCB substrate (31); the microchip and the connecting plate are connected in the following manner: the microchip is positioned by the silk screen pattern (30) and connected to the PCB substrate (31) by epoxy resin glue, the surface pins of the microchip are connected to the surface square pad (29) by thin metal wires, the surface square pad (29) is connected to the via pad (28) by wires, and the via pad (28) is finally connected to the power supply by an external pin row to realize power supply of the chip.

7. The method for preparing ultracold atoms according to claim 5, characterized in that: The bias magnetic field is generated by a Helmholtz coil, and the Helmholtz coil is fixedly connected to the coil overall frame (27) via a magnetic field coil frame (23).

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