Method for manufacturing packaging substrate

Abstract

A method for manufacturing a package substrate includes sequentially forming a first metal layer and a second metal layer on two opposite surfaces of a plate body; forming a circuit structure on each of the second metal layers to form a multilayer plate group; arranging the multilayer plate group on opposite sides of a support; using the second metal layer closest to the support as a separation line to separate a processed plate member having the support member and two intermediate plates having the plate body; arranging the intermediate plate member with its circuit structure on opposite sides of another support member; removing the plate body and the first metal layer to obtain a processed plate member having the other support member; forming a wiring layer on the circuit structure of each of the processed plates by means of the second metal layer, and then removing each of the supports. Therefore, by configuring the support member, the toughness of the multilayer plate group in the process can be improved.

Description

Technical Field

[0001] The invention relates to a semiconductor packaging process, and in particular to a packaging substrate capable of improving reliability and a manufacturing method thereof. Background Art

[0002] With the rapid development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in shape, and their functions are developing in the direction of high performance, high functionality and high speed. Therefore, in order to meet the needs of high integration and miniaturization of semiconductor devices, packaging substrates with high-density and fine-pitch circuits are often used in the packaging process.

[0003] Figures 1A to 1D It is a cross-sectional schematic diagram of a conventional method for manufacturing a packaging substrate 1 .

[0004] like Figure 1A As shown, a carrier 9 is provided, wherein the two opposite surfaces of the plate body 90 thereof have a first metal layer 91 such as a thicker copper foil, and a second metal layer 92 such as a thinner copper foil is formed on each of the first metal layers 91 to form a wiring layer 10 on each of the second metal layers 92 .

[0005] like Figure 1B As shown, a circuit structure 11 is formed on each of the second metal layers 92, which includes a dielectric layer 110 formed on the second metal layer 92 and the wiring layer 10, a circuit layer 111 formed on the dielectric layer 110, and a plurality of conductive blind holes 112 formed in the dielectric layer 110, so that the plurality of conductive blind holes 112 electrically connect the circuit layer 111 and the wiring layer 10.

[0006] like Figure 1C As shown, another circuit structure 11 is formed on each of the circuit structures 11 .

[0007] like Figure 1D As shown, the carrier 9 is removed to form a plurality of coreless packaging substrates 1 .

[0008] However, the existing packaging substrate 1 is a coreless embedded circuit specification, so the packaging substrate 1 is relatively weak and is prone to warping, bending or other deformation problems during the process. Therefore, it is not suitable to use an ultra-thin dielectric layer 110, which makes it difficult to meet the thinning requirements.

[0009] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Summary of the invention

[0010] An object of the present invention is to provide a method for manufacturing a packaging substrate to solve at least one of the above problems.

[0011] In view of the various defects of the above-mentioned prior art, the present invention provides a method for manufacturing a packaging substrate, including: providing a carrier having a plate body, a first metal layer formed on two opposite surfaces of the plate body, and a second metal layer formed on the first metal layer; forming a first circuit structure on each of the second metal layers; forming a second circuit structure on each of the first circuit structures to form a multi-layer board group by the carrier, the first circuit structure and the second circuit structure; arranging the multi-layer board group on opposite sides of a first support member respectively; using the second metal layer of the carrier adjacent to the first support member as a separation line to separate a first processed board member having the first support member and two intermediate boards having the plate body; arranging the intermediate board member on opposite sides of a second support member; removing the plate body and the first metal layer on opposite sides of the second support member to obtain a second processed board member having the second support member; forming a wiring layer on the first circuit structures of the first processed board member and the second processed board member by means of the second metal layer; and removing the first and second supports to obtain multiple packaging substrates.

[0012] In the aforementioned manufacturing method, the first circuit structure includes a first dielectric layer formed on the second metal layer, a first circuit layer formed on the first dielectric layer, and a plurality of first conductive blind holes formed in the first dielectric layer, so that the plurality of first conductive blind holes electrically connect the first circuit layer and the wiring layer. Further, the second circuit structure includes a second dielectric layer formed on the first circuit structure, a second circuit layer formed on the second dielectric layer, and a plurality of second conductive blind holes formed in the second dielectric layer, so that the plurality of second conductive blind holes electrically connect the second circuit layer and the first circuit layer. For example, the first conductive blind hole and the second conductive blind hole are cone-shaped, and the first conductive blind hole and the second conductive blind hole are stacked in the same direction, so that the cone bottom of the first conductive blind hole butts against the cone top of the second conductive blind hole.

[0013] In the aforementioned manufacturing method, the first processed plate and the second processed plate have the same structure.

[0014] In the above-mentioned manufacturing method, the first support member and / or the second support member is a thermal dissociation tape or a temporarily removable plate with adhesiveness. For example, a solder mask is formed on the second circuit structure so that the multi-layer board assembly is bonded to the first support member with its solder mask, and the intermediate board is bonded to the second support member with its solder mask.

[0015] In the aforementioned manufacturing method, the first circuit structure includes a first dielectric layer formed on the second metal layer and a first circuit layer formed on the first dielectric layer, and when forming the wiring layer, a plurality of first conductive blind holes are formed in the first dielectric layer, so that the plurality of first conductive blind holes electrically connect the first circuit layer and the wiring layer. Further, the second circuit structure includes a second dielectric layer formed on the first circuit structure, a second circuit layer formed on the second dielectric layer, and a plurality of second conductive blind holes formed in the second dielectric layer, so that the plurality of second conductive blind holes electrically connect the second circuit layer and the first circuit layer. For example, the first conductive blind hole and the second conductive blind hole are cone-shaped, and the first conductive blind hole and the second conductive blind hole are stacked inversely with each other, so that the cone top of the first conductive blind hole butts against the cone top of the second conductive blind hole.

[0016] As can be seen from the above, the method for manufacturing the packaging substrate of the present invention mainly improves the toughness of the multilayer board group during the process by pressing the multilayer board group on the opposite sides of the first support member. Therefore, compared with the prior art, the first and second circuit structures of the present invention can effectively avoid the problems of warping, bending or other deformation during the process, so ultra-thin dielectric layers can be used as the first and second dielectric layers to meet the thinning requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figures 1A to 1D It is a cross-sectional schematic diagram of a conventional method for manufacturing a packaging substrate.

[0018] FIG. 2A to FIG. 2H It is a cross-sectional schematic diagram of a first embodiment of a method for manufacturing a packaging substrate of the present invention.

[0019] FIG. 3A to FIG. 3D It is a cross-sectional schematic diagram of a second embodiment of a method for manufacturing a packaging substrate of the present invention.

[0020] The reference numerals are as follows:

[0021] 1,2,3 Package substrate

[0022] 10,20 wiring layers

[0023] 11 Line structure

[0024] 110 Dielectric layer

[0025] 111 Circuit layer

[0026] 112 Conductive blind vias

[0027] 2a, 3a First processed plate

[0028] 2b, 3b Second processing plate

[0029] 21,31 First Line Structure

[0030] 210 first dielectric layer

[0031] 211 First circuit layer

[0032] 212,312 first conductive blind via

[0033] 22 Second Line Structure

[0034] 220 second dielectric layer

[0035] 221 Second circuit layer

[0036] 222 Second conductive blind hole

[0037] 23,24 solder mask

[0038] 6a First support member

[0039] 6b Second support member

[0040] 7 Multilayer Board Group

[0041] 8 Intermediary board

[0042] 9 Bearing

[0043] 90 plate body

[0044] 91 First Metal Layer

[0045] 92 Second metal layer DETAILED DESCRIPTION

[0046] The following is an explanation of the embodiments of the present invention by means of specific embodiments. A person skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0047] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be produced by the present invention, should still fall within the scope of the technical contents disclosed in the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0048] FIG. 2A to FIG. 2H It is a cross-sectional schematic diagram of a first embodiment of a method for manufacturing a packaging substrate 2 of the present invention.

[0049] like Figure 2A As shown, a carrier 9 is provided, which has a plate body 90, a first metal layer 91 formed on two opposite surfaces of the plate body 90, and a second metal layer 92 formed on the first metal layer 91, so as to form a first circuit structure 21 on each of the second metal layers 92, which includes a first dielectric layer 210 formed on the second metal layer 92, a first circuit layer 211 formed on the first dielectric layer 210, and a plurality of first conductive blind holes 212 formed in the first dielectric layer 210, so that the plurality of first conductive blind holes 212 electrically connect the first circuit layer 211 and the second metal layer 92.

[0050] In this embodiment, the first metal layer 91 is a thick copper layer such as copper foil, with a thickness of about 18 micrometers (um), so that the carrier 9 becomes a copper clad laminate (CCL). For example, the second metal layer 92 is a thin copper layer with a thickness of about 3 micrometers, which is formed on the first metal layer 91 by electroplating or deposition.

[0051] Furthermore, the first dielectric layer 210 is ABF film (Ajinomoto build-up film), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials.

[0052] In addition, the first circuit layer 211 is manufactured by electroplating metal (such as copper) or other methods using a build-up process. For example, a plurality of holes are first formed on the first dielectric layer 210 using a laser, and then copper is electroplated on the first dielectric layer 210 and in the holes to form the first circuit layer 211 and the first conductive blind via 212 as a whole.

[0053] In addition, the first circuit layer 211 and the first conductive blind via 212 adopt the specification of a redistribution layer (RDL), and the first conductive blind via 212 is in a cone-shaped column.

[0054] like Figure 2BAs shown, a second circuit structure 22 is formed on each of the first circuit structures 21 to form a multilayer board group 7 by the carrier 9, the first circuit structure 21 and the second circuit structure 22, wherein the second circuit structure 22 includes a second dielectric layer 220 formed on the first dielectric layer 210 and the first circuit layer 211, a second circuit layer 221 formed on the second dielectric layer 220 and a plurality of second conductive blind holes 222 formed in the second dielectric layer 220, so that the plurality of second conductive blind holes 222 electrically connect the first circuit layer 211 and the second circuit layer 221.

[0055] In this embodiment, the second dielectric layer 220 is ABF film (Ajinomoto build-up film), polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials.

[0056] Furthermore, the second circuit layer 221 is manufactured by electroplating metal (such as copper) or other methods using a build-up process. For example, a plurality of holes are first formed on the second dielectric layer 220 using a laser, and then copper is electroplated on the second dielectric layer 220 and in the holes to form the second circuit layer 221 and the second conductive blind via 222 as a whole.

[0057] In addition, the second circuit layer 221 and the second conductive blind via 222 adopt the specification of a redistribution layer (RDL), and the second conductive blind via 222 is in a cone-shaped column.

[0058] In addition, a solder mask 23 , such as green paint, is formed on the second circuit structure 22 (ie, the outermost circuit structure), and a plurality of openings are formed on each of the solder mask layers 23 to expose the second circuit layer 221 .

[0059] It should be understood that by using the build-up method, the number of layers of the circuit structure can be designed according to demand to produce the required number of circuit layers.

[0060] like Figure 2C As shown, the multi-layer board set 7 is respectively arranged on two opposite sides of a first support member 6a, and the multi-layer board set 7 is combined on the first support member 6a with its solder mask layer 23.

[0061] In this embodiment, the first support member 6a is a thermal release tape or a temporarily removable adhesive plate, such as a double-sided thermal release film.

[0062] like Figure 2DAs shown, the second metal layer 92 of the carrier 9 adjacent to the first support member 6a is used as a separation line for panel dismantling to separate a first processed panel 2a having the first support member 6a and two intermediate panels 8 having the panel body 90, wherein the first processed panel 2a has the second metal layer 92 on opposite sides.

[0063] like Figure 2E As shown, the intermediate board 8 is disposed on two opposite sides of a second support member 6 b , and the intermediate board 8 is combined on the second support member 6 b with its solder mask 23 .

[0064] In this embodiment, the second support member 6b is a thermal release tape or a temporarily removable adhesive plate, such as a double-sided thermal release film.

[0065] like Figure 2F As shown, the plate body 90 and the first metal layer 91 on the opposite sides of the second support member 6b are removed to obtain a second processed plate member 2b having the second support member 6b, so that the opposite sides of the second processed plate member 2b have the second metal layer 92.

[0066] In this embodiment, the first processing plate 2a (such as Figure 2D ) has the same structure as the second processed plate 2b.

[0067] like Figure 2G As shown, a patterned wiring process is performed on the first processing board 2a and the second processing board 2b to form a wiring layer 20 on the first circuit structure 21 by means of the second metal layer 92, so that the first conductive blind hole 212 electrically connects the wiring layer 20 and the first circuit layer 211.

[0068] In this embodiment, the wiring layer 20 adopts a redistribution layer (RDL) specification.

[0069] In addition, another solder mask 24, such as green paint, is formed on the first circuit structure 21, and a plurality of openings exposing the wiring layer 20 are formed on each of the solder mask layers 24, so that in subsequent processes, a plurality of solder balls (not shown) can be combined on the exposed surface of the wiring layer 20 and / or the second circuit layer 221 for external electronic devices (such as semiconductor chips, passive components, silicon interposers, circuit boards or other components).

[0070] like Figure 2H As shown, the first support member 6 a and the second support member 6 b are removed by heating to obtain a plurality of (eg, four) coreless packaging substrates 2 .

[0071] In this embodiment, the first conductive blind via 212 and the second conductive blind via 222 of the package substrate 2 are stacked in the same direction, so that the cone bottom of the first conductive blind via 212 butts against the cone top of the second conductive blind via 222 to form a tower shape.

[0072] Therefore, the manufacturing method of this embodiment mainly presses the multilayer board group 7 on the opposite sides of the first support member 6a to improve the toughness of the multilayer board group during the process. Therefore, compared with the prior art, the first circuit structure 21 and the second circuit structure 22 can avoid problems such as warping, bending or other deformation during the process, so that ultra-thin dielectric layers can be used as the first dielectric layer 210 and the second dielectric layer 220 to meet the thinning requirements.

[0073] Furthermore, by combining the extremely thin multilayer board group 7 to the two opposite surfaces of the first support member 6a for processing, the structural thickness required for the process is increased, so that the processability of the ultra-thin multilayer board group 7 is not limited by the equipment performance, so as to achieve the equipment capacity of the minimum board thickness. Therefore, the method for manufacturing the packaging substrate 2 can use traditional processing equipment to process any ultra-thin multilayer board group 7 in the above-mentioned manner (for example, the thickness of the multilayer board group 7 can be 0.01, 0.015, 0.02, 0.03, 0.04 mm, etc.), so there is no need to use special special equipment, which can greatly reduce the processing cost.

[0074] In addition, by combining two intermediate boards 8 having the board body 90 on opposite sides of the second support member 6b, and then removing the board body 90 and the first metal layer 91 on opposite sides of the second support member 6b to obtain another processed board (i.e., the second processed board 2b having the second support member 6b), the method for manufacturing the packaging substrate 2 can perform a patterned wiring process on two groups of processed boards (the first processed board 2a and the second processed board 2b) to obtain more packaging substrates 2, thereby increasing production.

[0075] In addition, the first support member 6a and the second support member 6b are removed by heating to weaken the adhesion between each support member and the solder mask 23, so that when the first support member 6a and the second support member 6b are removed, the surface of the package substrate 2 can be prevented from being damaged.

[0076] FIG. 3A to FIG. 3D The cross-sectional view of the second embodiment of the method for manufacturing the package substrate 3 of the present invention is shown in FIG. The difference between this embodiment and the first embodiment lies in the manufacturing sequence of the first conductive blind via 312 , and the other processes are substantially the same, so the same points will not be described in detail below.

[0077] like Figure 3A As shown in Figure 2AIn the process, the first conductive blind hole 212 is not formed when the first circuit structure 31 is manufactured. Therefore, the first circuit structure 31 includes a first dielectric layer 210 formed on the second metal layer 92 and a first circuit layer 211 formed on the first dielectric layer 210, but does not have a first conductive blind hole.

[0078] like Figure 3B As shown, using FIG. 2B to FIG. 2F The process is used to obtain a first processed plate 3a having the first support member 6a and a second processed plate 3b having the second support member 6b.

[0079] like Figure 3C As shown, a patterned wiring process is performed on the first processed board 3a and the second processed board 3b to form a wiring layer 20 on the first circuit structure 31 by means of the second metal layer 92, and when forming the wiring layer, a plurality of first conductive blind holes 312 are formed in the first dielectric layer 210 of the first circuit structure 31, so that the first conductive blind holes 312 electrically connect the wiring layer 20 and the first circuit layer 211.

[0080] In this embodiment, the wiring layer 20 is manufactured by a build-up process by electroplating metal (such as copper) or other methods. For example, a plurality of holes are first formed on the first dielectric layer 210 by laser, and then copper is electroplated on the first dielectric layer 210 and in the holes to form the wiring layer 20 and the first conductive blind via 312 as a whole.

[0081] Furthermore, the wiring layer 20 and the first conductive blind via 312 adopt the redistribution layer (RDL) specification, and the first conductive blind via 312 is in a cone-shaped column.

[0082] In addition, another solder mask 24, such as green paint, is formed on the first circuit structure 31, and a plurality of openings exposing the wiring layer 20 are formed on each of the solder mask layers 24, so that in subsequent processes, a plurality of solder balls (not shown) can be combined on the exposed surface of the wiring layer 20 and / or the second circuit layer 221 for external electronic devices (such as semiconductor chips, passive components, silicon interposers, circuit boards or other components).

[0083] like Figure 3D As shown, the first support member 6 a and the second support member 6 b are removed to obtain a plurality of coreless packaging substrates 3 .

[0084] In this embodiment, the first conductive blind via 312 and the second conductive blind via 222 of the package substrate 3 are stacked opposite to each other, so that the cone top of the first conductive blind via 312 butts against the cone top of the second conductive blind via 222 to form a gourd-like or X-shaped shape.

[0085] Therefore, the method for manufacturing the packaging substrate of the present invention improves the toughness of the multilayer board group during the process by pressing the multilayer board group on the opposite sides of the first support member. Therefore, the first and second circuit structures of the present invention can avoid problems such as warping, bending or other deformation during the process, and thus ultra-thin dielectric layers can be used as the first and second dielectric layers to meet the thinning requirements.

[0086] Furthermore, by combining a multilayer board group with extremely thin thickness onto two opposite surfaces of the first support member for processing, the structural thickness required for the process is increased, so that the processability of the ultra-thin multilayer board group is not limited by the performance of the equipment, so as to achieve the equipment capacity of the minimum board thickness. Therefore, the manufacturing method of the present invention can use traditional processing equipment to process any ultra-thin multilayer board group in the above manner, so there is no need to use special equipment, which can greatly reduce the processing cost.

[0087] In addition, by combining two intermediate boards with the board body on the opposite sides of the second support member, and then removing the board body and the first metal layer on the opposite sides of the second support member to obtain another processed board, the two sets of processed boards can be subjected to patterned wiring process to obtain more packaging substrates, thereby increasing production.

[0088] In addition, the support member is removed by heating to weaken the adhesion between the support member and the solder mask layer, so that when each support member is removed, damage to the surface of the packaging substrate can be avoided.

[0089] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Those skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. A method for manufacturing a packaging substrate, comprising: Providing a carrier having a plate body, a first metal layer formed on two opposite surfaces of the plate body, and a second metal layer formed on the first metal layer; forming a first circuit structure on each of the second metal layers; forming a second circuit structure on each of the first circuit structures, so as to form a multilayer board assembly by the carrier, the first circuit structure and the second structure; The multilayer board set is respectively arranged on two opposite sides of the first support member; Using the second metal layer of the carrier adjacent to the first support member as a separation line to separate a first processed plate member having the first support member and two intermediate plates having the plate bodies; The intermediate plate is disposed on two opposite sides of the second support member; Removing the plate body and the first metal layer on two opposite sides of the second support member to obtain a second processed plate member having the second support member; Forming a wiring layer on the first circuit structure of the first processed board and the second processed board by using the second metal layer; as well as The first supporting member and the second supporting member are removed to obtain a plurality of packaging substrates.

2. The method for manufacturing a packaging substrate according to claim 1, wherein: The first circuit structure includes a first dielectric layer formed on the second metal layer, a first circuit layer formed on the first dielectric layer, and a plurality of first conductive blind holes formed in the first dielectric layer, so that the plurality of first conductive blind holes electrically connect the first circuit layer and the wiring layer.

3. The method for manufacturing a packaging substrate according to claim 2, wherein: The second circuit structure includes a second dielectric layer formed on the first circuit structure, a second circuit layer formed on the second dielectric layer, and a plurality of second conductive blind vias formed in the second dielectric layer, so that the plurality of second conductive blind vias electrically connect the second circuit layer and the first circuit layer.

4. The method for manufacturing a packaging substrate according to claim 3, wherein: The first conductive blind hole and the second conductive blind hole are cone-shaped, and the first conductive blind hole and the second conductive blind hole are stacked in the same direction, so that the cone bottom of the first conductive blind hole butts against the cone top of the second conductive blind hole.

5. The method for manufacturing a packaging substrate according to claim 1, wherein: The first processed plate and the second processed plate have the same structure.

6. The method for manufacturing a packaging substrate according to claim 1, wherein: The first supporting member and / or the second supporting member is a thermally dissociable adhesive tape or a temporarily removable adhesive plate.

7. The method for manufacturing a packaging substrate according to claim 6, wherein: A solder mask is formed on the second circuit structure, so that the multi-layer board assembly is combined with the first support member by its solder mask, and the intermediate board is combined with the second support member by its solder mask.

8. The method for manufacturing a packaging substrate according to claim 1, wherein: The first circuit structure includes a first dielectric layer formed on the second metal layer and a first circuit layer formed on the first dielectric layer. When forming the wiring layer, a plurality of first conductive blind holes are formed in the first dielectric layer so that the plurality of first conductive blind holes electrically connect the first circuit layer and the wiring layer.

9. The method for manufacturing a packaging substrate according to claim 8, wherein: The second circuit structure includes a second dielectric layer formed on the first circuit structure, a second circuit layer formed on the second dielectric layer, and a plurality of second conductive blind vias formed in the second dielectric layer, so that the plurality of second conductive blind vias electrically connect the second circuit layer and the first circuit layer.

10. The method for manufacturing a packaging substrate according to claim 9, wherein: The first conductive blind hole and the second conductive blind hole are cone-shaped, and the first conductive blind hole and the second conductive blind hole are stacked opposite to each other, so that the cone top of the first conductive blind hole butts against the cone top of the second conductive blind hole.

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