A built-in high-side charge pump circuit

Abstract

The present invention relates to a built-in high-side charge pump circuit, which belongs to the field of monolithic bridge drive circuit design. It is mainly composed of a clock control circuit, a pump circuit and a limiting circuit. The clock control circuit is composed of a non-overlapping clock generation circuit and a control tube, which generates two non-overlapping clock signals from a square wave signal CLK with a certain amplitude; the pump circuit is mainly composed of a capacitor and a switch tube, the working frequency of the switch tube determines the charging and discharging time of the capacitor, and the high-side suspension ground HS is pumped up by the charge conservation law of the capacitor to control the power supply voltage VDD to output the high-side power supply potential HB. The limiting circuit is mainly composed of a voltage regulator tube and a diode cascade, so that the charge pump voltage is output stably. The built-in high-side charge pump circuit of the high-low-side dual-channel drive chip solves the charge supplement problem of the high-side drive circuit powered by an external bootstrap capacitor working in a continuous on-state when outputting a high-level drive signal, and provides a stable high-side power supply.

Description

Technical Field

[0001] The invention belongs to the field of monolithic bridge drive circuit design, and in particular relates to a built-in high-side charge pump circuit. Background Art

[0002] With the introduction of concepts such as miniaturization and high reliability of DC motor drive systems, higher-level requirements have been put forward for the working mode of monolithic bridge drive circuits. DC motor drive systems mainly include three topologies: high- and low-side dual-circuit, H-bridge, and three-phase bridge. They are made of monolithic bridge drive circuits combined with high- and low-side totem pole N-type power switch tubes. Sufficient gate-source voltage and switching speed are required to drive the high- and low-side N-type power switch tubes to turn on and off during operation.

[0003] Figure 1 The figure shows an existing high-side and low-side dual-path drive circuit. When the high-side power tube is turned off and the low-side power tube is turned on, one end HS of the bootstrap capacitor is switched to the common ground, and the other end HB is charged by the VDD power supply through the bootstrap diode to supply power to the high-side driver chip when it is turned off; when the high-side power tube is turned on and the low-side power tube is turned off, one end HS of the bootstrap capacitor is switched to the power supply, and the other end HB is bootstrapped to increase a VDD voltage to supply power to the high-side driver chip when it is turned on. The disadvantage of this circuit structure is that when the high-side power tube is turned on, the high-side drive circuit is completely powered by the external bootstrap capacitor. With the power consumption of the high-side drive circuit and the demand for the gate capacitance of the power switch tube, the stored charge of the bootstrap capacitor is transferred in large quantities. If sufficient gate-source voltage of the high-side power tube is to be guaranteed, the bootstrap capacitor must be charged periodically, that is, the bridge drive circuit works in a pulse width modulation (PWM) mode to drive the high-side and low-side power tubes to switch alternately. When the low-frequency drive or high-side drive circuit is in a high duty cycle, the bootstrap capacitor cannot obtain an effective charging cycle, and the stored charge cannot guarantee a reasonable high-side drive conduction state output, and may even be lower than the undervoltage threshold of the high-side drive circuit power supply (HB-HS), and the high-side power switch tube cannot be effectively turned on. Its application in motor drive systems is severely limited. Summary of the invention

[0004] The present invention aims to provide a circuit design of a built-in high-side charge pump. Figure 2 As shown in the figure, when the high-side drive is turned on through the built-in high-side charge pump, a 100uA current output capability is provided to supplement the charge of the external bootstrap capacitor, ensuring that the external bootstrap capacitor has a stable HB-HS voltage, which is used to solve the application problem of low-frequency drive or high-side drive circuit at a duty cycle of up to 100%. As a common application technology, it ensures the continuous and stable operation of the high-side gate drive circuit and provides stable high-side power supply for motor drive systems of various topologies.

[0005] The technical solution adopted by the present invention to achieve the above-mentioned purpose is:

[0006] A built-in high-side charge pump circuit comprises a clock control circuit, a pump circuit and a limiter circuit; the clock control circuit structure is a non-overlapping clock generation circuit, which generates two non-overlapping clock signals from a certain square wave signal CLK and transmits them to the pump circuit; the pump circuit is a switch tube that switches to alternately charge and discharge a secondary capacitor to thereby realize HS potential boosting and transmit it to the limiter circuit; the limiter circuit is composed of a voltage regulator tube and a diode cascade to realize HB-HS voltage stable output.

[0007] The clock control circuit specifically includes inverter 001, inverter 002, inverter 003, inverter 004, NAND gate 001, NAND gate 002, NAND gate 003, NMMOS tubes NMOS8, NMOS12, PMOS tubes PMOS8, PMOS12; the specific connection method is as follows:

[0008] The power supply of the inverter 001 is connected to VDD, the ground of the inverter 001 is connected to VSS, the input terminal of the inverter 001 is connected to the EN enable signal, and the output terminal of the inverter 001 is connected to the input terminal A of the NAND gate 001;

[0009] The power supply of the NAND gate 001 is connected to VDD, the ground of the NAND gate 001 is connected to VSS, the input terminal B of the NAND gate 001 is connected to the square wave signal CLK, and the output terminal of the NAND gate 001 is connected to the input terminal of the inverter 002 and the input terminal A of the NAND gate 003;

[0010] The power supply of the inverter 002 is connected to VDD, the ground of the inverter 002 is connected to VSS, and the output terminal of the inverter 002 is connected to the input terminal A of the NAND gate 002;

[0011] The power supply of the NAND gate 002 is connected to VDD, the ground of the NAND gate 002 is connected to VSS, the input terminal B of the NAND gate 002 is connected to the output terminal of the NAND gate 003, and the output terminal of the NAND gate 002 is connected to the input terminal of the inverter 003 and the input terminal A of the NAND gate 003;

[0012] The power supply of the inverter 003 is connected to VDD, the ground of the inverter 003 is connected to VSS, and the output terminal of the inverter 003 is connected to the gate of the NMOS 8;

[0013] The source of NMOS8 is connected to the ground VSS, the source of PMOS8 is connected to the power supply VDD, the gate of PMOS8 is connected to the output end of the NAND gate 003, and the drains of NMOS8 and PMOS8 are short-circuited as the output end Y2 of the clock control circuit connected to the pump circuit;

[0014] The power supply of the NAND gate 003 is connected to VDD, the ground of the NAND gate 003 is connected to VSS, and the output terminal of the NAND gate 003 is connected to the input terminal of the inverter 004;

[0015] The power supply of the inverter 004 is connected to VDD, the ground of the inverter 004 is connected to VSS, and the output terminal of the inverter 004 is connected to the gate of the NMOS 12;

[0016] The source of NMOS12 is connected to the ground VSS, the source of PMOS12 is connected to the power supply VDD, the gate of PMOS12 is connected to the output end of NAND gate 002, and the drains of NMOS12 and PMOS12 are short-circuited as the output end Y1 of the clock control circuit connected to the pump circuit.

[0017] The pump circuit includes capacitors C1 and C2, and NPN tubes Q1, Q2, and Q3; the upper plate of C1 is connected to the output terminal Y1 of the clock control circuit, the lower plate of C1 is connected to the base and collector of Q1, and the emitter of Q2, and the emitter of Q1 is connected to the high-side drive floating power supply HB pin; the upper plate of C2 is connected to the output terminal Y2 of the clock control circuit, the lower plate of C2 is connected to the base and collector of Q2, and the emitter of Q3, and the emitter of Q3 is connected to the high-side drive floating ground HS pin.

[0018] The limiting circuit includes Zener diodes D0 and D1, a capacitor C3, and N forward conducting diodes DN connected in series; the anode of DN is connected to the HB pin, the cathode of DN is connected to the cathode of D0, the anode of D0 is connected to the cathode of D1, and the anode of D1 is connected to the HS pin; the upper plate of C3 is connected to the HB pin, and the lower plate of C3 is connected to the HS pin.

[0019] The EN input terminal control method is that when a high level "1" is applied to the EN terminal, the clock control circuit is in a disabled state, and the entire built-in high-side charge pump circuit does not work. When a low level "0" is applied to the EN terminal, the clock control circuit is in an enabled state, and the square wave signal CLK with an amplitude of 0 to VDD and a frequency of 1MHz generates two non-overlapping clock signals, and the capacitor potential is periodically switched through the switch tube.

[0020] Compared with the prior art, the present invention has the following beneficial effects and advantages:

[0021] 1. Make full use of the built-in high-side charge pump circuit as an auxiliary power supply to supplement the charge loss when the external bootstrap capacitor is powered, without affecting the topology of the chip's external devices.

[0022] 2. The present invention can be applied to a high-side gate driver chip in a low-frequency or high-duty-cycle PWM or even a constant-on working mode, and can effectively solve the power supply stability problem when the high-side gate driver output is in the on state.

[0023] 3. The built-in high-side charge pump circuit designed in the present invention has a simple structure, clear principle, good process compatibility, can be integrated with the existing high-side gate driver on a single chip, and can be widely used in high-side gate driver chips of bridge drivers with different topologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is the topological structure diagram of the existing high-side and low-side driver chips;

[0025] Figure 2 It is a topological structure diagram of the high and low side driver chip of the present invention;

[0026] Figure 3 The high-side charge pump circuit structure diagram of the present invention;

[0027] Figure 4 A clock control circuit diagram of the present invention;

[0028] Figure 5 A pump circuit diagram of the present invention;

[0029] Figure 6 It is the limiting circuit diagram of the present invention. DETAILED DESCRIPTION

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation method of the present invention is described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the invention, so the present invention is not limited by the specific implementation disclosed below.

[0031] The present invention provides a built-in high-side charge pump circuit, such as Figure 3 As shown, it includes a clock control circuit, a pump circuit and a limiter circuit. The clock control circuit structure is a non-overlapping clock generation circuit, which generates two non-overlapping clock signals from a certain square wave signal CLK; the pump circuit is a switch tube that switches to alternately charge and discharge the secondary capacitor to achieve HS potential boost; the limiter circuit is a limiter for the output of the charge pump, thereby achieving a stable HB-HS voltage output.

[0032] Specifically, the clock control circuit, such as Figure 4As shown, it includes PMOS tube PMOS1, PMOS tube PMOS2, PMOS tube PMOS3, PMOS tube PMOS4, PMOS tube PMOS5, PMOS tube PMOS6, PMOS tube PMOS7, PMOS tube PMOS8, PMOS tube PMOS9, PMOS tube PMOS10, PMOS tube PMOS11, and PMOS tube PMOS12; NMOS tube NMOS1, NMOS tube NMOS2, NMOS tube NMOS3, NMOS tube NMOS4, NMOS tube NMOS5, NMOS tube NMOS6, NMOS tube NMOS7, NMOS tube NMOS8, NMOS tube NMOS9, NMOS tube NMOS10, NMOS tube NMOS11, and NMOS tube NMOS12.

[0033] The connection method is as follows: PMOS1 and NMOS1 form an inverter 001, the source of PMOS1 is connected to VDD as the power supply of the inverter 001, the source of NMOS1 is connected to VSS as the ground of the inverter 001, the gate of PMOS1 and the gate of NMOS1 are short-circuited as the input terminal of the inverter 001 and connected to the EN enable signal, and the drain of PMOS1 and the drain of NMOS1 are short-circuited as the output terminal of the inverter 001 and connected to the input terminal A of the NAND gate 001.

[0034] PMOS2, PMOS3 and NMOS2, NMOS3 form a NAND gate 001. The sources of PMOS2 and PMOS3 are connected to VDD as the power supply of the NAND gate 001, the source of NMOS3, the drain of NMOS2, and the source of NMOS2 are connected to VSS as the ground of the NAND gate 001. The gates of PMOS2 and NMOS2 are short-circuited as the input terminal A of the NAND gate 001 connected to the output terminal of the inverter 001, the gates of PMOS3 and NMOS3 are short-circuited as the input terminal B of the NAND gate 001 connected to the square wave signal CLK, and the drains of PMOS2, PMOS3 and NMOS3 are short-circuited as the output terminal of the NAND gate 001 connected to the input terminal of the inverter 002 and the input terminal A of the NAND gate 003.

[0035] PMOS4 and NMOS4 form an inverter 002, the source of PMOS4 is connected to VDD as the power supply of the inverter 002, the source of NMOS4 is connected to VSS as the ground of the inverter 002, the gate of PMOS4 and the gate of NMOS4 are short-circuited as the input end of the inverter 002 connected to the output end of the NAND gate 001, and the drain of PMOS4 and the drain of NMOS4 are short-circuited as the output end of the inverter 002 connected to the input end A of the NAND gate 002.

[0036] PMOS5, PMOS6 and NMOS5, NMOS6 form a NAND gate 002, the sources of PMOS5 and PMOS6 are connected to VDD as the power supply of the NAND gate 002, the source of NMOS6 and the drain of NMOS5, the source of NMOS5 is short-circuited as the ground of the NAND gate 002 and connected to VSS, the gates of PMOS5 and NMOS5 are short-circuited as the input terminal A of the NAND gate 002 connected to the output terminal of the inverter 002, the gates of PMOS6 and NMOS6 are short-circuited as the input terminal B of the NAND gate 002 connected to the output terminal of the NAND gate 003, and the drains of PMOS5, PMOS6 and NMOS6 are short-circuited as the output terminal of the NAND gate 002 connected to the input terminal of the inverter 003 and the input terminal A of the NAND gate 003.

[0037] PMOS7 and NMOS7 form an inverter 003, the source of PMOS7 is connected to VDD as the power supply of the inverter 003, the source of NMOS7 is connected to VSS as the ground of the inverter 003, the gate of MOS7 and the gate of NMOS7 are short-circuited as the input of the inverter 003 connected to the output of the NAND gate 002, and the drain of PMOS7 and the drain of NMOS7 are short-circuited as the output of the inverter 003 connected to the gate of NMOS8.

[0038] The source of NMOS8 is connected to the ground VSS, the gate of NMOS8 is connected to the output of the inverter 003, the source of PMOS8 is connected to the power supply VDD, the gate of PMOS8 is connected to the output of the NAND gate 003, and the drains of NMOS8 and PMOS8 are short-circuited as the output terminal Y2 of the clock control circuit connected to the upper plate of the capacitor C2 in the pump circuit.

[0039] PMOS9, PMOS10 and NMOS9, NMOS10 form a NAND gate 003, the sources of PMOS9 and PMOS10 are connected to VDD as the power supply of the NAND gate 003, the source of NMOS10 and the drain of NMOS9, the source of NMOS9 is connected to VSS as the ground of the NAND gate 003, the gates of PMOS9 and NMOS9 are short-circuited as the input terminal A of the NAND gate 003 connected to the output terminal of the NAND gate 002, the gates of PMOS10 and NMOS10 are short-circuited as the input terminal B of the NAND gate 003 connected to the output terminal of the NAND gate 001, and the drains of PMOS9, PMOS10 and NMOS10 are short-circuited as the output terminal of the NAND gate 003 connected to the input of the inverter 004 and the input terminal B of the NAND gate 002.

[0040] PMOS11 and NMOS11 form an inverter 004, the source of PMOS11 is connected to VDD as the power supply of the inverter 004, the source of NMOS11 is connected to VSS as the ground of the inverter 004, the gate of PMOS11 and the gate of NMOS11 are short-circuited as the input of the inverter 004 connected to the output of the NAND gate 003, and the drain of PMOS11 and the drain of NMOS11 are short-circuited as the output of the inverter 004 connected to the gate of NMOS12.

[0041] The source of NMOS12 is connected to the ground VSS, the gate of NMOS12 is connected to the output of inverter 004, the source of PMOS12 is connected to the power supply VDD, the gate of PMOS12 is connected to the output of NAND gate 002, and the drains of NMOS12 and PMOS12 are short-circuited as the output terminal Y1 of the clock control circuit connected to the upper plate of capacitor C1 in the pump circuit.

[0042] The EN input terminal enables the working state of the whole circuit. EN and the square wave signal CLK are applied to the clock control circuit as two inputs of the NAND gate 001. The positive and negative signals are output through the inverter 002 and enter the trigger circuit composed of the NAND gates 002 and 003 in the subsequent stage, generating two non-overlapping clock signals, and outputting their respective inverted signals through the inverters 003 and 004 respectively.

[0043] Specifically, the pump circuit is as follows Figure 5 As shown in the left figure, it includes capacitors C1 and C2, and NPN tubes Q1, Q2, and Q3. The upper plate of C1 is connected to the output terminal Y1 of the clock control circuit, and the lower plate of C1 is connected to the base and collector of Q1 and the emitter of Q2. The emitter of Q1 is connected to the high-side driver floating power supply (HB) pin. The upper plate of C2 is connected to the output terminal Y2 of the clock control circuit, and the lower plate of C2 is connected to the base and collector of Q2 and the emitter of Q3. The emitter of Q3 is connected to the high-side driver floating ground (HS) pin.

[0044] The pump circuit uses C1 and C2 as pump capacitors. The two non-overlapping clock signals output by the clock control circuit control the switching of the switch tubes PMOS12, NMOS12, PMOS8, and NMOS8, so that the pump capacitor plates are alternately connected to VDD or VSS to realize the charge transfer between the capacitors. At the same time, the cascade structure of three diode-connected NPN tubes (bc junction short-circuited) Q1, Q2, and Q3 is used as forward transmission and reverse cutoff to realize the boosting of the floating potential HS to HB, provide a current output capacity of 100uA, and supplement the charge loss of the external capacitor.

[0045] Specifically, the limiting circuit, such as Figure 6As shown, it includes Zener diodes D0 and D1, capacitor C3, and N series-connected forward conducting diodes DN, in this embodiment, N=1. The anode of DN is connected to the HB pin, the cathode of DN is connected to the cathode of D0, the anode of D0 is connected to the cathode of D1, and the anode of D1 is connected to the HS pin. The upper plate of C3 is connected to the HB pin, and the lower plate of C3 is connected to the HS pin.

[0046] The limiting circuit uses voltage regulator tubes D1, D0 and forward diode DN cascaded between HB and HS. The voltage regulator voltage value V m is 4.8V. According to the supply voltage HB-HS value, N forward diodes are required in series. , where VBE is the forward diode voltage drop.

[0047] like Figure 4 As shown, the enable signal EN enables the clock control circuit working state. When EN is at a low level "0", the inverted square wave signal CLK of the NAND gate 001 is used as the clock control signal of the two logic circuits. The latch composed of the NAND gate 002 and the NAND gate 003 generates a non-overlapping clock signal, which is divided into 4 square wave signals through the inverter 003 and the inverter 004, respectively controlling the gates of the 4 switch tubes PMOS12, NMOS12, PMOS8, and NMOS8. As the phases of the 4 square wave signals change periodically, the 4 switch tubes are switched to be connected to VDD or VSS.

[0048] like Figure 5 As shown in the right figure, when the HS pin is switched from the external circuit to the common ground, HB is fed by VDD through the bootstrap diode, and the pump circuit does not work. When the HS pin is switched from the external circuit to the power supply, HB is raised by the external bootstrap capacitor, and the bootstrap diode between VDD is reverse biased. The pump circuit works alternately under the cycle changes of the two phases (phase 1 and phase 2) provided by the clock control circuit. Ignoring the voltage drop caused by the diode connection of the NPN, during the phase 1 cycle, as shown Figure 5 As shown in the upper right figure, when the upper plate of C2 switches to VSS and the upper plate of C1 switches to VDD=12V, HS charges the upper plates of C1 and C2 through Q1 and Q2 respectively. The voltage drop of C2 is approximately HS. After C1 is fully charged, it is reversely cut off for Q2, so it will be output to HB through Q3. In Phase 2 cycle, Figure 5 As shown in the circuit in the lower right figure, the upper plate of C2 switches to VDD, the upper plate of C1 switches to VSS, the potential of the lower plate of C2 suddenly changes to HS+VDD, C2 charges C1, and the potential of the lower plate of C1 is HS+. After several cycles of clock alternation, HB=HS+VDD is output.

[0049] like Figure 6As shown, Zener diodes D0 and D1 are connected in series with the forward conducting diode DN to limit the HB-HS voltage. The output voltage of the charge pump can be adjusted by programming the number of forward conducting diodes DN in series, providing a discharge path for the excess voltage. Capacitor C3 filters the HB-HS output voltage.

Claims

1. A built-in high-side charge pump circuit, characterized in that: It includes a clock control circuit, a pump circuit, and a limiter circuit; the clock control circuit structure is a non-overlapping clock generation circuit, which generates two non-overlapping clock signals from a square wave signal CLK and transmits them to the pump circuit; the pump circuit is a switch tube that switches to alternately charge and discharge the secondary capacitor to achieve HS potential boost and transmit it to the limiter circuit; the limiter circuit is composed of a voltage regulator tube and a diode cascade to achieve HB-HS voltage stable output; HB is a high-side power supply, and HS is a high-side ground; The clock control circuit specifically includes inverter 001, inverter 002, inverter 003, inverter 004, NAND gate 001, NAND gate 002, NAND gate 003, NMOS tubes NMOS8, NMOS12, PMOS tubes PMOS8, PMOS12; the specific connection method is as follows: The power supply of the inverter 001 is connected to VDD, the ground of the inverter 001 is connected to VSS, the input terminal of the inverter 001 is connected to the EN enable signal, and the output terminal of the inverter 001 is connected to the input terminal A of the NAND gate 001; The power supply of the NAND gate 001 is connected to VDD, the ground of the NAND gate 001 is connected to VSS, the input terminal B of the NAND gate 001 is connected to the square wave signal CLK, and the output terminal of the NAND gate 001 is connected to the input terminal of the inverter 002 and the input terminal A of the NAND gate 003; The power supply of the inverter 002 is connected to VDD, the ground of the inverter 002 is connected to VSS, and the output terminal of the inverter 002 is connected to the input terminal A of the NAND gate 002; The power supply of the NAND gate 002 is connected to VDD, the ground of the NAND gate 002 is connected to VSS, the input terminal B of the NAND gate 002 is connected to the output terminal of the NAND gate 003, and the output terminal of the NAND gate 002 is connected to the input terminal of the inverter 003 and the input terminal A of the NAND gate 003; The power supply of the inverter 003 is connected to VDD, the ground of the inverter 003 is connected to VSS, and the output terminal of the inverter 003 is connected to the gate of the NMOS 8; The source of NMOS8 is connected to the ground VSS, the source of PMOS8 is connected to the power supply VDD, the gate of PMOS8 is connected to the output end of the NAND gate 003, and the drains of NMOS8 and PMOS8 are short-circuited as the output end Y2 of the clock control circuit connected to the pump circuit; The power supply of the NAND gate 003 is connected to VDD, the ground of the NAND gate 003 is connected to VSS, and the output terminal of the NAND gate 003 is connected to the input terminal of the inverter 004; The power supply of the inverter 004 is connected to VDD, the ground of the inverter 004 is connected to VSS, and the output terminal of the inverter 004 is connected to the gate of the NMOS 12; The source of NMOS12 is connected to the ground VSS, the source of PMOS12 is connected to the power supply VDD, the gate of PMOS12 is connected to the output end of NAND gate 002, and the drains of NMOS12 and PMOS12 are short-circuited as the output end Y1 of the clock control circuit connected to the pump circuit; The pump circuit includes capacitors C1 and C2, and NPN tubes Q1, Q2, and Q3; the upper plate of C1 is connected to the output terminal Y1 of the clock control circuit, the lower plate of C1 is connected to the base and collector of Q1, and the emitter of Q2, and the emitter of Q1 is connected to the high-side drive floating power supply HB pin; the upper plate of C2 is connected to the output terminal Y2 of the clock control circuit, the lower plate of C2 is connected to the base and collector of Q2, and the emitter of Q3, and the collector of Q3 is connected to the high-side drive floating ground HS pin; The limiting circuit includes Zener diodes D0 and D1, a capacitor C3, and N forward conducting diodes DN connected in series; the anode of DN is connected to the HB pin, the cathode of DN is connected to the cathode of D0, the anode of D0 is connected to the cathode of D1, and the anode of D1 is connected to the HS pin; the upper plate of C3 is connected to the HB pin, and the lower plate of C3 is connected to the HS pin.

2. A built-in high-side charge pump circuit according to claim 1, characterized in that: The clock control circuit comprises PMOS tubes PMOS1, PMOS tube PMOS2, PMOS tube PMOS3, PMOS tube PMOS4, PMOS tube PMOS5, PMOS tube PMOS6, PMOS tube PMOS7, PMOS tube PMOS8, PMOS tube PMOS9, PMOS tube PMOS10, PMOS tube PMOS11, and PMOS tube PMOS12; NMOS tubes NMOS1, NMOS tube NMOS2, NMOS tube NMOS3, NMOS tube NMOS4, NMOS tube NMOS5, NMOS tube NMOS6, and NMOS tube NMOS OS7, NMOS tube NMOS8, NMOS tube NMOS9, NMOS tube NMOS10, NMOS tube NMOS11, NMOS tube NMOS12; the connection method is as follows: PMOS1 and NMOS1 form an inverter 001, the source of PMOS1 is connected to VDD as the power supply of the inverter 001, the source of NMOS1 is connected to VSS as the ground of the inverter 001, the gate of PMOS1 and the gate of NMOS1 are short-circuited as the input terminal of the inverter 001 connected to the EN enable signal, and the drain of PMOS1 and the drain of NMOS1 are short-circuited as the output terminal of the inverter 001 connected to the input terminal A of the NAND gate 001; PMOS2, PMOS3 and NMOS2, NMOS3 form a NAND gate 001, the source of PMOS2 and PMOS3 is connected to VDD as the power supply of the NAND gate 001, the source of NMOS3 is connected to the drain of NMOS2, the source of NMOS2 is connected to VSS as the ground of the NAND gate 001, the gates of PMOS2 and NMOS2 are short-circuited as the input terminal A of the NAND gate 001 connected to the output terminal of the inverter 001, the gates of PMOS3 and NMOS3 are short-circuited as the input terminal B of the NAND gate 001 connected to the square wave signal CLK, the drains of PMOS2, PMOS3 and NMOS3 are short-circuited as the output terminal of the NAND gate 001 connected to the input terminal of the inverter 002 and the input terminal A of the NAND gate 003; PMOS4 and NMOS4 form an inverter 002, the source of PMOS4 is connected to VDD as the power supply of the inverter 002, the source of NMOS4 is connected to VSS as the ground of the inverter 002, the gate of PMOS4 and the gate of NMOS4 are short-circuited as the input end of the inverter 002 connected to the output end of the NAND gate 001, and the drain of PMOS4 and the drain of NMOS4 are short-circuited as the output end of the inverter 002 connected to the input end A of the NAND gate 002; PMOS5, PMOS6 and NMOS5, NMOS6 form a NAND gate 002, the sources of PMOS5 and PMOS6 are connected to VDD as the power supply of the NAND gate 002, the source of NMOS6 and the drain of NMOS5 are connected, the source of NMOS5 is connected to VSS as the ground of the NAND gate 002, the gates of PMOS5 and NMOS5 are short-circuited as the input terminal A of the NAND gate 002 connected to the output terminal of the inverter 002, the gates of PMOS6 and NMOS6 are short-circuited as the input terminal B of the NAND gate 002 connected to the output terminal of the NAND gate 003, and the drains of PMOS5, PMOS6 and NMOS6 are short-circuited as the output terminal of the NAND gate 002 connected to the input terminal of the inverter 003 and the input terminal A of the NAND gate 003; PMOS7 and NMOS7 form an inverter 003, the source of PMOS7 is connected to VDD as the power supply of the inverter 003, the source of NMOS7 is connected to VSS as the ground of the inverter 003, the gate of MOS7 and the gate of NMOS7 are short-circuited as the input terminal of the inverter 003 connected to the output terminal of the NAND gate 002, and the drain of PMOS7 and the drain of NMOS7 are short-circuited as the output terminal of the inverter 003 connected to the gate of NMOS8; The source of NMOS8 is connected to the ground VSS, the gate of NMOS8 is connected to the output of the inverter 003, the source of PMOS8 is connected to the power supply VDD, the gate of PMOS8 is connected to the output of the NAND gate 003, and the drains of NMOS8 and PMOS8 are short-circuited as the output terminal Y2 of the clock control circuit connected to the upper plate of the capacitor C2 in the pump circuit; PMOS9, PMOS10 and NMOS9, NMOS10 form a NAND gate 003, the source of PMOS9 and PMOS10 are connected to VDD as the power supply of the NAND gate 003, the source of NMOS10 and the drain of NMOS9 are connected, the source of NMOS9 is connected to VSS as the ground of the NAND gate 003, the gates of PMOS9 and NMOS9 are short-circuited as the input terminal A of the NAND gate 003 connected to the output terminal of the NAND gate 002, the gates of PMOS10 and NMOS10 are short-circuited as the input terminal B of the NAND gate 003 connected to the output terminal of the NAND gate 001, and the drains of PMOS9, PMOS10 and NMOS10 are short-circuited as the output terminal of the NAND gate 003 connected to the input of the inverter 004 and the input terminal B of the NAND gate 002; PMOS11 and NMOS11 form an inverter 004, the source of PMOS11 is connected to VDD as the power supply of the inverter 004, the source of NMOS11 is connected to VSS as the ground of the inverter 004, the gate of PMOS11 and the gate of NMOS11 are short-circuited as the input end of the inverter 004 and connected to the output end of the NAND gate 003, the drain of PMOS11 and the drain of NMOS11 are short-circuited as the output end of the inverter 004 and connected to the gate of NMOS12; The source of NMOS12 is connected to the ground VSS, the gate of NMOS12 is connected to the output of inverter 004, the source of PMOS12 is connected to the power supply VDD, the gate of PMOS12 is connected to the output of NAND gate 002, and the drains of NMOS12 and PMOS12 are short-circuited as the output terminal Y1 of the clock control circuit connected to the upper plate of capacitor C1 in the pump circuit.

3. A built-in high-side charge pump circuit according to claim 2, characterized in that: When the N series-connected forward-conducting diodes DN are connected in series, N=(HB-HS-V m *2) / VBE, where V m is the voltage value of the Zener diode, and VBE is the forward diode voltage drop.

Images