Bonding structure and method of forming the same, bonding method

Abstract

The present disclosure relates to the field of semiconductor technology, and discloses a bonding structure, a forming method of the bonding structure and a bonding method. The bonding structure comprises a first dielectric layer, a metal interconnection line, a conductive connecting part, a first barrier layer, a second dielectric layer and a bonding part. The metal interconnection line is embedded in the first dielectric layer. The conductive connecting part is disposed in the first dielectric layer, and one end of the conductive connecting part is connected with the metal interconnection line, and the other end of the conductive connecting part is flush with the top surface of the first dielectric layer. The first barrier layer covers the surface of the first dielectric layer and the conductive connecting part. The second dielectric layer covers the surface of the first barrier layer. The bonding part penetrates through the first barrier layer and the second dielectric layer, and is connected with the end of the conductive connecting part away from the metal interconnection line. The bonding part is annular, and the orthographic projection of the bonding part on the conductive connecting part covers the edge region of the conductive connecting part. The bonding structure disclosed by the present disclosure can reduce bonding defects and improve product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a bonding structure and a method for forming and bonding the same. Background Technology

[0002] With the continuous development of semiconductor technology, three-dimensional integrated circuit (3D-IC) technology has been widely used. In the 3D-IC manufacturing process, different wafers are stacked together using bonding technology. Currently, wafer bonding technology usually adopts hybrid bonding, including inter-metal and inter-dielectric bonding. During the bonding process, structural defects are prone to occur, resulting in low product yield.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In view of this, the present disclosure provides a bonding structure and a method for forming the same, as well as a bonding method, which can reduce structural defects and improve product yield.

[0005] According to one aspect of this disclosure, a bonding structure is provided, comprising:

[0006] A first dielectric layer and metal interconnects embedded in the first dielectric layer;

[0007] A conductive connection portion is disposed within the first dielectric layer, with one end connected to the metal interconnect and the other end flush with the top surface of the first dielectric layer.

[0008] A first barrier layer covers the surfaces of the first dielectric layer and the conductive connection portion;

[0009] A second dielectric layer covers the surface of the first barrier layer;

[0010] The bonding portion extends through the first barrier layer and the second dielectric layer, and is connected to the end of the conductive connection portion away from the metal interconnect. The bonding portion is annular, and the orthographic projection of the bonding portion onto the conductive connection portion covers the edge region of the conductive connection portion.

[0011] In one exemplary embodiment of this disclosure, the bonding structure further includes:

[0012] A second barrier layer covers the surface of the second dielectric layer; the bonding portion also penetrates the second barrier layer.

[0013] In one exemplary embodiment of this disclosure, the conductive connection portion includes:

[0014] A conductive layer is disposed within the first dielectric layer, with one end connected to the metal interconnect and the other end flush with the top surface of the first dielectric layer.

[0015] A first barrier layer conformally covers the sidewalls of the conductive layer.

[0016] In one exemplary embodiment of this disclosure, the bonding portion includes:

[0017] A bonding layer, wherein the orthographic projection of the bonding layer onto the conductive connection portion at least partially coincides with the edge region of the conductive connection portion;

[0018] The second barrier layer conformally covers the sidewalls of the bonding layer and the space between the bonding layer and the first dielectric layer.

[0019] In one exemplary embodiment of this disclosure, the materials of the first barrier layer and the second barrier layer are at least one of tantalum, tantalum nitride, or titanium nitride; the materials of the conductive layer and the bonding layer are both copper; when the bonding structure includes the second barrier layer, the materials of the first barrier layer and the second barrier layer are silicon nitride.

[0020] In one exemplary embodiment of this disclosure, the thickness of both the first barrier layer and the second barrier layer is 20 nm to 40 nm.

[0021] In one exemplary embodiment of this disclosure, the top end of the bonding portion is lower than the top surface of the second dielectric layer, and the height difference between the top end of the bonding portion and the top surface of the second dielectric layer is less than or equal to 10 nm.

[0022] In one exemplary embodiment of this disclosure, there are multiple conductive connection portions, each of which is electrically connected to the metal interconnect; there are multiple bonding portions, each of which is connected to each conductive connection portion in a one-to-one correspondence.

[0023] In one exemplary embodiment of this disclosure, the bonding structure further includes:

[0024] A pseudo-bonding portion is located in the peripheral region of the distribution area of ​​each of the bonding portions, and the pseudo-bonding portion passes through the first barrier layer and the second dielectric layer;

[0025] When the bonding structure further includes a second barrier layer, the pseudo-bonded portion also passes through the second barrier layer.

[0026] According to one aspect of this disclosure, a method for forming a bonding structure is provided, comprising:

[0027] Provide substrate;

[0028] A first dielectric layer and metal interconnects embedded within the first dielectric layer are formed on the substrate;

[0029] A conductive connection portion is formed in the first dielectric layer, one end of which is connected to the metal interconnect line, and the other end is flush with the top surface of the first dielectric layer.

[0030] A first barrier layer is formed covering the surfaces of the first dielectric layer and the conductive connection portion;

[0031] A second dielectric layer is formed on the surface of the first barrier layer;

[0032] A bonding portion is formed that penetrates the first barrier layer and the second dielectric layer. The bonding portion is connected to the end of the conductive connection portion away from the metal interconnect. The bonding portion is annular, and the orthographic projection of the bonding portion on the conductive connection portion covers the edge region of the conductive connection portion.

[0033] In one exemplary embodiment of this disclosure, forming the conductive connection portion includes:

[0034] The first dielectric layer is etched to form a conductive contact hole within the first dielectric layer, the conductive contact hole exposing the metal interconnect;

[0035] A first barrier layer is formed on the sidewall of the conductive contact hole;

[0036] A conductive layer is formed within the conductive contact hole having the first barrier layer, the conductive layer filling the conductive contact hole, and the surface of the conductive layer away from the substrate is flush with the top surface of the first dielectric layer.

[0037] In one exemplary embodiment of this disclosure, before forming the bonding portion, the forming method further includes:

[0038] A second barrier layer is formed on the surface of the second dielectric layer;

[0039] Forming the bonding portion includes:

[0040] The first barrier layer, the second dielectric layer, and the second barrier layer are etched to form a bonding hole; the bonding hole is annular and exposes at least a portion of the edge region of the conductive connection.

[0041] A second barrier layer is formed on the sidewall and bottom of the bonding hole;

[0042] A bonding layer is formed within the bonding hole having the second barrier layer, the top of the bonding layer being lower than the top surface of the second barrier layer, and the height difference between the top of the bonding layer and the top surface of the second barrier layer being less than or equal to 10 nm.

[0043] In an exemplary embodiment of this disclosure, the number of conductive connections is plurality of, and each conductive connection is electrically connected to the metal interconnect; the number of bonding portions is plurality of, and each bonding portion is connected to each conductive connection in a one-to-one correspondence; the forming method further includes:

[0044] A pseudo-bonded portion is formed in the peripheral region of the distribution area of ​​each of the bonding portions, and the pseudo-bonded portion passes through the first barrier layer and the second dielectric layer;

[0045] When a second barrier layer is formed on the surface of the second dielectric layer, the pseudo-bonding portion also penetrates the second barrier layer.

[0046] According to one aspect of this disclosure, a bonding method is provided, the bonding method being used to bond the bonding structure described in any one of the above claims to another bonding structure described in any one of the above claims, wherein the bonding structure described in any one of the above claims is a first bonding structure, and the bonding structure described in any one of the above claims is a second bonding structure, wherein the bonding portion of the first bonding structure and the bonding portion of the second bonding structure have different dimensions, and the first bonding structure and the second bonding structure are bonded together through the bonding portion of the first bonding structure and the bonding portion of the second bonding structure.

[0047] According to one aspect of this disclosure, a bonding method is provided for bonding two bonding structures as described in any one of the above claims, wherein the bonding portions of the two bonding structures are of different sizes, and the two bonding structures are bonded together through the bonding portions of the two bonding structures.

[0048] The bonding structure and its formation method disclosed herein, since the first barrier layer covers the surfaces of the first dielectric layer and the conductive connection, and the second dielectric layer covers the surface of the first barrier layer, can prevent ions in the conductive connection from diffusing into the second dielectric layer, thus helping to reduce structural defects, improve device stability, and consequently improve product yield. Simultaneously, since the top of the conductive connection is covered by the first barrier layer, the probability of oxidation of the top of the conductive connection is reduced, further reducing structural defects and improving product yield. Furthermore, because the bonding portion is annular, the amount of material within the bonding portion is reduced, and the expansion of the material within the bonding portion during subsequent bonding processes is also reduced. Therefore, the problem of voids or material extrusion is less likely to occur, further helping to reduce structural defects and improve product yield.

[0049] The bonding method disclosed herein, due to the different sizes of the bonding portions of the two bonding structures, can help increase the process window during bonding and reduce the process difficulty. At the same time, since the second barrier layer of the second bonding structure covers the surface of the second dielectric layer of the second bonding structure, even if misalignment occurs during bonding, the second barrier layer can prevent ions in the conductive connection portion of the first bonding structure bonded to the second bonding structure from diffusing into the second dielectric layer of the second bonding structure, which helps to improve device stability.

[0050] The bonding method disclosed herein, due to the different sizes of the bonding portions of the two bonding structures, can help increase the process window during bonding and reduce the process difficulty. At the same time, since both bonding structures include a second barrier layer, and the two second barrier layers respectively cover the surface of the second dielectric layer of the two different bonding structures, even if misalignment occurs during bonding, the second barrier layer can prevent ions in the conductive connection portion of the other bonding structure bonded to it from diffusing into the second dielectric layer of that bonding structure, which helps to improve device stability.

[0051] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0052] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0053] Figure 1 This is a schematic diagram of a bonding structure in a related technology.

[0054] Figure 2 This is a schematic diagram of a bonding structure in another related technology.

[0055] Figure 3 This is a schematic diagram of the bonding structure in one embodiment of the present disclosure.

[0056] Figure 4 This is a schematic diagram of the substrate, metal interconnects, conductive connections, and first barrier layer in an embodiment of this disclosure.

[0057] Figure 5 This is a schematic diagram of the second dielectric layer in an embodiment of this disclosure.

[0058] Figure 6 This is a top view of the bonding portion in one embodiment of the present disclosure.

[0059] Figure 7This is a top view of the bonding portion in one embodiment of the present disclosure.

[0060] Figure 8 This is a top view of the bonding portion in one embodiment of the present disclosure.

[0061] Figure 9 This is a top view of the bonding portion in one embodiment of the present disclosure.

[0062] Figure 10 This is a schematic diagram of the bonding structure in another embodiment of the present disclosure.

[0063] Figure 11 This is a flowchart of a method for forming a bonding structure in an embodiment of this disclosure.

[0064] Figure 12 This is a schematic diagram of the first photoresist layer and the first developing area in an embodiment of this disclosure.

[0065] Figure 13 This is a schematic diagram after step S210 is completed in an embodiment of this disclosure.

[0066] Figure 14 This is a schematic diagram after step S220 is completed in an embodiment of this disclosure.

[0067] Figure 15 This is a schematic diagram after step S230 is completed in an embodiment of this disclosure.

[0068] Figure 16 This is a schematic diagram of the second photoresist layer and the second developing area in an embodiment of this disclosure.

[0069] Figure 17 This is a schematic diagram after step S310 is completed in an embodiment of this disclosure.

[0070] Figure 18 This is a schematic diagram of the third photoresist layer and the third developing area in an embodiment of this disclosure.

[0071] Figure 19 This is a schematic diagram after step S410 is completed in an embodiment of this disclosure.

[0072] Figure 20 This is a schematic diagram after step S420 is completed in an embodiment of this disclosure.

[0073] Figure 21 This is a schematic diagram of the copper plating process in an embodiment of this disclosure.

[0074] Figure 22 This is a schematic diagram of the first bonding structure and the second bonding structure after bonding in an embodiment of this disclosure.

[0075] Figure 23 This is a schematic diagram of the two second bonding structures after bonding in an embodiment of this disclosure.

[0076] Explanation of reference numerals in the attached figures:

[0077] 100. Substrate; 1. First dielectric layer; 2. Metal interconnect; 3. Conductive connection; 31. Conductive layer; 32. First barrier layer; 301. Conductive contact hole; 4. First barrier layer; 5. Second dielectric layer; 6. Bonding portion; 61. Second barrier layer; 62. Bonding layer; 601. Bonding hole; 602. Copper; 7. Second barrier layer; 8. Pseudo-bonding portion; 801. Pseudo-bonding hole; 9. Sacrificial layer; 200. First photoresist layer; 201. First developing area; 300. Second photoresist layer; 310. Second developing area; 400. Third photoresist layer; 410. Third developing area; A. First bonding structure; B. Second bonding structure. Detailed Implementation

[0078] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0079] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0080] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first” and “second” are used only as markers and are not a limitation on the number of objects.

[0081] In semiconductor manufacturing processes, 3D integrated circuit (3D-IC) technology transforms integrated circuit design from two-dimensional planar design to three-dimensional design. By stacking different wafers, devices and circuits with different functions are integrated to produce semiconductor devices with high capacity and high processing speed, further improving the performance of semiconductor devices.

[0082] In 3D integrated circuits, wafer bonding is primarily used to stack and bond different wafers. Wafer bonding methods include adhesive and wafer bonding, direct wafer bonding, metal bonding, and hybrid metal / polymer wafer bonding. However, for miniaturized semiconductor devices, hybrid bonding methods are typically used, where metal layers on different wafers are electrically connected, and dielectric layers are bonded intermolecularly.

[0083] Currently, dielectric layers can be formed on the bonding surfaces of different wafers to serve as electrical isolation and adjust the bonding morphology, and chemical mechanical polishing (CMP) can be used to integrate the wafer bonding morphology. However, during CMP, due to the different materials of the dielectric layer and the metal layer, the polishing rate varies, which can lead to pits in the area where the metal layer is located. If the pits are too large, gaps are likely to appear between the two bonded structures after bonding (e.g., ...). Figure 1 (As shown); if the pit is too small, the metal material between the two bonded structures is easily squeezed out, forming a protrusion 20 (as shown). Figure 2 As shown in the figure, this causes structural defects. Therefore, it is necessary to design a new bonding structure or seek a new bonding process to solve the above problems.

[0084] Based on this, embodiments of the present disclosure provide a bonding structure. Figure 3 A schematic diagram of a bonding structure according to an embodiment of the present disclosure is shown, such as... Figure 3 As shown, the bonding structure includes a first dielectric layer 1, a metal interconnect 2, a conductive connection portion 3, a first barrier layer 4, a second dielectric layer 5, and a bonding portion 6, wherein:

[0085] Metal interconnect 2 is embedded in the first dielectric layer 1;

[0086] The conductive connection portion 3 is disposed within the first dielectric layer 1, with one end connected to the metal interconnect 2 and the other end flush with the top surface of the first dielectric layer 1.

[0087] The first barrier layer 4 covers the surfaces of the first dielectric layer 1 and the conductive connection portion 3;

[0088] The second dielectric layer 5 covers the surface of the first barrier layer 4;

[0089] The bonding portion 6 penetrates the first barrier layer 4 and the second dielectric layer 5, and is connected to the end of the conductive connection portion 3 away from the metal interconnect 2. The bonding portion 6 is annular, and the orthographic projection of the bonding portion 6 on the conductive connection portion 3 covers the edge region of the conductive connection portion 3.

[0090] The bonding structure disclosed herein, since the first barrier layer 4 covers the surfaces of the first dielectric layer 1 and the conductive connection portion 3, and the second dielectric layer 5 covers the surface of the first barrier layer 4, can prevent ions in the conductive connection portion 3 from diffusing into the second dielectric layer 5, thus helping to reduce structural defects, improve device stability, and consequently improve product yield. Simultaneously, since the top of the conductive connection portion 3 is covered by the first barrier layer 4, the probability of oxidation of the top of the conductive connection portion 3 is reduced, further reducing structural defects and improving product yield. Furthermore, since the bonding portion 6 is annular, the amount of material within the bonding portion 6 is reduced, and the expansion of the material within the bonding portion 6 during subsequent bonding processes is also reduced. Therefore, the problem of voids or material extrusion is less likely to occur, further helping to reduce structural defects and improve product yield.

[0091] The following provides a detailed description of each part of the bonding structure disclosed herein and its specific details:

[0092] like Figure 4 As shown, a substrate 100 can be provided, which can be any semiconductor structure in wafer or semiconductor manufacturing process, without special limitation. For example, it can be a semiconductor structure after the completion of word lines, bit lines, capacitors, peripheral contact plugs, and other process technologies.

[0093] A first dielectric layer 1 can be formed on the substrate 100. The material of the first dielectric layer 1 can be an insulating material, such as silicon oxide. The first dielectric layer 1 can be formed on the substrate 100 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the first dielectric layer 1 can also be formed by other methods. No special limitation is made here on the formation method of the first dielectric layer 1.

[0094] The metal interconnect 2 may be made of a conductive material, such as copper and / or titanium nitride. The metal interconnect 2 may be embedded within the first dielectric layer 1 and may be electrically connected to conductive structures (e.g., capacitors or peripheral contact plugs) in the substrate 100. The metal interconnect 2 can electrically lead out the conductive structures within the substrate 100. The first dielectric layer 1 may cover the surface of the metal interconnect 2 to insulate it from other structures, thereby reducing the risk of short circuits.

[0095] The conductive connection portion 3 may be columnar and may be disposed within the first dielectric layer 1. The conductive connection portion 3 may extend in a direction perpendicular to the substrate 100. In the extension direction of the conductive connection portion 3, it may be a columnar structure with equal dimensions everywhere, or it may be a columnar structure with gradually increasing dimensions from bottom to top (for example, in the direction perpendicular to the substrate 100, the dimensions of the conductive connection portion 3 gradually increase from bottom to top), without any particular limitation. In the direction parallel to the substrate 100, the cross-section of the conductive connection portion 3 may be circular, elliptical, rectangular, polygonal, or irregular in shape, without any particular limitation on the shape of the conductive connection portion 3.

[0096] In the direction parallel to the substrate 100, the size (diameter, length or width) of the conductive connection portion 3 can be 0.3um to 0.8um, for example, it can be 0.3um, 0.4um, 0.5um, 0.6um, 0.7um or 0.8um, of course, it can also be other sizes, which will not be listed here.

[0097] In an exemplary embodiment of this disclosure, one end of the conductive connection portion 3 may be connected to the metal interconnect 2, and the other end may extend away from the metal interconnect 2 in a direction perpendicular to the substrate 100, and the end away from the metal interconnect 2 is flush with the top surface of the first dielectric layer 1 (i.e., the surface away from the substrate 100).

[0098] The conductive connection portion 3 can be made of a conductive material, through which the metal interconnect 2 can be electrically led out. For example, the conductive connection portion 3 may include a metallic material, such as tungsten or copper. The conductive connection portion 3 may also include a blocking material, such as titanium nitride, tantalum, or tantalum nitride.

[0099] The number of conductive connection portions 3 can be one or more. For example, multiple conductive connection portions 3 can be formed in the first dielectric layer 1. The multiple conductive connection portions 3 can be spaced apart, and each of the multiple conductive connection portions 3 can be electrically connected to the metal interconnect 2. Different conductive connection portions 3 can be connected to different areas of the metal interconnect 2.

[0100] In some embodiments of this disclosure, the conductive connection portion 3 may include a conductive layer 31 and a first barrier layer 32, wherein:

[0101] A conductive layer 31 is disposed within the first dielectric layer 1. The conductive layer 31 may be columnar and extend in a direction perpendicular to the substrate 100, with one end contacting the metal interconnect 2 and the other end flush with the top surface of the first dielectric layer 1. The material of the conductive layer 31 may be tungsten or copper. The first barrier layer 32 may conformally cover the sidewalls of the conductive layer 31, and its thickness may be 20 nm to 40 nm. For example, its thickness may be 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm. Of course, other thicknesses are also possible, which will not be listed here. In some embodiments of this disclosure, the material of the first barrier layer 32 may be at least one of tantalum, tantalum nitride, or titanium nitride. In the conductive connection portion 3, since the material of the first barrier layer 32 has ion-blocking function, metal ions in the conductive layer 31 can be prevented from diffusing into other surrounding structures (e.g., the first dielectric layer 1) through the first barrier layer 32, which helps to improve device stability.

[0102] Please continue reading Figure 4 As shown, the first barrier layer 4 can cover the surfaces of the first dielectric layer 1 and the conductive connection portion 3. Since the top of the conductive connection portion 3 is covered by the first barrier layer 4, it helps to reduce the probability of oxidation of the top of the conductive connection portion 3, which can further reduce structural defects and improve product yield. The material of the first barrier layer 4 can be an insulating material, for example, silicon nitride. The first barrier layer 4 can be formed on the surface of the structure jointly formed by the first dielectric layer 1 and the conductive connection portion 3 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the first barrier layer 4 can also be formed by other methods, and the formation method of the first barrier layer 4 is not specifically limited here. In some embodiments of this disclosure, the thickness of the first barrier layer 4 can be 60nm to 100nm, for example, it can be 60nm, 70nm, 80nm, 90nm or 100nm. Of course, it can also be other thicknesses, which will not be listed here.

[0103] like Figure 5 As shown, the second dielectric layer 5 can cover the surface of the first barrier layer 4. The second dielectric layer 5 can be a thin film or a coating formed on the surface of the first barrier layer 4. No specific limitation is made on the specific form of the second dielectric layer 5. The first barrier layer 4 can prevent ions in the conductive connection portion 3 from diffusing into the second dielectric layer 5, which helps reduce structural defects, improve device stability, and thus improve product yield. The material of the second dielectric layer 5 can be the same as the material of the first dielectric layer 1. For example, both the first dielectric layer 1 and the second dielectric layer 5 can be made of silicon oxide.

[0104] Please refer to some embodiments of this disclosure. Figure 3As shown, the bonding portion 6 may be columnar and may extend in a direction perpendicular to the substrate 100. For example, the bonding portion 6 may penetrate the first barrier layer 4 and the second dielectric layer 5, and one end of it may be connected to the end of the conductive connection portion 3 away from the metal interconnect 2, while the other end extends in a direction perpendicular to the substrate 100 toward the side away from the conductive connection portion 3.

[0105] In some embodiments of this disclosure, the top of the bonding portion 6 may be lower than the top surface of the second dielectric layer 5, and the height difference between the top of the bonding portion 6 and the top surface of the second dielectric layer 5 may be less than or equal to 10 nm. This design ensures that during subsequent bonding processes, the expanded metal in the bonding portion 6 fills the height difference between the top of the bonding portion 6 and the top surface of the second dielectric layer 5, and does not overflow outwards.

[0106] The bonding portion 6 may be made of a conductive material, through which the conductive connection portion 3 can be electrically led out. For example, the bonding portion 6 may include a metallic material, such as tungsten or copper. The bonding portion 6 may also include a barrier material, such as titanium nitride, tantalum, or tantalum nitride.

[0107] In some embodiments of this disclosure, such as Figures 6-9 As shown, in a direction parallel to the substrate 100, the cross-section of the bonding portion 6 can be annular, which helps to increase the process window during the bonding process. The bonding portion 6 may include an inner ring and an outer ring, with the material constituting the bonding portion 6 located between the inner ring and the outer ring. The interior of the inner ring is filled with the second dielectric layer 5, and the area outside the outer ring is also filled with the second dielectric layer 5. It should be noted that the shape of the inner ring may be the same as or different from the shape of the outer ring, and no special limitation is made here.

[0108] For example, such as Figure 6 As shown, both the inner and outer rings of the annular bonding portion 6 can be circular; or, as... Figure 7 As shown, both the inner and outer rings of the annular bonding portion 6 can be rectangular; or, as shown... Figure 8 As shown, the inner ring of the annular bonding portion 6 is circular, and the outer ring is rectangular; or, as... Figure 9 As shown, the inner ring of the annular bonding part 6 is rectangular and the outer ring is circular; of course, the inner and outer rings can also be other shapes, which will not be listed here.

[0109] In some embodiments of this disclosure, the outer ring size of the annular bonding portion 6 can be 0.5um to 1.5um. For example, its outer ring size can be 0.5um, 1.0um, or 1.5um. Of course, it can also be other sizes, which will not be listed here. The inner ring size of the annular bonding portion 6 can be 0.15um to 0.4um. For example, its inner ring size can be 0.15um, 0.2um, 0.25um, 0.3um, 0.35um, or 0.4um. Of course, it can also be other sizes, which will not be listed here.

[0110] In one embodiment, the orthographic projection of the bonding portion 6 onto the conductive connection portion 3 can cover the edge region of the conductive connection portion 3. For example, its orthographic projection can cover a portion of the edge region of the conductive connection portion 3; or, its orthographic projection can cover the entire perimeter of the edge of the conductive connection portion 3. For instance, the bonding portion 6 can be electrically connected to a portion of the edge region of the conductive connection portion 3, or it can be in contact with the entire perimeter of the edge of the conductive connection portion 3, which helps to increase the contact area between the bonding portion 6 and the conductive connection portion 3, thereby reducing the contact resistance. At the same time, since the bonding portion 6 is annular, the amount of material within the bonding portion 6 is reduced, and the expansion of the material within the bonding portion 6 during subsequent bonding processes will also be reduced. Therefore, it is less likely to have voids or material extrusion problems, which helps to further reduce structural defects and improve product yield.

[0111] In some embodiments of this disclosure, the number of bonding portions 6 may be one or more. For example, the number of bonding portions 6 may match the number of conductive connection portions 3. For instance, when the number of conductive connection portions 3 is one, the number of bonding portions 6 may also be one; when the number of conductive connection portions 3 is multiple, the number of bonding portions 6 may also be multiple, and each bonding portion 6 may be connected to each conductive connection portion 3 in a one-to-one correspondence.

[0112] In one exemplary embodiment of this disclosure, the bonding portion 6 may include a bonding layer 62 and a second barrier layer 61, wherein:

[0113] The bonding layer 62 can penetrate the second dielectric layer 5 and the first barrier layer 4. The bonding layer 62 can be columnar and can extend in a direction perpendicular to the substrate 100. One end of the bonding layer 62 is connected to the conductive connection portion 3, and the other end extends away from the conductive connection portion 3 in a direction perpendicular to the substrate 100. The end of the bonding layer 62 away from the conductive connection portion 3 has a height difference with the surface of the second dielectric layer 5, which can be less than or equal to 10 nm. In a direction parallel to the substrate 100, the cross-section of the bonding layer 62 can be annular, and the orthographic projection of the bonding layer 62 on the conductive connection portion 3 at least partially coincides with the edge region of the conductive connection portion 3. In some embodiments, the material of the bonding layer 62 can be a metallic material, for example, tungsten or copper.

[0114] The second barrier layer 61 conformally covers the sidewalls of the bonding layer 62 and the space between the bonding layer 62 and the first dielectric layer 1. The thickness of the second barrier layer 61 can be 20 nm to 40 nm, for example, it can be 20 nm, 25 nm, 30 nm, 35 nm or 40 nm, and of course, other thicknesses are also possible, which will not be listed here. In some embodiments of this disclosure, the material of the second barrier layer 61 can be at least one of tantalum, tantalum nitride or titanium nitride. In the bonding portion 6, since the material of the second barrier layer 61 has ion-blocking function, it can prevent metal ions in the bonding layer 62 from diffusing into other surrounding structures (e.g., the first dielectric layer 1 and the second dielectric layer 5), which helps to improve device stability.

[0115] In other embodiments of this disclosure, such as Figure 10 As shown, the bonding structure disclosed herein may further include a second barrier layer 7, which may cover the surface of the second dielectric layer 5. During the bonding process, even if misalignment occurs, the second barrier layer 7 can prevent ions in other bonding structures bonded to the bonding structure from diffusing into the second dielectric layer 5 of the bonding structure, thereby helping to improve device stability.

[0116] The second barrier layer 7 can be a thin film or a coating covering the surface of the second dielectric layer 5. No specific limitation is made to the specific form of the second barrier layer 7. The material of the second barrier layer 7 can be an insulating material, such as silicon nitride. The second barrier layer 7 can be formed on the surface of the second dielectric layer 5 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the second barrier layer 7. No specific limitation is made to the formation method of the second barrier layer 7. In some embodiments of this disclosure, the thickness of the second barrier layer 7 can be 60 nm to 100 nm, for example, it can be 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm. Of course, other thicknesses are also possible, which will not be listed here.

[0117] It should be noted that when the bonding structure also includes a second barrier layer 7, the bonding portion 6 can also penetrate the second barrier layer 7. For example, the bonding portion 6 can penetrate the second dielectric layer 5, the first barrier layer 4, and the second barrier layer 7 in a direction perpendicular to the substrate 100. In this case, there is a height difference between the bonding portion 6 and the top surface of the second barrier layer 7, which can be less than or equal to 10 nm.

[0118] In some embodiments of this disclosure, such as Figure 3 and Figure 10As shown, the bonding structure may also include a pseudo-bonding portion 8, which may be located in the peripheral region of the distribution area of ​​each bonding portion 6. For example, the substrate 100 may be divided into a central region and a peripheral region. The central region may be adjacent to the peripheral region, and the peripheral region may surround the central region. Each bonding portion 6 may be located in the central region, and the pseudo-bonding portion 8 may be located in the peripheral region.

[0119] like Figure 3 As shown, the dummy bonding portion 8 can pass through the first barrier layer 4 and the second dielectric layer 5. The structure and material of the dummy bonding portion 8 are the same as those of the bonding portion 6. The difference between the dummy bonding portion 8 and the bonding portion 6 is that the bottom of the bonding portion 6 is connected to the conductive connection portion 3, while the dummy bonding portion 8 is not connected to the conductive connection portion 3. The design of the dummy bonding portion 8 can help dissipate heat and, at the same time, balance the uniformity of material distribution within the bonding structure, reduce warpage, and thus reduce the difficulty of subsequent processes. Figure 10 As shown, when the bonding structure also includes a second barrier layer 7, the pseudo-bonding part 8 can also pass through the second barrier layer 7, thereby ensuring that the structure of the pseudo-bonding part 8 is consistent with the structure of the bonding part 6.

[0120] This disclosure also provides a method for forming a bonding structure, which is used to form the bonding structure in any of the above embodiments. Figure 11 A flowchart illustrating the method for forming the bonding structure of this disclosure is shown; please refer to [link / reference]. Figure 11 As shown, the forming method includes steps S110-S160, wherein:

[0121] Step S110: Provide a substrate;

[0122] Step S120: A first dielectric layer and metal interconnects embedded in the first dielectric layer are formed on the substrate;

[0123] Step S130: A conductive connection portion is formed in the first dielectric layer, one end of the conductive connection portion is connected to the metal interconnect line, and the other end is flush with the top surface of the first dielectric layer.

[0124] Step S140: Form a first barrier layer covering the surface of the first dielectric layer and the conductive connection portion;

[0125] Step S150: A second dielectric layer is formed on the surface of the first barrier layer;

[0126] Step S160: A bonding portion is formed that penetrates the first barrier layer and the second dielectric layer. The bonding portion is connected to the end of the conductive connection portion away from the metal interconnect. The bonding portion is annular, and the orthographic projection of the bonding portion on the conductive connection portion covers the edge region of the conductive connection portion.

[0127] The steps and specific details of the bonding structure formation method disclosed herein are described in detail below:

[0128] like Figure 11 As shown, in step S110, a substrate 100 is provided.

[0129] like Figure 4 As shown, the substrate 100 can be any semiconductor structure in wafer or semiconductor manufacturing process, without any special limitation. For example, it can be a semiconductor structure after the completion of word lines, bit lines, capacitors, peripheral contact plugs, and other process technologies.

[0130] like Figure 11 As shown, in step S120, a first dielectric layer 1 and a metal interconnect 2 embedded in the first dielectric layer 1 are formed on the substrate 100.

[0131] The material of the first dielectric layer 1 can be an insulating material, for example, silicon oxide. The first dielectric layer 1 can be formed on the substrate 100 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, etc. Of course, the first dielectric layer 1 can also be formed by other methods. No special limitation is made here on the formation method of the first dielectric layer 1.

[0132] The metal interconnect 2 may be made of a conductive material, such as copper and / or titanium nitride. The metal interconnect 2 may be embedded within the first dielectric layer 1 and may be electrically connected to conductive structures (e.g., capacitors or peripheral contact plugs) in the substrate 100. The metal interconnect 2 can electrically lead out the conductive structures within the substrate 100. The first dielectric layer 1 may cover the surface of the metal interconnect 2 to insulate it from other structures, thereby reducing the risk of short circuits.

[0133] In some embodiments of this disclosure, a dielectric material can be deposited on a substrate 100 first, and then a dielectric material layer can be formed on the substrate 100. Metal interconnects 2 can be formed on the surface of the dielectric material layer. After the metal interconnects 2 are formed, dielectric material can be deposited on the surface of the structure jointly formed by the dielectric material layer and the metal interconnects 2, and then the metal interconnects 2 can be embedded in the dielectric material. The dielectric material layer and the dielectric material deposited after the formation of the metal interconnects 2 can be used together as the first dielectric layer 1.

[0134] like Figure 11 As shown, in step S130, a conductive connection portion 3 is formed in the first dielectric layer 1. One end of the conductive connection portion 3 is connected to the metal interconnect 2, and the other end is flush with the top surface of the first dielectric layer 1.

[0135] The conductive connection portion 3 may be columnar and may be disposed within the first dielectric layer 1. The conductive connection portion 3 may extend in a direction perpendicular to the substrate 100. In the extension direction of the conductive connection portion 3, it may be a columnar structure with equal dimensions everywhere, or it may be a columnar structure with gradually increasing dimensions from bottom to top (for example, in the direction perpendicular to the substrate 100, the dimensions of the conductive connection portion 3 gradually increase from bottom to top), without any particular limitation. In the direction parallel to the substrate 100, the cross-section of the conductive connection portion 3 may be circular, elliptical, rectangular, polygonal, or irregular in shape, without any particular limitation on the shape of the conductive connection portion 3.

[0136] In the direction parallel to the substrate 100, the size (diameter, length or width) of the conductive connection portion 3 can be 0.3um to 0.8um, for example, it can be 0.3um, 0.4um, 0.5um, 0.6um, 0.7um or 0.8um, of course, it can also be other sizes, which will not be listed here.

[0137] In an exemplary embodiment of this disclosure, one end of the conductive connection portion 3 may be connected to the metal interconnect 2, and the other end may extend away from the metal interconnect 2 in a direction perpendicular to the substrate 100, and the end away from the metal interconnect 2 is flush with the top surface of the first dielectric layer 1 (i.e., the surface away from the substrate 100).

[0138] The conductive connection portion 3 can be made of a conductive material, through which the metal interconnect 2 can be electrically led out. For example, the conductive connection portion 3 may include a metallic material, such as tungsten or copper. The conductive connection portion 3 may also include a blocking material, such as titanium nitride, tantalum, or tantalum nitride.

[0139] The number of conductive connection portions 3 can be one or more. For example, multiple conductive connection portions 3 can be formed in the first dielectric layer 1. The multiple conductive connection portions 3 can be spaced apart, and each of the multiple conductive connection portions 3 can be electrically connected to the metal interconnect 2. Different conductive connection portions 3 can be connected to different areas of the metal interconnect 2.

[0140] In an exemplary embodiment of this disclosure, forming the conductive connection portion 3 may include steps S210-S230, wherein:

[0141] Step S210: Etch the first dielectric layer 1 to form a conductive contact hole 301 in the first dielectric layer 1, the conductive contact hole 301 exposing the metal interconnect 2.

[0142] like Figure 12As shown, a first photoresist layer 200 can be formed on the surface of the first dielectric layer 1 by spin coating or other methods. The material of the first photoresist layer 200 can be positive or negative photoresist, without special limitation. A mask can be used to expose and develop the first photoresist layer 200 to form a first developing region 201. The orthogonal projection of the first developing region 201 on the substrate 100 at least partially overlaps with the metal interconnect 2. The number of first developing regions 201 can be one or more, without special limitation. The metal interconnect 2 can be used as an etch stop layer, and the first dielectric layer 1 can be etched in the first developing region 201 to form a conductive contact hole 301 exposing the metal interconnect 2. In this embodiment, the structure after step S210 is as follows: Figure 13 As shown.

[0143] In the direction parallel to the substrate 100, the shape of the conductive contact hole 301 can be circular, elliptical, rectangular, polygonal, or irregular. No specific limitation is made to the shape of the conductive contact hole 301. In the direction parallel to the substrate 100, the size of the conductive contact hole 301 can be 0.3µm to 0.8µm, for example, it can be 0.3µm, 0.4µm, 0.5µm, 0.6µm, 0.7µm, or 0.8µm. Of course, other sizes are also possible, which will not be listed here.

[0144] In step S220, a first barrier layer 32 is formed on the sidewall of the conductive contact hole 301.

[0145] After forming the conductive contact hole 301, the first photoresist layer 200 can be removed, thereby exposing the surface of the first dielectric layer 1 having the conductive contact hole 301. Subsequently, a first barrier layer 32 can be formed on the sidewall of the conductive contact hole 301 by means of chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the first barrier layer 32 can also be formed by other means, and the formation method of the first barrier layer 32 is not specifically limited here. In the embodiment of this disclosure, the structure after completing step S220 is as follows: Figure 14 As shown.

[0146] In step S230, a conductive layer 31 is formed in the conductive contact hole 301 having the first barrier layer 32. The conductive layer 31 fills the conductive contact hole 301, and the surface of the conductive layer 31 away from the substrate 100 is flush with the top surface of the first dielectric layer 1.

[0147] The conductive layer 31 can be formed within the conductive contact hole 301 having the first barrier layer 32 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or electroplating. Of course, other methods can also be used to form the conductive layer 31, and no specific limitation is made here. For example, when the material of the conductive layer 31 is copper, a thin layer of copper can first be deposited within the conductive contact hole 301 having the first barrier layer 32 by atomic layer deposition. Then, copper can be electroplated within the conductive contact hole 301 using the thin copper as the cathode until the copper fills the conductive contact hole 301. In some embodiments of this disclosure, the surface of the conductive layer 31 can also be planarized. For example, after electroplating copper within the conductive contact hole 301, the surface of the structure jointly formed by the first dielectric layer 1, the first barrier layer 32, and the copper can be chemically mechanically polished to eliminate surface height differences and provide a flat process reference for subsequent processes. The remaining copper within the conductive contact hole 301 after polishing can be used as the conductive layer 31. In this embodiment of the disclosure, the structure after completing step S230 is as follows: Figure 15 As shown.

[0148] like Figure 11 As shown, in step S140, a first barrier layer 4 is formed covering the surfaces of the first dielectric layer 1 and the conductive connection portion 3.

[0149] Please continue reading Figure 4 As shown, the first barrier layer 4 can cover the surfaces of the first dielectric layer 1 and the conductive connection portion 3. Since the top of the conductive connection portion 3 is covered by the first barrier layer 4, it helps to reduce the probability of oxidation of the top of the conductive connection portion 3, which can further reduce structural defects and improve product yield. The material of the first barrier layer 4 can be an insulating material, for example, silicon nitride. The first barrier layer 4 can be formed on the surface of the structure jointly formed by the first dielectric layer 1 and the conductive connection portion 3 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the first barrier layer 4 can also be formed by other methods, and the formation method of the first barrier layer 4 is not specifically limited here. In some embodiments of this disclosure, the thickness of the first barrier layer 4 can be 60nm to 100nm, for example, it can be 60nm, 70nm, 80nm, 90nm or 100nm. Of course, it can also be other thicknesses, which will not be listed here.

[0150] like Figure 11 As shown, in step S150, a second dielectric layer 5 is formed on the surface of the first barrier layer 4.

[0151] The material of the second dielectric layer 5 can be the same as that of the first dielectric layer 1. For example, both the first dielectric layer 1 and the second dielectric layer 5 can be made of silicon oxide. The second dielectric layer 5 can be formed on the surface of the first barrier layer 4 by methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the second dielectric layer 5, and no specific limitation is made here. Since the first barrier layer 4 is located between the second dielectric layer 5 and the conductive connection portion 3, it can prevent ions in the conductive connection portion 3 from diffusing into the second dielectric layer 5, which helps to reduce structural defects, improve device stability, and thus improve product yield.

[0152] like Figure 11 As shown, in step S160, a bonding portion 6 is formed that penetrates the first barrier layer 4 and the second dielectric layer 5. The bonding portion 6 is connected to the end of the conductive connection portion 3 away from the metal interconnect 2. The bonding portion 6 is annular, and the orthographic projection of the bonding portion 6 on the conductive connection portion 3 covers the edge region of the conductive connection portion 3.

[0153] Please continue reading Figure 3 As shown, the bonding portion 6 may be columnar and may extend in a direction perpendicular to the substrate 100. For example, the bonding portion 6 may penetrate the first barrier layer 4 and the second dielectric layer 5, and one end of it may be connected to the end of the conductive connection portion 3 away from the metal interconnect 2, while the other end extends in a direction perpendicular to the substrate 100 toward the side away from the conductive connection portion 3.

[0154] In some embodiments of this disclosure, the top of the bonding portion 6 may be lower than the top surface of the second dielectric layer 5, and the height difference between the top of the bonding portion 6 and the top surface of the second dielectric layer 5 may be less than or equal to 10 nm. This design ensures that during subsequent bonding processes, the expanded metal in the bonding portion 6 fills the height difference between the top of the bonding portion 6 and the top surface of the second dielectric layer 5, and does not overflow outwards.

[0155] The bonding portion 6 may be made of a conductive material, through which the conductive connection portion 3 can be electrically led out. For example, the bonding portion 6 may include a metallic material, such as tungsten or copper. The bonding portion 6 may also include a barrier material, such as titanium nitride, tantalum, or tantalum nitride.

[0156] In some embodiments of this disclosure, the cross-section of the bonding portion 6 may be annular in a direction parallel to the substrate 100, which helps to increase the process window during the bonding process. The bonding portion 6 may include an inner ring and an outer ring, with the material constituting the bonding portion 6 located between the inner ring and the outer ring. The interior of the inner ring is filled with the second dielectric layer 5, and the area outside the outer ring is also filled with the second dielectric layer 5. It should be noted that the shape of the inner ring may be the same as or different from the shape of the outer ring, and no special limitation is made here.

[0157] For example, both the inner and outer rings of the annular bonding portion 6 can be circular; or both the inner and outer rings of the annular bonding portion 6 can be rectangular; or the inner ring of the annular bonding portion 6 can be circular and the outer ring can be rectangular; or the inner ring of the annular bonding portion 6 can be rectangular and the outer ring can be circular; of course, the inner and outer rings can also be other shapes, which will not be listed here.

[0158] In some embodiments of this disclosure, the outer ring size of the annular bonding portion 6 can be 0.5um to 1.5um. For example, its outer ring size can be 0.5um, 1.0um, or 1.5um. Of course, it can also be other sizes, which will not be listed here. The inner ring size of the annular bonding portion 6 can be 0.15um to 0.4um. For example, its inner ring size can be 0.15um, 0.2um, 0.25um, 0.3um, 0.35um, or 0.4um. Of course, it can also be other sizes, which will not be listed here.

[0159] In one embodiment, the orthographic projection of the bonding portion 6 onto the conductive connection portion 3 can cover the edge region of the conductive connection portion 3. For example, its orthographic projection can cover a portion of the edge region of the conductive connection portion 3; or, its orthographic projection can cover the entire perimeter of the edge of the conductive connection portion 3. For instance, the bonding portion 6 can be electrically connected to a portion of the edge region of the conductive connection portion 3, or it can be in contact with the entire perimeter of the edge of the conductive connection portion 3, which helps to increase the contact area between the bonding portion 6 and the conductive connection portion 3, thereby reducing the contact resistance. At the same time, since the bonding portion 6 is annular, the amount of material within the bonding portion 6 is reduced, and the expansion of the material within the bonding portion 6 during subsequent bonding processes will also be reduced. Therefore, it is less likely to have voids or material extrusion problems, which helps to further reduce structural defects and improve product yield.

[0160] In some embodiments of this disclosure, the number of bonding portions 6 may be one or more. For example, the number of bonding portions 6 may match the number of conductive connection portions 3. For instance, when the number of conductive connection portions 3 is one, the number of bonding portions 6 may also be one; when the number of conductive connection portions 3 is multiple, the number of bonding portions 6 may also be multiple, and each bonding portion 6 may be connected to each conductive connection portion 3 in a one-to-one correspondence.

[0161] In one exemplary embodiment of this disclosure, forming the bonding portion 6 may include steps S310-S320, wherein:

[0162] Step S310: Etch the first barrier layer 4 and the second dielectric layer 5 to form a bonding hole 601; the bonding hole 601 is annular and exposes at least a portion of the edge region of the conductive connection portion 3.

[0163] like Figure 16 As shown, a second photoresist layer 300 can be formed on the surface of the second dielectric layer 5 by spin coating or other methods. The material of the second photoresist layer 300 can be positive or negative photoresist, without special limitation. A mask can be used to expose and develop the second photoresist layer 300 to form a second developing region 310. The orthogonal projection of the second developing region 310 on the substrate 100 coincides with at least a portion of the edge region of the conductive connection portion 3. The number of second developing regions 310 can be one or more, without special limitation. The conductive connection portion 3 can be an etch stop layer. The second dielectric layer 5 and the first barrier layer 4 can be etched in the second developing region 310 to form an annular bonding hole 601 exposing the conductive connection portion 3. The structure after step S310 in this embodiment is as follows: Figure 17 As shown.

[0164] In step S320, a second barrier layer 61 is formed on the sidewall and bottom of the bonding hole 601.

[0165] After the bonding via 601 is formed, the second photoresist layer 300 can be removed, thereby exposing the surface of the second dielectric layer 5. Please continue to the next section. Figure 3 As shown, a second barrier layer 61 can be formed within the bonding hole 601 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The second barrier layer 61 can conformally cover the sidewalls and bottom of the bonding hole 601. The thickness of the second barrier layer 61 can be 20 nm to 40 nm, for example, it can be 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm. Of course, other thicknesses are also possible, which will not be listed here. In some embodiments of this disclosure, the material of the second barrier layer 61 can be at least one of tantalum, tantalum nitride, or titanium nitride.

[0166] In step S330, a bonding layer 62 is formed in the bonding hole 601 having the second barrier layer 61. The top end of the bonding layer 62 is lower than the top surface of the second dielectric layer 5, and the height difference between the top end of the bonding layer 62 and the top surface of the second dielectric layer 5 is less than or equal to 10 nm.

[0167] Please continue reading Figure 3 As shown, a bonding layer 62 can be formed within the bonding hole 601 with the second barrier layer 61 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or electroplating. Of course, other methods can also be used to form the bonding layer 62, and no special limitation is made here. For example, when the material of the bonding layer 62 is copper, a thin layer of copper can first be deposited in the bonding hole 601 with the second barrier layer 61 by atomic layer deposition. Then, copper can be electroplated in the bonding hole 601 using the thin copper as the cathode until the copper fills the bonding hole 601.

[0168] In some embodiments of this disclosure, the surface of the bonding layer 62 can also be planarized. For example, after copper plating inside the bonding hole 601, the surface of the structure formed by the second dielectric layer 5, the second barrier layer 61, and the copper can be chemically mechanically polished to eliminate surface height differences and provide a flat process reference for subsequent processes. The remaining copper inside the bonding hole 601 after polishing can be used as the bonding layer 62, and the bonding layer 62 and the remaining second barrier layer 61 can together form the bonding portion 6. In the bonding portion 6, since the material of the second barrier layer 61 has ion-blocking function, the metal ions in the bonding layer 62 can be prevented from diffusing into other surrounding structures (e.g., the first dielectric layer 1 and the second dielectric layer 5), which helps to improve device stability.

[0169] In some embodiments of this disclosure, since different materials have different grinding rates during the grinding process, for example, the grinding rate of the second dielectric layer 5 is less than that of copper, after grinding, the top of the bonding portion 6 is lower than the top surface of the second dielectric layer 5, and the height difference between the top of the bonding portion 6 and the top surface of the second dielectric layer 5 is less than or equal to 10 nm. This design can ensure that in the subsequent bonding process, the expanded metal in the bonding portion 6 fills the height difference between the top of the bonding portion 6 and the top surface of the second dielectric layer 5, and will not overflow outward.

[0170] In one exemplary embodiment of this disclosure, such as Figure 18 As shown, before forming the bonding portion 6 (i.e., before forming the bonding hole 601), the formation method of this disclosure may further include forming a second barrier layer 7 on the surface of the second dielectric layer 5. Since the second barrier layer 7 covers the surface of the second dielectric layer 5, even if misalignment occurs during the bonding process, the second barrier layer 7 can prevent ions in other bonding structures bonded to the bonding structure from diffusing into the second dielectric layer 5 of the bonding structure, which helps to improve device stability.

[0171] The second barrier layer 7 can be a thin film or a coating covering the surface of the second dielectric layer 5. No specific limitation is made to the specific form of the second barrier layer 7. The material of the second barrier layer 7 can be an insulating material, such as silicon nitride. The second barrier layer 7 can be formed on the surface of the second dielectric layer 5 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the second barrier layer 7. No specific limitation is made to the formation method of the second barrier layer 7. In some embodiments of this disclosure, the thickness of the second barrier layer 7 can be 60 nm to 100 nm, for example, it can be 60 nm, 70 nm, 80 nm, 90 nm, or 100 nm. Of course, other thicknesses are also possible, which will not be listed here.

[0172] When a second barrier layer 7 is formed before the bonding portion 6 is formed, the formation of the bonding portion 6 may include steps S410-S430, wherein:

[0173] In step S410, the first barrier layer 4, the second dielectric layer 5, and the second barrier layer 7 are etched to form a bonding hole 601; the bonding hole 601 is annular and exposes at least a portion of the edge region of the conductive connection portion 3.

[0174] Please continue reading Figure 18 As shown, before forming the bonding hole 601, a sacrificial layer 9 can be formed on the surface of the second barrier layer 7. The thickness of the sacrificial layer 9 can be 80nm to 120nm, and the material of the sacrificial layer 9 can be silicon oxide. A third photoresist layer 400 can be formed on the surface of the sacrificial layer 9 by spin coating or other methods. The material of the third photoresist layer 400 can be positive or negative photoresist, without special limitation. The third photoresist layer 400 can be exposed and developed using a mask to form a third development area 410. The orthogonal projection of the third development area 410 on the substrate 100 coincides with at least a portion of the edge region of the conductive connection portion 3. The number of third development areas 410 can be one or more, without special limitation. The conductive connection portion 3 can be used as an etch stop layer. The sacrificial layer 9, the second barrier layer 7, the second dielectric layer 5, and the first barrier layer 4 are etched in the third development area 410 to form an annular bonding hole 601 exposing the conductive connection portion 3. In the embodiment of this disclosure, the structure after completing step S410 is as follows: Figure 19 As shown.

[0175] In step S420, a second barrier layer 61 is formed on the sidewall and bottom of the bonding hole 601.

[0176] It should be noted that step S420 is similar to step S320, and its specific details can be found in step S320; therefore, it will not be repeated here. In this embodiment of the disclosure, the structure after completing step S420 is as follows: Figure 20 As shown.

[0177] In step S430, a bonding layer 62 is formed in the bonding hole 601 having the second barrier layer 61, the top end of the bonding layer 62 is lower than the top surface of the second barrier layer 7, and the height difference between the top end of the bonding layer 62 and the top surface of the second barrier layer 7 is less than or equal to 10 nm.

[0178] like Figure 21As shown, a bonding layer 62 can be formed within the bonding hole 601 with the second barrier layer 61 by means of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or electroplating. Of course, the bonding layer 62 can also be formed by other means, and no special limitation is made here. For example, when the material of the bonding layer 62 is copper, a thin layer of copper can first be deposited in the bonding hole 601 with the second barrier layer 61 by atomic layer deposition. Then, copper 602 can be electroplated in the bonding hole using the thin copper as the cathode until the copper 602 fills the bonding hole 601.

[0179] In some embodiments of this disclosure, the surface of the bonding layer 62 may also be planarized. For example, after electroplating copper 602 in the bonding hole 601, a chemical mechanical polishing process may be used for planarization. During this process, the sacrificial layer 9 and the copper 602 on the surface of the sacrificial layer 9 may be removed, and the remaining copper 602 in the bonding hole 601 after polishing may be used as the bonding layer 62. The bonding layer 62 and the remaining second barrier layer 61 may together form the bonding portion 6.

[0180] In some embodiments of this disclosure, during the grinding process, due to the different grinding rates of different materials, the top of the bonding portion 6 may be lower than the top surface of the second dielectric layer 5, and the height difference between the top of the bonding portion 6 and the top surface of the second dielectric layer 5 is less than or equal to 10 nm. In the subsequent bonding process, the expanded metal in the bonding portion 6 fills the height difference between the top of the bonding portion 6 and the top surface of the second dielectric layer 5, and does not overflow outward.

[0181] In an exemplary embodiment of this disclosure, the method for forming the bonding structure may further include: forming a pseudo-bonding portion 8 in the peripheral region of the distribution area of ​​each bonding portion 6. The pseudo-bonding portion 8 can pass through the first barrier layer 4 and the second dielectric layer 5. For example, the pseudo-bonding portion 8 can be formed simultaneously during the formation of the bonding portion 6. The pseudo-bonding portion 8 can pass through the first barrier layer 4 and the second dielectric layer 5, and its structure and material are the same as those of the bonding portion 6. The difference between the pseudo-bonding portion 8 and the bonding portion 6 is that the bottom of the bonding portion 6 is connected to the conductive connection portion 3, while the pseudo-bonding portion 8 is not connected to the conductive connection portion 3. The design of the pseudo-bonding portion 8 can help dissipate heat and balance the uniformity of material distribution within the bonding structure, reducing warpage and thus reducing the difficulty of subsequent processes.

[0182] For example, the substrate 100 can be divided into a central region and a peripheral region. The central region can be adjacent to the peripheral region, and the peripheral region can surround the central region. Each bonding portion 6 can be located within the central region, and the dummy bonding portion 8 can be located within the peripheral region. When forming the bonding portion 6, a bonding hole 601 can be formed in the central region. At the same time, a dummy bonding hole 801 can be formed in the peripheral region. The orthogonal projection of the dummy bonding hole 801 on the first dielectric layer 1 does not overlap with the conductive connection portion 3. The dummy bonding hole 801 can penetrate the first barrier layer 4 and the second dielectric layer 5. During the formation of the second barrier layer 61 and the bonding layer 62 within the bonding hole 601, the second barrier layer 61 and the bonding layer 62 can be formed simultaneously within the dummy bonding hole 801. The second barrier layer 61 and the bonding layer 62 located within the dummy bonding hole 801 can together constitute the dummy bonding portion 8.

[0183] It should be noted that when the second barrier layer 7 is formed on the surface of the second dielectric layer 5, the pseudo-bonding part 8 can also pass through the second barrier layer 7, thereby ensuring that the structure of the pseudo-bonding part 8 is consistent with the structure of the bonding part 6.

[0184] In this disclosure, for ease of distinction, the bonding structure excluding the second barrier layer 7 can be defined as the first bonding structure A, and the bonding structure including the second barrier layer 7 can be defined as the second bonding structure B.

[0185] This disclosure also provides a bonding method that can be used to bond a first bonding structure A in any of the above embodiments to a second bonding structure B in any of the above embodiments. For example, the bonding portion 6 of the first bonding structure A can be aligned with the bonding portion 6 of the second bonding structure B, and the first bonding structure A and the second bonding structure B can be bonded through the bonding portion 6 of the first bonding structure A and the bonding portion 6 of the second bonding structure B.

[0186] In some embodiments of this disclosure, the bonding temperature can be 300℃ to 400℃, for example, it can be 300℃, 320℃, 340℃, 360℃, 380℃ or 400℃. Of course, other bonding temperatures are also possible, which will not be listed here. The bonding time can be 5h to 10h, for example, it can be 5h, 6h, 7h, 8h, 9h or 10h. Of course, other bonding times are also possible, which will not be listed here.

[0187] In some embodiments of this disclosure, the bonding portion 6 of the first bonding structure A and the bonding portion 6 of the second bonding structure B have the same shape but different dimensions. Because the bonding portions 6 of the two bonding structures have different dimensions, it helps to increase the process window during bonding and reduce process difficulty. For example, when the distance between the inner and outer rings of the first bonding structure A is 'a' and the distance between the inner and outer rings of the second bonding structure B is 'b', the tolerance for offset error during bonding of the first bonding structure A and the second bonding structure B is 'ab'. Simultaneously, since the second barrier layer 7 of the second bonding structure covers the surface of the second dielectric layer 5 of the second bonding structure, even if misalignment occurs during bonding, the second barrier layer 7 can prevent ions in the conductive connection portion 3 of the first bonding structure bonded to the second bonding structure from diffusing into the second dielectric layer 5 of the second bonding structure, thus helping to improve device stability. In embodiments of this disclosure, the structure after bonding the first bonding structure A and the second bonding structure B is as follows: Figure 22 As shown.

[0188] This disclosure also provides a bonding method that can bond the two second bonding structures B described above. For example, the bonding portions 6 of the two second bonding structures B can be aligned, and the two second bonding structures B can be bonded together through the bonding portions 6. The specific details of the bonding are similar to those of the above-described bonding method embodiments, and therefore will not be repeated here.

[0189] It should be noted that the bonding portions 6 of the two second bonding structures B have the same shape but different sizes. Because the bonding portions 6 of the two second bonding structures B have different sizes, it helps to increase the process window during bonding and reduce the process difficulty. For example, in the two second bonding structures B, when the distance between the inner and outer rings of one second bonding structure B is 'a' and the distance between the inner and outer rings of the other second bonding structure B is 'b', the tolerance for misalignment error during bonding of the two second bonding structures B is 'ab'. Simultaneously, since both bonding structures include a second barrier layer 7, and the two second barrier layers 7 respectively cover the surface of the second dielectric layer 5 of the two different bonding structures, even if misalignment occurs during bonding, the second barrier layer 7 can prevent ions in the conductive connection portion 3 of the other bonding structure bonded to it from diffusing into the second dielectric layer 5 of that bonding structure, thus helping to improve device stability. In the embodiments of this disclosure, the structure after bonding the two second bonding structures B is as follows: Figure 23 As shown.

[0190] It should be noted that although the method for forming the bonded structure and the steps of the bonding method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0191] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A bonding structure, characterized in that, include: A first dielectric layer and metal interconnects embedded in the first dielectric layer; A conductive connection portion is disposed within the first dielectric layer, with one end connected to the metal interconnect and the other end flush with the top surface of the first dielectric layer. A first barrier layer covers the surfaces of the first dielectric layer and the conductive connection portion; A second dielectric layer covers the surface of the first barrier layer; A bonding portion extends through the first barrier layer and the second dielectric layer, and is connected to the end of the conductive connection portion away from the metal interconnect. The bonding portion is annular, and the orthographic projection of the bonding portion onto the conductive connection portion covers the edge region of the conductive connection portion. The bonding portion includes an inner ring and an outer ring, with the material constituting the bonding portion located between the inner ring and the outer ring, and the area inside the inner ring and outside the outer ring being filled by the second dielectric layer.

2. The bonding structure according to claim 1, characterized in that, The bonding structure further includes: A second barrier layer covers the surface of the second dielectric layer; the bonding portion also penetrates the second barrier layer.

3. The bonding structure according to claim 2, characterized in that, The conductive connection portion includes: A conductive layer is disposed within the first dielectric layer, with one end connected to the metal interconnect and the other end flush with the top surface of the first dielectric layer. A first barrier layer conformally covers the sidewalls of the conductive layer.

4. The bonding structure according to claim 3, characterized in that, The bonding portion includes: A bonding layer, wherein the orthographic projection of the bonding layer onto the conductive connection portion at least partially coincides with the edge region of the conductive connection portion; The second barrier layer conformally covers the sidewalls of the bonding layer and the space between the bonding layer and the first dielectric layer.

5. The bonding structure according to claim 4, characterized in that, The first barrier layer and the second barrier layer are both made of at least one of tantalum, tantalum nitride, or titanium nitride; the conductive layer and the bonding layer are both made of copper; when the bonding structure includes the second barrier layer, the first barrier layer and the second barrier layer are made of silicon nitride.

6. The bonding structure according to claim 4, characterized in that, The thickness of both the first barrier layer and the second barrier layer is 20nm~40nm.

7. The bonding structure according to claim 1, characterized in that, The top of the bonding portion is lower than the top surface of the second dielectric layer, and the height difference between the top of the bonding portion and the top surface of the second dielectric layer is less than or equal to 10 nm.

8. The bonding structure according to claim 1 or 2, characterized in that, The number of conductive connection portions is multiple, and each conductive connection portion is electrically connected to the metal interconnect; the number of bonding portions is multiple, and each bonding portion is connected to each conductive connection portion in a one-to-one correspondence.

9. The bonding structure according to claim 8, characterized in that, The bonding structure further includes: A pseudo-bonding portion is located in the peripheral region of the distribution area of ​​each of the bonding portions, and the pseudo-bonding portion passes through the first barrier layer and the second dielectric layer; When the bonding structure further includes a second barrier layer, the pseudo-bonded portion also passes through the second barrier layer.

10. A method for forming a bonded structure, characterized in that, include: Provide substrate; A first dielectric layer and metal interconnects embedded within the first dielectric layer are formed on the substrate; A conductive connection portion is formed in the first dielectric layer, one end of which is connected to the metal interconnect line, and the other end is flush with the top surface of the first dielectric layer. A first barrier layer is formed covering the surfaces of the first dielectric layer and the conductive connection portion; A second dielectric layer is formed on the surface of the first barrier layer; A bonding portion is formed that penetrates the first barrier layer and the second dielectric layer. The bonding portion is connected to the end of the conductive connection portion away from the metal interconnect. The bonding portion is annular, and the orthographic projection of the bonding portion on the conductive connection portion covers the edge region of the conductive connection portion. The bonding portion includes an inner ring and an outer ring. The material constituting the bonding portion is located between the inner ring and the outer ring, and the area inside the inner ring and the area outside the outer ring are both filled by the second dielectric layer.

11. The forming method according to claim 10, characterized in that, The conductive connection portion includes: The first dielectric layer is etched to form a conductive contact hole within the first dielectric layer, the conductive contact hole exposing the metal interconnect; A first barrier layer is formed on the sidewall of the conductive contact hole; A conductive layer is formed within the conductive contact hole having the first barrier layer, the conductive layer filling the conductive contact hole, and the surface of the conductive layer away from the substrate is flush with the top surface of the first dielectric layer.

12. The forming method according to claim 10, characterized in that, Before forming the bonding portion, the forming method further includes: A second barrier layer is formed on the surface of the second dielectric layer; Forming the bonding portion includes: The first barrier layer, the second dielectric layer, and the second barrier layer are etched to form a bonding hole; the bonding hole is annular and exposes at least a portion of the edge region of the conductive connection. A second barrier layer is formed on the sidewall and bottom of the bonding hole; A bonding layer is formed within the bonding hole having the second barrier layer, the top of the bonding layer being lower than the top surface of the second barrier layer, and the height difference between the top of the bonding layer and the top surface of the second barrier layer being less than or equal to 10 nm.

13. The forming method according to any one of claims 10-12, characterized in that, The number of conductive connections is plurality of, and each conductive connection is electrically connected to the metal interconnect; the number of bonding portions is plurality of, and each bonding portion is connected to each conductive connection portion in a one-to-one correspondence; the forming method further includes: A pseudo-bonded portion is formed in the peripheral region of the distribution area of ​​each of the bonding portions, and the pseudo-bonded portion passes through the first barrier layer and the second dielectric layer; When a second barrier layer is formed on the surface of the second dielectric layer, the pseudo-bonding portion also penetrates the second barrier layer.

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