A monolithic integrated overvoltage protection power switch

Abstract

The present invention discloses a monolithic integrated overvoltage protection power switch, comprising a main power switch tube, a surge discharge power switch tube, a switch gate control circuit, a surge detection circuit, an input end and an output end, wherein the gate of the main power switch tube is controlled by the switch gate control circuit, the drain of the main power switch tube is connected to the drain and input end of the surge discharge power switch tube, the gate of the surge discharge power switch tube is controlled by the surge detection circuit, the main power switch tube and the surge discharge power switch tube are both vertical DMOS structures, and the drains of the main power switch tube and the surge discharge power switch tube are short-circuited by metal on the back of the silicon wafer. The present invention realizes a power switch tube with ultra-low on-resistance and a higher-level surge protection tube.

Description

Technical Field

[0001] The invention relates to a power switch, in particular to a monolithic integrated overvoltage protection power switch, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] Electrical overstress is currently the main cause of device failure in integrated circuit chips. In particular, those chip pins that are directly connected to the system's external ports are very susceptible to various types of electrical overstress. These electrical overstress factors include unstable power output, various overvoltage and overcurrent noises, surge currents during hot-swap applications, moisture or mechanical short-circuit phenomena, and electrostatic discharge, etc. For these chip pins connected to the system interface, special attention should be paid to electrical overstress protection. At present, the main method for electrical overstress protection of chips is to add discrete surge protection devices to the outside of the chip on the system circuit board, such as transient voltage suppression diodes (TVS) for electrical overstress protection. The external discrete protection device is a functional device that realizes electrical overstress protection clamping and current discharge, and is required to have strong clamping voltage and discharge current capabilities. However, with the trend of thinner and lighter mobile terminals, the main research direction of interface chips is to integrate electrical overstress protection functions, eliminate external voltage clamping devices, and achieve maximum integration. Especially in some systems that already have primary protection, the chip interface only needs to have residual voltage overstress protection capabilities after primary protection to meet the requirements.

[0003] The idea of ​​the prior art is to use a high-voltage LDMOS switch tube as a high-voltage power switch, and another high-voltage LDMOS as a surge discharge tube. The drain of the LDMOS of the surge discharge tube is connected to the input end together with the drain of the high-voltage power switch, and the gate is controlled by the surge detection circuit. The overshoot detection circuit module is used to control the opening of the clamp protection tube to achieve voltage clamping and discharge the system ESD and surge pulse energy, thereby protecting the internal switch tube. Figure 4 As shown, label 1-a is the input terminal, label 6-a is the output terminal, label 2-a is the LDMOS power switch tube in the plane BCD, its drain is connected to 1-a, source is connected to 6-a, and the gate is controlled by the switch gate control circuit labeled 4-a. Label 3-a is the surge discharge power switch tube between the input 1-a and the substrate ground GND, the drain is connected to 1-a, the source is connected to the substrate ground GND, and the gate is controlled by the surge detection circuit 5-a.

[0004] A major drawback of this solution is that the source and drain are brought out from the surface, making it difficult to achieve a low on-resistance power switch, such as a switch below 10 milliohms, and greater surge protection. This is because for a planar lateral LDMOS, the drain and source are both on the surface of the silicon wafer, requiring a finger layout method, and the parasitic resistance of the metal trace will increase with the increase in the number of fingers fn of the NLDMOS and the width W of a single finger, thus limiting the further reduction of the on-resistance. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a monolithic integrated overvoltage protection power switch to achieve ultra-low on-resistance.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A monolithic integrated overvoltage protection power switch comprises a main power switch tube VDMOS1, a surge discharge power switch tube VDMOS2, a switch gate control circuit, a surge detection circuit, an input terminal Input and an output terminal Output, wherein the gate of the main power switch tube VDMOS1 is connected to the output terminal of the switch gate control circuit and is controlled by the switch gate control circuit, the source of the main power switch tube VDMOS1 is connected to the output terminal Output, the drain of the main power switch tube VDMOS1 is connected to the drain of the surge discharge power switch tube VDMOS2 and the input terminal Input The gate of the surge discharge power switch tube VDMOS2 is connected to the output end of the surge detection circuit and is controlled by the surge detection circuit. The source of the surge discharge power switch tube VDMOS2 is grounded. The main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are both vertical DMOS structures and the drains of the main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are short-circuited by the metal on the back of the silicon wafer. The main power switch tube VDMOS1, the surge discharge power switch tube VDMOS2, the switch gate control circuit, and the surge detection circuit are all integrated on a single chip.

[0008] Furthermore, the input end of the switch gate control circuit and the input end of the surge detection circuit are both connected to the input end Input.

[0009] Furthermore, a ground terminal of the surge detection circuit is grounded.

[0010] Furthermore, the main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are located on both sides of the switch gate control circuit and the surge detection circuit in terms of layout arrangement.

[0011] Furthermore, the main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are arranged in a ring shape around the switch gate control circuit and the surge detection circuit.

[0012] Furthermore, the main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are respectively composed of a plurality of VDMOS tubes connected in parallel.

[0013] Furthermore, each of the VDMOS tubes comprises a heavily doped N-type silicon substrate, a back metal electrode layer, an input pin, a source pin, an N-type epitaxy, a trench of a VDMOS terminal junction, a shielding gate lead-out polysilicon, a trench of a VDMOS unit region, a source of the VDMOS, a back gate lead-out and a gate polysilicon of the VDMOS, the back metal electrode layer is arranged on the lower side of the heavily doped N-type silicon substrate, the input pin is arranged on the back metal electrode layer, the N-type epitaxy is arranged on the upper side of the heavily doped N-type silicon substrate, the trench of the VDMOS terminal junction and the trench of the VDMOS unit region are arranged on the upper surface of the N-type epitaxy, the shielding gate lead-out polysilicon is arranged in the trench of the VDMOS terminal junction, the source and back gate lead-out of the VDMOS are arranged on the upper surface of the N-type epitaxy, the gate polysilicon of the VDMOS and the shielding gate are arranged in the trench of the VDMOS unit region and the gate polysilicon of the VDMOS is located on the upper surface of the N-type epitaxy, and the source pin is connected to the source and back gate of the VDMOS tube.

[0014] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a monolithic integrated overvoltage protection power switch, the main power switch tube and the surge discharge power tube are both realized by a vertical high-voltage MOS tube on a silicon wafer, and since their drains are on the back of the silicon wafer, the influence of the metal interconnect parasitic overvoltage resistance limitation between the drain and source of the LDMOS in the existing planar BCD is eliminated, thereby realizing a power switch tube with ultra-low on-resistance and a higher-level surge protection tube. At the same time, since the upper and lower surfaces of the silicon wafer are covered with metal, the thermal resistance becomes smaller, and the area efficiency of the surge protection is also greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of a monolithic integrated overvoltage protection power switch of the present invention.

[0016] Figure 2 It is a schematic diagram of the layout of a monolithic integrated overvoltage protection power switch of the present invention.

[0017] Figure 3 It is a cross-sectional view along the AA direction of the layout arrangement of a monolithic integrated overvoltage protection power switch of the present invention.

[0018] Figure 4Schematic diagram of a single-chip integrated overvoltage protection load switch in the prior art. DETAILED DESCRIPTION

[0019] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0020] like Figure 1 As shown, a monolithic integrated overvoltage protection power switch of the present invention comprises a main power switch tube VDMOS1, a surge discharge power switch tube VDMOS2, a switch gate control circuit, a surge detection circuit, an input terminal Input and an output terminal Output, the gate of the main power switch tube VDMOS1 is connected to the output terminal of the switch gate control circuit and is controlled by the switch gate control circuit, the source of the main power switch tube VDMOS1 is connected to the output terminal Output, the drain of the main power switch tube VDMOS1 is connected to the drain of the surge discharge power switch tube VDMOS2 and the input terminal Inpu t connection, the gate of the surge discharge power switch tube VDMOS2 is connected to the output end of the surge detection circuit and is controlled by the surge detection circuit, the source of the surge discharge power switch tube VDMOS2 is grounded, the main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are both vertical DMOS structures and the drains of the main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are short-circuited by the metal on the back of the silicon wafer, the main power switch tube VDMOS1, the surge discharge power switch tube VDMOS2, the switch gate control circuit and the surge detection circuit are all integrated on a single chip.

[0021] The present invention can realize an ultra-low on-resistance, such as an ultra-low on-resistance power switch below 10mohm, and can also realize a surge protection capability of 100V-300V and above according to application requirements.

[0022] The input end of the switch gate control circuit and the input end of the surge detection circuit are both connected to the input end Input. The ground end of the surge detection circuit is grounded.

[0023] In one embodiment of the present invention, Figure 2 As shown, the main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are located on both sides of the switch gate control circuit and the surge detection circuit in the layout arrangement.

[0024] In another embodiment of the present invention, the main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are arranged in a ring shape around the periphery of the switch gate control circuit and the surge detection circuit.

[0025] The main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are respectively composed of a plurality of VDMOS tubes connected in parallel.

[0026] like Figure 3 As shown, each VDMOS tube includes a heavily doped N-type silicon substrate 1, a back metal electrode layer 2, an input pin 31, a source pin, an N-type epitaxial 3, a trench 4 of a VDMOS terminal junction, a shielding gate lead polysilicon 5, a trench 22 of a VDMOS cell region, a source 10 of the VDMOS, a back gate lead 6, and a gate polysilicon 7 of the VDMOS. The back metal electrode layer 2 is arranged on the lower side of the heavily doped N-type silicon substrate 1, the input pin 31 is arranged on the back metal electrode layer 2, the N-type epitaxial 3 is arranged on the upper side of the heavily doped N-type silicon substrate 1, and the trench 4 of the VDMOS terminal junction and the trench 22 of the VDMOS cell region are arranged on the upper surface of the N-type epitaxial 3. The shielding gate lead-out polysilicon 5 is arranged in the trench 4 of the VDMOS terminal junction, the source 10 and the back gate lead-out 6 of the VDMOS are arranged on the upper surface of the N-type epitaxial 3, the gate polysilicon 7 and the shielding gate 9 of the VDMOS are arranged in the trench 22 of the VDMOS unit area and the gate polysilicon 7 of the VDMOS is located on the upper surface of the N-type epitaxial 3, the source pin is connected to the source and the back gate of the VDMOS tube, wherein the source pin 32 of the surge discharge power switch tube leads the source and the back gate of the surge discharge power switch tube VDMOS2 to the ground GND, and the source pin 33 of the main power switch tube leads the source and the back gate of the main power switch tube VDMOS1 to the output terminal Output.

[0027] Among them, the gates of the main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are driven by their own gate control circuits and surge detection circuits on the front side of the silicon wafer, respectively. The front side is isolated from the high-voltage N-type substrate by a deep P-well, and the gate control circuit and surge detection circuit are formed in the deep P-well area on the front side of the silicon wafer. The main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are surrounded by terminal rings in the source and gate areas on the front side of the chip. The N-type epitaxy outside the terminal ring can lead the drain potential from the front side to realize the detection function of the circuit.

[0028] The main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 may be a common trench structure, or may be a MOSFET with an SGT (Split Gate) or (Shielding Gate) trench structure, or may be a trench MOSFET with other structures.

[0029] like Figure 3 As shown, the switch gate control circuit includes a P well isolation 11, a cathode 12 of a Zener tube, an anode 13 of a Zener tube, a P well 14 of a CMOS, an N well 16 of a PMOS, a Poly gate 15 of a PMOS, a Poly gate 17 of an NMOS, a P well 18 of an NMOS, a P well potential lead-out terminal 19, an N+ well region 20 for leading out the back drain potential (i.e., at the input pin 31), and an N well region 21 for leading out the back drain potential. The cathode 12 of the Zener tube and the anode 13 of the Zener tube can be formed by the N+ and P back gates of the VDMOS. The specific circuit principles and chip layout structures of the switch gate control circuit and the surge detection circuit are prior art, so they are not repeated here.

[0030] The present invention provides a monolithic integrated overvoltage protection power switch, which is implemented using a vertical VDMOS BCD process platform, eliminating the metal interconnect parasitic resistance limitation of the surface structure LDMOS itself, and the upper and lower metal electrodes of the power switch tube of the vertical structure current path and the thinner substrate enhance the heat dissipation performance, greatly improving the power handling capacity of the single chip. In addition, it can realize ultra-low on-resistance (below 10mohm) high-power power switch and surge protection tube (higher area efficiency to achieve 100V and above surge protection capability).

[0031] It is particularly suitable for chips with large power switch tubes, and can provide a very significant system ESD and EOS surge electrical overstress self-protection function without occupying the surface area. It saves transient voltage suppression diodes outside the chip, saves system board area, and does not increase the chip area itself. It is a very efficient, low-cost integrated protection solution for electrical overstress protection.

[0032] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A monolithic integrated overvoltage protection power switch, characterized in that: The invention comprises a main power switch tube VDMOS1, a surge discharge power switch tube VDMOS2, a switch gate control circuit, a surge detection circuit, an input terminal Input and an output terminal Output. The gate of the main power switch tube VDMOS1 is connected to the output terminal of the switch gate control circuit and is controlled by the switch gate control circuit. The source of the main power switch tube VDMOS1 is connected to the output terminal Output. The drain of the main power switch tube VDMOS1 is connected to the drain of the surge discharge power switch tube VDMOS2 and the input terminal Input. The gate of the gate tube VDMOS2 is connected to the output end of the surge detection circuit and is controlled by the surge detection circuit. The source of the surge discharge power switch tube VDMOS2 is grounded. The main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are both vertical DMOS structures, and the drains of the main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are short-circuited by the metal on the back of the silicon wafer. The main power switch tube VDMOS1, the surge discharge power switch tube VDMOS2, the switch gate control circuit, and the surge detection circuit are all integrated on a single chip. The main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are respectively composed of a plurality of VDMOS tubes connected in parallel; Each of the VDMOS tubes comprises a heavily doped N-type silicon substrate, a back metal electrode layer, an input pin, a source pin, an N-type epitaxy, a trench of a VDMOS terminal junction, a shielding gate lead-out polysilicon, a trench of a VDMOS unit region, a source of the VDMOS, a back gate lead-out and a gate polysilicon of the VDMOS. The back metal electrode layer is arranged on the lower side of the heavily doped N-type silicon substrate, the input pin is arranged on the back metal electrode layer, the N-type epitaxy is arranged on the upper side of the heavily doped N-type silicon substrate, the trench of the VDMOS terminal junction and the trench of the VDMOS unit region are arranged on the upper surface of the N-type epitaxy, the shielding gate lead-out polysilicon is arranged in the trench of the VDMOS terminal junction, the source and back gate lead-out of the VDMOS are arranged on the upper surface of the N-type epitaxy, the gate polysilicon of the VDMOS and the shielding gate are arranged in the trench of the VDMOS unit region and the gate polysilicon of the VDMOS is located on the upper surface of the N-type epitaxy, and the source pin is connected to the source and back gate of the VDMOS tube.

2. The monolithic integrated overvoltage protection power switch according to claim 1, characterized in that: The input end of the switch gate control circuit and the input end of the surge detection circuit are both connected to the input end Input.

3. The monolithic integrated overvoltage protection power switch according to claim 1, characterized in that: The ground terminal of the surge detection circuit is grounded.

4. The monolithic integrated overvoltage protection power switch according to claim 1, characterized in that: The main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are located on both sides of the switch gate control circuit and the surge detection circuit in terms of layout.

5. The monolithic integrated overvoltage protection power switch according to claim 1, characterized in that: The main power switch tube VDMOS1 and the surge discharge power switch tube VDMOS2 are arranged in a ring shape around the periphery of the switch gate control circuit and the surge detection circuit.

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