A decision feedback equalization circuit, a deserialization circuit chip and an electronic device
By pre-emphasizing the original signal and delay signal of the received data in the time domain, the implementation of the judgment feedback equalization circuit is simplified, the complexity and high power consumption of the traditional DFE circuit are solved, and the equalization processing of the received data and the improvement of the clock performance are achieved.
Patent Information
- Application Number
- CN202411266936.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2044-09-11
AI Technical Summary
The traditional judgment feedback equalization (DFE) circuit is complex to implement, with large power consumption, large area, high clock performance requirements, and difficult to meet the needs of high-speed signal transmission.
By combining pre-emphasis technology, the original signal and delay signal of the received data are processed, and the width of the received data is pre-adjusted, simplifying the implementation of equalization processing.
The equalization processing of received data is realized, power consumption and area are reduced, clock performance is improved, and the problems of complexity and high power consumption of traditional DFE circuits are solved.
Smart Images
Figure CN118972212B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor chips, and in particular to a decision feedback equalization circuit, a deserialization circuit chip and an electronic device. Background Art
[0002] As the resolution of multimedia videos increases, the speed of transmission between chips needs to be faster and faster. However, it is limited by the transmission medium, cost and competition considerations. The transmission medium loss of high-speed signals is large, and the high-frequency components of the signals are severely attenuated. In this regard, in the prior art, a decision feedback equalizer (DFE) circuit is usually used to equalize the data at the receiving end, which can reduce the distortion related to the data and the channel without amplifying the noise. However, the traditional DFE circuit is complex to implement, consumes a lot of power, has a large area, and has high requirements for clock performance. Summary of the invention
[0003] In view of the above-mentioned defects or deficiencies in the prior art, the present invention provides a decision feedback equalization circuit, a deserialization circuit chip and an electronic device, which, in combination with the pre-emphasis technology, pre-adjusts the width of the received data signal by processing the original signal and the delayed signal of the received data, and finally realizes the equalization processing of the received data, and the implementation method is simpler, the power consumption is lower and the area is smaller.
[0004] In a first aspect, an embodiment of the present invention provides a decision feedback equalization circuit, including:
[0005] A time domain pre-emphasis generation module, a decision feedback module and an alignment circuit module;
[0006] The first end of the time domain pre-emphasis generation module is connected to the forward differential signal, the second end of the time domain pre-emphasis generation module is connected to the reverse differential signal, the third end of the time domain pre-emphasis generation module is connected to the first end of the decision feedback module, the fourth end of the time domain pre-emphasis generation module is connected to the second end of the decision feedback module, the third end of the decision feedback module is connected to the first end of the alignment circuit module, the fourth end of the decision feedback module is connected to the second end of the alignment circuit module, the fifth end of the decision feedback module is connected to the third end of the alignment circuit module, and the sixth end of the decision feedback module is connected to the fourth end of the alignment circuit module;
[0007] The time domain pre-emphasis generation module is configured to generate pre-emphasis in the time domain for the connected forward differential signal and the reverse differential signal, and the gain is controllable; the decision feedback module samples the data and the data edge, and selects the pre-emphasis processing path of its adjacent data according to the signal of the previous data; the alignment circuit module is configured to align the sampled data and the data edge to unify the clock domain.
[0008] Optionally, in some embodiments of the present invention, the time domain pre-emphasis generation module includes a first buffer, a second buffer, a first delay unit, a second delay unit, a first OR gate, a third buffer, a fourth buffer, a fifth buffer, a third delay unit, a fourth delay unit, a second OR gate and an inverting buffer;
[0009] The first end of the first buffer is connected to the first end of the first delay unit and connected to the positive differential signal, the second end of the first buffer is connected to the first end of the second buffer, the second end of the second buffer is connected to the first end of the first OR gate, the second end of the first delay unit is connected to the first end of the second delay unit, the second end of the second delay unit is connected to the second end of the first OR gate, the third end of the first OR gate is connected to the first end of the third buffer, and the second end of the third buffer is connected to the first end of the decision feedback module;
[0010] The first end of the fourth buffer is connected to the first end of the third delay unit and is connected to the reverse differential signal, the second end of the fourth buffer is connected to the first end of the fifth buffer, the second end of the fifth buffer is connected to the first end of the second OR gate, the second end of the third delay unit is connected to the first end of the fourth delay unit, the second end of the fourth delay unit is connected to the second end of the second OR gate, the third end of the second OR gate is connected to the first end of the inverting buffer, and the second end of the inverting buffer is connected to the second end of the decision feedback module.
[0011] Optionally, in some embodiments of the present invention, the decision feedback module includes a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a sixth trigger, a seventh trigger, an eighth trigger, a first selector, a second selector, a third selector, a fourth selector, a ninth trigger and a tenth trigger;
[0012] The first end of the first trigger, the first end of the third trigger, the first end of the fifth trigger and the first end of the seventh trigger are all connected to the third end of the time domain pre-emphasis generation module, the first end of the second trigger, the first end of the fourth trigger, the first end of the sixth trigger and the first end of the eighth trigger are all connected to the fourth end of the time domain pre-emphasis generation module; the second end of the first trigger and the second end of the second trigger are both connected to the first clock signal, the second end of the third trigger and the second end of the fourth trigger are both connected to the third clock signal, the second end of the fifth trigger and the second end of the sixth trigger are both connected to the second clock signal, the second end of the seventh trigger and the second end of the eighth trigger are both connected to the fourth clock signal; the third end of the first trigger is connected to the second end of the first selector, the third end of the second trigger is connected to the first end of the first selector, the third end of the third trigger is connected to the second end of the third selector, and the The third end is connected to the first end of the third selector, the third end of the fifth trigger is connected to the second end of the second selector, the third end of the sixth trigger is connected to the first end of the second selector, the third end of the seventh trigger is connected to the second end of the fourth selector, and the third end of the eighth trigger is connected to the first end of the fourth selector; the third end of the first selector is connected to the first end of the ninth trigger, the second end of the ninth trigger is connected to the first clock signal, the third end of the ninth trigger is connected to the fourth end of the third selector, the fourth end of the fourth selector and the first end of the alignment circuit module, the third end of the third selector is connected to the first end of the tenth trigger, the second end of the tenth trigger is connected to the third clock signal, the third end of the tenth trigger is connected to the fourth end of the first selector, the fourth end of the second selector and the second end of the alignment circuit module, the third end of the second selector is connected to the third end of the alignment circuit module, and the third end of the fourth selector is connected to the fourth end of the alignment circuit.
[0013] Optionally, in some embodiments of the present invention, the alignment circuit includes an eleventh flip-flop, a twelfth flip-flop, a thirteenth flip-flop, a fourteenth flip-flop, a fifteenth flip-flop, a sixteenth flip-flop and a seventeenth flip-flop;
[0014] The first end of the eleventh trigger is connected to the third end of the decision feedback module, the second end of the eleventh trigger is connected to the third clock signal, and the third end of the eleventh trigger outputs the first path of data. The first end of the twelfth trigger is connected to the fourth end of the decision feedback module, the second end of the twelfth trigger is connected to the third clock signal, and the third end of the twelfth trigger outputs the second path of sampled data. The first end of the thirteenth trigger is connected to the fifth end of the decision feedback module, the second end of the thirteenth trigger is connected to the second clock signal, the third end of the thirteenth trigger is connected to the first end of the fourteenth trigger, the second end of the fourteenth trigger is connected to the first clock signal, the third end of the fourteenth trigger is connected to the first end of the fifteenth trigger, the second end of the fifteenth trigger is connected to the third clock signal, and the third end of the fifteenth trigger outputs the first path of sampled data edge. The first end of the sixteenth trigger is connected to the sixth end of the decision feedback module, the second end of the sixteenth trigger is connected to the fourth clock signal, the third end of the sixteenth trigger is connected to the first end of the seventeenth trigger, the second end of the seventeenth trigger is connected to the third clock signal, and the third end of the seventeenth trigger outputs the second path of sampled data edge.
[0015] Optionally, in some embodiments of the present invention, the time domain pre-emphasis generation module includes a pre-addition path and a pre-subtraction path, and the pre-addition path performs an OR operation on the original signal and the delayed signal of the forward differential signal to widen the high level and shorten the low level;
[0016] The pre-subtraction path performs an OR operation on the original signal and the delayed signal of the reverse differential signal to widen the low level and shorten the high level.
[0017] Optionally, in some embodiments of the present invention, the first trigger, the second trigger, the third trigger, the fourth trigger, the fifth trigger, the sixth trigger, the seventh trigger, the eighth trigger, the ninth trigger and the tenth trigger are all D triggers, and the first ends of the first trigger, the second trigger, the third trigger, the fourth trigger, the fifth trigger, the sixth trigger, the seventh trigger, the eighth trigger, the ninth trigger and the tenth trigger are all data input ends of the D trigger, the second ends are all clock signal ends of the D trigger, and the third ends are all data output ends of the D trigger;
[0018] The first selector, the second selector, the third selector and the fourth selector are all dual-way data selectors, and the first ends of the first selector, the second selector, the third selector and the fourth selector are all data input ends selected by the control signal high level, the second ends are all data input ends selected by the control signal low level, the third ends are all data output ends, and the fourth ends are all control signal ends.
[0019] Optionally, in some embodiments of the present invention, the eleventh trigger, the twelfth trigger, the thirteenth trigger, the fourteenth trigger, the fifteenth trigger, the sixteenth trigger and the seventeenth trigger are all D triggers, and the first ends of the eleventh trigger, the twelfth trigger, the thirteenth trigger, the fourteenth trigger, the fifteenth trigger, the sixteenth trigger and the seventeenth trigger are all data input ends of the D trigger, the second ends are all clock signal ends of the D trigger, and the third ends are all data output ends of the D trigger.
[0020] Optionally, in some embodiments of the present invention, the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are sampling clocks with equal phase difference, and the phase difference is 90 degrees.
[0021] In a second aspect, an embodiment of the present invention provides a deserialization circuit chip, wherein the deserialization circuit chip includes the decision feedback equalization circuit described in any one of the first aspects.
[0022] In a third aspect, an embodiment of the present invention provides an electronic device, comprising a serial circuit chip, a transmission medium, and the deserialization circuit chip described in the second aspect, wherein the transmission medium is arranged between the serial circuit chip and the deserialization circuit chip.
[0023] It can be seen from the above technical solutions that the embodiments of the present invention have the following advantages:
[0024] A decision feedback equalization circuit, a deserialization circuit chip, and an electronic device provided by an embodiment of the present invention realize the pre-addition and pre-subtraction functions of the data width by performing OR operation processing on the original signal and the delayed signal of the input data from the time domain perspective, and selects its adjacent data for pre-addition or pre-subtraction according to the previous data, so as to pre-adjust the adjacent data width. At the same time, by adjusting the delay size of the pre-addition and pre-subtraction paths, the gain of the decision feedback equalization circuit can be adjusted, and finally the equalization of the received data is achieved. Compared with the implementation method of the traditional decision feedback equalization circuit that compares the amplitude of the decision signal to achieve equalization, the present invention combines the pre-emphasis technology to realize the pre-adjustment of the data width in the time domain, and the gain is controllable, the implementation method is simpler, the power consumption is lower, and the area is smaller. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:
[0026] Figure 1 It is a structural block diagram of a decision feedback equalization circuit provided by an embodiment of the present invention;
[0027] Figure 2 is a specific example of a decision feedback equalization circuit provided by an embodiment of the present invention;
[0028] Figure 3 This is a pre-emphasis effect diagram of a decision feedback equalization circuit provided by an embodiment of the present invention;
[0029] Figure 4 is a timing diagram of a decision feedback equalization circuit provided by an embodiment of the present invention;
[0030] Figure 5 is a structural block diagram of a deserialization circuit chip provided by an embodiment of the present invention;
[0031] Figure 6 It is a structural block diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0033] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.
[0034] It should be understood that although the terms first, second, third, etc. may be used to describe the acquisition modules in the embodiments of the present invention, the acquisition modules should not be limited to these terms. These terms are only used to distinguish the acquisition modules from each other.
[0035] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.
[0036] It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present invention are described at the angles shown in the drawings and should not be understood as limiting the embodiments of the present invention. In addition, in the context, it should also be understood that when it is mentioned that an element is formed "on" or "under" another element, it can not only be formed directly "on" or "under" another element, but also be formed "on" or "under" another element indirectly through an intermediate element.
[0037] See also Figure 1 , an embodiment of the present invention provides a decision feedback equalization circuit 1, the decision feedback equalization circuit 1 includes a time domain pre-emphasis generation module 11, a decision feedback module 12 and an alignment circuit module 13;
[0038] The first end of the time domain pre-emphasis generation module 11 is connected to the forward differential signal, the second end of the time domain pre-emphasis generation module 11 is connected to the reverse differential signal, the third end of the time domain pre-emphasis generation module 11 is connected to the first end of the decision feedback module 12, the fourth end of the time domain pre-emphasis generation module 11 is connected to the second end of the decision feedback module 12, the third end of the decision feedback module 12 is connected to the first end of the alignment circuit module 13, the fourth end of the decision feedback module 12 is connected to the second end of the alignment circuit module 13, the fifth end of the decision feedback module 12 is connected to the third end of the alignment circuit module 13, and the sixth end of the decision feedback module 12 is connected to the fourth end of the alignment circuit module 13;
[0039] Among them, the time domain pre-emphasis generation module 11 generates pre-emphasis in the time domain for the connected forward differential signal and reverse differential signal, and the gain is controllable; the decision feedback module 12 samples the data and the data edge, and selects the pre-emphasis processing path of its adjacent data according to the signal of the previous data; the alignment circuit module 13 aligns the sampled data and the data edge to unify the clock domain.
[0040] refer to Figure 1 , 2 , the specific circuit structure of each component module of a decision feedback equalization circuit 1 provided in an embodiment of the present invention is described.
[0041] Exemplarily, the time domain pre-emphasis generation module 11 may include but is not limited to a buffer buf1, a buffer buf2, a delay unit dly1, a delay unit dly2, an OR gate OR1, a buffer buf3, a buffer buf4, a buffer buf5, a delay unit dly3, a delay unit dly4, an OR gate OR2, and an inverting buffer buf6;
[0042] The first end of the buffer buf1 is connected to the first end of the delay unit dly1 and connected to the forward differential signal in_p, the second end of the buffer buf1 is connected to the first end of the buffer buf2, the second end of the buffer buf2 is connected to the first end of the OR gate OR1, the second end of the delay unit dly1 is connected to the first end of the delay unit dly2, the second end of the delay unit dly2 is connected to the second end of the OR gate OR1, the third end of the OR gate OR1 is connected to the first end of the buffer buf3, and the second end of the buffer buf3 is connected to the first end of the decision feedback module 12, which is the pre-emphasis path of the time domain pre-emphasis generation module, see Figure 3 , the pre-addition path performs an OR operation on the original signal and the delayed signal of the forward differential signal, widens the high level, keeps the total data width unchanged, and narrows the low level synchronously; illustratively, the forward differential signal in_p is processed by buffers buf1 and buf2 to obtain the original signal d1_buffer, the forward differential signal in_p passes through delay units dly1 and dly2 to obtain the delayed signal d1_dly, the original signal d1_buffer and the delayed signal d1_dly are processed by an OR gate OR1 to obtain a processed signal d1_dfe, and then passes through the buffer buf3 to output the pre-addition path signal dp_op with a widened high level and a narrowed low level;
[0043] The first end of the buffer buf4 is connected to the first end of the delay unit dly3 and connected to the reverse differential signal in_n, the second end of the buffer buf4 is connected to the first end of the buffer buf5, the second end of the buffer buf5 is connected to the first end of the OR gate OR2, the second end of the delay unit dly3 is connected to the first end of the delay unit dly4, the second end of the delay unit dly4 is connected to the second end of the OR gate OR2, the third end of the OR gate OR2 is connected to the first end of the inverting buffer buf6, and the second end of the inverting buffer buf6 is connected to the second end of the decision feedback module 12, which is the pre-reduction path of the time domain pre-emphasis generation module 11, see Figure 3 The pre-reduction path performs an OR operation on the original signal and the delayed signal of the reverse differential signal, widens the low level, keeps the total data width unchanged, and narrows the high level synchronously.
[0044] At the same time, the delay of the pre-addition and pre-subtraction paths is adjusted through the buffer to adjust the gain of the decision feedback equalization circuit 1.
[0045] This embodiment combines the pre-emphasis technology to generate two pre-emphasis paths of pre-addition and pre-subtraction for adjusting the data width, and the gain is controllable, so that subsequent pre-decision feedback can be performed on the next data according to the current input data.
[0046] Exemplarily, the decision feedback module 12 includes a trigger D1, a trigger D2, a trigger D3, a trigger D4, a trigger D5, a trigger D6, a trigger D7, a trigger D8, a selector MUX0, a selector MUX1, a selector MUX2, a selector MUX3, a trigger D9, and a trigger D10;
[0047] The first end of the trigger D1, the first end of the trigger D3, the first end of the trigger D5, and the first end of the trigger D7 are all connected to the third end of the time domain pre-emphasis generation module 11, and the first end of the trigger D2, the first end of the trigger D4, the first end of the trigger D6, and the first end of the trigger D8 are all connected to the fourth end of the time domain pre-emphasis generation module 11; the second end of the trigger D1 and the second end of the trigger D2 are both connected to the clock signal clk_0, the second end of the trigger D3 and the second end of the trigger D4 are both connected to the clock signal clk_2, the second end of the trigger D5 and the second end of the trigger D6 are both connected to the clock signal clk_1, and the second end of the trigger D7 and the second end of the trigger D8 are both connected to the clock signal clk_3;
[0048] The decision feedback equalization circuit of the embodiment of the present invention adopts a half-rate architecture, the clock speed is half of the data, and an inverted clock signal is used to sample the odd and even channel data respectively. For example, see Figure 4 , clock signals clk_0, clk_1, clk_2 and clk_3 are sampling clocks with equal phase difference, and the phase difference is 90 degrees. Clock signals clk_0 and clk_2 are inverted clock signals. Clock signal clk_0 samples the data d0 of the even path, and clock signal clk_2 samples the data d1 of the odd path. Similarly, inverted clock signals clk_1 and clk_3 are used to sample the data edge, so that the subsequent clock and data recovery (CDR) circuit can calculate the relative position of the sampled clock signal and the sampled data.
[0049] The third end of the trigger D1 is connected to the second end of the selector MUX0, the third end of the trigger D2 is connected to the first end of the selector MUX0, the third end of the trigger D3 is connected to the second end of the selector MUX2, the third end of the trigger D4 is connected to the first end of the selector MUX2, the third end of the trigger D5 is connected to the second end of the selector MUX1, the third end of the trigger D6 is connected to the first end of the selector MUX1, the third end of the trigger D7 is connected to the second end of the selector MUX3, the third end of the trigger D8 is connected to the first end of the selector MUX3; the third end of the selector MUX0 is connected to the first end of the trigger D9, and the trigger The second end of the trigger D9 is connected to the clock signal clk_0, the third end of the trigger D9 is connected to the fourth end of the selector MUX2, the fourth end of the selector MUX3 and the first end of the alignment circuit module 13, the third end of the selector MUX2 is connected to the first end of the trigger D10, the second end of the trigger D10 is connected to the clock signal clk_2, the third end of the trigger D10 is connected to the fourth end of the selector MUX0, the fourth end of the selector MUX1 and the second end of the alignment circuit module 13, the third end of the selector MUX1 is connected to the third end of the alignment circuit module 13, and the third end of the selector MUX3 is connected to the fourth end of the alignment circuit module 13.
[0050] Preferably, the trigger D1, the trigger D2, the trigger D3, the trigger D4, the trigger D5, the trigger D6, the trigger D7, the trigger D8, the trigger D9 and the trigger D10 are all D triggers, the first ends of the triggers are all data input ends of the D triggers, the second ends are all clock signal ends of the D triggers, and the third ends are all data output ends of the D triggers;
[0051] Selectors MUX0, MUX1, MUX2, and MUX3 are all dual-way selectors. The first ends of the above selectors are all data input ends selected by the high-level control signal of the dual-way selector, the second ends are all data input ends selected by the low-level control signal of the dual-way selector, the third ends are all data output ends of the dual-way selector, and the fourth ends are all control signal ends of the dual-way selector.
[0052] The output signal of trigger D9 is used as the selection signal of the selectors MUX2 and MUX3 of the next stage, and the output signal of trigger D10 is used as the selection signal of the selectors MUX0 and MUX1 of the next stage, and the sampled signal is judged and fed back to realize pre-emphasis. For example, see Figure 3When the data jumps, the current data d0 is low level, and the subsequent data d1 is high level, d0 controls the selector MUX2 of the next level to select dp_clk_2, that is, selects the pre-addition path signal to widen the subsequent high-level data d1; the current data d0 is high level, and the subsequent data d1 is low level, then d0 controls the selector MUX2 of the next level to select dm_clk_2, that is, selects the pre-reduction path signal to widen the subsequent low-level data d1;
[0053] When the data does not jump, the current data d0 is at a high level, and the subsequent data d1 is also at a high level, then d0 controls the selector MUX2 of the next level to select dm_clk_2, that is, the pre-reduction path signal. This signal widens the low level, and the total data width remains unchanged. Therefore, the width of the high level is synchronously compressed to achieve the narrowing of the subsequent high level data d1, and vice versa.
[0054] In this embodiment, the selector determines and feeds back the next data pre-emphasis path according to the current data result, completes pre-emphasis, adjusts the data width, and realizes balanced processing of data.
[0055] Exemplarily, the alignment circuit module 13 includes a trigger D11, a trigger D12, a trigger D13, a trigger D14, a trigger D15, a trigger D16, and a trigger D17;
[0056] The first end of the trigger D11 is connected to the third end of the decision feedback module 12, the second end of the trigger D11 is connected to the clock signal clk_2, the third end of the trigger D11 outputs the first data path, exemplarily, the first data path is even data, the first end of the trigger D12 is connected to the fourth end of the decision feedback module 12, the second end of the trigger D12 is connected to the clock signal clk_2, the third end of the trigger D12 outputs the second data path, exemplarily, the second data path is odd data, the first end of the trigger D13 is connected to the fifth end of the decision feedback module 12, the second end of the trigger D13 is connected to the clock signal clk_1, the first end of the trigger D13 is connected to the fifth end of the decision feedback module 12, the second end of the trigger D13 is connected to the clock signal clk_2, the third end of the trigger D13 is connected to the clock signal clk_1, The three terminals are connected to the first terminal of the trigger D14, the second terminal of the trigger D14 is connected to the clock signal clk_0, the third terminal of the trigger D14 is connected to the first terminal of the trigger D15, the second terminal of the trigger D15 is connected to the clock signal clk_2, the third terminal of the trigger D15 outputs the data edge of the first sampling, the first terminal of the trigger D16 is connected to the sixth terminal of the decision feedback module 12, the second terminal of the trigger D16 is connected to the clock signal clk_3, the third terminal of the trigger D16 is connected to the first terminal of the trigger D17, the second terminal of the trigger D17 is connected to the clock signal clk_2, and the third terminal of the trigger D17 outputs the data edge of the second sampling.
[0057] Preferably, trigger D11, trigger D12, trigger D13, trigger D14, trigger D15, trigger D16 and trigger D17 are all D triggers, and the first ends of the above triggers are all data input ends of the D triggers, the second ends are all clock signal ends of the D triggers, and the third ends are all data output ends of the D triggers.
[0058] The alignment circuit module 13 unifies the sampled data and the data along the clock domain and sends them to the subsequent CDR circuit.
[0059] See also Figure 5 The embodiment of the present invention further provides a deserialization circuit chip 2, which may include but is not limited to Figure 1 , 2 The decision feedback equalization circuit 1 in the corresponding embodiment.
[0060] See also Figure 6 The embodiment of the present invention further provides an electronic device 3, the electronic device 3 includes a serial circuit chip 31, a transmission medium 32 and Figure 5 Corresponding to the deserialization circuit chip 2 in the embodiment, the transmission medium 32 is disposed between the serialization circuit chip 31 and the deserialization circuit chip 2 .
[0061] A decision feedback equalization circuit, a deserialization circuit chip, and an electronic device provided by an embodiment of the present invention realize the pre-addition and pre-subtraction functions of the data width by performing OR operation processing on the original signal and the delayed signal of the input data from the time domain perspective, and selects its adjacent data for pre-addition or pre-subtraction according to the previous data, thereby pre-adjusting the adjacent data width. At the same time, adjusting the delay size of the pre-addition and pre-subtraction paths can adjust the gain of the decision feedback equalization circuit, and finally achieve equalization of the received data. The present invention pre-adjusts the data width in the time domain, and the gain is controllable, and finally achieves equalization. Compared with the traditional decision feedback equalization circuit, the implementation method is simpler, so the power consumption is lower and the area is smaller.
[0062] The above description is only a preferred embodiment of the present invention. Those skilled in the art should understand that the scope of disclosure involved in the present invention is not limited to the technical solution formed by a specific combination of the above technical features, but also should cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present invention (but not limited to) to form a technical solution.
Claims
1. A decision feedback equalization circuit, characterized in that: include: A time domain pre-emphasis generation module, a decision feedback module and an alignment circuit module; The first end of the time domain pre-emphasis generation module is connected to the forward differential signal, the second end of the time domain pre-emphasis generation module is connected to the reverse differential signal, the third end of the time domain pre-emphasis generation module is connected to the first end of the decision feedback module, the fourth end of the time domain pre-emphasis generation module is connected to the second end of the decision feedback module, the third end of the decision feedback module is connected to the first end of the alignment circuit module, the fourth end of the decision feedback module is connected to the second end of the alignment circuit module, the fifth end of the decision feedback module is connected to the third end of the alignment circuit module, and the sixth end of the decision feedback module is connected to the fourth end of the alignment circuit module; The time domain pre-emphasis generation module is configured to generate pre-emphasis in the time domain for the connected forward differential signal and the reverse differential signal, and the gain is controllable; the time domain pre-emphasis generation module includes a pre-addition path and a pre-reduction path, the pre-addition path performs an OR operation on the original signal and the delayed signal of the forward differential signal, widens the high level, and narrows the low level; the pre-reduction path performs an OR operation on the original signal and the delayed signal of the reverse differential signal, widens the low level, and narrows the high level; The decision feedback module is configured as a half-rate architecture, and adopts an inverted clock signal to sample the odd and even path data and their data edges respectively, and selects the pre-emphasis processing path of its adjacent data according to the signal of the previous data; the alignment circuit module is configured to align the sampled data and data edges to unify the clock domain.
2. A decision feedback equalization circuit according to claim 1, characterized in that: The time domain pre-emphasis generation module includes: a first buffer, a second buffer, a first delay unit, a second delay unit, a first OR gate, a third buffer, a fourth buffer, a fifth buffer, a third delay unit, a fourth delay unit, a second OR gate and an inverting buffer; The first end of the first buffer is connected to the first end of the first delay unit and connected to the positive differential signal, the second end of the first buffer is connected to the first end of the second buffer, the second end of the second buffer is connected to the first end of the first OR gate, the second end of the first delay unit is connected to the first end of the second delay unit, the second end of the second delay unit is connected to the second end of the first OR gate, the third end of the first OR gate is connected to the first end of the third buffer, and the second end of the third buffer is connected to the first end of the decision feedback module; The first end of the fourth buffer is connected to the first end of the third delay unit and is connected to the reverse differential signal, the second end of the fourth buffer is connected to the first end of the fifth buffer, the second end of the fifth buffer is connected to the first end of the second OR gate, the second end of the third delay unit is connected to the first end of the fourth delay unit, the second end of the fourth delay unit is connected to the second end of the second OR gate, the third end of the second OR gate is connected to the first end of the inverting buffer, and the second end of the inverting buffer is connected to the second end of the decision feedback module.
3. The decision feedback equalization circuit according to claim 1, characterized in that: The decision feedback module includes: a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a sixth trigger, a seventh trigger, an eighth trigger, a first selector, a second selector, a third selector, a fourth selector, a ninth trigger and a tenth trigger; The first end of the first trigger, the first end of the third trigger, the first end of the fifth trigger and the first end of the seventh trigger are all connected to the third end of the time domain pre-emphasis generation module, the first end of the second trigger, the first end of the fourth trigger, the first end of the sixth trigger and the first end of the eighth trigger are all connected to the fourth end of the time domain pre-emphasis generation module; the second end of the first trigger and the second end of the second trigger are both connected to the first clock signal, the second end of the third trigger and the second end of the fourth trigger are both connected to the third clock signal, the second end of the fifth trigger and the second end of the sixth trigger are both connected to the second clock signal, the second end of the seventh trigger and the second end of the eighth trigger are both connected to the fourth clock signal; the third end of the first trigger is connected to the second end of the first selector, the third end of the second trigger is connected to the first end of the first selector, the third end of the third trigger is connected to the second end of the third selector, and the The third end is connected to the first end of the third selector, the third end of the fifth trigger is connected to the second end of the second selector, the third end of the sixth trigger is connected to the first end of the second selector, the third end of the seventh trigger is connected to the second end of the fourth selector, and the third end of the eighth trigger is connected to the first end of the fourth selector; the third end of the first selector is connected to the first end of the ninth trigger, the second end of the ninth trigger is connected to the first clock signal, the third end of the ninth trigger is connected to the fourth end of the third selector, the fourth end of the fourth selector and the first end of the alignment circuit module, the third end of the third selector is connected to the first end of the tenth trigger, the second end of the tenth trigger is connected to the third clock signal, the third end of the tenth trigger is connected to the fourth end of the first selector, the fourth end of the second selector and the second end of the alignment circuit module, the third end of the second selector is connected to the third end of the alignment circuit module, and the third end of the fourth selector is connected to the fourth end of the alignment circuit.
4. The decision feedback equalization circuit according to claim 1, characterized in that: The alignment circuit comprises: an eleventh trigger, a twelfth trigger, a thirteenth trigger, a fourteenth trigger, a fifteenth trigger, a sixteenth trigger and a seventeenth trigger; The first end of the eleventh trigger is connected to the third end of the decision feedback module, the second end of the eleventh trigger is connected to the third clock signal, and the third end of the eleventh trigger outputs the first path of data. The first end of the twelfth trigger is connected to the fourth end of the decision feedback module, the second end of the twelfth trigger is connected to the third clock signal, and the third end of the twelfth trigger outputs the second path of sampled data. The first end of the thirteenth trigger is connected to the fifth end of the decision feedback module, the second end of the thirteenth trigger is connected to the second clock signal, the third end of the thirteenth trigger is connected to the first end of the fourteenth trigger, the second end of the fourteenth trigger is connected to the first clock signal, the third end of the fourteenth trigger is connected to the first end of the fifteenth trigger, the second end of the fifteenth trigger is connected to the third clock signal, and the third end of the fifteenth trigger outputs the first path of sampled data edge. The first end of the sixteenth trigger is connected to the sixth end of the decision feedback module, the second end of the sixteenth trigger is connected to the fourth clock signal, the third end of the sixteenth trigger is connected to the first end of the seventeenth trigger, the second end of the seventeenth trigger is connected to the third clock signal, and the third end of the seventeenth trigger outputs the second path of sampled data edge.
5. The decision feedback equalization circuit according to claim 3, characterized in that: The first trigger, the second trigger, the third trigger, the fourth trigger, the fifth trigger, the sixth trigger, the seventh trigger, the eighth trigger, the ninth trigger and the tenth trigger are all D triggers, and the first ends of the first trigger, the second trigger, the third trigger, the fourth trigger, the fifth trigger, the sixth trigger, the seventh trigger, the eighth trigger, the ninth trigger and the tenth trigger are all data input ends of the D trigger, the second ends are all clock signal ends of the D trigger, and the third ends are all data output ends of the D trigger; The first selector, the second selector, the third selector and the fourth selector are all dual-way data selectors, and the first ends of the first selector, the second selector, the third selector and the fourth selector are all data input ends selected by the control signal high level, the second ends are all data input ends selected by the control signal low level, the third ends are all data output ends, and the fourth ends are all control signal ends.
6. A decision feedback equalization circuit according to claim 4, characterized in that: The eleventh flip-flop, the twelfth flip-flop, the thirteenth flip-flop, the fourteenth flip-flop, the fifteenth flip-flop, the sixteenth flip-flop and the seventeenth flip-flop are all D flip-flops, and the first ends of the eleventh flip-flop, the twelfth flip-flop, the thirteenth flip-flop, the fourteenth flip-flop, the fifteenth flip-flop, the sixteenth flip-flop and the seventeenth flip-flop are all data input ends of the D flip-flop, the second ends are all clock signal ends of the D flip-flop, and the third ends are all data output ends of the D flip-flop.
7. A decision feedback equalization circuit according to claim 3 or 4, characterized in that: The first clock signal, the second clock signal, the third clock signal and the fourth clock signal are sampling clocks with equal phase difference, and the phase difference is 90 degrees.
8. A deserialization circuit chip, characterized in that: The deserialization circuit chip comprises the decision feedback equalization circuit as described in any one of claims 1 to 7.
9. An electronic device, characterized in that: The electronic device comprises a serial circuit chip, a transmission medium, and the deserialization circuit chip according to claim 8, wherein the transmission medium is arranged between the serial circuit chip and the deserialization circuit chip.
Citation Information
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