Signal processing method and device, electronic equipment and computer readable storage medium

Abstract

The embodiment of the invention provides a signal processing method and device, electronic equipment and a computer readable storage medium. The signal processing method comprises the following steps: caching a target signal in a preset system, and converting the target signal into symbol data; the preset system is one or more systems; generating a read address and a read enable corresponding to the symbol data on line; restoring the symbol data read from the cache into I-path read data and Q-path read data according to the read address and the read enable, and filtering the two-path read data according to the channel type to obtain filtered data; carrying out optimization processing on the filtering data to obtain a target baseband signal; caching the target baseband signal; and reading the cached data according to a set delay value, and then performing interface conversion and radio frequency (RF) processing. According to the scheme of the embodiment, multi-system fusion processing is realized, and the cost and the power consumption are reduced; the synchronization of the uplink signal and the uplink time delay are ensured to be the same under different sampling rates, MCS scheduling and bandwidth scenes.

Description

Technical Field

[0001] The present disclosure relates to the field of core networks, and particularly to a signal processing method, apparatus, electronic device, and computer-readable storage medium. Background Art

[0002] With the development of mobile communication technologies, using LTEA (Long-Term Evolution-Advanced) and NR (New Radio) for NSA (Non-Standalone) networking has become a widely used method in the 5G (5th Generation Mobile Communication Technology) networking mode. When a terminal device using the NSA networking mode performs OFDM (Orthogonal Frequency Division Multiplexing) signal modulation, it needs to support both the NR and LTEA systems simultaneously.

[0003] For OFDM modulated signals, in order to eliminate the inter-symbol interference and inter-carrier interference existing in OFDM, generally, a cyclic prefix is inserted into the signal after IFFT (Invert Fast Fourier Transformation) processing as a guard interval, and at the same time, additional windowing or filtering means are required to suppress out-of-band spectral leakage and smooth the inter-symbol phase discontinuity caused by the cyclic prefix. Summary of the Invention

[0004] Embodiments of the present disclosure provide a signal processing method, apparatus, electronic device, and computer-readable storage medium.

[0005] In a first aspect, embodiments of the present disclosure provide a signal processing method, which may include:

[0006] Buffering a target signal under a preset system, and converting the target signal into symbol data; the preset system is one or more systems;

[0007] Online generating a read address and a read enable corresponding to the symbol data in the buffer;

[0008] Restoring the symbol data read from the buffer into two readout data of the I channel and the Q channel according to the read address and the read enable, and performing corresponding filtering processing on the two readout data according to the channel types of the two readout data of the I channel and the Q channel to obtain filtered data;

[0009] Performing optimization processing on the filtered data to obtain a target baseband signal;

[0010] Buffering the target baseband signal;

[0011] After reading the cached data according to the set delay value, perform interface conversion and radio frequency (RF) processing on the read cached data.

[0012] In a second aspect, an embodiment of the present disclosure provides a signal processing device, including:

[0013] A first cache module, configured to cache a target signal in a preset format and convert the target signal into symbol data; the preset format is one or more formats;

[0014] A generation module, configured to online generate a read address and a read enable corresponding to the symbol data in the cache;

[0015] A filtering module, configured to restore the symbol data read from the cache to two readout data of an I channel and a Q channel according to the read address and the read enable, and perform corresponding filtering processing on the two readout data according to the channel type of the two readout data of the I channel and the Q channel to obtain filtered data;

[0016] An optimization module, configured to perform optimization processing on the filtered data to obtain a target baseband signal;

[0017] A second cache module, configured to cache the target baseband signal;

[0018] A processing module, configured to, after reading the cached data according to the set delay value, perform interface conversion and radio frequency (RF) processing on the read cached data.

[0019] In a third aspect, an embodiment of the present disclosure provides an electronic device, where the electronic device includes:

[0020] One or more processors;

[0021] A memory, on which one or more programs are stored. When the one or more programs are executed by the one or more processors, the one or more processors implement the signal processing method as described above;

[0022] One or more input / output (I / O) interfaces, connected between the processor and the memory, and configured to implement information interaction between the processor and the memory.

[0023] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the signal processing method as described above is implemented.

[0024] The preset mode in the embodiments of the present disclosure is one or more modes. By processing the target signal in the preset mode, the integration processing of multiple modes, such as NR and LTE-A, etc., is realized, reducing the implementation cost and system power consumption; by online generating the read address and read enable corresponding to the symbol data in the cache, the synchronization of the uplink signal is ensured; by caching the target baseband signal, it can ensure that the uplink delay is the same (absolute time) under various sampling rates, various MCS (Modulation and Coding Scheme) scheduling and bandwidth scenarios, and is convenient for fine-tuning the delay of each channel and carrier. Description of the Drawings

[0025] In the drawings of the embodiments of the present disclosure:

[0026] Figure 1 It is a structural block diagram of a general OFDM modulation system;

[0027] Figure 2 It is a flowchart of the signal processing method provided by the embodiments of the present disclosure;

[0028] Figure 3 It is a schematic diagram of the control flow of the read address and read enable provided by the embodiments of the present disclosure;

[0029] Figure 4 It is a schematic diagram of the HBF filter with 6 HBFs cascaded provided by the embodiments of the present disclosure;

[0030] Figure 5 It is a schematic diagram of 12 FIR units cascaded provided by the embodiments of the present disclosure;

[0031] Figure 6 It is a schematic diagram of the timing points of the first cache module and the second cache module provided by the embodiments of the present disclosure;

[0032] Figure 7 It is a block diagram of the signal processing device provided by the embodiments of the present disclosure;

[0033] Figure 8 It is a schematic structural diagram of the signal processing device provided by the embodiments of the present disclosure;

[0034] Figure 9 It is a block diagram of the composition of the electronic device provided by the embodiments of the present disclosure;

[0035] Figure 10 It is a block diagram of the composition of the computer-readable storage medium provided by the embodiments of the present disclosure. Detailed Embodiments

[0036] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the communication perception data processing method and computer-readable storage medium provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0037] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings. However, the illustrated embodiments may be embodied in different forms and the present disclosure should not be construed as limited to the embodiments set forth hereinafter. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0038] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification. They are used together with the detailed embodiments to explain the present disclosure, and do not constitute a limitation to the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

[0039] The present disclosure may be described with reference to the plan view and / or sectional view by means of the ideal schematic diagrams of the present disclosure. Therefore, the example illustrations may be modified according to the manufacturing technology and / or tolerances.

[0040] In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0041] The terms used in the present disclosure are only for describing specific embodiments and are not intended to limit the present disclosure. As used in the present disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used in the present disclosure, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. As used in the present disclosure, the terms "comprising", "made of...", specify the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used in the present disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless the present disclosure clearly so defines.

[0043] The present disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings have schematic properties, and the shapes of the regions shown in the figures illustrate the specific shapes of the regions of the elements, but are not intended to be restrictive.

[0044] With the development of mobile communication technology, it has become a widely used method in the 5G (5th generation mobile communication technology) networking mode to use LTEA (Long-Term Evolution-Advanced) and NR (NR: New Radio) for NSA (Non-Standalone) networking. When a terminal device using the NSA networking mode performs OFDM (Orthogonal Frequency Division Multiplexing) signal modulation, it needs to support both the NR and LTEA systems simultaneously.

[0045] For OFDM modulated signals, in order to eliminate the inter-symbol interference and inter-carrier interference existing in OFDM, generally a cyclic prefix is inserted into the signal after IFFT (Invert Fast Fourier Transformation) processing as a guard interval. At the same time, additional windowing or filtering means are needed to suppress out-of-band spectral leakage and smooth the inter-symbol phase discontinuity caused by the cyclic prefix.

[0046] The structural block diagram of a general OFDM modulation system in a communication system is as shown in the appendix Figure 1 As shown, the OFDM modulation system parallel-transmits serial data through multiple overlapping and mutually orthogonal sub-carriers, and uses IFFT to achieve the modulation of OFDM signals, with excellent fading suppression ability and high-frequency band resource utilization rate.

[0047] In view of the above background, the existing technical solutions mainly have the following problems:

[0048] 1. Implement the OFDM signal modulation process through software. This solution is simple to implement and highly flexible. However, the OFDM signal modulation process involves a large amount of data calculation, with a long operation time and a large amount of resource occupation, which will increase the implementation cost of the product.

[0049] 2. Implement the OFDM signal modulation process through hardware. Since there are many scenarios involved in different systems and the process control is complex and inconvenient to unify, most of the current hardening solutions separately implement their respective processing processes for each system to meet the requirements. The control is independent and convenient, but the implementation area is large, which is not conducive to reducing the equipment cost.

[0050] 3. Use a high-order filter for filtering during the OFDM signal modulation process to obtain good out-of-band performance. However, the implementation complexity of the high-order filter is high, and it cannot reduce the cost for multi-system terminal devices. Moreover, the working time of the filter is long. If the design is improper, it will introduce a large amount of power consumption and is not conducive to equipment energy conservation.

[0051] To overcome the problems in the related art, such as the complex OFDM signal modulation process and large implementation area in multiple systems, the embodiments of the present disclosure provide a signal processing method, such as a post-processing method for OFDM modulated signals, which can focus on implementing the post-processing process of OFDM modulated signals in current mainstream wireless communication systems at low cost and low power consumption.

[0052] In the solution of the embodiments of the present disclosure, the preset system is one or more systems. By processing the target signal under the preset system, the integrated processing of systems such as NR and LTE-A is realized, reducing the implementation cost and system power consumption; by online generating the read address and read enable corresponding to the symbol data in the cache, the synchronization of the uplink signal is ensured; by caching the target baseband signal, it is possible to ensure that the uplink delay is the same (absolute time) under various sampling rates, various MCS (Modulation and Coding Scheme) scheduling, and bandwidth scenarios, and it is convenient to finely adjust the delay of each channel and carrier.

[0053] The signal processing and sending method of the embodiments of the present disclosure can be executed by any electronic device that needs to perform similar signal processing, such as a terminal device or a server. The terminal device may include, but is not limited to: in-vehicle devices, user equipment (UE), mobile devices, computing devices, wearable devices, etc. For example, it includes, but is not limited to, cellular phones, cordless phones, personal digital assistants (PDAs), portable computers, etc. The USSD notification sending method can be implemented by the processor calling the computer-readable program instructions stored in the memory, or can be implemented by the server.

[0054] The signal processing and sending of the embodiments of the present disclosure can be applied to, but is not limited to, various wireless communication system-related products such as 4G (Fourth Generation Mobile Communication Technology), 5G, WiFi (Wireless Fidelity), NB-IoT (NR: New Radio, new wireless / new air interface; IoT: Internet of Things), V2X (V2X: Vehicle To Everything, vehicle's exchange of all external information).

[0055] The solution of the embodiments of the present disclosure can be used for an OFDM modulation device that supports both NR and LTE-A systems simultaneously, or can be used for OFDM modulation of a single NR or LTE-A, or the processes in the device of the solution of the embodiments of the present disclosure can be split, and some implementation solutions can be selected for the OFMD demodulation device.

[0056] The following details the solution of the embodiments of the present disclosure.

[0057] An embodiment of the present disclosure provides a signal processing method, as Figure 2 shown, the method includes steps S11 - S16:

[0058] S11. Cache the target signal under a preset modulation format and convert the target signal into symbol data; the preset modulation format is one or more modulation formats.

[0059] In the embodiment of the present disclosure, the preset modulation format may include, but is not limited to: New Radio (NR) modulation format and / or Long Term Evolution - Advanced (LTE - A) modulation format. The target signal may include, but is not limited to: an Orthogonal Frequency Division Multiplexing (OFDM) modulation signal obtained by performing Inverse Fast Fourier Transform (IFFT) processing;

[0060] In the embodiment of the present disclosure, converting the target signal under the preset modulation format into symbol data and caching the symbol data includes:

[0061] Performing IFFT processing on the OFDM modulation signal to obtain symbol data;

[0062] Symbol data of different modulation formats are cached in the same first cache module in a time - division multiplexing manner, and ping - pong storage is performed on the symbol data.

[0063] In the embodiment of the present disclosure, the first cache module can be used to store the symbol data obtained by performing IFFT processing on the OFDM modulation signal of the NR or LTE - A modulation format, and the first cache module can be reused under multiple modulation formats. When writing the OFDM modulation signal into the first cache module, such as a Random Access Memory (RAM), two sets of RAM can be used to perform ping - pong caching by symbol to prepare for subsequent online windowing.

[0064] S12. Online generate a read address and a read enable corresponding to the symbol data in the cache.

[0065] In the embodiment of the present disclosure, online generating a read address and a read enable corresponding to the symbol data in the cache includes:

[0066] Online add a Cyclic Prefix (CP) to the symbol data and adjust the Timing Advance (TA) in the cache;

[0067] Generate a read address and a read enable corresponding to the symbol data after adding CP and adjusting TA based on the control scenario.

[0068] In the embodiments of the present disclosure, a read address corresponding to symbol data after adding CP (Cyclic Prefix) and adjusting TA (Timing Advance) for NR or LTE-A is generated online, and a corresponding read enable is generated according to a set read start time. When adding a cyclic prefix, in order to maintain uplink synchronization, the TA adjustment value also needs to be considered. Considering the uplink TA adjustment, the hardware processing delay needs to be consistent in different control scenarios (or scheduling scenarios). The solution of the embodiments of the present disclosure can adjust the transmission start time of the baseband signal in the second cache module (introduced in the following content), and flexibly adjust the read start time of the first cache module according to different control scenarios of different systems to adapt thereto, so as to reduce the RAM area cost of the second cache module.

[0069] In the embodiments of the present disclosure, as Figure 3 shown, generating a read address and a read enable corresponding to symbol data after adding CP and TA adjustment based on a control scenario may include:

[0070] Obtaining scenario parameters of a control scenario; the scenario parameters may include but are not limited to: address parameters, time parameters, and symbol length parameters;

[0071] Generating a read start address according to the address parameters, generating a read start time according to the time parameters, and generating a symbol length threshold according to the symbol length parameters;

[0072] Starting a preset symbol length counter according to the read start time and the symbol length threshold, and generating a read address according to the read start address and the count of the symbol length counter;

[0073] Generating a read enable according to the read start time and the symbol length threshold.

[0074] In the embodiments of the present disclosure, as Figure 3 shown, the address parameters may include but are not limited to any one or more of the following: system, sampling rate, subcarrier spacing, channel type, symbol position, and TA adjustment value;

[0075] The time parameters may include but are not limited to any one or more of the following: system, sampling rate, subcarrier spacing, and channel type;

[0076] The symbol length parameters may include but are not limited to any one or more of the following: system, sampling rate, subcarrier spacing, channel type, symbol position, and TA adjustment value.

[0077] In the embodiments of the present disclosure, when generating a read address and a read enable, the results corresponding to parameters such as different formats, sampling rates, channel types, and TA adjustment values are different, and there are many control scenarios involved. If the enumeration method is used, the control is complex and it is easy to miss or make mistakes. Therefore, in the embodiments of the present application, the influence of each parameter on the read address and the read enable is represented by different variable factors, and the read address and the read enable are generated by combining the variable factors, which can significantly reduce the implementation complexity.

[0078] In the embodiments of the present disclosure, according to the attached Figure 3 As shown in the schematic diagram of the control flow of the read address and the read enable, first, various parameters required for calculating the read address and the read enable are obtained through software configuration, such as format, sampling rate, subcarrier spacing, channel type, symbol position, TA adjustment value, etc. Then, different variable factors (for example, address parameters, time parameters, and symbol length parameters, etc.) are obtained based on the influence of various parameters on the read address and the read enable. The read start address, the read start time, and the symbol length threshold are obtained by combining the variable factors. Then, the symbol length counter is started to accumulate based on the read start time and the symbol length threshold, and the read enable is generated. Finally, the read start address is combined with the symbol length counter to online generate the read address of the corresponding symbol data.

[0079] S13. Restore the symbol data read from the buffer into two readout data of the I channel and the Q channel according to the read address and the read enable, and perform corresponding filtering processing on the two readout data according to the channel types of the I channel and the Q channel to obtain filtered data.

[0080] In the embodiments of the present disclosure, performing corresponding filtering processing on the two readout data of the I channel and the Q channel according to the channel types of the two readout data to obtain filtered data may include:

[0081] When the channel type is a PRACH (Physical Random Access Channel) channel, upsampling filtering is performed on the readout data using a cascaded low-order filter; the low-order filter refers to a filter whose filtering order is less than a preset order threshold;

[0082] When the channel type is not a PRACH channel, windowing and finite impulse response FIR filtering are performed on the readout data.

[0083] In the embodiments of the present disclosure, after sequentially and cyclically reading data from the first buffer module according to the read address and the read enable, the data is restored into I / Q two-channel data to obtain two readout data, and then different subsequent processes are selected according to the channel type.

[0084] In the embodiments of the present disclosure, if the channel type is a PRACH channel, the data is upsampled and filtered using a cascaded low-order filter. If the channel type is not a PRACH channel, windowing or FIR (Finite Impulse Response) filtering is performed. Another equivalent implementation scheme can use a buffer to offline store the symbol data corresponding to the cyclic prefix and TA adjustment value to be added, and then splice it with the valid symbol data. The disadvantage of this scheme is that it introduces multiple buffer units, increasing the design area.

[0085] In the embodiments of the present disclosure, upsampling and filtering the read symbol data using a cascaded low-order filter includes:

[0086] For the long code of the PRACH channel, perform IFFT transformation according to the original sampling points of the PRACH sequence in the PRACH channel to obtain the transformation result;

[0087] Use a cascaded low-order filter to upsample the transformation result to the sampling points corresponding to the long code for filtering.

[0088] In the embodiments of the present disclosure, the low-order filter may include, but is not limited to, an HBF (Half Band Filter).

[0089] In the embodiments of the present disclosure, cascaded HBF upsampling filtering can be performed on some PRACH scenarios to generate PRACH preambles and suppress out-of-band leakage, and the remaining PRACH scenarios and non-PRACH scenarios that do not require upsampling are bypassed (i.e., no longer filtered).

[0090] In the embodiments of the present disclosure, for the PRACH long code, the length of its preamble SEQ (sequence) is relatively long, and theoretically, the required number of IFFT points is also large. For example, at a data sampling rate of 30.72 MHz (megahertz), the non-repeating SEQ lengths of PRACH formats 0 to 2 are 24576, and at this time, the theoretical number of IFFT points is 24576. Directly implementing an IFFT with such a large number of points (24576) consumes too much resources, and when the sampling rate increases, the SEQ length also becomes correspondingly longer. To solve this problem, the solution in the embodiments of the present disclosure uses a method of first performing an IFFT with a small number of points (such as 1536), then upsampling the IFFT transformation result to the corresponding number of points (24576) and then performing filtering.

[0091] In the embodiments of the present disclosure, for scenarios where a relatively high upsampling multiple is to be achieved, the solution of the embodiments of the present disclosure uses a cascaded low-order filter method, which can greatly reduce the order of the filter and also reduce power consumption. The upsampling multiple used in the cascading process of the solution of the embodiments of the present disclosure is 2. Therefore, an HBF half-band filter can be used, and this structure can further save resources. Another equivalent implementation solution can also complete upsampling once when reading data from the first cache module and then perform FIR filtering, or perform FIR filtering after multiple upsamplings. However, this solution requires a larger filter order, has a high implementation cost, and also has a large power consumption.

[0092] In the embodiments of the present disclosure, based on the above description, the embodiments of the present disclosure can support 2 N times upsampling through the cascading of N (N is a positive integer) HBFs. Each stage of HBF supports bypass. When the number of cascaded stages is less than N, the required number of cascaded HBF stages is preferentially enabled from front to back, and the remaining ones are bypassed. When upsampling is not performed, all are bypassed. The hardware structure of each stage of HBF remains consistent at different sampling rates to flexibly support different upsampling multiple requirements. Taking the cascading of 6 HBFs (such as HBF0, HBF1, HBF2, HBF3, HBF4, HBF5) as an example, it supports a maximum upsampling multiple of 64, and the corresponding implementation structure is as Figure 4 shown.

[0093] In the embodiments of the present disclosure, the clock of the cascaded low-order filter includes two levels of gating; the two levels of gating may include: overall gating of the cascaded low-order filter and gating of each stage of the low-order filter; among them, the clock of each stage of the low-order filter can be turned on only when each stage of the low-order filter is enabled.

[0094] In the embodiments of the present disclosure, for example, there are two levels of clock gating for power consumption reduction in the cascaded HBF filter. The first level is the gating of the entire cascaded HBF, and the second level is the gating of each stage of HBF. The actual working clk (clock) is valid only when the corresponding stage of HBF is enabled.

[0095] In the embodiments of the present disclosure, each stage of the cascaded low-order filter uses multiple phases.

[0096] In the embodiments of the present disclosure, for example, to save area and power consumption, each stage of HBF adopts a multi-phase implementation solution, and the solution of the embodiments of the present disclosure is set to two phases.

[0097] In the embodiments of the present disclosure, before windowing and / or finite impulse response FIR filtering of the read data, the method may further include:

[0098] Set the FIR unit in advance based on the number of multiply-accumulate operations that can be performed in the next sampling period at the highest data sampling rate.

[0099] Cascade multiple FIR units to obtain a FIR filter with configurable order.

[0100] Obtain the target FIR filter of the corresponding order by controlling the number of FIR units in the enabled FIR filter; among them, the target FIR filter of any achievable order in the FIR filter can be reused.

[0101] In the embodiments of the present disclosure, out-of-band leakage of the transmitted signal can be suppressed by any one or a combination of two of windowing and FIR (Finite Impulse Response) filtering.

[0102] In the embodiments of the present disclosure, due to the insertion of CP between adjacent OFDM symbol data, the phase is discontinuous and there is a phase jump between symbols. Windowing or filtering is required to smooth the transition between symbol data and suppress out-of-band leakage of the transmitted signal. At different data sampling rates, the window length supports different lengths and windowing bypass is supported.

[0103] In the embodiments of the present disclosure, the process of windowing mainly uses a section of cosine-like function (-π to 0) to achieve the "slow rise" of data, and another section of cosine-like function (0 to π) to achieve the "slow fall" of data, so as to achieve the filtering effect.

[0104] In the embodiments of the present disclosure, a scheme that supports both windowing and filtering is supported to reduce the order of the FIR filter. The filtering order can be configured according to different frequency ranges and different sampling rates, and filtering bypass is also supported.

[0105] In the embodiments of the present disclosure, when the filter is implemented, the data is processed online. The solution of the embodiments of the present disclosure uses a fixed working clock frequency in different scenarios to reduce the implementation cost. The multiply-accumulate operation of the filter is performed according to the number of working clocks included in 1Ts (i.e., one sampling period, the actual sampling rate) at different sampling rates, and the data shift is in units of Ts. In order to have a unified hardware implementation scheme at different data sampling rates, the solution of the actual example of the present disclosure is based on the number of multiply-accumulate operations that can be performed in 1Ts at the highest data sampling rate, and sets a filtering granule FIR Group (i.e., the aforementioned FIR unit). Different orders call different numbers of FIR Groups for cascading to maximize the reuse of hardware resources, facilitate unified control, simplify the control logic, and reduce the overall area of the filtering part.

[0106] In the embodiments of the present disclosure, the clock of the FIR filter includes two levels of gating;

[0107] The two - level gating includes: gating of the FIR filter and gating of each FIR unit;

[0108] Among them, the clock of the FIR unit can only be enabled when the corresponding FIR unit is enabled.

[0109] In the embodiment of the present disclosure, to further reduce the system power consumption, the clock of the filtering part is two - level gated in the embodiment of the present disclosure. The first level is the gating of the entire FIR, and the second level is the gating of the FIR Group. The clock of the filtering particle is only enabled when the corresponding FIRGroup is enabled, and within the FIR Group, the shift and multiply - accumulate operations are performed only under the enable signal with the actual working clk (clock) pulled high, so that the power consumption can be greatly reduced.

[0110] In the embodiment of the present disclosure, a set of hardware structures can be used to flexibly support different filter orders to adapt to the order requirements of different scenarios. For example, the device uses multiple FIR Groups in cascade to implement FIR filtering, and uses multiple mux (multiplexers) to call different numbers of FIR Groups to adapt to different orders. For example, taking 12 FIR Groups and 5 muxes as an example for illustration, that is, the FIR filter includes 12 FIR Groups and 5 muxes, and the corresponding cascade implementation structure is as follows Figure 5 shown, which includes 12 FIR Groups as FIR Group0, FIR Group1, FIR Group2, FIR Group3, FIR Group4, FIRGroup5, FIR Group6, FIR Group7, FIR Group8, FIR Group9, FIR Group10, FIR Group11, and includes 5 muxes as mux0, mux1, mux2, mux3, mux4. mux0 can be connected to the D - type flip - flop, and each FIR Group can be connected to the adder.

[0111] In the embodiment of the present disclosure, if you want to work at the maximum order, then enable 12 FIR Groups, and the input data is poured into from FIR Group0. If you want to work at a low order, then preferentially enable the required number of cascaded FIR Groups from back to front, and use the mux to pour the input data into the first FIR Group of the corresponding order.

[0112] In the embodiment of the present disclosure, performing finite - impulse - response (FIR) filtering on the read - out data may include:

[0113] Determining the filter order required for the read - out data;

[0114] Start the target FIR filter of the corresponding order from the FIR filter according to the required filtering order, and filter the read data.

[0115] In the embodiments of the present disclosure, on the basis of obtaining the above FIR filter, the order of the filter can be configured according to requirements to obtain the target FIR filter, and after determining the order, it is only necessary to input data from the first FIR Group of the corresponding mux of the filter of the corresponding order.

[0116] In the embodiments of the present disclosure, the above filtering order can be obtained through the input filtering order-related parameters.

[0117] S14. Optimize the filtered data to obtain the target baseband signal.

[0118] In the embodiments of the present disclosure, the optimization process may include but is not limited to:

[0119] Selectively perform power ramp-up and roll-off processing on continuous filtered data; and / or,

[0120] Compensate the phase and frequency of the filtered data.

[0121] In the embodiments of the present disclosure, in addition to windowing, in order to suppress out-of-band leakage of the transmitted signal, power ramp-up and roll-off processing may also be optionally supported at the head and tail of a continuous transmission, that is, scale (ramp up) a section of data sampling, forming a process in which the amplitude of the transmitted signal gradually increases at the head and gradually decreases at the tail.

[0122] In the embodiments of the present disclosure, phase and frequency offsets during the operation of the device may also be compensated. The solution of the embodiments of the present disclosure can be compensated online by calling multiple sets of CORDIC (Coordinate rotation digital computer) units for parallel processing, which can reduce the design complexity and logical area.

[0123] In the embodiments of the present disclosure, power ramp-up and roll-off processing can be performed first, and then phase and frequency compensation can be performed.

[0124] S15. Cache the target baseband signal.

[0125] In the embodiments of the present disclosure, the generated target baseband signal (for example, OFDM baseband signal) can be stored using the second cache module.

[0126] In the embodiments of the present disclosure, based on the foregoing first cache module and adding the second cache module, the solution of the embodiments of the present disclosure provides two cache modules. The main function of the two cache modules is considered in the case of uplink TA adjustment, where the hardware processing delay needs to be consistent under different subcarrier spacings, different sampling rates, and different scheduling schemes to ensure that the receiving end can receive the corresponding signal within a fixed time window. However, when generating the target baseband signal, the processing delays of each step are different. If the processing delays of each step are fixed, then each step needs to be controlled according to the actual control scenarios of different systems, and the hardware control logic will be relatively complex and not easy to transplant. Therefore, the solution of the embodiments of the present disclosure uses a unified cache module to adjust the read start time ① of the post-processing flow of the OFDM modulation signal (adjusted by the first cache module) and the transmission start time point ② of the target baseband signal (adjusted by the second cache module).

[0127] In the embodiments of the present disclosure, on the one hand, the second cache module ensures that the uplink delay is the same (absolute time) under each sampling rate, each MCS scheduling, and bandwidth scenario, and on the other hand, it is considered that fine-tuning of the delay for each channel and carrier may be required.

[0128] In the embodiments of the present disclosure, as Figure 6 shown, it is a timing point schematic diagram of two cache modules (the first cache module and the second cache module). Since the read start time ① unifies the processing delay before the first cache module, the maximum time difference corresponding to the transmission time of the transmission start time point ② is at most the processing delay of the subsequent process of the read start time ①. On this basis, adding the channel delay can obtain the depth of the second cache module, and there is no need to cache data of the entire symbol length, thereby reducing the area of the cache module. Moreover, in the case of a small bandwidth, low sampling rate scenario or a multi-stage HBF cascade scenario, the processing delay of the filter is very large, but the delay of the process before the read start time ① (such as channel coding and IFFT processing, etc.) is small. By adjusting the read start time ① forward, part of the processing delay of the filter can be absorbed, so that the depth of the second cache module can be further reduced.

[0129] S16. Read the cached data according to the set delay value, and then perform interface conversion and radio frequency (RF) processing on the read cached data.

[0130] In the embodiments of the present disclosure, after the processing of the above-mentioned various processes, the final target OFDM baseband signal is generated. Then, the data is read out from the second cache module at a fixed time according to the set delay value, and finally transmitted by the antenna after interface conversion and RF (Radio Frequency) processing.

[0131] The embodiments of the present disclosure also provide a signal processing device 100, as Figure 7 shown, including:

[0132] The first cache module 101 is used to cache the target signal under a preset modulation format and convert the target signal into symbol data; the preset modulation format is one or more modulation formats;

[0133] The generation module 102 is used to generate the read address and read enable corresponding to the symbol data online in the cache;

[0134] The filtering module 103 is used to restore the symbol data read from the cache into two readout data of the I channel and the Q channel according to the read address and the read enable, and perform corresponding filtering processing on the two readout data according to the channel types of the I channel and the Q channel to obtain filtered data;

[0135] The optimization module 104 is used to perform optimization processing on the filtered data to obtain the target baseband signal;

[0136] The second cache module 105 is used to cache the target baseband signal;

[0137] The processing module 106 is used to read out the cache data according to the set delay value and perform interface conversion and radio frequency (RF) processing on the read cache data.

[0138] In the embodiment of the present disclosure, as Figure 8 shown, the generation module 102 can implement read address logic control. The filtering module 103 can perform cascaded HBF upsampling filtering on the readout data in the PRACH channel, and perform windowing and / or FIR filtering on non-PRACH channels or PRACH scenarios that do not require upsampling.

[0139] In the embodiment of the present disclosure, the optimization module 104 may include a power ramp and roll-off processing unit 1041, and may further include a compensation unit 1042. The power ramp and roll-off processing unit 1041 can implement power ramp and roll-off processing, and the compensation unit 1042 can implement compensation for the phase and frequency of the filtered data.

[0140] In the embodiment of the present disclosure, the processing module 106 may include an interface conversion unit 1061 and an RF unit 1062.

[0141] The solution of the embodiment of the present disclosure has at least the following advantages:

[0142] 1. The solution of the embodiment of the present disclosure realizes the fusion of the post-processing of OFDM modulation signals in the NR and LTE-A systems. The hardware structure of the entire signal processing device remains the same in different scheduling scenarios, which is convenient for unified control, can reduce the complexity of the control logic in each scenario after fusion, and some processing flows support the bypass function, so as to maximize the reuse of the post-processing flows of OFDM modulation signals in different systems. Overall, it can significantly reduce the implementation area of the system and the overall chip area cost.

[0143] 2. For the filtering process involved in OFDM post-processing, the large-order filter is split into a cascade of small-order filters by using a fixed clock frequency point for scenario-level reuse, which can flexibly support the different order requirements of each system. For example, both the HBF upsampling filter and the FIR filter in the solution of this embodiment are implemented by cascading small-order filters. At the same time, multi-level gating is adopted to perform refined clock gating on each filter to reduce power consumption, and the cascaded HBF scheme is appropriately used based on the scenario to replace the ordinary FIR implementation scheme.

[0144] 3. Operations such as adding OFDM cyclic prefix and TA adjustment are performed in an online manner.

[0145] 4. A smaller cache module is used to realize the timed output of the OFDM modulation signal after out-of-band suppression processing, and two cache modules (the first cache module and the second cache module) are used to control the timed reading and output of the OFDM modulation signal, ensuring the group delay stability of the transmission link in different systems and different scheduling scenarios, and ensuring that the receiving end can receive the corresponding signal within a fixed time window.

[0146] The embodiment of the present disclosure also provides an electronic device 200, as Figure 9 shown, the electronic device 200 includes:

[0147] One or more processors 201;

[0148] A memory 202, on which one or more programs are stored. When the one or more programs are executed by the one or more processors 201, the one or more processors 201 implement the signal processing method described above;

[0149] One or more input / output I / O interfaces 203, connected between the processor 201 and the memory 202, configured to realize the information interaction between the processor 201 and the memory 202.

[0150] Among them, the processor 201 is a device with data processing capabilities, including but not limited to a central processing unit (CPU), etc.; the memory 202 is a device with data storage capabilities, including but not limited to a random access memory (RAM, more specifically such as SDRAM, DDR, etc.), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), and a flash memory (FLASH); the I / O interface (read / write interface) 203 is connected between the processor 201 and the memory 202 and can realize the information interaction between the processor 201 and the memory 202, including but not limited to a data bus (Bus), etc.

[0151] In some embodiments, the processor 201, the memory 202, and the I / O interface 203 are interconnected through a bus 204 and are further connected to other components of the computing device.

[0152] The embodiment of the present disclosure also provides a computer-readable storage medium 300, such as Figure 10 As shown, a computer program is stored on the computer-readable storage medium 300, and when the computer program is executed by the processor, the signal processing method described above is implemented.

[0153] Those of ordinary skill in the art can understand that all or some of the function modules / units disclosed above can be implemented as software, firmware, hardware, and their appropriate combinations.

[0154] In the hardware implementation, the division between the function modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component can have multiple functions, or a function or step can be executed by several physical components in cooperation.

[0155] Some or all of the physical components may be implemented as software executed by a processor such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory (FLASH), or other magnetic disk storage; compact disc read only memory (CD-ROM), digital versatile disc (DVD), or other optical disc storage; magnetic cassettes, tapes, magnetic disk storage, or other magnetic storage; and any other medium that can be used to store the desired information and that can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically embody computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery media.

[0156] The present disclosure has disclosed example embodiments, and although specific terms have been employed, they are used only and should be interpreted only as of a general illustrative meaning and not for a limiting purpose. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly stated. Accordingly, those skilled in the art will understand that various forms and details may be changed without departing from the scope of the present disclosure as set forth by the appended claims.

Claims

1. A signal processing method, characterized in that, the method includes: Converting a target signal under a preset format into symbol data and caching the symbol data; the preset format is one or more formats; Online generating a read address and a read enable corresponding to the symbol data in the cache; Restoring the symbol data read from the cache to two readout data of an I channel and a Q channel according to the read address and the read enable, and performing corresponding filtering processing on the two readout data according to the channel types of the I channel and the Q channel to obtain filtered data; Performing optimization processing on the filtered data to obtain a target baseband signal; Caching the target baseband signal; Reading the cached data according to a set delay value and performing interface conversion and radio frequency (RF) processing on the read cached data.

2. The signal processing method according to claim 1, characterized in that, the target signal includes: an orthogonal frequency division multiplexing (OFDM) modulation signal; The converting the target signal under a preset format into symbol data and caching the symbol data includes: Performing inverse fast Fourier transform (IFFT) processing on the OFDM modulation signal to obtain the symbol data; The symbol data of different formats are cached in the same first cache module in a time-division multiplexing manner, and ping-pong storage is performed on the symbol data.

3. The signal processing method according to claim 1, characterized in that, The online generating a read address and a read enable corresponding to the symbol data in the cache includes: Online adding a cyclic prefix (CP) to the symbol data and adjusting the timing advance (TA) in the cache; Generating the read address and the read enable corresponding to the symbol data after adding CP and adjusting TA based on a control scenario.

4. The signal processing method according to claim 3, characterized in that, The generating the read address and the read enable corresponding to the symbol data after adding CP and adjusting TA based on a control scenario includes: Obtaining the scenario parameters of the control scenario; the scenario parameters include: address parameters, time parameters, and symbol length parameters; Generating a read start address according to the address parameters, generating a read start time according to the time parameters, and generating a symbol length threshold according to the symbol length parameters; Starting a preset symbol length counter according to the read start time and the symbol length threshold, and generating the read address according to the read start address and the count of the symbol length counter; Generating the read enable according to the read start time and the symbol length threshold.

5. The signal processing method according to claim 4, characterized in that, the address parameters include any one or more of the following: the format, sampling rate, subcarrier spacing, channel type, symbol position, and TA adjustment value; the time parameters include any one or more of the following: the format, the sampling rate, the subcarrier spacing, and the channel type; the symbol length parameters include any one or more of the following: the format, the sampling rate, the subcarrier spacing, the channel type, the symbol position, and the TA adjustment value.

6. The signal processing method according to claim 1, characterized in that, Performing corresponding filtering processing on the read data of the two channels according to the channel type of the I-channel and Q-channel to obtain filtered data, including: In the case where the channel type is a Physical Random Access Channel (PRACH), upsampling filtering is performed on the read data using a cascaded low-order filter; the low-order filter refers to a filter whose filtering order is less than a preset order threshold; In the case where the channel type is not a PRACH, windowing and Finite Impulse Response (FIR) filtering are performed on the read data.

7. The signal processing method according to claim 6, characterized in that, The upsampling filtering of the read symbol data using a cascaded low-order filter includes: For the long code of the PRACH channel, performing Inverse Fast Fourier Transform (IFFT) according to the original sampling points of the PRACH sequence in the PRACH channel to obtain a transformation result; Using the cascaded low-order filter to upsample the transformation result to the sampling points corresponding to the long code for filtering.

8. The signal processing method according to claim 6 or 7, characterized in that, The low-order filter includes: a Half-Band Filter (HBF); Each stage of the cascaded low-order filter uses multiple phases; and / or, The clock of the cascaded low-order filter includes two-stage gating; the two-stage gating includes: overall gating of the cascaded low-order filter and gating of each stage of the low-order filter; wherein, the clock of each stage of the low-order filter can only be enabled when each stage of the low-order filter is enabled.

9. The signal processing method according to claim 6, characterized in that, Before performing windowing and / or Finite Impulse Response (FIR) filtering on the read data, the method further includes: Pre-setting FIR units based on the number of multiply-accumulate operations that can be performed in one sampling period at the highest data sampling rate; Cascading multiple of the FIR units to obtain a FIR filter with configurable order; Obtaining a target FIR filter of the corresponding order by controlling the enabling of the number of FIR units in the FIR filter; wherein, the target FIR filter of any achievable order in the FIR filter can be reused.

10. The signal processing method according to claim 9, characterized in that, The clock of the FIR filter includes two-stage gating; The two-stage gating includes: gating of the FIR filter and gating of each FIR unit; wherein, the clock of the FIR unit can only be enabled when the corresponding FIR unit is enabled.

11. The signal processing method according to claim 9 or 10, characterized in that, Performing Finite Impulse Response (FIR) filtering on the read data includes: Determining the required filtering order of the read data; Starting a target FIR filter of the corresponding order from the FIR filter according to the required filtering order to filter the read data.

12. The signal processing method according to claim 1, characterized in that, The optimization processing includes: Selectively perform power ramping and roll-off processing on the continuous filtered data; and / or, Compensate for the phase and frequency of the filtered data.

13. A signal processing device, Characterized in that, It includes: A first cache module for caching a target signal under a preset format and converting the target signal into symbol data; The preset format is one or more formats; A generation module for online generating a read address and a read enable corresponding to the symbol data in the cache; A filtering module for restoring the symbol data read from the cache into two readout data of an I channel and a Q channel according to the read address and the read enable, and performing corresponding filtering processing on the two readout data according to the channel type of the two readout data of the I channel and the Q channel to obtain filtered data; An optimization module for performing optimization processing on the filtered data to obtain a target baseband signal; A second cache module for caching the target baseband signal; A processing module for performing interface conversion and radio frequency (RF) processing on the cached data read out according to a set delay value.

14. An electronic device, Characterized in that, The electronic device includes: One or more processors; A memory having one or more programs stored thereon, when the one or more programs are executed by the one or more processors, enabling the one or more processors to implement the signal processing method according to any one of claims 1-12; One or more input / output (I / O) interfaces connected between the processor and the memory and configured to implement information interaction between the processor and the memory.

15. A computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, implementing the signal processing method according to any one of claims 1-12.

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