A transfer plate structure and preparation method thereof, a packaging structure and preparation method thereof

Abstract

The present disclosure provides an adapter plate structure and a preparation method thereof, a packaging structure and a preparation method thereof, wherein the adapter plate structure includes a first sub-adapter plate structure and a second sub-adapter plate structure electrically connected along a first direction; the first sub-adapter plate structure includes a first groove and a plurality of first conductive pillars, and the second sub-adapter plate structure includes a second groove and a plurality of second conductive pillars; an opening direction of the first groove is arranged opposite to an opening direction of the second groove, and at least one first conductive pillar and at least one second conductive pillar are electrically connected one-to-one.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a transfer plate structure and a preparation method thereof, a packaging structure and a preparation method thereof. Background Art

[0002] With the continuous advancement of semiconductor processes and technologies, chips and electronic products are developing in the direction of miniaturization, high density, and high performance. Integrating chips with higher performance and more functions in a limited area has become an inevitable trend. At the same time, as the development of Moore's Law gradually slows down, chip stacking and packaging technology can not only make up for the limitations of the slowdown of Moore's Law to a certain extent, but also show significant advantages in some aspects. Therefore, the position of chip stacking and packaging technology in the electronic product industry chain is becoming more and more important.

[0003] At present, most of the through silicon via (TSV) adapters are vertically interconnected, using TSV adapters to form 2.5D packaging, encapsulating the chip on the TSV adapter, and using the redistribution layer on the TSV adapter for interconnection. However, in related technologies, 2.5D packaging is to lay the chip flat on the same large-sized TSV adapter, which makes it difficult to achieve a multi-layer chip stacking structure, resulting in high difficulty in preparing the adapter structure, low yield, large occupied area, low integration, and high cost. Summary of the invention

[0004] Embodiments of the present disclosure provide a transfer plate structure and a method for preparing the same, and a packaging structure and a method for preparing the same.

[0005] In a first aspect, an embodiment of the present disclosure provides an adapter plate structure, the adapter plate structure comprising a first sub-adapter plate structure and a second sub-adapter plate structure electrically connected along a first direction;

[0006] The first sub-adapter board structure includes a first groove and multiple first conductive pillars, and the second sub-adapter board structure includes a second groove and multiple second conductive pillars; the opening direction of the first groove is arranged opposite to the opening direction of the second groove, and at least one of the first conductive pillars and at least one of the second conductive pillars are electrically connected one by one.

[0007] In some embodiments, the interposer structure further includes a first redistribution layer, the first redistribution layer being located between the first sub-interposer structure and the second sub-interposer structure; the first redistribution layer includes a plurality of first pads;

[0008] The first sub-interposer structure is electrically connected to the second sub-interposer structure through the first pad.

[0009] In some embodiments, the accommodation space of the first groove and / or the accommodation space of the second groove includes at least one first pad.

[0010] In a second aspect, an embodiment of the present disclosure provides a method for preparing an adapter plate structure, the method comprising:

[0011] providing a first substrate and a second substrate;

[0012] forming a plurality of first conductive pillars in the first substrate, and forming a plurality of second conductive pillars in the second substrate;

[0013] Performing a bonding process on the first substrate and the second substrate to obtain a first initial transfer plate structure;

[0014] forming a second groove on the first surface of the first initial adapter plate structure, and forming a first groove on the second surface of the first initial adapter plate structure to obtain a second initial adapter plate structure; the first surface and the second surface are opposite to each other;

[0015] Cutting the second initial adapter plate structure between the first conductive pillars and / or between the second conductive pillars to obtain at least one adapter plate structure;

[0016] Among them, in the adapter board structure, the remaining first substrate, the first groove and the multiple first conductive pillars constitute a first sub-adapter board structure, and the remaining second substrate, the second groove and the multiple second conductive pillars constitute a second sub-adapter board structure; at least one first conductive pillar and at least one second conductive pillar are electrically connected one by one.

[0017] In some embodiments, the bonding process is performed on the first substrate and the second substrate to obtain a first initial transfer plate structure, including:

[0018] After forming the plurality of first conductive pillars, forming a first sub-redistribution layer on a surface of the first substrate close to the plurality of first conductive pillars, the first sub-redistribution layer comprising a plurality of first sub-pads;

[0019] After forming the plurality of second conductive pillars, forming a second sub-redistribution layer on a surface of the second substrate close to the plurality of second conductive pillars, the second sub-redistribution layer comprising a plurality of second sub-pads; the plurality of first sub-pads correspond to the plurality of second sub-pads one by one;

[0020] The multiple first sub-pads and the multiple second sub-pads are bonded to obtain the first initial adapter board structure; in the first initial adapter board structure, the first sub-rewiring layer and the second sub-rewiring layer constitute a first rewiring layer, and the first sub-pad and the corresponding second sub-pad constitute a first pad.

[0021] In a third aspect, an embodiment of the present disclosure provides a packaging structure, the packaging structure comprising a substrate and a chip stacking structure, the chip stacking structure being located on the substrate; the chip stacking structure comprising a transfer plate structure as described in any one of the first aspects, a first chip, a second chip, a third chip and a plurality of solder balls;

[0022] The first chip is located in the accommodation space of the first groove in the adapter plate structure and is electrically connected to the first groove;

[0023] The second chip is located in the accommodation space of the second groove in the adapter plate structure and is electrically connected to the second groove;

[0024] The third chip is electrically connected to the first surface of the adapter plate structure, and the plurality of solder balls are electrically connected to the second surface of the adapter plate structure;

[0025] The first surface of the adapter plate structure is a surface close to the first groove, and the second surface of the adapter plate structure is a surface close to the second groove.

[0026] In some embodiments, the chip stacking structure further includes a second redistribution layer, the second redistribution layer is located on the first surface of the transfer board structure; the second redistribution layer includes a plurality of second pads;

[0027] The third chip is electrically connected to the first surface of the transfer board structure through at least one of the second pads.

[0028] In some embodiments, the chip stacking structure further includes at least one chip layer stacked sequentially;

[0029] The at least one chip layer is electrically connected to the third chip, and the at least one chip layer is electrically connected to each other.

[0030] In some embodiments, the packaging structure further includes a packaging material, and the packaging material is filled in the gap of the packaging structure.

[0031] In some embodiments, the chip stacking structure includes a plurality of the adapter plate structures, and the plurality of adapter plate structures are sequentially arranged along the second direction;

[0032] At least one of the third chips electrically connects two adjacent transfer board structures.

[0033] In a fourth aspect, an embodiment of the present disclosure provides a method for preparing a packaging structure, the method comprising:

[0034] Providing a substrate and an adapter plate structure, placing the adapter plate structure on the substrate, with the second surface of the adapter plate structure facing the substrate;

[0035] A first chip is placed in the accommodation space of the first groove in the adapter plate structure, and the first chip is electrically connected to the first groove;

[0036] Placing a third chip on the first surface of the adapter plate structure, and bonding the third chip and the adapter plate structure to obtain an initial chip stacking structure;

[0037] Turning over the initial chip stacking structure, with the first surface of the initial chip stacking structure facing the substrate; and placing a second chip in the accommodation space of the second groove in the adapter plate structure, with the second chip being electrically connected to the second groove;

[0038] A ball planting process is performed on the second surface of the initial chip stacking structure to obtain the chip stacking structure.

[0039] In some embodiments, the step of bonding the third chip and the adapter plate structure to obtain an initial chip stacking structure includes:

[0040] forming a second redistribution layer on the first surface of the transfer board structure, wherein the second redistribution layer includes a plurality of second pads;

[0041] The third chip and at least one of the second pads are bonded to obtain the initial chip stacking structure.

[0042] The present disclosure provides an adapter plate structure and a preparation method thereof, a packaging structure and a preparation method thereof, wherein the adapter plate structure includes a first sub-adapter plate structure and a second sub-adapter plate structure electrically connected along a first direction; the first sub-adapter plate structure includes a first groove and a plurality of first conductive pillars, and the second sub-adapter plate structure includes a second groove and a plurality of second conductive pillars; the opening direction of the first groove is arranged opposite to the opening direction of the second groove, and at least one first conductive pillar and at least one second conductive pillar are electrically connected one by one. In this way, based on the adapter plate structure, vertical interconnection and packaging of multiple chips can be realized, the number of chips stacked can be increased, and a large-sized adapter plate structure can be prepared by splicing multiple adapter plate structures, thereby reducing the difficulty of preparing the adapter plate structure, improving the yield, reducing the occupied area, increasing the integration, and reducing the cost. It can also increase the packaging flexibility and reduce the product development time. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0044] Figure 1 is a schematic diagram of a packaging structure;

[0045] Figure 2 A schematic diagram of the structure of a transfer plate provided in an embodiment of the present disclosure;

[0046] Figure 3 A schematic diagram of a process for preparing a transfer plate structure provided in an embodiment of the present disclosure;

[0047] Figure 4 A schematic diagram of a process for preparing a transfer plate structure provided in an embodiment of the present disclosure Figure 1 ;

[0048] Figure 5 A schematic diagram of a process for preparing a transfer plate structure provided in an embodiment of the present disclosure Figure 2 ;

[0049] Figure 6 A schematic diagram of a process for preparing a transfer plate structure provided in an embodiment of the present disclosure Figure 3 ;

[0050] Figure 7 A schematic diagram of a process for preparing a transfer plate structure provided in an embodiment of the present disclosure Figure 4 ;

[0051] Figure 8 A schematic diagram of a process for preparing a transfer plate structure provided in an embodiment of the present disclosure Figure 5 ;

[0052] Fig. 9 A schematic diagram of a process for preparing a transfer plate structure provided in an embodiment of the present disclosure Figure 6 ;

[0053] Fig.10 A schematic diagram of a process for preparing a transfer plate structure provided in an embodiment of the present disclosure Figure 7 ;

[0054] Fig.11 A schematic diagram of a process for preparing a transfer plate structure provided in an embodiment of the present disclosure Figure 8 ;

[0055] Fig.12 A schematic diagram of a process for preparing a transfer plate structure provided in an embodiment of the present disclosure Figure 9 ;

[0056] Fig.13 A schematic diagram of a packaging structure provided in an embodiment of the present disclosure Figure 1 ;

[0057] Fig.14 A schematic diagram of a packaging structure provided in an embodiment of the present disclosure Figure 2 ;

[0058] Fig.15 A schematic diagram of a packaging structure provided in an embodiment of the present disclosure Figure 3 ;

[0059] Fig.16 A schematic diagram of a process for preparing a packaging structure provided by an embodiment of the present disclosure;

[0060] Fig.17 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 1 ;

[0061] Fig.18 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 2 ;

[0062] Fig.19 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 3 ;

[0063] Fig. 20 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 4 ;

[0064] Fig.21 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 5 ;

[0065] Fig. 22 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 6 ;

[0066] Fig.23 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 7 ;

[0067] Fig.24 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 8 ;

[0068] Fig.25 A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 9 ;

[0069] Fig.26A schematic diagram of a process for preparing a packaging structure provided in an embodiment of the present disclosure Figure 10 . DETAILED DESCRIPTION

[0070] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0071] In the following description, a large number of details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0072] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0073] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on other elements or layers, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part discussed, it does not mean that the present disclosure necessarily has the first element, component, region, layer or part.

[0074] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0075] TSV interposers (also called interposer structures) fabricated based on vertical through-hole interconnection and other processes are currently defined as the most clear, mature, and recognized means of surpassing Moore's Law due to their advantages such as short global interconnection, low latency, low power consumption, high bandwidth, and high integration. Moore's Law states: "The number of integrated circuits on an integrated circuit chip doubles every 18-24 months; the performance of a microprocessor doubles, or the price drops by half."

[0076] At present, most TSV adapters are vertically interconnected. TSV adapters are used to form 2.5D packages. The chips are packaged on the TSV adapters and interconnected using the redistribution layer (RDL) on the TSV adapters. However, it is difficult to achieve a multi-layer chip stacking structure through the TSV adapters. 2.5D packaging is an advanced heterogeneous chip packaging technology that allows multiple chips to achieve high-density line connections through an interposer and integrate into a package structure. The interposer can be made of silicon, glass or other materials, and can be implemented through a variety of technologies, such as TSV, through glass vias (TGV), etc.

[0077] See also Figure 1 , which shows a schematic diagram of a packaging structure. Figure 1 (a) is a three-dimensional schematic diagram. Figure 1 (b) is the corresponding cross-sectional schematic diagram. Figure 1 As shown, the interposer (also called adapter board) in the package structure 10 is implemented by TSV technology and is electrically connected to the package base or printed circuit board (PCB) through bumps. On the adapter board, multiple chips are laid flat, such as micro-electro-mechanical system (MEMS), storage, radio frequency, and logic chips, and the sizes of each chip are different.

[0078] In the related art, 2.5D packaging is to lay various chips flat on the same large-sized TSV adapter board, and multiple chips are stacked in a plane, which makes it difficult to achieve 3D stacking of multiple chips, resulting in a large area occupied by the adapter board in the packaging structure 10 and a low degree of integration. In addition, in the packaging structure 10, the adapter board is a whole large-sized adapter board, which is difficult to prepare and has a low yield. When it is partially damaged, it also needs to be replaced as a whole, resulting in large losses and high costs.

[0079] Based on this, the present disclosure provides an adapter plate structure, which includes a first sub-adapter plate structure and a second sub-adapter plate structure electrically connected along a first direction; the first sub-adapter plate structure includes a first groove and a plurality of first conductive pillars, and the second sub-adapter plate structure includes a second groove and a plurality of second conductive pillars; the opening direction of the first groove is arranged opposite to the opening direction of the second groove, and at least one first conductive pillar and at least one second conductive pillar are electrically connected one by one. In this way, based on the adapter plate structure, multiple chips can be vertically interconnected and packaged, the number of chips stacked can be increased, and a large-sized adapter plate structure can be prepared by splicing multiple adapter plate structures, thereby reducing the difficulty of preparing the adapter plate structure, improving the yield, reducing the occupied area, increasing the integration, and reducing the cost. It can also increase the packaging flexibility and reduce the product development time.

[0080] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0081] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the composition structure of a transfer plate structure provided by an embodiment of the present disclosure. Figure 2 As shown, the adapter plate structure 20 includes a first sub-adapter plate structure 21 and a second sub-adapter plate structure 22 electrically connected along a first direction;

[0082] The first sub-interposer structure 21 includes a first groove 211 and a plurality of first conductive pillars 212 ( Figure 2 Only one reference numeral 212 is shown, and the rest are omitted). The second sub-adapter plate structure 22 includes a second groove 221 and a plurality of second conductive pillars 222 ( Figure 2 Only one reference numeral 222 is shown, and the rest are omitted); the opening direction of the first groove 211 is arranged opposite to the opening direction of the second groove 221, and at least one first conductive column 212 and at least one second conductive column 222 are electrically connected in a one-to-one correspondence.

[0083] It should be noted that the adapter plate structure 20 can be applied to chip packaging to realize vertical interconnection and packaging of multiple chips to form a packaging structure with multiple layers of chips stacked.

[0084] It should also be noted that the material of the adapter plate structure 20 can be silicon or glass, that is, its substrate can be silicon-based or glass-based, etc., and there is no specific limitation on this. Exemplarily, the material of the adapter plate structure 20 is silicon, specifically a TSV adapter plate.

[0085] The first sub-adapter plate structure 21 and the second sub-adapter plate structure 22 form an adapter plate structure 20 along the first direction. Exemplarily, the first sub-adapter plate structure 21 is located above the second sub-adapter plate structure 22, the opening direction of the first groove 211 is upward along the first direction, and the opening direction of the second groove 221 is downward along the first direction.

[0086] It should also be noted that the present embodiment does not specifically limit the number and position of the first groove 211 and the second groove 221, and the number can be one or more, or one first groove 211 and more than one second groove 221, or more than one first groove 211 and one second groove 221; the first groove 211 can be located in the middle or on one side of the plurality of first conductive pillars 212, and the second groove 221 can be located in the middle or on one side of the plurality of second conductive pillars 222. For example, Figure 2 Only one first groove 211 and one second groove 221 are shown. In addition, the size and depth of the first groove 211 and the second groove 221 can be set according to the size and thickness of the chip to be electrically connected thereto later.

[0087] For example, Figure 2 Four first conductive pillars 212 and four second conductive pillars 222 are shown, and the four first conductive pillars 212 are all located on one side of the first groove 211, and the four second conductive pillars 222 are all located on one side of the second groove 221. In this embodiment, the number and position of the first conductive pillars 212 and the second conductive pillars 222 are not specifically limited. The number of the first conductive pillars 212 and the number of the second conductive pillars 222 may be equal or unequal. The plurality of first conductive pillars 212 may be located on one side or both sides of the first groove 211, and the plurality of second conductive pillars 222 may be located on one side or both sides of the second groove 221.

[0088] like Figure 2 As shown, the first conductive column 212 passes through the first sub-interposer structure 21, and the second conductive column 222 passes through the second sub-interposer structure 22. For example, Figure 2 It is shown that two first conductive pillars 212 and corresponding second conductive pillars 222 are electrically connected to realize the electrical connection between the first sub-interposer structure 21 and the second sub-interposer structure 22. In addition, the long conductive pillar formed by the electrical connection between the first conductive pillar 212 and the corresponding second conductive pillar 222 can be considered to penetrate the interposer structure 20.

[0089] like Figure 2As shown, in some embodiments, the interposer structure 20 may further include a first redistribution layer 23, the first redistribution layer 23 being located between the first sub-interposer structure 21 and the second sub-interposer structure 22; the first redistribution layer 23 includes a plurality of first pads 231;

[0090] The first sub-interposer structure 21 is electrically connected to the second sub-interposer structure 22 via the first pad 231 .

[0091] It should be noted that each first conductive column 212 and / or each second conductive column 222 is connected to the first redistribution layer 23 through the corresponding first pad 231, and the first conductive column 212 is electrically connected to the corresponding second conductive column 222 through the corresponding first pad 231. Figure 2 Six first pads 231 are shown.

[0092] It should also be noted that the plurality of first pads 231 are used to form a bonding interface, which may specifically be a mixed bonding interface.

[0093] like Figure 2 As shown, in some embodiments, the accommodation space of the first groove 211 and / or the accommodation space of the second groove 221 includes at least one first pad 231 .

[0094] In this way, electrical connection can be achieved with the corresponding chip. Figure 2 The accommodation space of the first groove 211 includes two first pads 231 , and the accommodation space of the second groove 221 includes two first pads 231 .

[0095] The present disclosure provides an adapter plate structure, which can realize vertical interconnection and packaging of multiple chips through a single adapter plate structure, and chips can be stacked on top of the adapter plate structure according to actual needs, thereby increasing the number of chips stacked and the packaging density.

[0096] In another embodiment of the present disclosure, see Figure 3 , which shows a schematic flow chart of a method for preparing a transfer plate structure provided by an embodiment of the present disclosure. Figure 3 As shown, the method may include:

[0097] S301 , providing a first substrate and a second substrate.

[0098] It should be noted that the preparation method provided in the embodiment of the present disclosure is applied to prepare the aforementioned adapter plate structure 20 .

[0099] See also Figure 4 , which shows a schematic diagram of a preparation process of a transfer plate structure provided by an embodiment of the present disclosure Figure 1 .like Figure 4As shown, when preparing the adapter plate structure 20, first provide a first substrate 41 and a second substrate 42. The first substrate 41 is the substrate of the first sub-adapter plate structure 21, and the second substrate 42 is the substrate of the second sub-adapter plate structure 22. The first substrate 41 and the second substrate 42 can be silicon-based, glass-based, etc., and are not specifically limited to this. Exemplarily, the first substrate 41 and the second substrate 42 are both silicon-based, that is, the material of the adapter plate structure 20 is silicon, specifically a TSV adapter plate.

[0100] S302 , forming a plurality of first conductive pillars in the first substrate, and forming a plurality of second conductive pillars in the second substrate.

[0101] like Figure 5 As shown, after providing the first substrate 41, etching is performed on the first surface of the first substrate 41 to form a plurality of first deep holes 411 ( Figure 5 Only one reference numeral 411 is shown, and the rest are omitted). The number and position of the plurality of first deep holes 411 are not specifically limited. For example, Figure 5 8 first deep holes 411 are shown in the figure, and the 8 first deep holes 411 are distributed on both sides of the first substrate 41.

[0102] It should be noted that the first deep hole 411 can be formed by a mask, a photoresist, or the like, and this is not specifically limited. Exemplarily, a photoresist layer is first formed on the first surface of the first substrate 41, and then the photoresist layer is exposed and developed based on a mask having a preset pattern to form a patterned photoresist layer, the patterned photoresist layer including a plurality of openings, and then the first surface of the first substrate 41 is etched based on each opening to form a plurality of first deep holes 411 in the first substrate.

[0103] It should also be noted that etching can be a dry etching process or a wet etching process. The gas used in dry etching can be one or any combination of trifluoromethane (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), hydrobromic acid (HBr), chlorine (Cl2) or sulfur hexafluoride (SF6). Wet etching can be performed using strong acids such as concentrated sulfuric acid, hydrofluoric acid, and concentrated nitric acid.

[0104] like Figure 6As shown, after forming a plurality of first deep holes 411, a conductive material is filled in the first deep holes 411 to form a plurality of first conductive pillars 412. The conductive material may include copper, tungsten, polysilicon, etc., which is not specifically limited. The process of filling the conductive material may include a deposition process, such as an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, etc., or may also include an electroplating process, which is not specifically limited in the embodiments of the present disclosure.

[0105] It should be noted that after forming the plurality of first conductive pillars 412 , a chemical mechanical polishing (CMP) process may be performed to make the first surface of the first substrate 41 flat.

[0106] like Figure 6 As shown, in some embodiments, after forming a plurality of first conductive pillars 412, a first sub-redistribution layer 413 is formed on a surface of the first substrate 41 close to the plurality of first conductive pillars 412, and the first sub-redistribution layer 413 includes a plurality of first sub-pads 4131 ( Figure 6 Only one label 4131 is shown, and the rest are omitted).

[0107] It should be noted that the first sub-redistribution layer 413 may be formed on the first surface of the first substrate 41 after grinding the first substrate 41. In addition, the first sub-redistribution layer 413 may be formed by a damascene process.

[0108] It should also be noted that the plurality of first sub-pads 4131 are used to form a bonding interface, which may be a mixed bonding interface. Figure 6 Twelve first sub pads 4131 are shown.

[0109] Similarly, if Figure 7 As shown, after providing the second substrate 42, etching is performed on the first surface of the second substrate 42 to form a plurality of second deep holes 421 ( Figure 7 Only one reference numeral 421 is shown, and the rest are omitted). The number and position of the plurality of second deep holes 421 are not specifically limited. For example, Figure 7 8 second deep holes 421 are shown in the figure, and the 8 second deep holes 421 are distributed in the middle of the second substrate 42.

[0110] like Figure 8As shown, after forming a plurality of second deep holes 421, a conductive material is filled in the second deep holes 421 to form a plurality of second conductive pillars 422. In addition, after forming a plurality of second conductive pillars 422, a chemical mechanical polishing process may be performed to make the first surface of the second substrate 42 flat.

[0111] like Figure 8 As shown, in some embodiments, after forming a plurality of second conductive pillars 422, a second sub-redistribution layer 423 is formed on a surface of the second substrate 42 close to the plurality of second conductive pillars 422, and the second sub-redistribution layer 423 includes a plurality of second sub-pads 4231 ( Figure 8 Only one label 4231 is shown, and the rest are omitted).

[0112] It should be noted that, after grinding the second substrate 42 , the second sub-redistribution layer 423 may be formed on the first surface of the second substrate 42 .

[0113] It should also be noted that the plurality of second sub-pads 4231 are used to form a bonding interface, which may be a mixed bonding interface. Figure 8 12 second sub-pads 4231 are shown in FIG. 1 , and the number and position of the plurality of first sub-pads 4131 and the plurality of second sub-pads 4231 correspond one to one.

[0114] Here, the process of forming the plurality of second deep holes 421 , the plurality of second conductive pillars 422 , and the second sub-redistribution layer 423 will not be described in detail.

[0115] S303 , performing a bonding process on the first substrate and the second substrate to obtain a first initial transfer plate structure.

[0116] like Figure 6 and Figure 8 As shown, in some embodiments, a first substrate and a second substrate are bonded to obtain a first initial transfer plate structure, including:

[0117] After forming a plurality of first conductive pillars 412, a first sub-redistribution layer 413 is formed on a surface of the first substrate 41 close to the plurality of first conductive pillars 412, wherein the first sub-redistribution layer 413 includes a plurality of first sub-pads 4131;

[0118] After forming the plurality of second conductive pillars 422, a second sub-redistribution layer 423 is formed on the surface of the second substrate 42 close to the plurality of second conductive pillars 422, and the second sub-redistribution layer 423 includes a plurality of second sub-pads 4231; the plurality of first sub-pads 4131 and the plurality of second sub-pads 4231 correspond to each other one by one;

[0119] like Fig. 9As shown, after forming multiple first sub-pads 4131 and multiple second sub-pads 4231, the multiple first sub-pads 4131 and the multiple second sub-pads 4231 are bonded to obtain a first initial transfer board structure 43; in the first initial transfer board structure 43, the first sub-rewiring layer 413 and the second sub-rewiring layer 423 constitute a first rewiring layer 431, and the first sub-pad 4131 and the corresponding second sub-pad 4231 constitute a first pad 4311.

[0120] It should be noted that, through the one-to-one bonding of the plurality of first sub-pads 4131 and the plurality of second sub-pads 4231, the first substrate 41 including the plurality of first conductive pillars 412 and the second substrate 42 including the plurality of second conductive pillars 422 are bonded to obtain the first initial transfer board structure 43. In addition, in the first initial transfer board structure 43, each first conductive pillar 412 and / or each second conductive pillar 422 is connected to the first redistribution layer 431 through the corresponding first pad 4311, and the first conductive pillar 412 is electrically connected to the corresponding second conductive pillar 422 through the corresponding first pad 4311; at least one first conductive pillar 412 and at least one second conductive pillar 422 are electrically connected one-to-one.

[0121] It should also be noted that in Figure 6 and Figure 8 In the embodiment, the first surfaces of the first substrate 41 and the second substrate 42 are both facing upwards, and in order to bond the first substrate 41 and the second substrate 42, either of the two substrates can be flipped over so that its first surface faces upwards and the second surface of the other substrate faces upwards, and then the bonding process is performed. For example, Fig. 9 The second substrate 42 is turned over, and the second substrate 42 is located above the first substrate 41 .

[0122] It should also be noted that the first substrate 41 and the second substrate 42 can be bonded by any bonding technology, and this is not specifically limited. For example, the first substrate 41 and the second substrate 42 are bonded by hybrid bonding technology. Hybrid bonding technology is a method that combines physical bonding and chemical bonding, which can form a bond with different types of bonding materials. This bonding method can overcome the limitations of a single bonding method, while greatly reducing the bonding spacing and improving the bonding density.

[0123] S304, forming a second groove on the first surface of the first initial adapter plate structure, and forming a first groove on the second surface of the first initial adapter plate structure to obtain a second initial adapter plate structure; the first surface and the second surface are opposite to each other.

[0124] After forming the first initial transfer plate structure 43, the surface close to the second conductive pillar 422, or the second surface of the second substrate 42, can be determined as the first surface, and the surface opposite thereto close to the first conductive pillar 412, or the second surface of the first substrate 41, can be determined as the second surface. Fig.10 As shown, the first surface of the first initial adapter plate structure 43 faces upward, and a second groove 432 is etched on the first surface. The number and position of the second groove 432 are not specifically limited in this embodiment. For example, Fig.10 Two second grooves 432 are shown and are located on both sides of the first initial adapter plate structure 43 .

[0125] It should be noted that before forming the second groove 432, the first surface of the first initial transfer plate structure 43 is thinned to be flush with the end surface of the second conductive column 422. The thinning process can be performed by mechanical grinding combined with chemical mechanical polishing, wet etching, dry etching or dry polishing, which is not specifically limited.

[0126] In some embodiments, the accommodation space of the second groove 432 includes at least one first pad 4311 to achieve electrical connection with the corresponding chip.

[0127] like Fig.11 As shown, after the first surface of the first initial adapter plate structure 43 is etched to form the second groove 432, the first initial adapter plate structure 43 is turned over so that its second surface faces upward, and then the first groove 433 is etched on its second surface to obtain the second initial adapter plate structure 44. This embodiment does not specifically limit the number and position of the first groove 433. For example, Fig.11 Two first grooves 433 are shown and are located in the middle of the second initial adapter plate structure 44 .

[0128] Similarly, before forming the first groove 433 , the second surface of the first initial transfer plate structure 43 is thinned to be flush with the end surface of the first conductive pillar 412 .

[0129] In some embodiments, the accommodation space of the first groove 433 includes at least one first pad 4311 to achieve electrical connection with the corresponding chip.

[0130] The etching process for forming the first groove 433 and the second groove 432 will not be described in detail herein.

[0131] S305 , cutting the second initial transfer plate structure between the first conductive pillars and / or between the second conductive pillars to obtain at least one transfer plate structure.

[0132] like Fig.12As shown, after the second initial transfer plate structure 44 is formed, it is cut to obtain at least one transfer plate structure 20. In the transfer plate structure 20, the remaining first substrate 41, the first groove 433 and the plurality of first conductive pillars 412 form a first sub-transfer plate structure 21, and the remaining second substrate 42, the second groove 432 and the plurality of second conductive pillars 422 form a second sub-transfer plate structure 22.

[0133] It should be noted that the present embodiment does not specifically limit the number of cutting times. For example, Fig.12 The second initial adapter plate structure 44 is cut only once in the direction of the arrow, so that two adapter plate structures 20 can be obtained. In addition, there is no specific limitation on the cutting position, and the cutting can be done between the first conductive pillars 412 and / or between the second conductive pillars 422, as long as the conductive pillars are avoided and not damaged. Fig.12 The cut is made in the middle of the second initial adapter plate structure 44 .

[0134] The disclosed embodiment provides a method for preparing an adapter plate structure. The adapter plate structure prepared by the method can realize vertical interconnection and packaging of multiple chips, and chips can be stacked on top of the adapter plate structure according to actual needs, thereby increasing the number of chips stacked and the packaging density.

[0135] In another embodiment of the present disclosure, see Fig.13 , which shows a schematic diagram of the composition structure of a packaging structure provided by an embodiment of the present disclosure Figure 1 .like Fig.13 As shown, the package structure 50 includes a substrate 51 and a chip stacking structure 52, and the chip stacking structure 52 is located on the substrate 51; the chip stacking structure 52 includes an adapter plate structure 521, a first chip 522, a second chip 523, a third chip 524 and a plurality of solder balls 525;

[0136] The first chip 522 is located in the accommodation space of the first groove in the adapter plate structure 521 and is electrically connected to the first groove;

[0137] The second chip 523 is located in the accommodation space of the second groove in the adapter plate structure 521 and is electrically connected to the second groove;

[0138] The third chip 524 is electrically connected to the first surface of the transfer plate structure 521 , and the plurality of solder balls 525 are electrically connected to the second surface of the transfer plate structure 521 ;

[0139] The first surface of the adapter plate structure 521 is a surface close to the first groove, and the second surface of the adapter plate structure 521 is a surface close to the second groove.

[0140] Here, the adapter plate structure 521 is the aforementioned adapter plate structure 20, and its composition and corresponding reference numerals are not shown again. Please refer to the description of the aforementioned embodiment for understanding. Exemplarily, the packaging structure 50 in this embodiment includes only one chip stacking structure 52, and the chip stacking structure 52 includes only one adapter plate structure 521.

[0141] It should be noted that the substrate 51 is used to place the chip stacking structure 52 for subsequent operations, and provides protection, support and other functions for the chip stacking structure 52. In addition, the material of the substrate 51 can be silicon or glass, etc., which is not specifically limited.

[0142] It should also be noted that the number and position of the first grooves and the second grooves in the adapter plate structure 521 are not specifically limited. For example, Fig.13 Only one first groove and one second groove are shown. In addition, the number of first chips 522 corresponds to the number of first grooves, and the number of second chips 523 corresponds to the number of second grooves. For example, Fig.13 Only one first chip 522 and one second chip 523 are shown.

[0143] It should also be noted that the number of the third chip 524 can be one or more, which can be determined according to actual conditions. The functions of the first chip 522, the second chip 523 and the third chip 524 can be different. The first chip 522, the second chip 523 and the third chip 524 can be radio frequency chips, logic chips, memory chips, etc., which are not specifically limited in this embodiment.

[0144] It should also be noted that the solder ball 525 is electrically connected to the second surface of the adapter plate structure 521 for subsequent connection to a PCB board, etc. The material of the solder ball 525 can be tin-lead, tin-silver-copper or tin-silver, etc.

[0145] like Fig.13 As shown, in some embodiments, the chip stacking structure 52 may further include a second redistribution layer 526, and the second redistribution layer 526 is located on the first surface of the transfer plate structure 521; the second redistribution layer 526 includes a plurality of second pads 5261;

[0146] The third chip 524 is electrically connected to the first surface of the transfer board structure 521 through at least one second pad 5261 .

[0147] It should be noted that the size of the third chip 524 is related to the number of the corresponding second pads 5261. Specifically, when the size of the third chip 524 is larger, the number of the corresponding second pads 5261 is larger; when the size of the third chip 524 is smaller, the number of the corresponding second pads 5261 is smaller. For example, Fig.13Six second pads 5261 are shown, there are two third chips 524 in total, one third chip 524 corresponds to two second pads 5261 , and another third chip 524 corresponds to four second pads 5261 .

[0148] It should also be noted that although Fig.13 Although not shown in the figure, there is also a redistribution layer between the solder ball 525 and the second surface of the interposer structure 521, and the redistribution layer includes a plurality of pads.

[0149] exist Fig.13 Based on the chip stacking structure 52 shown, as Fig.14 As shown, in some embodiments, the chip stacking structure 52 may further include at least one chip layer 527 stacked in sequence; at least one chip layer 527 is electrically connected to the third chip 524, and at least one chip layer 527 is electrically connected to each other.

[0150] It should be noted that this embodiment does not specifically limit the number of layers of the chip layer 527, nor the number and type of chips included therein. Fig.14 Only one chip layer 527 is shown, which includes three chips.

[0151] It should also be noted that although Fig.14 Although not shown, a redistribution layer is included between the third chip 524 and the chip layer 527, and between the multi-layer chip layers 527, and the redistribution layer includes a plurality of pads to achieve electrical connection. In this way, chips can be stacked on the adapter plate structure 521 according to actual needs to achieve a multi-layer chip stacking structure.

[0152] like Fig.13 As shown, in some embodiments, the packaging structure 50 may further include a packaging material 528 , and the packaging material 528 fills the gaps in the packaging structure 50 .

[0153] Chip packaging is a key manufacturing process in semiconductor chip production. It uses a mold to encapsulate the exposed chip with packaging materials under pressure and temperature to protect the chip.

[0154] It should be noted that the packaging material may be plastic, but there is no specific limitation to this.

[0155] like Fig.15 As shown, in some embodiments, the chip stacking structure 52 may include a plurality of adapter plate structures 521, and the plurality of adapter plate structures 521 are sequentially arranged along the second direction;

[0156] At least one third chip 524 electrically connects two adjacent interposer structures 521 .

[0157] It should be noted that, here, the first direction and the second direction intersect, that is, the first direction and the second direction are two non-parallel directions. In the embodiment of the present disclosure, the first direction and the second direction may be perpendicular to each other, or may intersect at other angles, and no specific limitation is made to this. Exemplarily, the specific implementation of the embodiment of the present disclosure is described in detail by taking the first direction and the second direction being perpendicular to each other as an example.

[0158] It should also be noted that the package structure 50 may include one or more chip stacking structures 52, and each chip stacking structure 52 may include one adapter plate structure 521 or multiple adapter plate structures 521, which is not specifically limited. Fig.15 It is shown that one chip stacking structure 52 includes two adapter plate structures 521 . The two adapter plate structures 521 are bridged by a common third chip 524 . The third chip 524 is electrically connected to two second pads 5261 in the two adapter plate structures 521 , respectively.

[0159] The disclosed embodiment provides a packaging structure, in which a single adapter plate structure can realize vertical interconnection and packaging of multiple chips, and chips can be arranged between multiple adapter plate structures to realize multi-chip bridging. In addition, chips can be stacked on the adapter plate structure according to actual needs, which increases the number of chips stacked and increases the packaging density. Further, the disclosed embodiment also provides a large-sized adapter plate structure flexibly prepared by a number of small-sized standard adapter plate structures (i.e., adapter plate structure 20), so that the standard adapter plate structure is a small-sized design, which improves the manufacturing yield and reduces the cost of the adapter plate structure; the standard adapter plate structure is assembled into a large-sized adapter plate structure through a back-end process and then manufactures a rewiring layer, which significantly reduces the process difficulty. The standard adapter plate structure can flexibly splice adapter plate structures of different types and sizes according to product requirements, which increases packaging flexibility and reduces product development time; and when a standard adapter plate structure in the assembled large-sized adapter plate structure is damaged, only the damaged adapter plate structure can be replaced, which further reduces the cost.

[0160] In another embodiment of the present disclosure, see Fig.16 , which shows a schematic flow chart of a method for preparing a packaging structure provided by an embodiment of the present disclosure. Fig.16 As shown, the method may include:

[0161] S601, providing a substrate and an adapter plate structure, placing the adapter plate structure on the substrate, with the second surface of the adapter plate structure facing the substrate.

[0162] It should be noted that the preparation method provided in the embodiment of the present disclosure is applied to prepare the aforementioned packaging structure 50. Exemplarily, the packaging structure 50 in this embodiment only includes one transfer plate structure.

[0163] See also Fig.17 , which shows a schematic diagram of a preparation process of a packaging structure provided by an embodiment of the present disclosure Figure 1 .like Fig.17 As shown, when preparing the packaging structure 50 , a substrate 71 and an adapter plate structure 72 are first provided.

[0164] It should be noted that the adapter plate structure 72 is the aforementioned adapter plate structure 20, and its components and corresponding reference numerals are not shown again. Please refer to the description of the aforementioned embodiment for understanding. Here, the second surface of the adapter plate structure 72 is opposite to the substrate 71, that is, the first surface of the adapter plate structure 72 faces upward.

[0165] S602: placing a first chip in the accommodation space of the first groove in the adapter plate structure, and the first chip is electrically connected to the first groove.

[0166] like Fig.18 As shown, the first chip 73 is placed in the first groove of the transfer plate structure 72 and is electrically connected to the first groove through two first pads.

[0167] S603 , placing a third chip on the first surface of the adapter plate structure, and performing a bonding process on the third chip and the adapter plate structure to obtain an initial chip stacking structure.

[0168] In some embodiments, bonding the third chip and the transfer plate structure to obtain an initial chip stacking structure includes:

[0169] Forming a second redistribution layer on the first surface of the transfer board structure, the second redistribution layer comprising a plurality of second pads;

[0170] The third chip and the at least one second pad are bonded to obtain an initial chip stacking structure.

[0171] like Fig.19 As shown, after the first chip 73 is placed in the first groove of the adapter plate structure 72, a second redistribution layer 74 is formed on the first surface of the adapter plate structure 72, and the second redistribution layer 74 includes a plurality of second pads 741; then, the third chip 75 is placed on the first surface of the adapter plate structure 72, that is, the third chip 75 is placed above the first chip 73, and the third chip 75 and at least one second pad 741 are bonded to obtain an initial chip stacking structure 76.

[0172] S604, turning over the initial chip stacking structure, with the first surface of the initial chip stacking structure facing the substrate; and placing a second chip in the accommodation space of the second groove in the adapter plate structure, with the second chip being electrically connected to the second groove.

[0173] like Fig. 20 As shown, after the initial chip stacking structure 76 is formed, the second surface of the initial chip stacking structure 76 faces upward, and the second chip 77 is placed in the second groove of the transfer plate structure 72 and electrically connected to the second groove through two first pads.

[0174] S605 , performing ball planting processing on the second surface of the initial chip stacking structure to obtain a chip stacking structure.

[0175] That is, a ball implantation process is performed on the second chip 77 to form a plurality of solder balls, and finally a chip stacking structure 52 is obtained.

[0176] It should be noted that although Fig. 20 Although not shown in the figure, the second surface of the transfer plate structure 72 also has a redistribution layer, and the redistribution layer includes a plurality of pads. After the redistribution layer is formed on the second surface of the transfer plate structure 72, a ball planting process is performed on the redistribution layer to form a plurality of solder balls.

[0177] like Fig. 20 As shown, in some embodiments, the method further includes filling the gaps of the packaging structure 50 with a packaging material 78 .

[0178] In some embodiments, the packaging structure 50 includes a plurality of transfer plate structures. This embodiment exemplarily provides a method for preparing a packaging structure, which is used to prepare a packaging structure 50 including two transfer plate structures.

[0179] like Fig.21 As shown, a substrate 81 and two adapter plate structures 82 are provided, and the adapter plate structure 82 is placed on the substrate 81, and the second surface of the adapter plate structure 82 is opposite to the substrate 81. Here, the two adapter plate structures 82 are arranged in sequence along the second direction.

[0180] In some embodiments, Fig. 22 As shown, the first chip 83 is placed in the accommodation space of the first grooves in the two adapter plate structures 82, and the first chip 83 is electrically connected to the first grooves.

[0181] like Fig.23 As shown, after the first chip 83 is placed in the first groove of the interposer structure 82, a second redistribution layer 84 is formed on the first surface of the interposer structure 82, and the second redistribution layer 84 includes a plurality of second pads 841; then a third chip 85 is placed on the first surfaces of the two interposer structures 82, and the third chip 85 and the interposer structure 82 are bonded to obtain an initial chip stacking structure 86. Exemplarily, three third chips 85 are placed on the first surfaces of the two interposer structures 82, and the middle third chip 85 bridges the two interposer structures 82.

[0182] In other embodiments, Fig.24 As shown, after the two adapter plate structures 82 are placed on the substrate 81, the substrate between the first grooves of the two adapter plate structures 82 is etched away, that is, the two first grooves are formed into a large groove.

[0183] like Fig.25 As shown, a first chip 83 is placed in the accommodation space of the large groove, and the first chip 83 is electrically connected to the large groove; illustratively, two third chips 85 are placed on the first chip 83 .

[0184] It should be noted that although Fig.25 Although not shown, there is also a redistribution layer between the first chip 83 and the third chip 85. Fig.25 On this basis, steps such as placing a second chip in the accommodating space of the second groove in the adapter plate structure, forming a redistribution layer on the second surface of the adapter plate structure and performing ball planting processing can also be performed. Please refer to other embodiments for understanding, and no further details will be given here.

[0185] In this way, by connecting two adapter plate structures through the first chip, the small-sized adapter plate structure can be spliced ​​into a large-sized adapter plate structure according to actual needs, and three-dimensional stacking of chips can be achieved at the same time.

[0186] exist Fig.23 On the basis of Fig.26 As shown, after the initial chip stacking structure 86 is formed, the initial chip stacking structure 86 is turned over so that its second surface faces upward, and then the second chip 87 is placed in the accommodation space of the second grooves in the two adapter plate structures 82, and the second chip 87 is electrically connected to the second groove. In addition, after the second chip 87 is placed, a ball planting process is performed on the second surface of the initial chip stacking structure 86 to obtain the aforementioned chip stacking structure 52 including the two adapter plate structures.

[0187] The disclosed embodiment provides a method for preparing a packaging structure. The packaging structure prepared by the method can realize multi-chip vertical interconnection and multi-chip bridging, increase the number of chip stacking, and increase the packaging density, thereby reducing the occupied area of ​​the packaging structure, increasing the integration, and reducing the cost. In addition, the disclosed embodiment also provides a method for preparing a large-sized adapter plate structure flexibly from a number of small-sized standard adapter plate structures, which improves the manufacturing yield and reduces the cost of the adapter plate structure, significantly reduces the process difficulty, increases the packaging flexibility, and reduces the product development time.

[0188] Details not disclosed in the embodiments of the present disclosure may be understood by referring to the description of the aforementioned embodiments.

[0189] In the several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0190] The features disclosed in several method or structural embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0191] The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A transfer plate structure, characterized in that: The adapter plate structure includes a first sub-adapter plate structure and a second sub-adapter plate structure electrically connected along a first direction; The first sub-adapter plate structure includes a first groove and a plurality of first conductive pillars, and the second sub-adapter plate structure includes a second groove and a plurality of second conductive pillars; the opening direction of the first groove is arranged opposite to the opening direction of the second groove and is staggered, and at least one of the first conductive pillars and at least one of the second conductive pillars are electrically connected in a one-to-one correspondence; the number of the first grooves is one or more, and the number of the second grooves is one or more; the accommodation space of the first groove corresponds to at least one of the second conductive pillars, and the accommodation space of the second groove corresponds to at least one of the first conductive pillars; At least one of the first conductive pillars located outside the first groove and at least one of the second conductive pillars located outside the second groove are aligned along the first direction.

2. The adapter plate structure according to claim 1, characterized in that: The adapter plate structure further includes a first redistribution layer, and the first redistribution layer is located between the first sub-adapter plate structure and the second sub-adapter plate structure; the first redistribution layer includes a plurality of first pads; The first sub-interposer structure is electrically connected to the second sub-interposer structure through the first pad.

3. The adapter plate structure according to claim 2, characterized in that: The accommodation space of the first groove and / or the accommodation space of the second groove includes at least one first pad.

4. A method for preparing an adapter plate structure, characterized in that: The method is used to prepare the adapter plate structure according to any one of claims 1 to 3, and the method comprises: providing a first substrate and a second substrate; forming a plurality of first conductive pillars in the first substrate, and forming a plurality of second conductive pillars in the second substrate; Performing a bonding process on the first substrate and the second substrate to obtain a first initial transfer plate structure; forming a second groove on the first surface of the first initial adapter plate structure, and forming a first groove on the second surface of the first initial adapter plate structure to obtain a second initial adapter plate structure; the first surface and the second surface are opposite to each other; Cutting the second initial adapter plate structure between the first conductive pillars and / or between the second conductive pillars to obtain at least one adapter plate structure; Among them, in the adapter board structure, the remaining first substrate, the first groove and the multiple first conductive pillars constitute a first sub-adapter board structure, and the remaining second substrate, the second groove and the multiple second conductive pillars constitute a second sub-adapter board structure; at least one first conductive pillar and at least one second conductive pillar are electrically connected one by one.

5. The method according to claim 4, characterized in that The step of bonding the first substrate and the second substrate to obtain a first initial transfer plate structure includes: After forming the plurality of first conductive pillars, forming a first sub-redistribution layer on a surface of the first substrate close to the plurality of first conductive pillars, the first sub-redistribution layer comprising a plurality of first sub-pads; After forming the plurality of second conductive pillars, forming a second sub-redistribution layer on a surface of the second substrate close to the plurality of second conductive pillars, the second sub-redistribution layer comprising a plurality of second sub-pads; the plurality of first sub-pads correspond to the plurality of second sub-pads one by one; The multiple first sub-pads and the multiple second sub-pads are bonded to obtain the first initial adapter board structure; in the first initial adapter board structure, the first sub-rewiring layer and the second sub-rewiring layer constitute a first rewiring layer, and the first sub-pad and the corresponding second sub-pad constitute a first pad.

6. A packaging structure, characterized in that: The packaging structure comprises a substrate and a chip stacking structure, wherein the chip stacking structure is located on the substrate; the chip stacking structure comprises an adapter plate structure according to any one of claims 1 to 3, a first chip, a second chip, a third chip and a plurality of solder balls; The first chip is located in the accommodation space of the first groove in the adapter plate structure and is electrically connected to the first groove; The second chip is located in the accommodation space of the second groove in the adapter plate structure and is electrically connected to the second groove; The third chip is electrically connected to the first surface of the adapter plate structure, and the plurality of solder balls are electrically connected to the second surface of the adapter plate structure; Wherein, the first surface of the adapter plate structure is a surface close to the first groove, and the second surface of the adapter plate structure is a surface close to the second groove; The chip stacking structure includes a plurality of adapter plate structures, and the plurality of adapter plate structures are arranged in sequence along the second direction; at least one of the third chips electrically connects two adjacent adapter plate structures.

7. The packaging structure according to claim 6, characterized in that: The chip stacking structure further includes a second redistribution layer, which is located on the first surface of the adapter plate structure; the second redistribution layer includes a plurality of second pads; The third chip is electrically connected to the first surface of the transfer board structure through at least one of the second pads.

8. The packaging structure according to claim 6, characterized in that: The chip stacking structure further comprises at least one chip layer stacked in sequence; The at least one chip layer is electrically connected to the third chip, and the at least one chip layer is electrically connected to each other.

9. The packaging structure according to claim 6, characterized in that: The packaging structure further includes a packaging material, and the packaging material is filled in the gap of the packaging structure.

10. A method for preparing a packaging structure, characterized in that: The method is used to prepare a packaging structure as claimed in any one of claims 6 to 9, and the method comprises: Providing a substrate and an adapter plate structure, placing the adapter plate structure on the substrate, with the second surface of the adapter plate structure facing the substrate; A first chip is placed in the accommodation space of the first groove in the adapter plate structure, and the first chip is electrically connected to the first groove; Placing a third chip on the first surface of the adapter plate structure, and bonding the third chip and the adapter plate structure to obtain an initial chip stacking structure; Turning over the initial chip stacking structure, with the first surface of the initial chip stacking structure facing the substrate; and placing a second chip in the accommodation space of the second groove in the adapter plate structure, with the second chip being electrically connected to the second groove; Performing ball planting on the second surface of the initial chip stacking structure to obtain the chip stacking structure; The method further comprises: Providing a plurality of the adapter plate structures, wherein the plurality of the adapter plate structures are arranged in sequence along the second direction; The first chip is placed in the accommodation space of the first groove in the plurality of adapter plate structures, and the first chip is electrically connected to the first groove; The third chip is placed on the first surfaces of the plurality of adapter plate structures, and the third chip and the adapter plate structure are bonded to connect the plurality of adapter plate structures through the third chip.

11. The method according to claim 10, characterized in that The step of bonding the third chip and the adapter plate structure to obtain an initial chip stacking structure includes: forming a second redistribution layer on the first surface of the transfer board structure, wherein the second redistribution layer includes a plurality of second pads; The third chip and at least one of the second pads are bonded to obtain the initial chip stacking structure.

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