Managing capacitor voltage dependency

Abstract

The present disclosure relates to managing capacitor voltage dependence. A system for reducing voltage dependence effects of a first capacitor caused by a first voltage can include a first capacitor that can include a first physical separation between a first capacitor terminal conductor of the first capacitor and a second capacitor terminal conductor of the first capacitor. The system can also include a second capacitor that can include a second physical separation between a first capacitor terminal conductor of the second capacitor and a second capacitor terminal conductor of the second capacitor, wherein the second physical separation is different than the first physical separation. The system can also include a compensation circuit that can be arranged to receive and at least partially offset voltage dependent signal contributions from each of the first and second capacitors for output to a signal processing circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to electronic devices, and more specifically, but not by way of limitation, to systems and methods for managing capacitor voltage dependence. BACKGROUND

[0002] Electronic systems can use capacitors for many purposes. For example, capacitors can be used to store charge or to transfer charge, or both. A capacitor can have a capacitance value that is expressed as a ratio of stored charge to voltage across the capacitor. The capacitance value of a capacitor can change depending on the voltage across the capacitor. SUMMARY

[0003] Capacitance variation depending on voltage level can result in nonlinearity of capacitor performance. The nonlinearity can be due to voltage-dependent characteristics of the dielectric. Nonlinearity in a capacitor can be partially or fully transferred to a circuit in which the capacitor is used, which can result in nonlinearity in the circuit. In one approach, capacitor plate spacing can be increased to reduce the voltage coefficient of the capacitor. However, this can result in an increase in capacitor size to achieve the same capacitance value.

[0004] The present inventors have recognized, among other things, that it can be desirable to manage capacitor voltage dependence. For example, a system can be configured to help remove some or all of the voltage dependence of a capacitor. Reducing nonlinearity in a capacitor or network of capacitors can help reduce nonlinearity in a system. It can be desirable to reduce the voltage dependence of a capacitor without increasing the plate spacing or size of the capacitor.

[0005] The present inventors have recognized, among other things, that a battery monitoring system can include at least one analog-to-digital converter (ADC) that experiences large common mode input. For example, an ADC that measures approximately 4 volt battery voltage near the top of a battery module can have a common mode input that exceeds 100 V due to the series structure of the module. Such an ADC can desire to have a large common mode rejection ratio (CMRR) to help more accurately measure battery cell voltages. The CMRR of the ADC can be limited in part by the nonlinearity or voltage dependence, or both, of capacitors in the ADC. For example, an ADC can include one or more capacitors in a first stage (e.g., an input or sampling stage) that can transfer their nonlinearity to the resulting digital value.

[0006] In one example, a system for reducing voltage dependent effects of a first capacitor caused by a first voltage can include the first capacitor, can include a first physical separation between a first capacitor terminal conductor of the first capacitor and a second capacitor terminal conductor of the first capacitor. The system can also include a second capacitor, can include a second physical separation between a first capacitor terminal conductor of the second capacitor and a second capacitor terminal conductor of the second capacitor, where the second physical separation is different than the first physical separation. The system can also include a compensation circuit, which can be arranged to receive and at least partially offset a voltage dependent signal contribution from each of the first and second capacitors for output to a signal processing circuit.

[0007] In one example, a method for reducing nonlinear effects of a first capacitor caused by a first voltage coefficient of the first capacitor can include using a first capacitor to provide a first voltage dependent contribution, the first capacitor including a first physical separation between a first capacitor terminal conductor of the first capacitor and a second capacitor terminal conductor of the first capacitor. The method can also include using a second capacitor to provide a second voltage dependent contribution, the second capacitor including a second physical separation between a first capacitor terminal conductor of the second capacitor and a second capacitor terminal conductor of the second capacitor, where the second physical separation can be different than the first physical separation. The method can also include using a compensation circuit to receive the first voltage dependent contribution and the second voltage dependent contribution, where the second voltage dependent contribution at least partially offsets the first voltage dependent contribution.

[0008] In one example, a system for reducing nonlinear effects of a first capacitor caused by a first voltage coefficient of the first capacitor can include the first capacitor coupled between a first port and a second port. The system can also include a second capacitor coupled between the first port and a third port, where the system is configured such that an effect of a capacitance coupled between the first port and the third port has a subtractive effect relative to an effect of a capacitance coupled between the first terminal and the second terminal, where the first voltage coefficient of the first capacitor is different than a second voltage coefficient of the second capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0009] In the drawings, which can be drawn without necessarily to scale, like numerals can describe substantially similar components throughout one or more views. Like numerals having different letter suffixes can represent different instances of substantially similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.

[0010] Figure 1is a schematic diagram of an example of portions of an analog-to-digital converter (ADC) system including portions of circuitry configured to reduce capacitor voltage-dependent effects of a capacitor.

[0011] Figure 2 is a schematic diagram of an example of portions of circuitry for managing voltage-dependent effects of a capacitor.

[0012] Figure 3 is a plot showing an example of an operational portion of circuitry for managing voltage-dependent effects of a capacitor.

[0013] Figure 4 is a plot showing an example of a method for operating portions of a system for managing voltage-dependent effects of a capacitor.

[0014] Figure 5 is a block diagram of an example of portions of a machine that can implement one or more portions of the present disclosure. DETAILED DESCRIPTION

[0015] The capacitance of an ideal capacitor is defined by Equation 1.

[0016] Equation 1

[0017] In Equation 1, is the capacitance, is the positive charge stored on the positive plate of the capacitor, is the voltage between the positive plate and the negative plate. In an ideal capacitor, the capacitance is a constant value for all voltages. However, a physical capacitor can differ from ideal behavior in one or more ways. For example, the capacitance value can not be constant, but can differ between one or more voltage levels.

[0018] The capacitance of a non-ideal physical capacitor can be defined by Equation 2.

[0019] Equation 2

[0020] In Equation 2, is the zero-voltage capacitance of the capacitor. The non-linear voltage coefficients (i.e., C1, C2, C3, etc.) each can be one or more of positive, negative, or zero. For example, a capacitor can have a zero first-order voltage coefficient C1 , , etc.) but a second-order voltage coefficient C2 with a positive value . There can be an infinite number of non-linear voltage coefficients.

[0021] The voltage dependence of a capacitor can be caused in part by the nonlinear characteristics of the dielectric between the capacitor plates. For example, the dielectric can have one or more characteristics that depend on voltage, such as can include the dielectric constant of the dielectric. The capacitance of the capacitor can also be defined by Equation 3.

[0022] Equation 3

[0023] In Equation 3, is the dielectric constant, is the area of the capacitor plate, is the distance between the capacitor plates. Equation 3 indicates that the voltage dependence effect of the dielectric constant can translate into a voltage related effect of the capacitance. The voltage dependence of the dielectric constant can be defined in terms of the voltage gradient (i.e., electric field) in the dielectric. The electric field in the dielectric can be defined by Equation 4.

[0024] Equation 4

[0025] In Equation 4, is the electric field strength in the dielectric. By changing the plate separation of the capacitor, the electric field strength in the dielectric can be changed. This can also change the voltage dependence effect of the capacitor. For example, a larger plate separation can result in a lower electric field in the dielectric, which can result in a decrease in the nonlinearity of the capacitor. However, increasing the plate separation can decrease the capacitance for a given plate area, which can result in one or more capacitors taking up more space or being more expensive.

[0026] The equations discussed above can apply to a parallel plate capacitor. However, these equations can be employed to apply to any capacitor construction, and the present disclosure is intended to apply to all capacitor constructions. Various other capacitor constructions can include one or more of a rolled capacitor, a finger capacitor, a polar capacitor, a non-polar capacitor, or a interleaved capacitor. Furthermore, a capacitor can be constructed by combining one or more capacitors in series or parallel.

[0027] Figure 1 is a schematic diagram of an example of portions of an analog-to-digital converter (ADC) system 100 including portions of circuitry configured to reduce capacitor voltage dependence effects of a capacitor. Figure 1 The ADC system 100 is shown to include a ground reference pin 102, a voltage reference pin 108, a first input pin 106, a second input pin 104, and a digital output connection 156. The ADC system 100 can also include a reference circuit 126, a chopping circuit 122, and an ADC 150.

[0028] The ADC system 100 can be configured to measure a voltage of one or more battery cells in the battery module 110. The battery module can include one or more batteries and can include the batteries in one or more of a series arrangement or a parallel arrangement. In one example, the battery module can include N batteries in series, and the ADC system 100 can be configured to measure a voltage of the Nth battery. The second input pin 104 can be coupled to a bottom of the battery 114 to be measured and can receive a signal equal to a total voltage of the battery minus the Nth battery. The first input pin 106 can be coupled to a top of the battery 114 to be measured and can receive a signal equal to a total voltage of the battery. This can result in a voltage of the signals received on the second input pin 104 and the first input pin 106 both having positive values, for example, can result in a common mode signal. For example, the voltage of the second input pin 104 can be equal to a voltage of the remaining cells 112. In one example, the common mode signal can include a voltage of 30 volts, 45 volts, 60 volts, 75 volts, 100 volts, or 150 volts.

[0029] The chopper circuit 122 can be coupled to the first input pin 106 and the second input pin 104 and can receive a clock signal on a clock input pin 123. The chopper circuit 122 can include one or more switches configured to provide a chopped representation of the signal received on the first input pin 106 to a first chopper input pin 124 and provide a chopped representation of the signal received on the second input pin 104 to a second chopper input pin 125. The chopper circuit 122 can convert a continuous-time analog signal received on one or more of the first input pin 106 or the second input pin 104 to a discrete-time signal in one or more of the first chopper input pin 124 or the second chopper input pin 125.

[0030] The chopper circuit 122 can form part of a first stage of the ADC system 100, for example, can sample a voltage to be converted onto one or more capacitors of the capacitor network 140. A frequency of the clock signal received on the clock input pin 123 can match a conversion frequency of the ADC 150.

[0031] The ADC 150 can include a first input 152, a second input 154, and a digital output connection 156. The ADC 150 can be a differential ADC and can generate a digital signal indicative of a difference between a signal on the first input 152 and a signal on the second input 154 on the digital output connection 156. The ADC 150 can convert an analog signal received on the first input 152 and the second input 154 to a digital signal on the digital output connection 156 using an analog-to-digital conversion circuit employing a conversion technique such as can include one or more of delta-sigma, successive approximation, flash, or integration.

[0032] The capacitor network 140 can include a first sampling capacitor 142, a first compensation capacitor 144, a second sampling capacitor 146, and a second compensation capacitor 148. The first sampling capacitor 142 can include a first terminal conductor coupled to the first chopping input pin 124 and a second terminal conductor connected to the first input 152. The second sampling capacitor 146 can include a first terminal conductor coupled to the second chopping input pin 125 and a second terminal conductor coupled to the second input 154. The first compensation capacitor 144 can include a first capacitor terminal conductor coupled to the first chopping input pin 124 and a second capacitor terminal conductor coupled to the second input 154. The second compensation capacitor 148 can include a first capacitor terminal conductor coupled to the second chopping input pin 125 and a second capacitor terminal conductor coupled to the first input 152. The first sampling capacitor 142 and the second sampling capacitor 146 can be coupled between the chopping circuit 122 and the ADC 150. The first compensation capacitor 144 and the second compensation capacitor 148 can be cross-coupled between the chopping circuit 122 and the ADC 150.

[0033] The first sampling capacitor 142 can include a first physical separation between the first capacitor terminal conductor and the second capacitor terminal conductor. The first compensation capacitor 144 can include a second physical separation between the first capacitor terminal conductor and the second capacitor terminal conductor. The second physical separation can be different than the first physical separation. For example, Figure 1 The first sampling capacitor 142 is shown as having a larger physical separation than the first compensation capacitor 144. The smaller physical separation of the first compensation capacitor 144 can result in the first compensation capacitor 144 having a larger voltage-dependent effect than the first sampling capacitor 142. The second sampling capacitor 146 can have the same physical separation as the first sampling capacitor 142, or can have a different physical separation. The second compensation capacitor 148 can have the same physical separation as the first compensation capacitor 144, or can have a different physical separation.

[0034] The capacitance of the first sampling capacitor 142 can be the same as the capacitance of the second sampling capacitor 146, or the capacitance of the first sampling capacitor 142 can be different than the capacitance of the second sampling capacitor 146. The capacitance of the first compensation capacitor 144 can be the same as the capacitance of the second compensation capacitor 148, or the capacitance of the first compensation capacitor 144 can be different than the capacitance of the second compensation capacitor 148. One or more capacitors in the capacitor network 140 can include one or more of a parallel plate structure or a finger structure. One or more capacitors in the capacitor network 140 can form part of a monolithic integrated circuit, for example can include capacitors fabricated during an integrated circuit fabrication process.

[0035] The reference circuit 126 can accept as inputs the signal on the ground reference pin 102, the signal on the voltage reference pin 108, and a pulse density modulated (PDM) signal on the PDM node 128. The signal on the ground reference pin 102 can be a ground reference or a floating ground reference, for example, can include a ground reference of a vehicle. The signal on the voltage reference pin 108 can include a reference voltage signal, for example, can be used to provide a reference for the ADC 150. The PDM signal received on the PDM node 128 can be a clock signal that matches the frequency of the signal on the clock input pin 123, or the frequencies can be different. The phase of the signal on the PDM node 128 can be different from the phase of the signal on the clock input pin 123. The received PDM signal can be an analog or digital duty cycle modulated signal, for example, can allow selection of an effective reference voltage provided to the ADC 150.

[0036] The reference circuit 126 can include one or more switches configured to provide a chopped representation of the signal received on the ground reference pin 102 to the first terminal conductor of the second reference capacitor 134 and to provide a chopped representation of the signal received on the voltage reference pin 108 to the first terminal conductor of the first reference capacitor 132. The second terminal conductor of the first reference capacitor 132 can be coupled to the second input 154 and the second terminal conductor of the second reference capacitor 134 can be coupled to the first input 152.

[0037] The ADC system 100 can be configured such that the signal on the digital output connection 156 is defined by Equation 5.

[0038] Equation 5

[0039] In Equation 5, is a digital representation of the analog signal carried by the digital output connection 156, is the voltage of the unit under test 114, is an equivalent sampling capacitance defined by Equation 6, is the capacitance of the first reference capacitor 132 and the second reference capacitor 134, is the voltage of the signal on the voltage reference pin 108. The equivalent sampling capacitance is defined by Equation 6.

[0040] Equation 6

[0041] In Equation 6, is the capacitance of the first sampling capacitor 142 and the second sampling capacitor 146, is the capacitance of the first compensation capacitor 144 and the second compensation capacitor 148.

[0042] Equation 6 shows that the cross-coupled compensation capacitors 144 and 148 have a subtractive effect with respect to the sampling capacitors 142 and 146. The capacitances of the cross-coupled compensation capacitors 144 and 148 can at least partially offset the capacitances of the sampling capacitors 142 and 146. The voltage-dependent signal contributions of the cross-coupled compensation capacitors 144 and 148 can at least partially cancel the voltage-dependent signal contributions of the sampling capacitors 142 and 146. In this way, the compensation capacitors 144 and 148 can help manage the voltage-dependent effects of the sampling capacitors 142 and 146. For example, the compensation capacitors 144 and 148 can reduce the voltage-dependent effects of the sampling capacitors 142 and 146.

[0043] If the nonlinearities of the compensation capacitors 144 and 148 are the same as the nonlinearities of the sampling capacitors 142 and 146 (i.e., the nonlinear voltage coefficients are the same), then the equivalent capacitances can have the same nonlinearities as the sampling capacitors 142 and 146 (i.e., the nonlinear voltage coefficients can be the same). However, if the nonlinearities of the compensation capacitors 144 and 148 are different from the nonlinearities of the sampling capacitors 142 and 146, then the equivalent capacitances can have nonlinearities that are different from the sampling filters 142 and 146 (e.g., can include reduced nonlinearities). Equation 7 defines the equivalent sampling capacitances from sampling capacitors and compensation capacitors with second-order voltage coefficients.

[0044] Equation 7

[0045] In Equation 7, is a second-order voltage coefficient of the sampling capacitors, is a first-order voltage coefficient of the compensation capacitors. Equation 7 can also be expressed as the equation in Equation 8.

[0046] Equation 8

[0047] Equation 8 shows that the equivalent sampling capacitances can be expressed in terms of the base capacitances and a second-order voltage coefficient . Equation 9 shows the condition in which the second-order voltage coefficient can equal zero.

[0048] Equation 9

[0049] The capacitance value and / or voltage coefficient of one or more of the first sampling capacitor 142, the second sampling capacitor 146, the first compensation capacitor 144, or the second compensation capacitor 148 can be selected to help achieve a desired substantially effective sampling capacitance while minimizing second order voltage coefficients. For example, the zero voltage capacitances of the sampling capacitor and the compensation capacitor can be selected to achieve a desired base capacitance, and the voltage coefficients can be selected to achieve a desired voltage dependent effect. In one example, the capacitance and / or voltage coefficients can be selected such that the sampling capacitance multiplied by the sampling voltage coefficient equals the compensation capacitance multiplied by the compensation voltage coefficient, for example can result in an effective capacitance that has no voltage coefficient (i.e., as shown in Equation 9).

[0050] Figure 2 is a schematic diagram of an example of portions of the circuit 200 for managing voltage dependent effects of capacitors. Figure 2 The circuit 200 is shown to include a capacitor 142 coupled between a first port 224 and a second port 252, and a compensation capacitor 144 coupled between the first port 224 and a third port 254. The circuit 200 can also include a compensation circuit 250, a signal processor 260, and an output node 256.

[0051] The first port 224 can receive an input signal, for example can include a signal to be one or more of measured, amplified, or converted. The circuit 200 can be a single ended ADC circuit that converts a signal received on the first port 224 to a digital signal representation on the output node 256. The circuit 200 can be an amplifier that amplifies a signal received on the first port 224 for output on the output node 256.

[0052] The capacitor 142 can be configured similar to the capacitor 142 of Figure 1 , or can differ in one or more aspects. The compensation capacitor 144 can be configured similar to the compensation capacitor 144 of Figure 1 , or can differ in one or more aspects. The capacitance of the capacitor 142 can differ from the capacitance of the first compensation capacitor 144. The physical terminal spacing of the capacitor 142 can differ from the physical terminal spacing of the compensation capacitor 144. One or more voltage coefficients of the capacitor 142 can differ from one or more voltage coefficient values of the compensation capacitor 144. The different voltage coefficients between the capacitor 142 or the compensation capacitor 144 can be implemented using one or more of a different plate spacing between the capacitor 142 and the compensation capacitor 44, a different dielectric material, or a different capacitor design. The different voltage coefficients can be implemented by using different finger spacings in a finger capacitor, for example can include a finger capacitor on a monolithic integrated circuit. In one example, the finger spacing can be more easily adjusted than the dielectric material or the capacitor design.

[0053] The compensation circuit 250 can include analog components, digital components, or both. The compensation circuit 250 can be configured such that a capacitance coupled between the first port 224 and the third port 254 has a subtractive effect with respect to a capacitance coupled between the first terminal 224 and the second terminal 252. For example, the compensation circuit 250 can include a differential ADC similar to Figure 1 The subtraction effect provided by the compensation circuit 250 can be implemented in the digital domain, the analog domain, or both. For example, the compensation circuit 250 can convert voltage and / or current signals received on the second port 252 and the third port 254 to digital signals, and then subtract the digital signal corresponding to the compensation capacitor 144 from the digital signal corresponding to the capacitor 142.

[0054] The first capacitance of the capacitor 142 and the second capacitance of the compensation capacitor 144 can be selected such that a difference between the first capacitance and the second capacitance provides a desired effective capacitance between the first port 224 and the second port 252. One or more voltage coefficients of the compensation capacitor 144 can be selected to at least partially offset one or more voltage coefficient values of the capacitor 142.

[0055] There can be more than two capacitors, for example there can be three capacitors, four capacitors, five capacitors, or six capacitors. The capacitors can be combined by the compensation circuit 250, for example the combination can include using addition, subtraction, or other calculations. Using more than two capacitors can help allow multiple voltage coefficients to be cancelled out. For example, a first compensation capacitor can be configured to compensate for a first order voltage coefficient, and a second compensation capacitor can be configured to compensate for a second order voltage coefficient. The compensation capacitors as a whole can be configured to compensate for one or more voltage dependent effects of the capacitor 142. For example, one or more of the compensation capacitors can subtract from the effects of the capacitor 142, and one or more of the compensation capacitors can add to the capacitor 142.

[0056] In one example, a series of cascaded analog circuits can be used to at least partially cancel out voltage dependent effects of the capacitor 142 and the first compensation capacitor 144. For example, two non-linear amplifiers can be cascaded, where the non-linearity of the second amplifier at least partially cancels out the non-linearity in the second amplifier.

[0057] The signal processor 260 can provide further analog and / or digital signal processing to the signal from the compensation circuit 250. The signal processor 260 can be a signal processing circuit. In one example, the compensation circuit 250 and the signal processor 260 can be combined. For example, the compensation circuit 250 and the signal processor 260 can together comprise a differential ADC. In one example, the signal processor 260 can not be included, and the compensation circuit 250 can be directly coupled to the output node 256. The compensation circuit 250, the signal processor 260, or one or more of the compensation circuit 250 in combination with the signal processor 260 can form one or more of a filter, an amplifier, an integrator, a summing circuit, or an ADC.

[0058] Figure 3 is a plot of lab record data showing an example of an operating portion of a circuit for managing voltage-dependent effects of a capacitor. Figure 3 Voltage nonlinearities are shown for a capacitor with a 0.65 micron plate separation, a capacitor with a 1.2 micron plate separation. Figure 3 Nonlinearities are shown in parts per million (ppm) at different voltages, which describe the nonlinearity as a ratio of the zero-voltage capacitance. The nonlinearity of the smaller plate separation capacitor is greater than the nonlinearity of the larger plate separation capacitor, for example possibly due to a larger volume gradient in the dielectric. The nonlinearities of both capacitors increase with increasing voltage, for example possibly due to an increase in the voltage gradient in the dielectric.

[0059] Figure 3 A combined nonlinearity is also shown, obtained by subtracting the 0.65 micron plate separation capacitor from the 1.2 micron plate separation capacitor, which has three times the capacitance of the 0.65 micron plate separation capacitor. Figure 3 It is shown that the effective nonlinearity is below 20 ppm over a voltage range of 0 volts to 100 volts. In this way, when the effect of the 1.2 micron plate separation capacitor is subtracted from the 0.65 micron plate separation capacitor, an effective capacitor is obtained with a voltage coefficient close to zero.

[0060] Figure 4is a schematic diagram illustrating an example of a method 400 for operating portions of a system for managing voltage-dependent effects of a capacitor. At 405, a first capacitor can be used, the first capacitor including a first physical separation between a first capacitor terminal conductor of the first capacitor and a first capacitor second capacitor terminal conductor of the first capacitor to provide a positive voltage-related contribution. At 410, a negative voltage-related contribution can be provided using a second capacitor, the second capacitor including a second physical separation between a first capacitor terminal conductor of the second capacitor and a second capacitor terminal conductor of the second capacitor, wherein the second physical separation is different than the first physical separation. At 415, a compensation circuit can receive the positive voltage-related contribution and the negative voltage-related contribution, wherein the negative voltage-related contribution at least partially cancels the positive voltage-related contribution. The order of the steps shown is not intended to limit the order in which the steps are performed. In one example, two or more steps can be performed simultaneously or at least partially simultaneously.

[0061] The first capacitance value in step 405 and the second capacitance value in step 410 can be selected based at least in part on respective voltage coefficients of the first capacitor and the second capacitor. For example, the capacitance values can be selected to minimize non-linearity in a combined effective capacitance value. One or more of the capacitance values can be selected based at least in part on experiments performed using a capacitor including the first physical separation and one capacitor including the second physical separation. For example, one or more of the capacitance values can be tuned to achieve a desired integrated voltage-related effect.

[0062] The methods and systems described herein are believed to be applicable to all capacitor constructions, and are not intended to be limited to metal-against-metal capacitors.

[0063] Figure 5This is a block diagram illustrating examples of portions of a machine 500 on which one or more portions of this disclosure may be implemented. As described herein, examples may include logic or multiple components or mechanisms in the machine 500, or that can be operated by them. A circuit (e.g., a processing circuit) is a collection of circuits implemented in a tangible entity of the machine 500, including hardware (e.g., simple circuits, gates, logic, etc.). Circuit membership may be flexible over time. A circuit includes components that can perform a particular operation individually or in combination during operation. In one example, the hardware of a circuit may be designed immutably to perform a particular operation (e.g., hardwired). In one example, the hardware of a circuit may include physically connected components (e.g., execution units, transistors, simple circuits, etc.) that include machine-readable media physically modified (e.g., magnetic, electrical, movable placement of immutable aggregated particles, etc.) to encode instructions for a particular operation. When the physical components are connected, the basic electrical characteristics of the hardware components change, for example, from an insulator to a conductor, and vice versa. Instructions enable embedded hardware (e.g., execution units or loading mechanisms) to create members of a circuit within the hardware via variable connections, to perform specific operations during operation. Thus, in one example, a machine-readable medium element is part of the circuit, or another component communicatively coupled to the circuit during device operation. In one example, any physical component can be used in more than one member of more than one circuit. For example, during operation, an execution unit may be used in a first circuit of a first circuit at one point in time and reused by a second circuit in the first circuit, or reused by a third circuit of the second circuit at a different time. The following are additional examples of these components relative to machine 500.

[0064] In alternative embodiments, machine 500 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, machine 500 may operate as a server machine, a client machine, or both in a server-client network environment. In one example, machine 500 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 500 may be a personal computer (PC), tablet computer, set-top box (STB), personal digital assistant (PDA), mobile phone, network device, network router, switch, or bridge, or any machine capable of executing instructions (sequential or otherwise) specifying the actions to be taken by that machine. Furthermore, although only a single machine is shown, the term "machine" should also be considered to include any collection of machines that individually or jointly execute a set (or more) of instructions to perform any one or more methods discussed herein, such as cloud computing, Software as a Service (SaaS), or other computer cluster configurations.

[0065] The machine (e.g., computer system) 500 can include a hardware processor 502 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 504, a static memory (e.g., memory or storage for firmware, microcode, a basic- input-output (BIOS), a unified extensible firmware interface (UEFI), etc.) 506, and a mass storage 508 (e.g., hard disk drive, tape drive, flash storage, or other block devices), some or all of which can communicate with one another via an interlink (e.g., bus) 530. The machine 500 can further include a display unit 510, an alphanumeric input device 512 (e.g., a keyboard), and a user interface (UI) navigation device 514 (e.g., a mouse). In one example, the display unit 510, input device 512 and UI navigation device 514 are a touch screen display. The machine 500 can additionally include a storage device (e.g., drive unit) 508, a signal generation device 518 (e.g., a speaker), a network interface device 520, and one or more sensors 516, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine 500 can include an output controller 528, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

[0066] The processor 502, the main memory 504, the static memory 506, or the mass storage 508 can be or include machine-readable media 522 on which is stored one or more sets of data structures or instructions 524 (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions 524 can also reside, completely or at least partially, within the processor 502, the main memory 504, the static memory 506, or the mass storage 508 during execution thereof by the machine 500. In one example, one or any combination of the hardware processor 502, the main memory 504, the static memory 506, or the mass storage 508 can constitute machine-readable media 522. While the machine-readable medium 522 is illustrated as a single medium, the term “machine-readable medium” can include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) configured to store the one or more instructions 524.

[0067] The term“machine-readable medium” can include any medium that is capable of storing, encoding, or carrying instructions for execution by the machine 500 and that cause the machine 500 to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting machine-readable medium examples can include solid-state memories, optical media, magnetic media, and signals (e.g., radio frequency signals, other optical-based signals, audio signals, etc.). In one example, the non-transitory machine-readable medium includes a machine-readable medium with a plurality of particles having invariant (e.g., rest) mass, such as those of a physical object. Thus, the non-transitory machine-readable medium is one that does not include a transitory propagating signal. Specific examples of non-transitory machine-readable media can include nonvolatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0068] In one example, the information stored or otherwise provided on the machine- readable medium 522 can represent instructions 524, such as the instructions 524 themselves or a format from which the instructions 524 can be derived. Such formats from which the instructions 524 can be derived can include source code, encoded instructions (e.g., in compressed or encrypted form), packaged instructions (e.g., into a package), etc. The information representing the instructions 524 in the machine-readable medium 522 can be processed by the processing circuitry into instructions to implement any of the operations discussed herein. For example, deriving the instructions 524 from the information (e.g., processing by the processing circuitry) can include compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, unencrypting, packaging, unpackaging, or otherwise manipulating the information into the instructions 524.

[0069] In one example, the derivation of the instructions 524 can include assembly, compilation, or interpretation of the information (e.g., by the processing circuitry) to create the instructions 524 from some intermediate or preprocessed format provided by the machine-readable medium 522. When the information is provided in multiple parts, it can be assembled, unpacked, and modified to create the instructions 524. For example, the information can be in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or more remote servers. The source code packages can be encrypted when transmitted over a network, and decrypted, un-compressed, assembled (e.g., linked), compiled or interpreted (e.g., compiled into a library, standalone executable, etc.) at the local machine as necessary, and executed by the local machine.

[0070] The instructions 524 can further be transmitted or received using a transmission medium via the network interface device 520 utilizing any one of a number of transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks can include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), LoRa / LoRaWAN, or satellite communications networks, a mobile telephone network (e.g., a cellular network such as a 3G, 4G LTE / LTE-A, or 5G standard-based network), a plain old telephone (POTS) network, and a wireless data network (e.g., a Wi-Fi® network, IEEE 802.15.4 standard networks, peer-to-peer (P2P) networks, among others). In one example, the network interface device 520 can include one or more physical jacks (e.g., Ethernet, coaxial, or phone jacks), or one or more antennas to connect to the communications network 526. In one example, the network interface device 520 can include a plurality of antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) techniques. The term “transmission medium” shall be taken to include any intangible medium that is capable of storing, encoding, or carrying the instructions for execution by the machine 500, and includes digital or analog communications signals or other intangible media to facilitate communication of such software. The transmission medium is a machine-readable medium.

[0071] Additional Descriptions and Examples

[0072] Example 1 is a system for reducing voltage-dependent effects of a first capacitor caused by a first voltage, the system comprising: a first capacitor comprising a first physical separation between a first capacitor terminal conductor of the first capacitor and a second capacitor terminal conductor of the first capacitor; a second capacitor comprising a second physical separation between a first capacitor terminal conductor of the second capacitor and a second capacitor terminal conductor of the second capacitor, wherein the second physical separation is different than the first physical separation; and a compensation circuit arranged to receive and at least partially offset a voltage-dependent signal contribution from each of the first capacitor and the second capacitor for output to a signal processing circuit.

[0073] In Example 2, the subject matter of Example 1 optionally includes wherein the compensation circuit comprises a switched capacitor circuit arranged to receive a charge contribution from each of the first capacitor and the second capacitor, and wherein a second voltage-dependent contribution from the second capacitor at least partially offsets a first voltage-dependent contribution from the first capacitor.

[0074] In Example 3, the subject matter of Example 2 optionally includes wherein the second voltage-dependent contribution is subtracted from the first voltage-dependent contribution.

[0075] In Example 4, the subject matter of any one or more of Examples 1-3 optionally includes wherein the compensation circuit includes a digital circuit, wherein the digital circuit is configured to receive a first digital representation corresponding to the first capacitor and a second digital representation corresponding to the second capacitor, wherein the digital circuit is configured to use the first digital representation and the second digital representation to at least partially offset voltage-dependent effects of the first capacitor.

[0076] In Example 5, the subject matter of any one or more of Examples 1-4 optionally includes wherein a first capacitance value of the first capacitor and a second capacitance value of the second capacitor are selected such that a difference between a voltage-dependent contribution of the first capacitor and a voltage-dependent contribution of the second capacitor provides a particular voltage-dependent effect in the system.

[0077] In Example 6, the subject matter of Example 5 optionally includes wherein the first capacitance value and the second capacitance value are further selected such that a first capacitance value of the first capacitor multiplied by a first voltage coefficient is equal to a second capacitance value of the second capacitor multiplied by a second voltage coefficient.

[0078] In Example 7, the subject matter of any one or more of Examples 1-6 optionally includes wherein the first capacitance value of the first capacitor is greater than the second capacitance value of the second capacitor, and the first physical separation is greater than the second physical separation.

[0079] In Example 8, the subject matter of any one or more of Examples 1-7 optionally includes wherein the signal processing circuit includes at least one of a filter, an amplifier, an integrator, a summing circuit, or an analog-to-digital converter (ADC).

[0080] In Example 9, the subject matter of any one or more of Examples 1-8 optionally includes a differential analog-to-digital converter (ADC) comprising: a first differential input terminal coupled to a second capacitor terminal conductor of the first capacitor; and a second differential input terminal coupled to a second capacitor terminal conductor of the second capacitor, wherein a first capacitor terminal conductor of the first capacitor and a first capacitor terminal conductor of the second capacitor are coupled together.

[0081] In Example 10, the subject matter of Example 9 optionally includes: a third capacitor including a third physical separation between a first capacitor terminal conductor of the third capacitor and a second capacitor terminal conductor of the third capacitor, wherein the second capacitor terminal conductor of the third capacitor is connected to the second differential input terminal; and a fourth capacitor including a fourth physical separation between a first capacitor terminal conductor of the fourth capacitor and a second capacitor terminal conductor of the fourth capacitor, wherein the first capacitor terminal conductor of the fourth capacitor is connected to the first capacitor terminal conductor of the third capacitor, wherein the second capacitor terminal conductor of the fourth capacitor is coupled to the first differential input terminal.

[0082] In Example 11, the subject matter of Example 10 optionally includes: wherein (1) the first physical separation is equal to the third physical separation, (2) a first capacitance of the first capacitor is equal to a third capacitance of the third capacitor, (3) the second physical separation is equal to the fourth physical separation, and (4) a second capacitance of the second capacitor is equal to a fourth capacitance of the fourth capacitor.

[0083] In Example 12, the subject matter of any one or more of Examples 1-11 optionally includes: wherein the system is included on a monolithic integrated circuit.

[0084] In Example 13, the subject matter of any one or more of Examples 1-12 optionally includes: wherein a construction of the first capacitor and the second capacitor includes at least one of a parallel plate type or a finger type.

[0085] Example 14 is a method for reducing a non-linear effect of a first capacitor caused by a first voltage coefficient of the first capacitor, the method comprising: using a first capacitor to provide a first voltage dependent contribution, the first capacitor including a first physical separation between a first capacitor terminal conductor of the first capacitor and a second capacitor terminal conductor of the first capacitor; using a second capacitor to provide a second voltage dependent contribution, the second capacitor including a second physical separation between a first capacitor terminal conductor of the second capacitor and a second capacitor terminal conductor of the second capacitor, wherein the second physical separation is different than the first physical separation; and using a compensation circuit to receive the first voltage dependent contribution and the second voltage dependent contribution, wherein the second voltage dependent contribution at least partially offsets the first voltage dependent contribution.

[0086] In Example 15, the subject matter of Example 14 optionally includes: using a first capacitance value of the first capacitor selected based at least in part on a voltage coefficient of each of the first capacitor and the second capacitor; and using a second capacitance value of the second capacitor selected based at least in part on a voltage coefficient of each of the first capacitor and the second capacitor.

[0087] In Example 16, the subject matter of Example 15 optionally includes, wherein using the first capacitance value and using the second capacitance value is to reduce non-linearity in a combined effective capacitance value.

[0088] In Example 17, the subject matter of any one or more of Examples 14-16 optionally includes using a first capacitance value of the first capacitor selected based at least in part on experiments performed on capacitors including the first physical separation and capacitors including the second physical separation; and using a second capacitance value of the second capacitor selected based at least in part on experiments performed on capacitors including the first physical separation and capacitors including the second physical separation.

[0089] Example 18 is a system for reducing non-linear effects of a first capacitor caused by a first voltage coefficient of the first capacitor, the system comprising: the first capacitor coupled between a first port and a second port; and a second capacitor coupled between the first port and a third port, wherein the system is configured such that an effect of a capacitance coupled between the first port and the third port relative to an effect of a capacitance coupled between the first terminal and the second terminal has a subtractive effect, wherein the first voltage coefficient of the first capacitor is different than a second voltage coefficient of the second capacitor.

[0090] In Example 19, the subject matter of Example 18 optionally includes, wherein the different voltage coefficients of the first capacitor and the second capacitor are implemented at least in part using at least one of a different plate separation, a different dielectric material, or a different capacitor design between the first capacitor and the second capacitor.

[0091] In Example 20, the subject matter of any one or more of Examples 18-19 optionally includes, wherein a first capacitance value of the first capacitor and a second capacitance value of the second capacitor are such that a difference between the first capacitance value and the second capacitance value provides a desired effective capacitance between the first port and the second port.

[0092] Example 21 is at least one machine readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-20.

[0093] Example 22 is an apparatus comprising any of Examples 1-20.

[0094] Example 23 is a system of any of Examples 1-20.

[0095] Example 24 is a method of any of Examples 1-20.

[0096] Each of the above non-limiting aspects can exist independently, or can be combined in various permutations or combinations with one or more of the other aspects or other subject matter described in this document.

[0097] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the application can be practiced. These embodiments are also referred to as "examples." Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0098] To the extent usage of terms does not consistent between this document and any document incorporated by reference, the usage in this document controls.

[0099] In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more, independent of any other instances or usages of "at least one" or "one or more." In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In this document, the terms "including" and "comprising" are used as synonymous for the terms "including" and "comprising," respectively. Furthermore, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such terms in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0100] Method examples described herein can be machine or computer- implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code can form portions of computer program products. The program instructions of an implementation can be provided to a processor of a computer system, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer system or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flow diagrams and / or diagrams.

[0101] Further, in one example, code can be tangibly stored on one or more volatile, non-transitory, or non-volatile computer-readable media, such as during

[0102] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be utilized, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to allow a quick determination of the disclosure's purpose. It is submitted with the sole purpose of enabling a quick determination of the disclosure's purpose. It is submitted with the sole purpose of enabling a quick determination of the disclosure's purpose. Furthermore, in the above Detailed Description, various features are grouped together in one or more embodiments for the purpose of streamlining the disclosure. This should not be interpreted as intending that the disclosed features are essential to any single embodiment. Rather, inventive subject matter can lie in less than all features of a particular disclosed embodiment. Therefore, the following claims are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment, and it is made apparent that special features of the embodiments can be utilized without reference to other features, and that certain claims can be directed to a sub-combination of features. The scope of the application should be determined, therefore, with reference to the appended claims and pertinent portions of the detailed description, rather than the summary.

Claims

1. A system for reducing the nonlinear effect of a first capacitor caused by a first voltage coefficient, the system comprising: The first capacitor includes a first physical gap between a first capacitor terminal conductor and a second capacitor terminal conductor of the first capacitor, wherein the first physical gap is the gap between the capacitor plates of the first capacitor; The second capacitor includes a second physical interval between a first capacitor terminal conductor and a second capacitor terminal conductor of the second capacitor, wherein the second physical interval is different from the first physical interval, and wherein the second physical interval is the interval between the capacitor plates of the second capacitor; and A compensation circuit is arranged to receive and at least partially offset the voltage-dependent signal contribution from each of the first capacitor and the second capacitor, for output to a signal processing circuit.

2. The system of claim 1, wherein the compensation circuit includes a switched capacitor circuit arranged to receive charge contributions from each of the first capacitor and the second capacitor, and wherein a second voltage-dependent contribution from the second capacitor is at least partially offset from a first voltage-dependent contribution from the first capacitor.

3. The system of claim 2, wherein the second voltage-related contribution is subtracted from the first voltage-related contribution.

4. The system of claim 1, wherein the compensation circuit includes digital circuitry, wherein the digital circuitry is configured to receive a first digital representation corresponding to the first capacitor and a second digital representation corresponding to the second capacitor, wherein the digital circuitry is configured to use the first digital representation and the second digital representation to at least partially offset the voltage-dependent effect of the first capacitor.

5. The system of claim 1, wherein the first capacitance value of the first capacitor and the second capacitance value of the second capacitor are selected such that the difference between the voltage-dependent contribution of the first capacitor and the voltage-dependent contribution of the second capacitor provides a specific voltage-dependent effect in the system.

6. The system of claim 5, wherein the first capacitance value and the second capacitance value are further selected such that the first capacitance value multiplied by the first voltage coefficient of the first capacitor is equal to the second capacitance value multiplied by the second voltage coefficient of the second capacitor.

7. The system of claim 1, wherein the first capacitance value of the first capacitor is greater than the second capacitance value of the second capacitor, and the first physical interval is greater than the second physical interval.

8. The system of claim 1, wherein the signal processing circuitry comprises at least one of a filter, an amplifier, an integrator, a summing circuit, or an analog-to-digital converter (ADC).

9. The system according to claim 1, comprising: Differential analog-to-digital converters (ADCs) include: The first differential input terminal is coupled to the second capacitor terminal conductor of the first capacitor; and The second differential input terminal is coupled to the second capacitor terminal conductor of the second capacitor, wherein the first capacitor terminal conductor of the first capacitor and the first capacitor terminal conductor of the second capacitor are coupled together.

10. The system according to claim 9, comprising: The third capacitor includes a third physical interval between the first capacitor terminal conductor and the second capacitor terminal conductor of the third capacitor, wherein the second capacitor terminal conductor of the third capacitor is connected to the second differential input terminal; and A fourth capacitor includes a fourth physical space between a first capacitor terminal conductor and a second capacitor terminal conductor of the fourth capacitor, wherein the first capacitor terminal conductor of the fourth capacitor is connected to the first capacitor terminal conductor of the third capacitor, and wherein the second capacitor terminal conductor of the fourth capacitor is coupled to the first differential input terminal.

11. The system of claim 10, wherein the first physical interval is equal to the third physical interval, the first capacitance of the first capacitor is equal to the third capacitance of the third capacitor, the second physical interval is equal to the fourth physical interval, and the second capacitance of the second capacitor is equal to the fourth capacitance of the fourth capacitor.

12. The system of claim 1, wherein the system is included on a monolithic integrated circuit.

13. The system of claim 1, wherein the first capacitor and the second capacitor are constructed of at least one of parallel plate type or finger type.

14. A method for reducing the nonlinear effect of a first capacitor caused by a first voltage coefficient of the first capacitor, the method comprising: The first capacitor is used to provide a first voltage-related contribution, the first capacitor including a first physical interval between a first capacitor terminal conductor and a second capacitor terminal conductor of the first capacitor, wherein the first physical interval is the interval between the capacitor plates of the first capacitor; A second capacitor is used to provide a second voltage-related contribution, the second capacitor including a second physical interval between a first capacitor terminal conductor and a second capacitor terminal conductor of the second capacitor, wherein the second physical interval is the interval between the capacitor plates of the second capacitor, and wherein the second physical interval is different from the first physical interval; and A compensation circuit is used to receive the first voltage-related contribution and the second voltage-related contribution, wherein the second voltage-related contribution is at least partially offset from the first voltage-related contribution.

15. The method of claim 14, comprising: The first capacitance value of the first capacitor is selected based at least in part on the voltage coefficients of the first capacitor and the second capacitor; and The second capacitance value of the second capacitor is selected based at least in part on the voltage coefficients of the first capacitor and the second capacitor, respectively.

16. The method of claim 15, wherein the use of the first capacitance value and the use of the second capacitance value are for reducing nonlinearity in the combined effective capacitance value.

17. The method of claim 14, comprising: The first capacitance value of the first capacitor is selected based at least in part on experiments conducted on a capacitor including the first physical interval and a capacitor including the second physical interval. and The second capacitance value of the second capacitor is selected based at least in part on experiments conducted on a capacitor including the first physical interval and a capacitor including the second physical interval.

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