Method, computer equipment and medium for realizing important product data functions through software

Abstract

The present application relates to the field of computer technology and provides a method, computer device and medium for realizing important product data functions by software. The technical solution of the present application avoids the overall update of hardware logic, can make full use of the offloading and virtualization technology of dedicated hardware, and at the same time meets the requirements of dynamic modification, cost reduction, fast response, reduced access delay and improved performance.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, computer equipment and medium for implementing important product data functions using software. Background Art

[0002] Vital Product Data (VPD) is a collection of configuration and information data related to a specific set of hardware or software. It records important information such as the device's part number (PN), serial number (SN), unique identification software and hardware, and is used to store information such as device performance or faults. Devices that comply with the peripheral component interconnect express (PCIE) standard are connected to the host through the PCIE bus. PCIE devices can have a VPD function, so that the performance parameters or fault information of the PCIE device can be backfilled into the corresponding VPD, which is convenient for debugging and using the device. In addition, PCIE devices with VPD functions can provide system software and hardware information for system administrators to make decisions at the system level. In the prior art, in order to meet the user's demand for customized input and output and the application of network virtualization technology, dedicated hardware is used to implement the offloading of network transmission functions and to provide various PCIE devices using virtualization technology. However, the hardware-based PCIE devices in the prior art involve the overall update of the hardware logic in terms of reading and writing VPD information, which makes it difficult to meet the requirements of dynamic modification and cost reduction. The existing software-based VPD information reading and writing mechanism has high access latency, which is not conducive to fast response and performance improvement.

[0003] To this end, the present application provides a method, computer device and medium for implementing important product data functions in software, avoiding the overall update of hardware logic, and making full use of the offloading and virtualization technology of dedicated hardware, while meeting the requirements of dynamic modification, cost reduction, rapid response, reduced access delay and improved performance. Summary of the invention

[0004] In a first aspect, the present application provides a method for implementing an important product data function with software. The method comprises: simulating and generating a quick peripheral component interconnect topology through system simulator software of a data processor, wherein the quick peripheral component interconnect topology comprises an upstream port, at least one downstream port and at least one quick peripheral component interconnect device of a first device type, the system simulator software runs in the memory of the data processor, the upstream port is connected to the root port of the host machine, and the at least one quick peripheral component interconnect device of the first device type has an important product data function; through the system simulator software, when initializing the upstream port, allocating in the memory an upstream port read-only important product data information memory space and an upstream port readable and writable important product data information memory space exclusively occupied by the upstream port, and when initializing the at least one downstream port, allocating in the memory a downstream port read-only important product data information memory space and a at least one downstream port readable and writable important product data information memory space shared between the at least one downstream port. At least one downstream port exclusively used by one downstream port can read and write important product data information memory space, and when initializing at least one peripheral component interconnect express device of the first device type, a first device type peripheral component interconnect express device read-only important product data information memory space shared between at least one peripheral component interconnect express device of the first device type and at least one first device type peripheral component interconnect express device read and write important product data information memory space exclusively used by at least one peripheral component interconnect express device of the first device type are allocated in the memory; by using the system simulator software, a first transaction layer data packet message including read important product data information sent by the host machine is parsed to perform an operation of reading important product data information, or a second transaction layer data packet message including write important product data information sent by the host machine is parsed to perform an operation of writing important product data information.

[0005] Through the first aspect of the present application, it is realized to distinguish and manage read-only important product data information and read-write important product data information, and to manage uplink ports, downlink ports and various types of quick peripheral component interconnect devices separately; different memory spaces are allocated during initialization, so that the layout of important product data information can be set according to the specifications of relevant protocols, thereby improving the read and write operations of important product data information and helping to improve operational flexibility; because it is the system simulator software that relies on the data processor to optimize the initialization process, parse the transaction layer data packet message, execute the read important product data information operation and execute the write important product data information operation, therefore, it is not necessary to update the hardware logic every time the important product data information of the quick peripheral component interconnect device is dynamically modified, avoiding the overall update of the hardware logic, and making full use of the unloading and virtualization technology of dedicated hardware; by distinguishing quick peripheral component interconnect devices of different device types, providing shared memory space for quick peripheral component interconnect devices of the same device type and allocating device-exclusive memory space, improving resource utilization, and also facilitating management and synchronization in combination with the common functional characteristics between devices of the same device type; meeting the requirements of dynamic modification, cost reduction, fast response, reduced access delay and improved performance.

[0006] In a possible implementation of the first aspect of the present application, when the first transaction layer data packet message indicates reading important product data information associated with the upstream port, the operation of reading the important product data information includes reading data from the starting position of the upstream port read-only important product data information memory space and then offsetting the data to the position indicated by the first transaction layer data packet message, and then storing the data in the important product data capability set configuration space associated with the express peripheral component interconnect topology at the position indicated by the first transaction layer data packet message.

[0007] In a possible implementation of the first aspect of the present application, when the second transaction layer data packet message indicates writing important product data information associated with the uplink port, the operation of writing the important product data information includes obtaining data from the position indicated by the second transaction layer data packet message in the important product data capability set configuration space, and then writing the data to the starting position of the uplink port's readable and writable important product data information memory space and then offsetting it to the position indicated by the second transaction layer data packet message.

[0008] In a possible implementation manner of the first aspect of the present application, the important product data information associated with the upstream port includes a maximum payload size and a maximum read request size.

[0009] In a possible implementation of the first aspect of the present application, when the first transaction layer data packet message indicates reading important product data information associated with a first downstream port among the at least one downstream port, the operation of reading the important product data information includes reading data from the starting position of the downstream port read-only important product data information memory space and then offsetting the data to the position indicated by the first transaction layer data packet message, and then storing the data in the important product data capability set configuration space associated with the express peripheral component interconnect topology at the position indicated by the first transaction layer data packet message.

[0010] In a possible implementation of the first aspect of the present application, when the second transaction layer data packet message indicates that important product data information associated with a second downstream port in the at least one downstream port is to be written, the operation of writing the important product data information includes obtaining data from the position indicated by the second transaction layer data packet message in the important product data capability set configuration space, and then writing the important product data information in the at least one downstream port readable and writable memory space of the downstream port exclusively occupied by the second downstream port to the starting position of the readable and writable important product data information memory space of the downstream port, which is offset by the position indicated by the second transaction layer data packet message.

[0011] In a possible implementation manner of the first aspect of the present application, the important product data information associated with the first downstream port and the important product data information associated with the second downstream port both include a maximum payload size and a maximum read request size.

[0012] In a possible implementation manner of the first aspect of the present application, when the first transaction layer data packet message indicates reading important product data information associated with a first peripheral component interconnect express device in at least one peripheral component interconnect express device of the first device type, the operation of reading the important product data information includes reading data from a starting position of a read-only important product data information memory space of the first device type peripheral component interconnect express device and then offsetting the data to a position indicated by the first transaction layer data packet message, and then storing the data in an important product data capability set configuration space associated with the peripheral component interconnect express topology at a position indicated by the first transaction layer data packet message.

[0013] In a possible implementation manner of the first aspect of the present application, when the second transaction layer data packet message indicates that important product data information associated with a second peripheral component interconnect express device in at least one peripheral component interconnect express device of the first device type is to be written, the operation of writing the important product data information includes, after acquiring data from the position indicated by the second transaction layer data packet message in the important product data capability set configuration space, writing the data into the first device type peripheral component interconnect express device readable and writable important product data information memory space exclusively occupied by the second peripheral component interconnect express device in the at least one first device type peripheral component interconnect express device readable and writable important product data information memory space, and then offsetting the starting position of the first device type peripheral component interconnect express device readable and writable important product data information memory space exclusively occupied by the second peripheral component interconnect express device by the position indicated by the second transaction layer data packet message.

[0014] In a possible implementation manner of the first aspect of the present application, the important product data information associated with the first peripheral component interconnect express device and the important product data information associated with the second peripheral component interconnect express device both include a part number and a serial number, wherein the part number is shared between at least one peripheral component interconnect express device of the first device type, and the at least one peripheral component interconnect express device of the first device type has different serial numbers.

[0015] In a possible implementation manner of the first aspect of the present application, the PCI Express topology further includes at least one PCI Express device of the second device type, and the at least one PCI Express device of the second device type has an important product data function. The method further includes: using the system simulator software, when initializing the at least one PCI Express device of the second device type, allocating in the memory a second device type PCI Express device read-only important product data information memory space shared between the at least one PCI Express device of the second device type and at least one second device type PCI Express device read-write important product data information memory space exclusively occupied by the at least one PCI Express device of the second device type.

[0016] In a possible implementation manner of the first aspect of the present application, a first association relationship is satisfied between the first device type and the second device type, and the first association relationship is also satisfied between an operation of writing important product data information for a memory space in which important product data information can be read and written by the at least one first device type peripheral component interconnect Express device and an operation of writing important product data information for a memory space in which important product data information can be read and written by the at least one second device type peripheral component interconnect Express device.

[0017] In a possible implementation of the first aspect of the present application, the first device type is a network device type, the second device type is a storage device type, and the first association relationship defines the linkage between important product data associated with changing the remote direct memory access function of the network device type and important product data associated with changing the remote direct memory access of the storage device type.

[0018] In a possible implementation manner of the first aspect of the present application, the peripheral component interconnect express topology generated by simulation by the system simulator software includes a peripheral component interconnect express device that does not have an important product data function, and the system simulator software does not allocate memory space for the peripheral component interconnect express device that does not have the important product data function to perform an operation of reading important product data information or performing an operation of writing important product data information.

[0019] In a possible implementation of the first aspect of the present application, the method also includes: determining, through the system simulator software, whether the second transaction layer data packet message sent by the host machine and including information on writing important product data is an operation type write or a save type write, thereby selectively executing a reset operation of the data processor.

[0020] In a second aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0021] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0022] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A flowchart of a method for implementing important product data functions using software provided in an embodiment of the present application;

[0025] Figure 2 A reference provided for the embodiments of this application Figure 1 The method of implementing the important product data function in the software shown is to simulate and generate a schematic diagram of a quick peripheral component interconnection topology;

[0026] Figure 3 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0028] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0029] Figure 1 A flowchart of a method for implementing important product data functions in software provided in an embodiment of the present application. Figure 1 As shown, the method includes the following steps.

[0030] Step S101: simulating and generating a peripheral component interconnect express topology through system simulator software of a data processor, wherein the peripheral component interconnect express topology includes an upstream port, at least one downstream port, and at least one peripheral component interconnect express device of a first device type, the system simulator software runs in a memory of the data processor, the upstream port is connected to a root port of a host machine, and the at least one peripheral component interconnect express device of the first device type has an important product data function.

[0031] Step S103: by means of the system simulator software, when initializing the upstream port, an upstream port read-only important product data information memory space and an upstream port readable and writable important product data information memory space exclusively occupied by the upstream port are allocated in the memory; and, when initializing the at least one downstream port, a downstream port read-only important product data information memory space shared among the at least one downstream port and at least one downstream port readable and writable important product data information memory space exclusively occupied by the at least one downstream port are allocated in the memory; and, when initializing at least one peripheral component interconnect express device of the first device type, a first device type peripheral component interconnect express device read-only important product data information memory space shared among at least one peripheral component interconnect express device of the first device type and at least one first device type peripheral component interconnect express device readable and writable important product data information memory space exclusively occupied by at least one peripheral component interconnect express device of the first device type are allocated in the memory.

[0032] Step S105: Through the system simulator software, parse the first transaction layer data packet message including the reading important product data information sent by the host machine to execute the reading important product data information operation, or parse the second transaction layer data packet message including the writing important product data information sent by the host machine to execute the writing important product data information operation.

[0033] Figure 1The method for implementing the important product data function in software shown can be applied to application scenarios such as data centers, artificial intelligence, and cloud computing. These application scenarios require customization of input and output resources according to the needs of various customers, and require dynamic modification of the important product data (VPD) information of various types of quick peripheral component interconnect devices, so that equipment debugging and equipment use can be performed. In addition, in actual applications, there may be various situations such as equipment addition, equipment removal, and equipment update, so requirements are also put forward for low access latency, high data transmission performance, and fast response. Here, the important product data is a collection of configuration and information data related to a set of specific hardware or software, recording important information such as the part number (PN) of the device, the serial number (SN), and the unique identification of hardware and software, and is used to store information such as device performance or failure. The data format of the important product data includes multiple segments, including one or more readable and writable key information items. The data format of the important product data is fixed, and the length of each segment and each item is also pre-set, and the order of each other is also fixed. Therefore, through displacement calculation, starting from the start identifier of the important product data to the end identifier, each segment and each item can be determined. Exemplary important product data may include, for example, large resource type identifiers, data length, date, keywords, and other items. In one example, the data format of important product data consists of four sections, which are, in order: the start identifier of the important product data, the large resource type identifier of the important product data (used to provide the product name of the device, etc.), then the read-only type key information items, then another large resource type identifier and readable and writable key information items, and finally the end identifier. Among them, read-only type key information items generally cannot be rewritten by software, and even if the data at these addresses is overwritten, it will not have any impact on the data in the area. Readable and writable key information items can be modified by software and can be used to store real-time equipment performance parameters or error codes and other information.

[0034] See also Figure 1In step S101, a peripheral component interconnect express topology is simulated and generated by a system simulator software of a data processor, wherein the peripheral component interconnect express topology includes an upstream port, at least one downstream port, and at least one peripheral component interconnect express device of a first device type, the system simulator software runs in the memory of the data processor, the upstream port is connected to the root port of the host machine, and the at least one peripheral component interconnect express device of the first device type has an important product data function. Here, the system simulator software is used to provide software implementations of various systems and platforms, and can run on an embedded central processing unit (Embedded CPU, ECPU) of the data processor. Using the system simulator software, a peripheral component interconnect express topology is simulated and generated in a software-implemented manner, including the specific structure thereof. The peripheral component interconnect express topology includes an upstream port, at least one downstream port, and at least one peripheral component interconnect express device of a first device type. Here, the upstream port is used to connect to the root port of the host machine, the downstream port is connected to the upstream port to further increase the level, and the peripheral component interconnect express device can be connected to the upstream port or the downstream port. Here, the at least one peripheral component interconnect express device of the first device type means that they are all of the same device type, such as some standardized peripheral component interconnect express devices, such as a network device type, a storage device type, and the like.

[0035] Continue reading Figure 1In step S103, the system simulator software allocates in the memory an upstream port read-only important product data information memory space and an upstream port readable and writable important product data information memory space exclusively occupied by the upstream port when initializing the upstream port, and allocates in the memory a downstream port read-only important product data information memory space shared between the at least one downstream port and at least one downstream port readable and writable important product data information memory space exclusively occupied by the at least one downstream port when initializing the at least one peripheral component interconnect express device of the first device type when initializing the at least one peripheral component interconnect express device of the first device type, and allocates in the memory a first device type peripheral component interconnect express device read-only important product data information memory space shared between at least one peripheral component interconnect express device of the first device type and at least one first device type peripheral component interconnect express device readable and writable important product data information memory space exclusively occupied by at least one peripheral component interconnect express device of the first device type. Here, by optimizing the process of initializing the peripheral component interconnect express topology of the system simulator software, a good foundation is laid for the subsequent execution of reading and writing important product data information. Specifically, when the system simulator software is initialized, for the uplink port, it allocates and initializes the memory space of the uplink port read-only important product data information for storing the uplink port read-only important product data information, and allocates and initializes the memory space of the uplink port readable and writable important product data information for storing the uplink port readable and writable important product data information. In this way, by distinguishing the read-only important product data information and the readable and writable important product data information associated with the uplink port, and allocating different memory spaces during initialization, the layout of the important product data information is set according to the specifications of the relevant protocol, such as the format defined by the PCIE protocol, which improves the read and write operations of the important product data information and helps to improve the operational flexibility.

[0036] Continue reading Figure 1, when the system simulator software is initialized, for the at least one downstream port, the memory space of the downstream port read-only important product data information shared between the at least one downstream port is allocated and initialized for storing the downstream port read-only important product data information, and the memory space of the at least one downstream port read-write important product data information exclusively used by the at least one downstream port is allocated and initialized for storing the downstream port read-write important product data information of the at least one downstream port. In this way, by distinguishing the downstream port read-only important product data information shared between the downstream ports and the downstream port read-write important product data information of each downstream port, and allocating different memory spaces during initialization, the layout of the important product data information is set according to the specifications of the relevant protocol, such as the format defined by the PCIE protocol, so that the read and write operations of the important product data information are improved, which helps to improve the operational flexibility. Further, when there are multiple downstream ports, the memory space of the downstream port read-only important product data information is shared between the multiple downstream ports, so the keyword information of the read-only type can be stored in the memory space of the downstream port read-only important product data information, and the shared information and shared storage space can be used to more effectively utilize resources and perform global synchronization. In addition, when there are multiple downstream ports, each of the multiple downstream ports exclusively occupies the corresponding downstream port readable and writable important product data information memory space. Therefore, the readable and writable keyword information can be stored in the corresponding downstream port readable and writable important product data information memory space. By utilizing the exclusive information and the exclusive storage space, the differentiated characteristics can be better utilized, such as setting differentiated performance parameters or error correction mechanisms, etc., which helps to dynamically modify the important product data information of various types of quick peripheral component interconnect devices and meet the needs of customers for customized input and output resources.

[0037] Continue reading Figure 1When the system simulator software is initialized, for at least one peripheral component interconnect express device of the first device type, the system simulator software allocates and initializes a first device type peripheral component interconnect express device read-only important product data information memory space allocated in the memory and shared between at least one peripheral component interconnect express device of the first device type, for storing the first device type peripheral component interconnect express device read-only important product data information, and allocates and initializes at least one first device type peripheral component interconnect express device read-write important product data information memory space exclusively used by at least one peripheral component interconnect express device of the first device type, for at least one peripheral component interconnect express device of the first device type, for storing the first device type peripheral component interconnect express device read-write important product data information of the at least one peripheral component interconnect express device of the first device type. In this way, by distinguishing the first device type Peripheral Component Interconnect Express device read-only important product data information shared between at least one Peripheral Component Interconnect Express device of the first device type, and the first device type Peripheral Component Interconnect Express device of each at least one Peripheral Component Interconnect Express device of each first device type can read and write important product data information, and different memory spaces are allocated during initialization, so that the layout of the important product data information is set according to the specifications of the relevant protocol, such as the format defined by the PCIE protocol, thereby improving the read and write operations of the important product data information and helping to improve the operational flexibility. Further, when there are multiple first device type Peripheral Component Interconnect Express devices, the multiple first device type Peripheral Component Interconnect Express devices share the first device type Peripheral Component Interconnect Express device read-only important product data information memory space, so that the read-only type keyword information can be stored in the first device type Peripheral Component Interconnect Express device read-only important product data information memory space, and by using shared information and shared storage space, resources can be used more effectively and global synchronization can be performed. In addition, when there are multiple first-type peripheral component interconnect express devices, each of the multiple first-type peripheral component interconnect express devices exclusively occupies the corresponding first-type peripheral component interconnect express device readable and writable important product data information memory space, so the readable and writable keyword information can be stored in the corresponding first-type peripheral component interconnect express device readable and writable important product data information memory space, and by using the exclusive information and the exclusive storage space, the differentiated characteristics can be better utilized, such as setting differentiated performance parameters or error correction mechanisms, etc., which is helpful to dynamically modify the important product data information of various types of peripheral component interconnect express devices and meet the customer's demand for customized input and output resources.

[0038] Continue reading Figure 1In step S105, the system simulator software parses the first transaction layer data packet message including the read important product data information sent by the host machine to perform the read important product data information operation, or parses the second transaction layer data packet message including the write important product data information sent by the host machine to perform the write important product data information operation. In this way, based on the optimization of the initialization process of the system simulator software, it is realized to distinguish and manage the read-only important product data information and the read-write important product data information, and to manage the upstream port, the downstream port and various types of peripheral component interconnection devices separately, and to collect the read-only important product data information of the peripheral component interconnection devices of the same device type. By parsing the transaction layer packet (Transaction Layer Packet, TLP) message, for the read important product data information, the system simulator software returns the information of the memory space corresponding to the device type of the peripheral component interconnection device, and notifies the host machine to read the information; for the write important product data information, the system simulator software writes the information into the memory space corresponding to the peripheral component interconnection device, performs the corresponding operation, and notifies the host machine that the information writing is completed. In this way, different memory spaces are allocated during initialization, so that the layout of important product data information is set according to the specifications of the relevant protocols, such as the format defined by the PCIE protocol, which improves the read and write operations of important product data information and helps to improve operational flexibility. In addition, because the system simulator software of the data processor is relied on to optimize the initialization process, parse the transaction layer data packet message, perform the read important product data information operation and perform the write important product data information operation, therefore, it is not necessary to update the hardware logic every time the important product data information of the quick peripheral component interconnect device is dynamically modified, but can be accurately written into the exclusive memory space of the target PCIE device through the write important product data information operation. In addition, by distinguishing quick peripheral component interconnect devices of different device types, providing shared memory space for quick peripheral component interconnect devices of the same device type and allocating device exclusive memory space, the resource utilization rate is improved, and it is also conducive to combining the common functional characteristics between devices of the same device type for management and synchronization.

[0039] In conclusion, Figure 1The method for implementing the important product data function with software shown in the figure realizes the management of read-only important product data information and read-write important product data information, and manages the upstream port, downstream port and various types of quick peripheral component interconnect devices separately; allocates different memory spaces during initialization, so that the layout of the important product data information can be set according to the specifications of the relevant protocol, thereby improving the read and write operations of the important product data information and helping to improve the operational flexibility; because the system simulator software relying on the data processor is used to optimize the initialization process, parse the transaction layer data packet message, perform the read important product data information operation and the write important product data information operation, therefore, it is not necessary to update the hardware logic every time the important product data information of the quick peripheral component interconnect device is dynamically modified, avoiding the overall update of the hardware logic, and making full use of the unloading and virtualization technology of the dedicated hardware; by distinguishing the quick peripheral component interconnect devices of different device types, providing the quick peripheral component interconnect devices of the same device type with a shared memory space and allocating the device-exclusive memory space, improving the resource utilization rate, and also facilitating the management and synchronization by combining the common functional characteristics between devices of the same device type; meeting the requirements of dynamic modification, cost reduction, fast response, reduced access delay and improved performance.

[0040] Figure 2 A reference provided for the embodiments of this application Figure 1 The method of implementing important product data functions in the software shown is to simulate and generate a schematic diagram of a quick peripheral component interconnection topology. Figure 2As shown, the system simulator software 205 of the data processor simulates and generates a peripheral component interconnect express topology. The peripheral component interconnect express topology includes an upstream port 211, at least one downstream port 221, and at least one peripheral component interconnect express device of the first device type (device type A peripheral component interconnect express device A231 and device type A peripheral component interconnect express device B241), and at least one peripheral component interconnect express device of the second device type (device type B peripheral component interconnect express device 251). The system simulator software 205 runs in the memory of the data processor, the upstream port 211 is connected to the root port 203 of the host machine 201, and the at least one peripheral component interconnect express device of the first device type has an important product data function. Through the system simulator software 205, when the upstream port 211 is initialized, the upstream port read-only important product data information memory space 291 and the upstream port read-write important product data information memory space 213 exclusively occupied by the upstream port 211 are allocated in the memory. Furthermore, when initializing the at least one downstream port 221, a downstream port read-only important product data information memory space 293 shared between the at least one downstream port 221 and at least one downstream port read-write important product data information memory space 223 exclusively used by the at least one downstream port 221 are allocated in the memory. Furthermore, when initializing at least one peripheral component interconnect express device of the first device type (device type A peripheral component interconnect express device A 231 and device type A peripheral component interconnect express device B 241), a first device type peripheral component interconnect express device read-only important product data information memory space (device type A peripheral component interconnect express device read-only important product data information memory space 295) shared between at least one peripheral component interconnect express device of the first device type (device type A peripheral component interconnect express device A 231 and device type A peripheral component interconnect express device B 241) and at least one first device type peripheral component interconnect express device read-write important product data information memory space exclusively used by at least one peripheral component interconnect express device of the first device type are allocated in the memory. Figure 2It is exemplarily shown in the figure that the device type A peripheral component interconnect express device A231 is connected to the upstream port 211 and exclusively occupies the device type A peripheral component interconnect express device readable and writable important product data information memory space A233, and the device type A peripheral component interconnect express device B241 is connected to the downstream port 221 and exclusively occupies the device type A peripheral component interconnect express device readable and writable important product data information memory space B243. In addition, the device type B peripheral component interconnect express device 251 is connected to the downstream port 221 and exclusively occupies the device type B peripheral component interconnect express device readable and writable important product data information memory space 253. When initializing at least one peripheral component interconnect express device of the second device type (device type B peripheral component interconnect express device 251), the system simulator software 205 allocates in the memory a second device type peripheral component interconnect express device read-only important product data information memory space (device type B peripheral component interconnect express device read-only important product data information memory space 297) shared between at least one peripheral component interconnect express device of the second device type (device type B peripheral component interconnect express device 251). In this way, reference is made to Figure 1 The method of implementing important product data functions in the software shown is used to simulate and generate a fast peripheral component interconnection topology, meeting the requirements of dynamic modification, cost reduction, fast response, reduced access latency and improved performance.

[0041] See also Figure 1 and Figure 2 In a possible implementation, when the first transaction layer data packet indicates reading the important product data information associated with the uplink port, the operation of reading the important product data information includes, after reading the data from the starting position of the memory space of the uplink port read-only important product data information and then offsetting the position indicated by the first transaction layer data packet, storing the data in the important product data capability set configuration space associated with the peripheral component interconnect Express topology at the position indicated by the first transaction layer data packet. In this way, it is realized to distinguish and manage the read-only important product data information and the read-write important product data information, and to manage the uplink port, the downlink port and various types of peripheral component interconnect Express devices separately; different memory spaces are allocated during initialization, so that the layout of the important product data information can be set according to the specifications of the relevant protocol, which improves the read and write operations of the important product data information and helps to improve the operational flexibility.

[0042] In some embodiments, when the second transaction layer data packet message indicates writing the important product data information associated with the uplink port, the operation of writing the important product data information includes, after obtaining data from the position indicated by the second transaction layer data packet message in the important product data capability set configuration space, writing the starting position of the memory space of the uplink port readable and writable important product data information and then offsetting the position indicated by the second transaction layer data packet message. In this way, it is realized to distinguish and manage the read-only important product data information and the readable and writable important product data information, and to manage the uplink port, the downlink port and various types of peripheral component interconnect devices separately; different memory spaces are allocated during initialization, so that the layout of the important product data information can be set according to the specifications of the relevant protocol, which improves the read and write operations of the important product data information and helps to improve the operational flexibility.

[0043] In some embodiments, the important product data information associated with the upstream port includes a maximum load size and a maximum read request size. In this way, it is possible to distinguish and manage read-only important product data information and read-write important product data information, and to manage the upstream port, the downstream port and various types of peripheral component interconnect devices separately; different memory spaces are allocated during initialization, so that the layout of the important product data information can be set according to the specifications of the relevant protocol, which improves the read and write operations of the important product data information and helps to improve the operational flexibility.

[0044] In a possible implementation, when the first transaction layer data packet indicates reading the important product data information associated with the first downstream port of the at least one downstream port, the operation of reading the important product data information includes, after reading the data from the starting position of the memory space of the read-only important product data information of the downstream port and then offsetting the position indicated by the first transaction layer data packet, storing the data in the important product data capability set configuration space associated with the peripheral component interconnect express topology at the position indicated by the first transaction layer data packet. In this way, it is realized to distinguish and manage the read-only important product data information and the read-write important product data information, and to manage the upstream port, the downstream port and various types of peripheral component interconnect express devices separately; different memory spaces are allocated during initialization, so that the layout of the important product data information can be set according to the specifications of the relevant protocol, which improves the read and write operations of the important product data information and helps to improve the operational flexibility. In addition, indicating the corresponding position through the transaction layer data packet helps to finely locate and manage the associated important product data information.

[0045] In some embodiments, when the second transaction layer data packet message indicates that the important product data information associated with the second downstream port in the at least one downstream port is to be written, the operation of writing the important product data information includes, after obtaining data from the position indicated by the second transaction layer data packet message in the important product data capability set configuration space, writing the starting position of the readable and writable important product data information memory space of the downstream port exclusively occupied by the second downstream port in the readable and writable important product data information memory space of the at least one downstream port and then offsetting the position indicated by the second transaction layer data packet message. In this way, it is realized to distinguish and manage the read-only important product data information and the readable and writable important product data information, and to manage the upstream port, the downstream port and various types of quick peripheral component interconnect devices separately; different memory spaces are allocated during initialization, so that the layout of the important product data information can be set according to the specifications of the relevant protocol, which improves the read and write operations of the important product data information and helps to improve the operational flexibility. In addition, indicating the corresponding position through the transaction layer data packet message helps to finely locate and manage the associated important product data information.

[0046] In some embodiments, the important product data information associated with the first downstream port and the important product data information associated with the second downstream port both include a maximum payload size and a maximum read request size. In this way, it is possible to distinguish and manage the read-only important product data information and the read-write important product data information, and to manage the upstream port, the downstream port and various types of peripheral component interconnect devices separately; different memory spaces are allocated during initialization, so that the layout of the important product data information can be set according to the specifications of the relevant protocol, which improves the read and write operations of the important product data information and helps to improve the operational flexibility.

[0047] In a possible implementation, when the first transaction layer data packet indicates reading important product data information associated with a first peripheral component interconnect express device in at least one peripheral component interconnect express device of the first device type, the operation of reading the important product data information includes, after reading data from the starting position of the memory space of the read-only important product data information of the first device type peripheral component interconnect express device and then offsetting the position indicated by the first transaction layer data packet, storing the data in the important product data capability set configuration space associated with the peripheral component interconnect express topology at the position indicated by the first transaction layer data packet. In this way, it is realized to distinguish and manage the read-only important product data information and the read-write important product data information, and to manage the upstream port, the downstream port and various types of peripheral component interconnect express devices separately; different memory spaces are allocated during initialization, so that the layout of the important product data information can be set according to the specifications of the relevant protocol, so that the read and write operations of the important product data information are improved, which helps to improve the operational flexibility. In addition, indicating the corresponding position through the transaction layer data packet helps to finely locate and manage the associated important product data information.

[0048] In some embodiments, when the second transaction layer data packet indicates that the important product data information associated with the second peripheral component interconnect express device is to be written into at least one peripheral component interconnect express device of the first device type, the operation of writing the important product data information includes, after acquiring data from the position indicated by the second transaction layer data packet in the important product data capability set configuration space, writing the starting position of the first device type peripheral component interconnect express device readable and writable important product data information memory space exclusively occupied by the second peripheral component interconnect express device in the at least one first device type peripheral component interconnect express device readable and writable important product data information memory space of the first device type peripheral component interconnect express device, and then offsetting the position indicated by the second transaction layer data packet. In this way, it is realized to distinguish and manage the read-only important product data information and the read-write important product data information, and to manage the upstream port, the downstream port and various types of peripheral component interconnect express devices separately; different memory spaces are allocated during initialization, so that the layout of the important product data information can be set according to the specifications of the relevant protocol, so that the read and write operations of the important product data information are improved, which is helpful to improve the operation flexibility. In addition, indicating the corresponding position through the transaction layer data packet is helpful to finely locate and manage the associated important product data information.

[0049] In some embodiments, the important product data information associated with the first peripheral component interconnect express device and the important product data information associated with the second peripheral component interconnect express device both include a part number and a serial number, wherein the part number is shared between at least one peripheral component interconnect express device of the first device type, and at least one peripheral component interconnect express device of the first device type has different serial numbers. In this way, it is possible to distinguish and manage the read-only important product data information and the read-write important product data information, and to manage the upstream port, the downstream port and various types of peripheral component interconnect express devices separately; different memory spaces are allocated during initialization, so that the layout of the important product data information can be set according to the specifications of the relevant protocol, thereby improving the read and write operations of the important product data information and helping to improve the operational flexibility.

[0050] In a possible implementation, the PCI Express topology further includes at least one PCI Express device of the second device type, and the at least one PCI Express device of the second device type has an important product data function. The method further includes: using the system simulator software, when initializing the at least one PCI Express device of the second device type, allocating in the memory a second device type PCI Express device read-only important product data information memory space shared between the at least one PCI Express device of the second device type and at least one second device type PCI Express device read-write important product data information memory space exclusively occupied by the at least one PCI Express device of the second device type. In this way, by distinguishing PCI Express devices of different device types, providing shared memory space for PCI Express devices of the same device type and allocating device exclusive memory space, resource utilization is improved, and it is also beneficial to manage and synchronize in combination with the common functional characteristics between devices of the same device type.

[0051] In some embodiments, the first device type and the second device type satisfy a first association relationship, and the write important product data information operation for the read and write important product data information memory space of at least one first device type Peripheral Component Interconnect Express device and the write important product data information operation for the read and write important product data information memory space of at least one second device type Peripheral Component Interconnect Express device also satisfy the first association relationship. In this way, by distinguishing Peripheral Component Interconnect Express devices of different device types, providing shared memory space for Peripheral Component Interconnect Express devices of the same device type and allocating device-exclusive memory space, resource utilization is improved, and it is also beneficial to manage and synchronize in combination with the common functional characteristics between devices of the same device type. In addition, by using the first association relationship, device management and global configuration can be better performed.

[0052] In some embodiments, the first device type is a network device type, the second device type is a storage device type, and the first association relationship defines the linkage between the important product data associated with the modification of the remote direct memory access function of the network device type and the important product data associated with the modification of the remote direct memory access of the storage device type. In this way, by distinguishing between quick peripheral component interconnect devices of different device types, providing shared memory space for quick peripheral component interconnect devices of the same device type and allocating device-exclusive memory space, resource utilization is improved, and it is also beneficial to manage and synchronize the common functional characteristics between devices of the same device type. In addition, by using the first association relationship, device management and global configuration can be better performed. Here, remote direct memory access involves the linkage between network devices and storage devices. Therefore, changes to the important product data of one device type may affect the important product data of another device type.

[0053] In a possible implementation, the peripheral component interconnect express topology generated by the simulation of the system simulator software includes a peripheral component interconnect express device without an important product data function, and the system simulator software does not allocate memory space for the peripheral component interconnect express device without an important product data function to perform an operation of reading important product data information or performing an operation of writing important product data information. This helps to improve resource utilization.

[0054] In a possible implementation, the method further includes: determining, by the system simulator software, whether the second transaction layer data packet message including the write information of important product data sent by the host machine is an operation type write or a save type write, thereby selectively executing the reset operation of the data processor. In this way, by parsing the second transaction layer data packet message for writing important product data information, it is possible to determine which type of write it is, and then trigger the reset operation of the data processor, for example, it can be set to execute the reset operation when it is confirmed to be an operation type write. In this way, the flexibility of the operation is improved.

[0055] Figure 33 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application, and the computing device 300 includes: one or more processors 310, a communication interface 320 and a memory 330. The processor 310, the communication interface 320 and the memory 330 are interconnected via a bus 340. Optionally, the computing device 300 may also include an input / output interface 350, and the input / output interface 350 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 300 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 310 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 300 can refer to the specific details in the above-mentioned embodiments, such as the processor 310 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 300 may be used to implement part or all of the functions of one or more components in the above-mentioned apparatus embodiment. In addition, the communication interface 320 may be specifically used to perform the communication functions necessary to implement the functions of these apparatuses and components, and the processor 310 may be specifically used to perform the processing functions necessary to implement the functions of these apparatuses and components.

[0056] It should be understood that Figure 3 The computing device 300 may include one or more processors 310, and the multiple processors 310 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 310 may form a processor sequence or a processor array, or the multiple processors 310 may be divided into a main processor and an auxiliary processor, or the multiple processors 310 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 3 The computing device 300 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 300 may include Figure 3 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0057] The processor 310 may have a variety of specific implementation forms. For example, the processor 310 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 310 may also be a single-core processor or a multi-core processor. The processor 310 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 310 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 320 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0058] The memory 330 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 330 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 330 may also be used to store program codes and data, so that the processor 310 calls the program codes stored in the memory 330 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 3 Show more or fewer components, or have different component configurations.

[0059] The bus 340 may be a peripheral component interconnect express (PCIE) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 340 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 340 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 3 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0060] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0061] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0062] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0063] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0064] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A method for implementing important product data functions by software, characterized in that: The method comprises: Simulating and generating a peripheral component interconnect express topology through system simulator software of a data processor, wherein the peripheral component interconnect express topology includes an upstream port, at least one downstream port, and at least one peripheral component interconnect express device of a first device type, the system simulator software runs in a memory of the data processor, the upstream port is connected to a root port of a host machine, and the at least one peripheral component interconnect express device of the first device type has an important product data function; By means of the system simulator software, when initializing the upstream port, an upstream port read-only important product data information memory space and an upstream port readable and writable important product data information memory space exclusively occupied by the upstream port are allocated in the memory, and when initializing the at least one downstream port, a downstream port read-only important product data information memory space shared among the at least one downstream port and at least one downstream port readable and writable important product data information memory space exclusively occupied by the at least one downstream port are allocated in the memory, and when initializing at least one peripheral component interconnect express device of the first device type, a first device type peripheral component interconnect express device read-only important product data information memory space shared among at least one peripheral component interconnect express device of the first device type and at least one first device type peripheral component interconnect express device readable and writable important product data information memory space exclusively occupied by at least one peripheral component interconnect express device of the first device type are allocated in the memory; By means of the system simulator software, a first transaction layer data packet message including the read important product data information sent by the host machine is parsed to thereby execute an operation of reading the important product data information, or a second transaction layer data packet message including the write important product data information sent by the host machine is parsed to thereby execute an operation of writing the important product data information, When the first transaction layer data packet indicates reading important product data information associated with a first downstream port of the at least one downstream port, the operation of reading the important product data information includes reading data from a starting position of the downstream port read-only important product data information memory space and then offsetting the data to a position indicated by the first transaction layer data packet, and then storing the data in an important product data capability set configuration space associated with the peripheral component interconnect express topology at a position indicated by the first transaction layer data packet, When the first transaction layer data packet indicates reading important product data information associated with a first peripheral component interconnect express device in at least one peripheral component interconnect express device of the first device type, the operation of reading the important product data information includes reading data from a starting position of a read-only important product data information memory space of the first device type peripheral component interconnect express device and then offsetting the data to a position indicated by the first transaction layer data packet, and then storing the data in an important product data capability set configuration space associated with the peripheral component interconnect express topology at a position indicated by the first transaction layer data packet, The PCI Express topology further includes at least one PCI Express device of a second device type, the at least one PCI Express device of the second device type having a vital product data function, the method further including: By means of the system simulator software, when initializing at least one PCI Express device of the second device type, a second device type PCI Express device read-only important product data information memory space shared among at least one PCI Express device of the second device type and at least one second device type PCI Express device read-write important product data information memory space exclusively used by at least one PCI Express device of the second device type are allocated in the memory.

2. The method according to claim 1, characterized in that When the first transaction layer data packet message indicates reading important product data information associated with the uplink port, the operation of reading the important product data information includes reading data from the starting position of the uplink port read-only important product data information memory space and then offsetting the data to the position indicated by the first transaction layer data packet message, and then storing the data in the position indicated by the first transaction layer data packet message in the important product data capability set configuration space associated with the peripheral component interconnect express topology.

3. The method according to claim 2, characterized in that When the second transaction layer data packet message indicates writing important product data information associated with the uplink port, the operation of writing the important product data information includes obtaining data from the position indicated by the second transaction layer data packet message in the important product data capability set configuration space, and then writing the data to the starting position of the uplink port readable and writable important product data information memory space and then offsetting it to the position indicated by the second transaction layer data packet message.

4. The method according to claim 3, characterized in that Important product data information associated with the upstream port includes a maximum payload size and a maximum read request size.

5. The method according to claim 1, characterized in that When the second transaction layer data packet message indicates that important product data information associated with a second downstream port in the at least one downstream port is to be written, the operation of writing the important product data information includes obtaining data from the position indicated by the second transaction layer data packet message in the important product data capability set configuration space, and then writing the important product data information in the memory space of the at least one downstream port readable and writable important product data information to the starting position of the memory space of the downstream port readable and writable important product data information exclusively occupied by the second downstream port, and then offsetting it by the position indicated by the second transaction layer data packet message.

6. The method according to claim 5, characterized in that The important product data information associated with the first downstream port and the important product data information associated with the second downstream port both include a maximum payload size and a maximum read request size.

7. The method according to claim 1, characterized in that When the second transaction layer data packet message indicates that important product data information associated with a second peripheral component interconnect express device in at least one peripheral component interconnect express device of the first device type is to be written, the operation of writing the important product data information includes, after acquiring data from the position indicated by the second transaction layer data packet message in the important product data capability set configuration space, writing the important product data information in the first device type peripheral component interconnect express device readable and writable important product data information memory space exclusively occupied by the second peripheral component interconnect express device in the at least one first device type peripheral component interconnect express device readable and writable important product data information memory space to a starting position offset by the position indicated by the second transaction layer data packet message.

8. The method according to claim 7, characterized in that The vital product data information associated with the first peripheral component interconnect express device and the vital product data information associated with the second peripheral component interconnect express device both include a part number and a serial number, wherein the part number is shared between at least one peripheral component interconnect express device of the first device type, and the at least one peripheral component interconnect express device of the first device type has a different serial number.

9. The method according to claim 1, characterized in that: A first association relationship is satisfied between the first device type and the second device type, and the first association relationship is also satisfied between an operation of writing important product data information in a memory space in which the at least one first device type peripheral component interconnect Express device can read and write important product data information and an operation of writing important product data information in a memory space in which the at least one second device type peripheral component interconnect Express device can read and write important product data information.

10. The method according to claim 9, characterized in that The first device type is a network device type, the second device type is a storage device type, and the first association relationship defines the linkage between important product data associated with changing the remote direct memory access function of the network device type and important product data associated with changing the remote direct memory access of the storage device type.

11. The method according to claim 1, characterized in that: The peripheral component interconnect express topology generated by simulation by the system simulator software includes a peripheral component interconnect express device without a critical product data function, and the system simulator software does not allocate memory space for the peripheral component interconnect express device without a critical product data function to perform a critical product data information read operation or a critical product data information write operation.

12. The method according to claim 1, characterized in that The method further comprises: Through the system simulator software, it is determined that the second transaction layer data packet message including the writing information of important product data sent by the host machine is an operation type write or a save type write, thereby selectively executing the reset operation of the data processor.

13. A computer device, characterized in that: The computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 12.

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