Method, computing device, medium and program product for building a trusted execution environment

Abstract

The present invention relates to the field of artificial intelligence, and to a method, computing device, medium and program product for building a trusted execution environment. The method comprises: configuring multiple virtual machines on the host side; isolating the multiple virtual machines; and configuring a hardware-isolated GPU instance on the device side to form an independent hardware access path with at least one of the configured multiple virtual machines for building a trusted execution environment supporting confidential computing. The present invention can effectively build a trusted execution environment supporting confidential computing.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of artificial intelligence, and more specifically to a method, a computing device, a computer-readable storage medium, and a computer program product for building a trusted execution environment. Background Art

[0002] Trusted Execution Environments (TEEs) are a key element in the functioning of confidential computing. As there is an increasing demand for confidential computing, it is becoming increasingly important to build a trusted execution environment that can effectively support confidential computing.

[0003] Although there are some encryption technologies that can protect static data in storage and data transmitted over the network, traditional computing devices (for example, computing devices used for computing in the field of artificial intelligence) are usually difficult to build a trusted execution environment that is sufficient to support confidential computing. The main reason is that confidential computing requires protection for the data and applications in use, and for traditional computing devices, they mainly include a host (for example, a central processing unit, or "CPU") and a device (for example, a graphics processing unit, or "GPU"). To protect the data and applications in use, the hardware on the device side needs to meet higher security isolation requirements, and specific code needs to be enabled in the application. The implementation of the above requirements is somewhat difficult.

[0004] In summary, the shortcoming of traditional computing devices is that it is difficult to build a trusted execution environment that supports confidential computing. Summary of the invention

[0005] The present invention provides a method, a computing device, a computer-readable storage medium, and a computer program product for building a trusted execution environment, which can effectively build a trusted execution environment that supports confidential computing.

[0006] According to a first aspect of the present invention, a method for building a trusted execution environment is provided. The method comprises: configuring multiple virtual machines on a host side; isolating the multiple virtual machines; and configuring a hardware-isolated GPU instance on a device side to form an independent hardware access path with at least one of the configured multiple virtual machines, so as to build a trusted execution environment supporting confidential computing.

[0007] In some embodiments, configuring a hardware-isolated GPU instance includes: isolating an address space of hardware on the device side; and isolating memory, a command processor, and computing cores associated with the configured GPU instance from each other.

[0008] In some embodiments, building a trusted execution environment that supports confidential computing includes: configuring multiple GPU instances that are hardware isolated from each other; building the trusted execution environment based on an independent hardware access path formed by at least one GPU instance among the multiple GPU instances and a corresponding virtual machine among multiple virtual machines; and managing data flow and memory access internally in at least one GPU instance used to build the trusted execution environment.

[0009] In some embodiments, internal management of data flow and memory access of at least one GPU instance used to build the trusted execution environment includes: in a process run by the GPU instance, sending a command with an address space identifier to a command queue so that a main module in the GPU instance for processing the command obtains the command; the main module processes the command to initiate an access request to the memory; the system memory management unit searches a context matching table through the address space identifier to obtain a valid context descriptor to obtain a page table entry, wherein the valid context descriptor indicates the GPU instance; the system memory management unit sends a memory request to a physical address generator, wherein the memory request indicates a system memory management unit address; and converts the system memory management unit address into a target physical address of the memory via the physical address generator.

[0010] In some embodiments, internal management of data flow and memory access in at least one GPU instance used to build the trusted execution environment includes: sending an access request for memory on the device side via a host, the access request indicating a PCIe address on the device side; converting the PCIe address into a system memory management unit address via a host portal on the device side so as to provide the system memory management unit address to a physical address generator; and converting the system memory management unit address into a target physical address of the memory on the device side via the physical address generator.

[0011] In some embodiments, isolating the address space of the hardware on the device side includes dividing the system address space, the PCIe address space, the high-speed bus address, and the low-speed bus address so as to be mapped with the configured GPU instance.

[0012] In some embodiments, constructing the trusted execution environment based on an independent hardware access path formed by at least one GPU instance among multiple GPU instances and a corresponding virtual machine among multiple virtual machines includes any of the following: forming a hardware access path based on each GPU instance among multiple GPU instances and a corresponding virtual machine among multiple virtual machines, thereby forming multiple hardware access paths; or forming multiple hardware access paths based on a GPU instance among multiple GPU instances with multiple corresponding virtual machines among multiple virtual machines through multiplexing.

[0013] In some embodiments, based on an independent hardware access path formed by at least one GPU instance among multiple GPU instances and a corresponding virtual machine among multiple virtual machines, building the trusted execution environment includes: enabling the corresponding virtual machine used to form the hardware access path to directly access the at least one GPU instance; and configuring a separate memory space, interrupt, and direct memory access data transmission for the formed hardware access path.

[0014] In some embodiments, the system address space, PCIe address space, high-speed bus address, and low-speed bus address are divided for mapping with the configured GPU instance, including: virtualizing the PCIe address space into multiple blocks, so that the virtualized multiple blocks are respectively mapped with the configured multiple GPU instances.

[0015] According to a second aspect of the present invention, a computing device is also provided. The computing device comprises: at least one processor; and a memory in communication connection with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the computing device can perform the method of the first aspect of the present invention.

[0016] According to a third aspect of the present invention, a computer-readable storage medium is provided, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a machine, the method of the first aspect of the present invention is executed.

[0017] According to a fourth aspect of the present invention, there is further provided a computer program product, comprising a computer program, wherein when the computer program is executed by a machine, the method according to the first aspect of the present invention is performed.

[0018] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other features, advantages and aspects of the embodiments of the present invention will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements.

[0020] Figure 1 The figure schematically shows a computing device for implementing a method for building a trusted execution environment according to an embodiment of the present invention.

[0021] Figure 2 A flow chart of a method for building a trusted execution environment according to an embodiment of the present invention is shown.

[0022] Figure 3 A schematic diagram of a trusted execution environment according to some embodiments of the present invention is shown.

[0023] Figure 4 A flow chart of a method for managing data flow and memory access within a GPU instance according to some embodiments of the present invention is shown.

[0024] Figure 5 A schematic diagram of a method for managing data flow and memory access within a GPU instance according to some embodiments of the present invention is shown.

[0025] Figure 6 A flowchart of a method for managing data flow and memory access within a GPU instance according to some other embodiments of the present invention is shown.

[0026] Figure 7 A schematic diagram of a PCIe SR-IOV device according to some embodiments of the present invention is schematically shown.

[0027] In the various drawings, the same or corresponding reference numerals represent the same or corresponding parts. DETAILED DESCRIPTION

[0028] The preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0029] As used herein, the term "including" and its variations mean open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects.

[0030] As described above, the shortcoming of traditional computing devices is that it is difficult to build a trusted execution environment that supports confidential computing.

[0031] In order to at least partially solve one or more of the above problems and other potential problems, an exemplary embodiment of the present invention proposes a method for building a trusted execution environment. In this method, by configuring multiple virtual machines on the host side; isolating the multiple virtual machines; and configuring a hardware-isolated GPU instance on the device side, so as to form an independent hardware access path with at least one of the multiple virtual machines configured, in order to build a trusted execution environment based on virtual machines that supports confidential computing, the present invention can form an independent hardware access path through the virtual machine configured on the host and the hardware-isolated GPU instance configured on the device side, thereby providing hardware-isolated GPU instances for multiple users sharing a single device, thereby significantly improving the security isolation performance while ensuring device sharing, thereby effectively protecting the data and applications in use. Therefore, the present invention can effectively build a trusted execution environment that supports confidential computing.

[0032] Figure 1 A schematic diagram of a computing device 100 for implementing a method for building a trusted execution environment according to an embodiment of the present invention is schematically shown. Figure 1As shown, the computing device 100 may have one or more processing units, including special processing units such as a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or a general-purpose graphics processing unit (GPGPU), and a general-purpose processing unit such as a CPU. In some embodiments, the computing device 100 is also configured with at least: a virtual machine configuration module 102, a virtual machine isolation module 104, and a hardware access path formation module 106. In some embodiments, the above-mentioned virtual machine configuration module 102, the virtual machine isolation module 104, and the hardware access path formation module 106 are, for example, program modules running on the computing device 100.

[0033] The virtual machine configuration module 102 is used to configure multiple virtual machines on the host side.

[0034] The virtual machine isolation module 104 is used to isolate the multiple virtual machines.

[0035] Regarding the hardware access path forming module 106, it is used to configure a hardware-isolated GPU instance on the device side so as to form an independent hardware access path with at least one of the configured multiple virtual machines, so as to build a trusted execution environment that supports confidential computing.

[0036] The following will be combined Figure 2 and Figure 3 A method 200 for building a trusted execution environment according to an embodiment of the present invention is described. Figure 2 A flowchart of a method 200 for building a trusted execution environment according to an embodiment of the present invention is shown. Figure 3 FIG. 2 is a schematic diagram of a trusted execution environment 300 according to some embodiments of the present invention. It should be understood that the method 200 may be implemented, for example, in Figure 1 The method 200 is executed at the described computing device 100. The method 200 may also include additional actions not shown and / or may omit the actions shown, and the scope of the present invention is not limited in this respect.

[0037] At step 202, the computing device 100 configures multiple virtual machines on the host side.

[0038] Regarding the host, it is, for example, a CPU, such as Figure 3Indicated by the mark 310 in the figure. In some embodiments, at least a software stack is built on the CPU 310. For example, an operating system (OS) / system hypervisor is configured on the CPU 310, for example, Figure 3 The OS / system hypervisor indicated by the mark 312 in the figure. The OS / system hypervisor 312 is used to manage processes, storage, devices, etc. In some embodiments, the OS / system hypervisor 312 further includes a physical function (PF) driver. For example, Figure 3 The PF driver indicated by mark 311 in FIG.

[0039] Regarding a virtual machine (VM), it includes hardware and software, for example. The virtual machine runs on a host. Each virtual machine is configured to be allocated physical computing resources (such as a processor, memory, and storage), for example. For example, the physical computing resources of the host are configured into multiple blocks to form a container for the hardware.

[0040] Regarding the number of configured virtual machines, it is usually determined based on the application and the physical computing resources of the host. For example, the present invention can configure 4, 8, 16 or other numbers of virtual machines.

[0041] For example, Figure 3 As shown, multiple virtual machines are configured on the CPU 310. For example, four virtual machines are configured, including: a first virtual machine 322 (ie, VM0), a second virtual machine 324 (ie, VM1), a third virtual machine 326 (ie, VM2), and a fourth virtual machine 328 (ie, VM3).

[0042] At step 204, the computing device 100 isolates the plurality of virtual machines.

[0043] For example, there is no information interaction and access between the first virtual machine 322 to the fourth virtual machine 328; and the physical computing resources (such as processor, memory and storage) allocated to each virtual machine in the first virtual machine 322 to the fourth virtual machine 328 are independent and isolated from each other.

[0044] In some embodiments, the computing device 100 is configured with a virtual function (VF) driver in each virtual machine. In some embodiments, a security driver is configured in at least one of the multiple virtual machines on the host side to support confidential virtual machines. For example, the security driver is Figure 3 The VF driver 321 configured for the first virtual machine 322.

[0045] At step 206, the computing device 100 configures a hardware-isolated GPU instance on the device side to form an independent hardware access path with at least one of the configured multiple virtual machines for building a trusted execution environment that supports confidential computing.

[0046] Regarding the device, it is, for example, a GPU (e.g., Figure 3 340 in the figure). It should be understood that the hardware resources on the GPU include, for example, registers, memory, etc. In some embodiments, the GPU 340 also includes a peripheral component interconnect express (PCIe) physical function (abbreviated as "PCIe PF"). The PCIe PF 342 further includes: a graphics subsystem processor (Graphics Subsystem Processor, GSP).

[0047] Regarding the GPU instance, it is, for example, a virtual function (or virtual function module) of the GPU. In some embodiments, each GPU instance configured on the device side is configured with: a peripheral component interconnect express (PCIe) virtual function module (referred to as "PCIe VF"), a memory instance, a single operation DMA or a stream processor cluster (SPC), etc. In some embodiments, each GPU instance is configured with: CP / SDMA / SPC / VD / VE. Among them, CP stands for Command Processor; SDMA stands for System Direct Memory Access; SPC stands for Stream Processor Cluster; VD stands for Video Decoder; VE stands for Video Encoder.

[0048] Regarding the hardware access path, it can be formed by at least one GPU instance among the multiple GPU instances and a corresponding virtual machine among the multiple virtual machines. Specifically, regarding the method of forming an independent hardware access path, it includes, for example: the computing device 100 forms a hardware access path based on each GPU instance among the multiple GPU instances and a corresponding virtual machine among the multiple virtual machines, thereby forming multiple hardware access paths; or based on a GPU instance among the multiple GPU instances, through multiplexing, forms multiple hardware access paths with multiple corresponding virtual machines among the multiple virtual machines.

[0049] It should be understood that a GPU, for example, can be virtualized into multiple GPU instances. Figure 3 As shown, GPU340 virtualizes four GPU instances that are independent of each other in hardware. The four GPU instances that are independent of each other in hardware are, for example, a first GPU instance (i.e., VF0), a second GPU instance (i.e., VF1), a third GPU instance (i.e., VF2), and a fourth GPU instance (i.e., VF3). In some embodiments, the above four GPU instances that are independent of each other in hardware are used independently by four virtual machines configured on the CPU side. In terms of hardware, regarding the physical isolation between GPU instances, it includes, for example: memory isolation between GPU instances, command processor isolation, computing core isolation, and separate passwords between virtual machines. It should be understood that by adopting the above means, a relatively independent and separated environment from the CPU side to the GPU side can be provided for multiple users.

[0050] The method for configuring a hardware-isolated GPU instance includes, for example, the following steps: the computing device 100 isolates the address space of the hardware on the device side; and isolates the memory, command processor, and computing core associated with the configured GPU instance from each other. For example, for each of the multiple GPU instances configured on the device side, a corresponding computing core is allocated.

[0051] Regarding the method for isolating the address space of the hardware on the device side, for example, it includes: the computing device 100 divides the system address space, PCIe address space, high-speed bus address, and low-speed bus address for mapping with the configured GPU instance. Specifically, GPU hardware address space isolation can be constructed based on single-root I / O virtualization (ie, SR-IOV) technology. It should be understood that SR-IOV is a PCIe extension function that enables a physical device to appear as multiple virtual devices. Figure 7 Schematically shows a schematic diagram of a PCIe SR-IOV device 700 according to some embodiments of the present invention. A physical device is, for example, referred to as a physical function (PF). Figure 7 As indicated by the mark 714 in FIG. 4 , a virtual device is referred to as a virtual function (VF). Figure 7As indicated by mark 716, it should be understood that the PCIe SR-IOV device 700 can be configured with multiple virtual functions (VFs). Among them, the allocation of virtual functions (VFs) can be dynamically controlled by the physical function (PF) through the registers encapsulated in the function. The PCI configuration space of each virtual function (VF) can be accessed through its bus, device and function identifiers (routing ID). And each virtual function (VF) also has PCI memory space. It should be understood that SR-IOV technology provides a method for sharing the physical function (PF) of PCIeI / O devices. It allows devices to independently access their resources in various PCIe physical functions (PFs). By Figure 7 It can be seen that the access via the PCIe port 710 can be routed to the corresponding virtual function (VF) (for example, as indicated by the mark 716) via the internal routing 712. In addition, the SR-IOV technology realizes the separate allocation and use of the device, so that the virtual machine configured by the CPU can directly access the hardware of the GPU, and can provide a separate memory space, interrupt and DMA data transmission, etc. It should be understood that if the HBM on the GPU side is accessed from the CPU, for example, four rounds of address conversion are required to complete the addressing. First, the address on the CPU side is the address of the system address space; when accessing PCIe, the address of the system address space needs to be converted to the address of the PCIe address space; after entering through the PCIe path, for example, when transmitting on a low-speed bus, it needs to be converted to a low-speed bus address similar to the system memory management unit address (for example, SMMU_PA); if the HBM is connected to a high-speed bus, the address also needs to be converted to a high-speed bus address. The present invention can significantly improve the performance and security of the device-side hardware by constructing GPU hardware address space isolation based on single-root I / O virtualization (ie, SR-IOV) technology.

[0052] It should be understood that the access from the CPU to the GPU may be for reading / writing the memory on the GPU side, or it may be for reading / writing the registers on the GPU side. Regarding the access to the registers in SR-IOV virtualization, the GPU hardware will perform corresponding protection and address remapping. Usually, the bandwidth for register access is not high, so a relatively low-speed bus is used. Therefore, the address space of the low-speed bus needs to be divided. For example, the address space for the low-speed bus has 4G bytes. Taking 4 virtual functions (VFs) as an example, each virtual function (VF) can correspond to 1G bytes of the address space of the low-speed bus. Regarding the protection of access to registers in SR-IOV, a virtual function (VF) cannot access the dedicated memory mapping I / O (MMIO) space of the physical function (PF) or the register space of another virtual function (VF). Regarding the address remapping involved in accessing registers in SR-IOV, for those register spaces that can be programmed by a virtual function (VF), the hardware must convert these programmings from a logical register space inside a virtual function (VF) to a device physical space. It should be understood that the address space indicated by the access from the host (e.g., the CPU side) is, for example, a logical identifier, such as VF1 or VF3. The hardware entity on the device side needs to perform a corresponding conversion on the logical identifier, for example, converting the logical identifier VF1 or VF3 to the target physical address under the physical space of the corresponding device.

[0053] Regarding the method for building a trusted execution environment that supports confidential computing, for example, it includes: configuring a computing device 100 with multiple GPU instances that are hardware-isolated from each other; building the trusted execution environment based on an independent hardware access path formed by at least one GPU instance among the multiple GPU instances and a corresponding virtual machine among the multiple virtual machines; and managing data flow and memory access inside at least one GPU instance used to build the trusted execution environment. The specific implementation of the method for managing data flow and memory access inside a GPU instance will be described below in conjunction with Figures 4 to 6 The detailed description will not be repeated here.

[0054] For example, Figure 3As shown, the computing device 100 configures four GPU instances with hardware isolation from each other on the GPU 340. Then, based on the four GPU instances configured in the GPU 340 and the four corresponding virtual machines configured in the CPU 310, four independent hardware access paths are formed. They are: the first hardware access path 314, the second hardware access path 316, the third hardware access path 318 and the fourth hardware access path 320. In some embodiments, the computing device 100 builds the trusted execution environment for supporting confidential computing based on the first hardware access path 314 formed by the first virtual machine 322 (i.e., VM0) configured on the CPU side and the first GPU instance (i.e., VF0) configured on the GPU side. On the second hardware access path 316 formed by the second GPU instance (i.e., VF1) and the corresponding second virtual machine 324 (i.e., VM1), and the third hardware access path 318 and the fourth hardware access path 320 formed by the third GPU instance (i.e., VF2), the fourth GPU instance (i.e., VF3) and the corresponding virtual machine, ordinary applications are respectively run. It should be understood that the present invention can also construct the trusted execution environment for supporting confidential computing based on the formed first hardware access path 314 and the second hardware access path 316.

[0055] In some embodiments, regarding the method of building a trusted execution environment that supports confidential computing, in addition to configuring a hardware-isolated GPU instance on the GPU side, the method also includes: the computing device 100 builds a confidential virtual machine on the CPU side; builds a confidential GPU instance on the GPU side; and encrypts and transmits data between the confidential virtual machine and the confidential GPU instance. Among them, all content running in the confidential virtual machine should be confidential, such as drivers and libraries. It should be understood that the isolation between the confidential virtual machine and the virtual machine hypervisor, as well as other users, not only requires the isolation between the corresponding GPU instances, but also requires the CPU software to have security functions, such as secure access control, paging control, address translation, and data encryption. By adopting the above means, the present invention can further isolate the confidential virtual machine from other virtual machines and potential malicious virtual machine hypervisors, thereby further improving security.

[0056] In the above scheme, the present invention can form an independent hardware access path through the virtual machine configured on the host and the hardware-isolated GPU instance configured on the device side, so as to provide hardware-isolated GPU instances for multiple users sharing a single device, thereby significantly improving the security isolation performance while ensuring device sharing, thereby effectively protecting the data and applications in use. Therefore, the present invention can effectively build a trusted execution environment that supports confidential computing and prevent unauthorized users from accessing and modifying it.

[0057] The following will be combined Figure 4 and Figure 5 A method 400 for managing data flow and memory access within a GPU instance according to an embodiment of the present invention is described. Figure 4 A flow chart of a method 400 for managing data flow and memory access within a GPU instance according to some embodiments of the present invention is shown. Figure 5 4 is a schematic diagram showing a method for managing data flow and memory access within a GPU instance according to some embodiments of the present invention. It should be understood that the method 400 may be used, for example, in Figure 1 The method 400 is executed at the described computing device 100. The method 400 may also include additional actions not shown and / or may omit the actions shown, and the scope of the present invention is not limited in this respect.

[0058] It should be understood that memory addressing in a device (e.g., a GPU) can occur in multiple paths. It should be understood that the access received by the device may be from a direct instruction load or store access, or it may be a direct memory access (DMA), or it may be an access to a command packet or a register. Even access to device memory (e.g., access to high-bandwidth memory) can go through multiple paths. For example, the access request may be a device memory access between a host (e.g., a CPU) and a device (e.g., a GPU), or it may be a device memory access from a main module inside the GPU (the main module may include, for example, a command processor, a computing core, and a DMA processing unit, etc.).

[0059] Figure 5 The above two typical paths for accessing high-bandwidth memory are exemplified in the figure. For example, one path is: the CPU 510 sends a command with an address space ID (ASID) to the master module 520 (or Master IP Modules) of a GPU instance 530 of the GPU, and then the master module 520 initiates access to the high-bandwidth memory (HBM). For example, another path is: the CPU 510 directly accesses the high-bandwidth memory 528 via the PCIe switch 512, the host portal 514 (Host Aperture, referred to as "HA"), and the physical address generator 524. The following describes the method of managing data flow and memory access inside the GPU instance in conjunction with the scenario of an application accessing device memory.

[0060] At step 402, in a process run by a GPU instance, a command with an address space identifier is sent to a command queue so that a main module in the GPU instance for processing the command acquires the command.

[0061] Regarding the main module 520 of the GPU instance 530, it is a processing unit for processing commands. In some embodiments, the main module 520 is, for example, a command processor, a computing core, and a DMA processing unit.

[0062] Regarding the address space identifier (ASID), it includes, for example, a process identifier (eg, a process ID). In some embodiments, the command further indicates a virtual address and an identifier of a GPU instance.

[0063] For example, when an application on the CPU accesses the HBM, the GPU will initiate a process. In the scenario of the virtualized and isolated GPU instance of the present invention, generally, a process may run in a GPU instance configured in the GPU, for example, Figure 5 The GPU instance 530 shown in the figure is not run in the entire GPU. In the running process, a command packet about the software instruction sent by the CPU driver is transmitted. The command packet contains a command with an address space identifier (Adress Space ID, ASID). The command also includes, for example, a virtual address and an identifier of the GPU instance. The command is sent to, for example, a main module 520 (e.g., a command processor) for processing related commands.

[0064] At step 404, the main module processes the command to initiate an access request to the memory.

[0065] Regarding memory, it is the memory on the device side, which includes, for example: high bandwidth memory, or secondary cache. High bandwidth memory is also called "HBM". Secondary cache can also be called "L2 cache" or "L2 cache".

[0066] For example, the command processor processes the received command to initiate an access request to the HBM based on memory read / write to the HBM; and calls the System Memory Management Unit (SMMU) 522 .

[0067] At step 406, the system memory management unit searches the context matching table by the address space identifier to obtain a valid context descriptor, thereby obtaining a page table entry. The valid context descriptor indicates the GPU instance.

[0068] For example, via the system memory management unit 522 , a context matching table is searched based on the ASID indicated by the access request to obtain a context descriptor indicating the GPU instance, thereby obtaining a page table entry (PTE).

[0069] At step 408, the system memory management unit sends a memory request to the physical address generator, the memory request indicating the system memory management unit address.

[0070] For example, via the system memory management unit 522 , a memory request indicating a system memory management unit address (ie, SMMU_PA) is sent to the physical address generator 524 .

[0071] At step 410, the system memory management unit address is converted to a target physical address of the memory via a physical address generator.

[0072] For example, via the physical address generator 524 , the system memory management unit address (eg, SMMU_PA) is converted into a high-speed bus address; and via the high-speed bus 526 , the target physical address (ie, HBM_PA) for the high bandwidth memory 528 is addressed based on the high-speed bus address.

[0073] In the above scheme, the present invention can manage the internal management data flow and memory access of the GPU instance, thereby achieving hardware-level isolation.

[0074] The following will be combined Figure 5 and Figure 6 A method 600 for internally managing data flow and memory access for a GPU instance according to some other embodiments of the present invention is described. Figure 6 FIG. 6 is a flowchart of a method 600 for managing data flow and memory access within a GPU instance according to some other embodiments of the present invention. It should be understood that the method 600 may be implemented, for example, in Figure 1 The method 600 is executed at the described computing device 100. The method 600 may also include additional actions not shown and / or may omit the actions shown, and the scope of the present invention is not limited in this respect.

[0075] At step 602, an access request for a memory on the device side is sent via the host, where the access request indicates a PCIe address on the device side.

[0076] For example, via the CPU 510, an access request for the memory (e.g., HBM) on the device side (the access request, for example, indicates a PCIe address on the device side. The PCIe address is a physical address of the PCIe address space, or "PCIe_PA") is sent to the PCIe switch 512 (PCIe Switch); and then the access request is provided to the host portal 514 via the PCIe switch 512.

[0077] Regarding the PCIe switch 512, it is, for example, a device for expanding the connection capability of the PCIe bus, and is used to allow multiple PCIe devices to be connected to the same PCIe bus, thereby achieving management of communication and data transmission between multiple devices.

[0078] At step 604, the PCIe address is converted into a system memory management unit address via a host portal on the device side, so as to provide the system memory management unit address to a physical address generator.

[0079] Regarding the host portal (HA) on the device side, it has the ability of low-speed bus conversion.

[0080] At step 606, the system memory management unit address is converted into a target physical address of the memory on the device side via a physical address generator.

[0081] like Figure 5 As shown, the system memory management unit address (ie, SMMU_PA) is converted into a high-speed bus address via a physical address generator 524; and the target physical address (ie, HBM_PA) of the high bandwidth memory 528 is addressed based on the high-speed bus address via a high-speed bus 526.

[0082] In the above scheme, the present invention can enable the CPU to directly access the high-bandwidth memory via the PCIe switch, the host portal, and the physical address generator.

[0083] The various processes and processing described above, such as methods 200, 400, and 600, may be performed at a computing device. The computing device includes, for example: at least one processor (at least one graphics processor and at least one central processing unit); and a memory connected to the at least one processor in communication; wherein the memory stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor. In some embodiments, methods 200, 400, and 600 may be implemented as a computer software program or program product, which is tangibly contained in a machine-readable medium. In some embodiments, part or all of the computer program may be loaded and / or installed on a computing device via a read-only memory (ROM) and / or a communication unit. When the computer program is loaded into a random access memory (RAM) and executed by a GPU and a CPU, one or more actions of methods 200, 400, and 600 described above may be performed.

[0084] The present invention may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions for executing various aspects of the present invention. The computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof.

[0085] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. Various aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each box of the flowchart and / or block diagram, and the combination of boxes in the flowchart and / or block diagram, can be implemented by computer-readable program instructions.

[0086] These computer-readable program instructions can be provided to a central processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the central processing unit of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0087] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present invention. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the function involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be realized by a special hardware-based system that performs the function or action of the specification, or can be realized by a combination of special hardware and computer instructions.

[0088] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this application can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solution disclosed in this application can be achieved, and this document is not limited here.

[0089] The above specific implementations do not constitute a limitation on the protection scope of the present application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made according to design requirements and other factors.

Claims

1. A method for building a trusted execution environment, characterized in that: The method comprises: On the host side, configure multiple virtual machines; isolating the plurality of virtual machines; and On the device side, a hardware-isolated GPU instance is configured to form an independent hardware access path with at least one of the multiple virtual machines configured, so as to be used to build a trusted execution environment that supports confidential computing, wherein building the trusted execution environment that supports confidential computing includes: configuring multiple GPU instances that are hardware-isolated from each other; building the trusted execution environment based on an independent hardware access path formed by at least one GPU instance among the multiple GPU instances and a corresponding virtual machine among the multiple virtual machines; and managing data flow and memory access internally in at least one GPU instance used to build the trusted execution environment.

2. The method according to claim 1, characterized in that GPU instances configured for hardware isolation include: Isolate the address space of the hardware on the device side; and The memory, command processor, and computing cores associated with the configured GPU instances are isolated from each other.

3. The method according to claim 1, characterized in that Managing data flows and memory accesses within at least one GPU instance used to build the trusted execution environment includes: In a process run by the GPU instance, a command with an address space identifier is sent to a command queue so that a main module for processing the command in the GPU instance acquires the command; The main module processes the command to initiate an access request to the memory; The system memory management unit searches the context matching table through the address space identifier to obtain a valid context descriptor, thereby obtaining a page table entry, wherein the valid context descriptor indicates the GPU instance; The system memory management unit sends a memory request to the physical address generator, wherein the memory request indicates the system memory management unit address; and The system memory management unit address is converted to the target physical address of the memory through the physical address generator.

4. The method according to claim 1, characterized in that Managing data flows and memory accesses within at least one GPU instance used to build the trusted execution environment includes: Sending, via the host, an access request for a memory on the device side, wherein the access request indicates a PCIe address on the device side; converting the PCIe address into a system memory management unit address via a host portal on the device side, so as to provide the system memory management unit address to a physical address generator; and The system memory management unit address is converted to the target physical address of the memory on the device side via the physical address generator.

5. The method according to claim 2, characterized in that: Isolating the address space of the hardware on the device side includes: The system address space, the PCIe address space, the high-speed bus address, and the low-speed bus address are divided so as to be mapped with the configured GPU instance.

6. The method according to claim 1, characterized in that Building the trusted execution environment based on an independent hardware access path formed by at least one GPU instance among the multiple GPU instances and a corresponding virtual machine among the multiple virtual machines includes any of the following: Based on each GPU instance in the multiple GPU instances and a corresponding virtual machine in the multiple virtual machines, a hardware access path is formed respectively, thereby forming multiple hardware access paths; or Based on a GPU instance among the multiple GPU instances, multiple hardware access paths are respectively formed with multiple corresponding virtual machines among the multiple virtual machines through multiplexing.

7. The method according to claim 1, characterized in that Building the trusted execution environment based on an independent hardware access path formed by at least one GPU instance among the multiple GPU instances and a corresponding virtual machine among the multiple virtual machines includes: enabling a corresponding virtual machine used to form a hardware access path to directly access the at least one GPU instance; and Separate memory spaces, interrupts, and direct memory access data transfers are configured for the formed hardware access paths.

8. The method according to claim 5, characterized in that The system address space, PCIe address space, high-speed bus address, and low-speed bus address are divided for mapping with the configured GPU instance, including: The PCIe address space is virtualized into a plurality of blocks, so that the plurality of virtualized blocks are respectively mapped to the plurality of configured GPU instances.

9. A computing device, characterized in that: include: at least one processor; as well as a memory communicatively coupled to the at least one processor; in The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a machine, the method according to any one of claims 1 to 8 is performed.

11. A computer program product, characterized in that The invention comprises a computer program, which, when executed by a machine, performs the method according to any one of claims 1 to 8.

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