Processing module, instruction processing method and chip system

Abstract

This application discloses a processing module, instruction processing method, and chip system, belonging to the field of integrated circuit design technology. The method includes: in the instruction fetch stage of a reference instruction, predicting the instruction type of the reference instruction; if the predicted instruction type of the reference instruction is a RET instruction, predicting the first return address of the reference instruction, and queuing for instruction fetching according to the first return address; obtaining the second return address predicted in the pre-decoding stage of the reference instruction, verifying the first return address according to the second return address, and obtaining a verification result, which is used to control whether to continue queuing for instruction fetching according to the first return address. Predicting the first return address in the instruction fetch stage and queuing for instruction fetching in advance based on the first return address advances the instruction fetching time of the instruction corresponding to the first return address, making instruction fetching continuous and improving the processing efficiency of the processing module.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a processing module, instruction processing method, and chip system. Background Technology

[0002] In integrated circuit design, executing the RET (return) instruction results in a jump, redirecting the branch from the called program back to the calling program. Since the specific return address within the calling program is determined by the execution result of the RET instruction, waiting until the RET instruction finishes execution before fetching the instruction from its return address is inefficient and reduces processor performance. Therefore, a method is urgently needed to predict the return address of the RET instruction in advance during its processing.

[0003] In related technologies, the processor only begins to predict the RET instruction for reference instructions that belong to the RET instruction during the reference instruction pre-decoding stage, and then fetches the next instruction of the reference instruction based on the predicted jump address.

[0004] The above method predicts the return address and fetches the instruction only during the pre-decoding stage, and then starts processing the next instruction. There is a vacancy period between the processing time of the reference instruction and the processing time of the next instruction, resulting in low instruction processing efficiency of the processor. Summary of the Invention

[0005] This application provides a processing module, an instruction processing method, and a chip system, which can be used to solve problems existing in related technologies. The technical solution is as follows:

[0006] On one hand, embodiments of this application provide an instruction processing method, the method comprising:

[0007] During the instruction fetching phase of the reference instruction, the instruction type of the reference instruction is predicted;

[0008] If the prediction result indicates that the instruction type of the reference instruction is a RET instruction, predict the first return address of the reference instruction, and queue up the instruction fetching according to the first return address. The RET instruction is used to return when the called program ends the call.

[0009] Obtain the second return address predicted during the pre-decoding phase of the reference instruction, verify the first return address based on the second return address, and obtain a verification result. The verification result is used to control whether to continue queuing for instruction fetching based on the first return address.

[0010] In one possible implementation, predicting the instruction type of the reference instruction includes:

[0011] Obtain the identifier of at least one historical instruction, wherein the historical instruction is an executed RET instruction;

[0012] If the identifier of at least one historical instruction includes the identifier of the reference instruction, the instruction type of the reference instruction is determined to be the RET instruction; or, if the identifier of at least one historical instruction does not include the identifier of the reference instruction, the instruction type of the reference instruction is determined not to be the RET instruction.

[0013] In one possible implementation, the identifier of the reference instruction includes the hash result of the fetch address of the reference instruction, and the identifier of the historical instruction includes the hash result of the fetch address of the historical instruction.

[0014] In one possible implementation, predicting the first return address of the reference instruction includes:

[0015] Predict the first call instruction corresponding to the reference instruction during the instruction fetch phase;

[0016] The first jump address corresponding to the first call instruction is determined as the first return address.

[0017] In one possible implementation, the step of queuing for instruction fetching based on the first return address includes:

[0018] Write the first return address into the address queue to retrieve the instruction indicated by the first return address according to the queuing order of the first return address in the address queue.

[0019] In one possible implementation, obtaining the second return address predicted during the pre-decoding phase of the reference instruction includes:

[0020] Predict the second call instruction corresponding to the reference instruction in the pre-decoding stage;

[0021] The second jump address corresponding to the second call instruction is determined as the second return address.

[0022] In one possible implementation, verifying the first return address based on the second return address to obtain a verification result includes:

[0023] If the second return address and the first return address are the same, the verification result is determined to be that the first return address has passed verification;

[0024] Alternatively, if the second return address and the first return address are different, the verification result is determined to be that the verification of the first return address failed.

[0025] In one possible implementation, after verifying the first return address based on the second return address and obtaining the verification result, the method further includes:

[0026] If the verification result is that the first return address fails to be verified, the first return address used for queuing for instruction fetching is replaced with the second return address, so that instruction fetching can continue to be queued according to the second return address.

[0027] In one possible implementation, after predicting the instruction type of the reference instruction, the method further includes:

[0028] If the prediction result indicates that the instruction type of the reference instruction is not the RET instruction, the prediction of the first return address of the reference instruction is restricted.

[0029] The reference instruction is pre-decoded. If the pre-decoding result indicates that the instruction type is the RET instruction, the instruction is fetched in a queue according to the third return address, which is predicted during the pre-decoding stage of the reference instruction.

[0030] On the other hand, a processing module is provided, which includes an instruction prediction unit, an address control unit, and a verification unit. The instruction prediction unit and the address control unit are connected, and the verification unit is connected to both the instruction prediction unit and the address control unit.

[0031] The instruction prediction unit is used to predict the instruction type of the reference instruction during the instruction fetching stage of the reference instruction; if the prediction result indicates that the instruction type of the reference instruction is a RET instruction, it predicts the first return address of the reference instruction and sends the first return address to the address control unit and the verification unit. The RET instruction is used to return when the called program ends the call.

[0032] The address control unit is used to receive the first return address and queue up to fetch instructions according to the first return address;

[0033] The verification unit is configured to receive the first return address, obtain the second return address predicted during the pre-decoding stage of the reference instruction, verify the first return address based on the second return address, and obtain a verification result. The verification result is used to control whether the address control unit continues to queue for instruction fetching based on the first return address.

[0034] In one possible implementation, the instruction prediction unit is configured to acquire the identifier of at least one historical instruction, wherein the historical instruction is an executed RET instruction; if the identifier of the at least one historical instruction includes the identifier of the reference instruction, the instruction type of the reference instruction is determined to be the RET instruction; or, if the identifier of the at least one historical instruction does not include the identifier of the reference instruction, the instruction type of the reference instruction is determined not to be the RET instruction.

[0035] In one possible implementation, the identifier of the reference instruction includes the hash result of the fetch address of the reference instruction, and the identifier of the historical instruction includes the hash result of the fetch address of the historical instruction.

[0036] In one possible implementation, the first return address includes the first jump address corresponding to the first call instruction, and the first call instruction is the call instruction corresponding to the reference instruction in the instruction fetch stage;

[0037] The second return address includes the second jump address corresponding to the second call instruction, and the second call instruction is the call instruction corresponding to the reference instruction in the pre-decoding stage.

[0038] In one possible implementation, the address control unit is configured to write the first return address into an address queue to retrieve the instruction indicated by the first return address according to the queuing order of the first return address in the address queue.

[0039] In one possible implementation, the processing module further includes an instruction fetch bus, which is connected to the address control unit;

[0040] The address control unit is used to send the first return address to the instruction fetch bus;

[0041] The instruction fetch bus is used to receive the first return address, write the first return address into the address queue on the instruction fetch bus, and fetch the instruction indicated by the first return address according to the queuing order of the first return address in the address queue.

[0042] In one possible implementation, the verification unit is configured to determine that the verification result is that the first return address verification is successful when the second return address and the first return address are the same; or, when the second return address and the first return address are different, determine that the verification result is that the first return address verification is unsuccessful.

[0043] In one possible implementation, the verification unit is further configured to send the second return address to the address control unit if the verification result is that the first return address verification fails.

[0044] The address control unit is further configured to receive the second return address, replace the first return address used for queuing for instruction fetching with the second return address, and continue queuing for instruction fetching according to the second return address.

[0045] In one possible implementation, the processing module further includes a pre-decoding unit connected to the address control unit;

[0046] The instruction prediction unit is further configured to restrict the prediction of the first return address of the reference instruction when the prediction result indicates that the instruction type of the reference instruction is not the RET instruction;

[0047] The pre-decoding unit is used to pre-decode the reference instruction, determine the instruction type of the reference instruction based on the pre-decoding result, obtain a first determination result, and send the first determination result to the address control unit.

[0048] The address control unit is further configured to receive the first determination result, and when the first determination result indicates that the instruction type is the RET instruction, queue up for instruction fetching according to the third return address, which is predicted during the pre-decoding stage of the reference instruction.

[0049] In one possible implementation, the processing module further includes a prediction information unit, which is connected to both the verification unit and the instruction prediction unit.

[0050] The instruction prediction unit is used to send the first return address to the prediction information unit;

[0051] The prediction information unit is used to store the first return address and send the first return address to the verification unit during the pre-decoding stage of the reference instruction.

[0052] On the other hand, a computer device is provided, the computer device including a processor, the processor being configured to execute any of the instruction processing methods described above.

[0053] On the other hand, a chip system is also provided, which includes any of the processing modules described above.

[0054] The technical solution provided in this application brings at least the following beneficial effects:

[0055] During the instruction fetch phase, the instruction type of the reference instruction is predicted. Based on the prediction result, the first return address of the reference instruction is predicted. The first return address refers to the fetch address of the next instruction after the reference instruction returns. The next instruction is then queued and fetched based on this first return address. This advances the fetching time of the next instruction from the pre-decoding phase of the reference instruction to the fetch phase, improving the timeliness of next instruction processing, effectively eliminating processor idle time, and resulting in continuous instruction fetching and high processing efficiency. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a schematic diagram of an implementation environment provided in an embodiment of this application;

[0058] Figure 2 This is a flowchart of an instruction processing method provided in an embodiment of this application;

[0059] Figure 3 This is a schematic diagram of cavitation generation provided in an embodiment of this application;

[0060] Figure 4 This is a schematic diagram of the structure of a processing module provided in an embodiment of this application;

[0061] Figure 5 This is a schematic diagram of another processing module provided in an embodiment of this application;

[0062] Figure 6 This is a schematic diagram of the structure of another processing module provided in an embodiment of this application;

[0063] Figure 7 This is a schematic diagram of the structure of a computing module provided in an embodiment of this application;

[0064] Figure 8 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0065] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0066] This application provides an instruction processing method, please refer to... Figure 1The diagram illustrates the implementation environment of the method provided in this application embodiment. This implementation environment may include: a computer device 01. The computer device 01 has a processing module installed and running. The processing module is used to execute the instruction processing method provided in this application embodiment. When the reference instruction being processed is a RET instruction, the module fetches the next instruction after the RET instruction in advance based on the predicted first return address during the instruction fetch stage.

[0067] Optionally, computer device 01 can be any device with a processing module installed, such as a terminal, server, switch, or router. The installed processing module may be referred to as a processor in some cases. The processor may be a CPU (Central Processing Unit), such as a RISC-V CPU (RISC-V architecture CPU).

[0068] For example, the terminal can be any electronic product that allows human-computer interaction with the user through one or more methods such as a keyboard, touchpad, touchscreen, remote control, voice interaction, or handwriting device, such as PC (Personal Computer), mobile phone, smartphone, PDA (Personal Digital Assistant), wearable device, PPC (Pocket PC), tablet computer, smart car system, smart TV, smart speaker, etc. The server can be a single server or a server cluster composed of multiple servers.

[0069] Those skilled in the art should understand that the above-described computer device 01 is merely an example, and other existing or future devices that are applicable to this application should also be included within the scope of protection of this application, and are hereby incorporated by reference.

[0070] This application provides an instruction processing method that can be applied to the above-mentioned... Figure 1 In the implementation environment shown, this method can be executed by the processing module included in computer device 01, and the flowchart of the method is as follows. Figure 2 As shown, it includes steps 201-203.

[0071] In step 201, during the instruction fetching stage of the reference instruction, the instruction type of the reference instruction is predicted.

[0072] For example, the reference instruction can be any instruction to be processed. An instruction is a command that controls a computer device to perform a certain operation, including two parts: an opcode and operands. The opcode determines the operation to be performed, and the operands refer to the data involved in the operation and the address of the unit they reside in. Optionally, the reference instruction can be an instruction to be processed determined based on the execution result of an instruction that has already been executed, or it can be a predicted instruction to be processed. The embodiments of this application are not limited to operations performed based on reference instructions; they can be operations for running services, or operations for network maintenance or construction, etc.

[0073] In some cases, the processing module can employ pipelining technology to process reference instructions. Pipelining involves dividing the processing of an instruction into multiple stages, such as stage 1 and stage 2. For instructions A and B to be processed, after instruction B completes stage 1 and enters stage 2, the operation corresponding to stage 1 is executed on instruction B. Instruction B does not need to wait for instruction A to finish processing before starting processing; it can be processed in parallel during instruction B's processing, improving the instruction processing efficiency of the processing module. Optionally, the execution of the operation corresponding to the next stage can be based on the machine cycle, which is the processing time of an instruction at any stage, set based on experience and the implementation environment. After each machine cycle, it is determined that the instruction being processed has completed the operation of the current stage and enters the next stage to begin executing the operation corresponding to the next stage.

[0074] Optionally, the multiple stages of processing an instruction include, but are not limited to, the instruction fetch stage, the decode stage, the execution stage, the memory access stage, and the write-back stage. The instruction fetch stage refers to reading the instruction from memory. The decode stage decodes the fetched instruction, identifies the instruction type and the corresponding operand retrieval method for each instruction type, and then reads the operand from the GPR (General Purpose Register) within the processing module according to the operand retrieval method. If the operand is data in memory, the processing module can first execute a memory access instruction to read the operand from memory into the GPR, thereby obtaining the operand. In some cases, the decode stage includes a pre-decoding stage and a general decoding stage, which are used to perform different decoding operations.

[0075] Furthermore, depending on the number of pipeline stages, operand reading can be performed at different stages, such as the decoding stage or the execution stage. The execution stage executes the specific operation of the instruction based on the fetched operand. If the specific operation is an arithmetic operation, the processing module can determine the result during the execution stage. If the specific operation is to read the instruction from memory, the process enters the memory access stage, where data is read from memory as the result of the instruction operation. That is, the instruction may or may not go through the memory access stage; regardless of how the result of the instruction operation is obtained, it can be written to a general-purpose register during the write-back stage.

[0076] In one possible scenario, the processing operation can also be divided into an instruction fetch phase, a decoding phase, and an execution phase. Regardless of the phase division method used by the processing module, the reference instruction will always enter the instruction fetch phase and the pre-decoding phase. Optionally, since the reference instruction is a predicted instruction to be processed, that is, an instruction to be executed in advance based on the prediction result, the processing of the reference instruction is considered pre-processing. Therefore, the instruction fetch phase of the reference instruction can be called the pre-fetch phase in some cases.

[0077] For example, the reference instruction enters the fetch stage. In this case, the operation performed by the processing module is to fetch the reference instruction from memory. Since the fetch stage only performs the operation of retrieving the reference instruction from memory and does not parse the reference instruction, the processing module cannot determine the instruction type of the reference instruction during the fetch stage. Therefore, the processing module can predict the instruction type of the reference instruction during the fetch stage and obtain the prediction result.

[0078] In one possible approach, the process of predicting the instruction type includes: obtaining an identifier of at least one historical instruction, wherein the historical instruction is an executed RET instruction; if the identifier of at least one historical instruction includes an identifier of a reference instruction, determining that the instruction type of the reference instruction is a RET instruction; or if the identifier of at least one historical instruction does not include an identifier of a reference instruction, determining that the instruction type of the reference instruction is not a RET instruction.

[0079] For example, the RET instruction is used to return to the calling program when the called program finishes its call, and to bring back the value processed by the called program to the calling program, so that the calling program can continue running based on the returned value. The calling program refers to the program executed before the jump to the called program. The calling program and the called program can be, for example, functions or models.

[0080] In one possible scenario, for executed RET instructions (i.e., historical instructions), the processor will collect and store the identifiers of each historical instruction. These identifiers can be any distinguishable information, including but not limited to instruction name and fetch address. In some cases, due to the large amount of instruction address data and the high maintenance overhead of maintaining instruction addresses, the processing module can hash the fetch address of the historical instruction, obtain the hash result, and use the hash result as the identifier of the historical instruction, thereby reducing maintenance overhead. Optionally, the processing module stores the collected identifiers of historical instructions in the BTB (branch target buffer).

[0081] Regardless of the method or type of identifier stored by the processing module, the instruction type of the reference instruction can be predicted based on the identifier of the historical instruction after the reference instruction is retrieved. The following example, using the identifier obtained by hash calculation of the fetch address stored in the BTB, illustrates the process of determining whether the identifier of at least one historical instruction includes the identifier of the reference instruction.

[0082] Based on the historical instruction identifier obtained by hashing the fetch address of the historical instruction, the processing module also performs a hash calculation on the fetch address of the reference instruction to obtain the reference instruction identifier. Then, the processing module searches for the reference instruction identifier in the BTB (Block Execution Block). When the reference instruction identifier matches any identifier in the BTB, meaning at least one identifier in the BTB includes the reference instruction identifier, the reference instruction is determined to be a historical instruction to be executed again. The instruction type of the reference instruction is consistent with the instruction type of the historical instruction, which is a RET instruction.

[0083] When the identifier of a reference instruction does not match any identifier in the BTB (Bill of Materials), meaning at least one identifier in the BTB does not include the identifier of the reference instruction, it is determined that the reference instruction does not belong to the history of instructions to be executed again, and thus the reference instruction is determined not to be a RET instruction. Here, "reference instruction is not a RET instruction" means that the reference instruction predicted during the instruction fetch phase is not a RET instruction, rather than being used to limit the actual instruction type of the reference instruction. The reference instruction can be a RET instruction whose identifier is not stored in the BTB; for example, the reference instruction may be a RET instruction that has never been executed before, or it may be another instruction type.

[0084] Furthermore, in the process of searching through historical instruction identifiers using the identifier of the reference instruction, the identifier of the historical instruction can sometimes be referred to as the entry or index of the historical instruction. By determining whether the reference instruction is a historical instruction through this search, the instruction type can be successfully predicted during the instruction fetching stage when the reference instruction appears periodically.

[0085] In step 202, if the prediction result indicates that the instruction type of the reference instruction is RET, the first return address of the reference instruction is predicted, and the instruction is fetched in a queue according to the first return address. The RET instruction is used to return when the called program ends the call.

[0086] For example, if the processing module predicts that the reference instruction may be a RET instruction, it can predict the first return address of the reference instruction, which is also the fetch address of the next instruction after the predicted reference instruction.

[0087] Because the RET instruction involves a jump to an instruction branch—for example, a processor might have two instruction branches, one containing multiple instructions for the calling program and the other for the called program—the execution of the RET instruction jumps from the called program's instruction branch to the calling program's instruction branch. This means the next instruction after the RET instruction is located in the calling program's instruction branch. The processing module cannot treat the instruction following the RET instruction in the called program's instruction branch as the next instruction; instead, it predicts the next instruction within the calling program's instruction branch.

[0088] For branch jumps caused by the RET instruction, the processing module can predict the first return address of the RET instruction based on the corresponding call instruction. In some cases, the RET and call instructions appear in pairs, with the call instruction appearing first, followed by the RET instruction. The call instruction indicates that the program flow should be switched from the currently running calling program to the called program, while the RET instruction indicates that the program should return to the calling program after the called program finishes its call. Therefore, the RET instruction returns the location jumped to by the call instruction, and the next instruction executed after the call instruction is the adjacent instruction in the calling program. Based on this, the processing module can first predict the first call instruction corresponding to the reference instruction during the instruction fetch phase, and then determine the first jump address corresponding to the first call instruction as the first return address.

[0089] Optionally, the first call instruction is the most recently committed call instruction during the instruction fetch phase. Committing a call instruction means writing the jump address of the call instruction into a memory location, such as a destination register. The jump address is the PC (Program Counter) value of the instruction following the call instruction in the calling program. Since the call instruction also involves program jumps from the calling program to the called program, the processing module also writes the jump address of the call instruction into memory during the execution of the call instruction. Writing the jump address records the return position when the call instruction ends.

[0090] In one possible scenario, when multiple called programs are invoked, the program invoked first returns last. For example, during the execution of program A, function A is called. During the calculation of function A, function B is also called. Upon returning, the most recently called function B is returned first. The value calculated based on function B is returned to function A. Function A then continues its calculation based on the returned value and returns the result to program A, which then invokes the program based on the result. Function B is called later than function A, but function B returns earlier than function A.

[0091] Therefore, the most recently submitted call instruction during the instruction fetch stage can be identified as the first call instruction. Then, the first jump address corresponding to the first call instruction is searched in the memory location to obtain the first return address. In one possible implementation, the jump address used to write the call instruction is a stack. The stack processing principle is consistent with that of the call and RET instructions: Last-In-First-Out (LIFO). For example, the stack includes two jump addresses, jump address A and jump address B. Jump address A is pushed onto the stack before jump address B, and jump address B is popped from the stack before jump address A. The processing module maintains a stack. When the decoding stage determines that the instruction being processed is a call instruction, the fetch address of the next instruction following the call instruction is pushed onto the stack as the corresponding jump address.

[0092] When the processing module finds the jump address corresponding to the submitted call instruction by counting the stack, it can find and determine the first call instruction from the stack. For example, the processing module takes the call instruction corresponding to the jump address at the top of the stack as the first call instruction. At this time, the jump address at the top of the stack is also the first jump address. The processing module takes the first jump address as the first return address of the predicted reference instruction.

[0093] Since the first return address of the reference instruction indicates the fetch address of the next instruction to be executed after the reference instruction, the processing module can fetch the next instruction from memory in advance based on the first return address. Thus, after the reference instruction has been executed and the next instruction has been processed, the module can directly process the fetched next instruction, omitting the instruction fetching step and improving processing efficiency.

[0094] Optionally, the processing module can write the first return address into an address queue to retrieve the instruction indicated by the first return address according to the queuing order of the first return addresses in the address queue. In some cases, the address queue is provided by an instruction fetch BUS (bus) included in the processing module. The instruction fetch bus queues the received instruction fetch addresses sequentially to obtain the address queue, and retrieves the instruction indicated by the first return address according to the queuing order of the first return addresses in the address queue, that is, the next instruction to jump to based on the reference instruction. In one possible case, queuing for instruction fetching can also be understood as waiting for a machine cycle, that is, the address bus will queue and wait for the reference instruction to pass through the instruction fetch stage and enter the decoding stage before fetching the next instruction from memory according to the first return address.

[0095] For example, if the prediction result does not indicate that the instruction type of the reference instruction is RET, the processing module will restrict the prediction of the first return address of the reference instruction, that is, it will not predict the return address during the instruction fetch stage. After the reference instruction is fetched during the instruction fetch stage, it will wait to enter the pre-decoding stage.

[0096] In step 203, the second return address predicted during the pre-decoding stage of the reference instruction is obtained, and the first return address is verified based on the second return address to obtain the verification result. The verification result is used to control whether to continue queuing for instruction fetching based on the first return address.

[0097] For example, after the instruction fetch phase ends, the reference instruction may enter the pre-decoding phase. The processing module predicts a second return address during the pre-decoding phase of the reference instruction, and uses the second return address to verify the first return address to determine whether the first return address is accurate.

[0098] Since the first return address is predicted during the instruction fetch phase, there's a possibility that the reference instruction and its corresponding call instruction are located close to each other in the program, with a very short processing time. When the reference instruction is in the instruction fetch phase, the corresponding call instruction hasn't yet undergone the pre-decoding phase. Therefore, the jump address corresponding to the call instruction hasn't been written to memory, meaning the call instruction hasn't been committed. In this case, the most recently committed call instruction during the instruction fetch phase is not the call instruction corresponding to the reference instruction. The processing module will also predict the second call instruction corresponding to the reference instruction and determine the second jump address corresponding to the second call instruction as the second return address.

[0099] The process of predicting the second call instruction is similar to that of predicting the first call instruction. The second call instruction refers to the most recently submitted call instruction during the pre-decoding phase. Since call instructions are executed before RET instructions, when a reference instruction belonging to the RET instruction enters the pre-decoding phase, the corresponding call instruction has already passed through the pre-decoding phase and entered the next phase. The processing module can then use the most recently submitted call instruction as the second call instruction. Afterward, the processing module can determine the second return address using a similar operation to determining the first return address, which will not be repeated here.

[0100] Since the processing module may or may not predict the first return address during the instruction fetch phase, after obtaining the second return address, the processing module will also obtain the prediction result, determine whether the first return address predicted during the instruction fetch phase exists based on the prediction result, and verify the first return address based on the second return address if the first return address exists.

[0101] For example, during the processing of various instructions, including the reference instruction, the processing module stores the prediction results of each instruction. For instance, the prediction results of each instruction can be stored in a queue, which may reside in the memory space of a prediction information queue. The processing module can then retrieve the prediction result of the reference instruction from among the prediction results of multiple instructions.

[0102] Similar to the process of searching for the identifier of a reference instruction among multiple historical instruction identifiers, the prediction result of the reference instruction can also be searched based on the identifier of the reference instruction. That is, there is a one-to-one correspondence between entries and instructions in the queue. After extracting the prediction result of the reference instruction based on the identifier of the reference instruction, the processing module determines whether to predict it as a RET instruction based on the prediction result.

[0103] In one possible implementation, the processing module can also store the return addresses of each predicted instruction. When the reference instruction reaches the pre-decoding stage, it searches for the first return address from the stored multiple return addresses. The process of searching for the first return address is similar to searching for the prediction result; both can be based on the identifier of the reference instruction. If the processing module does not find the first return address among the multiple return addresses, it determines that the reference instruction was not predicted as a RET instruction during the instruction fetch stage, and therefore, the first return address for the reference instruction does not exist. If the processing module finds the first return address among the multiple return addresses, it determines that the reference instruction was predicted as a RET instruction during the instruction fetch stage, and therefore, the first return address for the reference instruction exists. The processing module can then verify the first return address.

[0104] In one possible scenario, the process of verifying the first return address includes: if the second return address and the first return address are the same, determining that the verification result is that the first return address has been verified successfully; or, if the second return address and the first return address are different, determining that the verification result is that the first return address has failed to be verified.

[0105] For example, the processing module compares the first return address and the second return address. When the first return address and the second return address are the same, that is, the call instruction recently submitted in the pre-decoding stage and the call instruction recently submitted in the instruction fetch stage are the same instruction, and no new call instruction is submitted during the period when the reference instruction enters the pre-decoding stage from the instruction fetch stage, the first call instruction predicted in the instruction fetch stage is the call instruction corresponding to the reference instruction. The first call instruction is predicted correctly, and the first return address determined based on the correctly predicted first call instruction is also correct. The first return address is verified.

[0106] When the first return address and the second return address are different, it indicates that the most recently submitted call instruction in the pre-decoding phase and the most recently submitted call instruction in the fetch phase are not the same instruction. During the period when the reference instruction enters the pre-decoding phase from the fetch phase, a new call instruction exists, namely the second call instruction. Based on the last-in-first-out (LIFO) principle of RET and call instructions, the most recently processed reference instruction should be the RET instruction corresponding to the most recently called call instruction. Therefore, the call instruction corresponding to the reference instruction should be the second call instruction, not the first call instruction. The jump address after the execution of the reference instruction should be the second jump address of the second call instruction, not the first jump address of the first call instruction. The first return address determined based on the first jump address is not the return address of the reference instruction; therefore, the verification of the first jump instruction fails.

[0107] Optionally, since the processing module performs the verification process of the first return address simultaneously during the pre-decoding of the reference instruction, it can control whether to continue queuing for instruction fetching based on the first return address based on the pre-decoding result and the verification result. Pre-decoding the reference instruction refers to converting the binary reference instruction into control signals, which are used to control various components in the computer device. Through pre-decoding, the processing module can identify the instruction type, operands, and execution method, and prepare for subsequent general decoding steps.

[0108] In one possible implementation, the pre-decoding result of the reference instruction includes the instruction type of the reference instruction. The processing module can determine the instruction type of the reference instruction based on the pre-decoding result to obtain a second determination result. If the second determination result indicates that the instruction type is a RET instruction and the verification result indicates that the first return address has been verified, the instruction fetching continues to be queued according to the first return address. Alternatively, if the second determination result indicates that the instruction type is not a RET instruction or the verification result indicates that the first return address has not been verified, the instruction fetching continues to be queued according to the first return address.

[0109] Since both the first and second return addresses are predicted based on the premise that the reference instruction is a RET instruction, and the decoded instruction type is RET, it indicates that the premise of predicting the first and second return addresses is correct. Therefore, the second return address is a correctly predicted return address. The first return address, which is verified based on the correctly predicted second return address, is also a correctly predicted return address. The instruction fetched based on the first return address is a valid instruction. The processing module does not need to re-fetch the instruction or adjust the instruction fetching process based on the first return address. The next instruction fetched in the instruction fetching stage can be processed directly, effectively eliminating the pipeline dummy period.

[0110] Figure 3 This is a schematic diagram of cavitation generation provided in an embodiment of this application. Figure 3 The `clock` parameter indicates the duration of a machine cycle in a stage of the pipeline. The `instruction` parameter processed by the processing module includes the `ret` instruction and `instru_b` (instruction b). The `fetch_address` parameter includes address a (a_addr), address ret (ret_addr), and address c (c_addr). Address a and address c are used to refer to the fetch addresses of other instructions different from the `ret` instruction. See also... Figure 3 The fetch_address and the return address ret_addr of the ret instruction are not successfully predicted until the ret instruction has gone through two stages, that is, until it reaches the decoding stage. Therefore, after fetching the ret instruction, although the processing module fetches a new instruction, the new instruction is on the wrong path and is an invalid instruction. The instruction_valid (valid instruction) executed by the processing module has a bubble.

[0111] based on Figure 3As can be seen, by using the instruction processing method provided in the embodiments of this application, the return address can be predicted when the reference instruction enters the instruction fetch stage. When the reference instruction enters the pre-decoding stage, the processing module accesses a new instruction in the instruction fetch stage. For example, the next instruction of the reference instruction is fetched according to the return address, thus eliminating cavitation in the instruction processing pipeline.

[0112] Optionally, if the second determination result indicates that the instruction type is not a RET instruction, then both the first and second return addresses predicted based on the premise that the reference instruction is a RET instruction are incorrectly predicted return addresses. In this case, regardless of whether the verification result of the first return address is successful or unsuccessful, the first return address is an incorrectly predicted return address, and the instruction queued for fetching based on the incorrectly predicted first return address is an invalid instruction. Therefore, the processing module can cancel continuing to queue for instruction fetching based on the first return address.

[0113] In one possible scenario, after canceling the instruction fetch queue based on the first return address, the processing module will further determine the fetch address of the next instruction after the reference instruction based on the decoded instruction type. For example, if the decoded instruction type indicates that the reference instruction is an instruction that did not involve a jump, the processing module can take the instruction following the reference instruction in the program containing the reference instruction as the next instruction, determine the fetch address of the next instruction, and adjust the instruction fetch queue process based on the fetch address of the next instruction. The process of adjusting the instruction fetch queue based on the fetch address of the next instruction is similar to the process of adjusting the instruction fetch queue based on the second return address, as described in the relevant embodiments below, and will not be repeated here.

[0114] For example, if the second determination result indicates that the instruction type is a RET instruction, but the verification result of the first return address indicates that the verification of the first return address fails, the processing module can adjust the address in the instruction fetch queue from the first return address to the second return address. For example, the first return address in the address queue can be replaced with the second return address so that instruction fetching can continue to be queued based on the second return address.

[0115] Optionally, the replacement can be performed by overwriting at the same location, or the original first return address in the address queue can be discarded and a new second return address can be written. If the first return address is early in the queue and an instruction has already been fetched based on the first return address when the second return address is predicted, the processing module will discard the prematurely fetched instruction and re-fetch it based on the second return address. For example, the second return address can be sent to the address bus to notify it to fetch the instruction from memory based on the received second return address. By correcting the first return address in case of prediction failure, pipeline flushing caused by instructions fetched based on the first return address is prevented from flowing to subsequent stages, thus avoiding more cavitation.

[0116] In one possible scenario, the pre-decoding result, besides controlling and adjusting the instruction fetching queue, can also adjust the identifiers of historical instructions. If the decoded instruction type is a RET instruction, but the instruction type predicted during the fetching stage is not a RET instruction, the processing module can write the identifier of the reference instruction into a storage unit used to store identifiers of historical instructions, such as the BTB in the above embodiment. By writing the identifiers of unpredicted RET instructions, the richness of the historical instruction identifiers stored in the BTB is increased, resulting in higher accuracy for subsequent instruction type predictions based on a richer BTB.

[0117] Alternatively, if the decoded instruction type is not RET, but the prediction result indicates that the instruction type is RET, the processing module can delete the reference instruction identifier stored in the storage unit used to store historical instruction identifiers. Timely deletion of erroneous identifiers stored in the storage unit improves the accuracy of the stored identifiers, thereby improving the accuracy of the prediction results based on the stored identifiers.

[0118] For example, if the processing module determines, based on the prediction result, that the reference instruction was not predicted as a RET instruction during the instruction fetch stage, and the reference instruction did not predict a first return address during the instruction fetch stage, i.e., the first return address does not exist, the processing module can determine the instruction type of the reference instruction based on the pre-decoding result after pre-decoding the reference instruction, obtaining a first determination result; if the first determination result indicates that the instruction type is a RET instruction, the instruction is fetched in a queue based on a third return address, which is predicted during the pre-decoding stage of the reference instruction.

[0119] Optionally, the process of predicting the third return address is similar to the process of predicting the second return address. The operation of queuing for instruction fetching based on the predicted third return address is similar to the operation of queuing for instruction fetching based on the first return address; see the relevant description in step 201, which will not be repeated here. Since this embodiment of the application performs prediction for the RET instruction not only in the instruction fetch stage but also in the pre-decoding stage, the above instruction processing process can, in some cases, be referred to as a two-stage prediction for the RET instruction. In one possible implementation, the processing module executes the coremark program to employ the above instruction processing method.

[0120] In summary, the instruction processing method provided in this application predicts the instruction type of a reference instruction during the instruction fetch stage. Based on the prediction result of the instruction type, it begins to predict the first return address of the reference instruction. The first return address indicates the next instruction that may be executed after the reference instruction. By fetching instructions in advance based on the first return address, the processing time of the next instruction following the reference instruction is advanced, ensuring timely processing of the next instruction, effectively eliminating idling periods in the processing pipeline, making instruction fetching continuous, and improving processing efficiency. Subsequently, when the reference instruction reaches the pre-decoding stage, the first return address is verified to ensure the accuracy of the predicted first return address.

[0121] This application embodiment also provides a processing module for executing Figure 2 The instruction processing method is shown. See also Figure 4 The processing module includes an instruction prediction unit 11, an address control unit 12, and a verification unit 13. The instruction prediction unit 11 and the address control unit 12 are connected, and the verification unit 13 is connected to both the instruction prediction unit 11 and the address control unit 12.

[0122] For example, the instruction prediction unit 11 may predict the instruction type of a reference instruction during the instruction fetching stage. In one possible scenario, the instruction prediction unit 11 may obtain the identifier of the reference instruction during the instruction fetching stage to predict the instruction type of the reference instruction based on the identifier.

[0123] The prediction process includes, but is not limited to: obtaining the identifier of at least one historical instruction, wherein the historical instruction is an executed RET instruction; if the identifier of at least one historical instruction includes the identifier of a reference instruction, determining that the instruction type of the reference instruction is a RET instruction; or if the identifier of at least one historical instruction does not include the identifier of a reference instruction, determining that the instruction type of the reference instruction is not a RET instruction.

[0124] For example, when the identifier of a historical instruction includes the hash result of the fetch address of the historical instruction, the identifier of the reference instruction used by the instruction prediction unit 11 includes the hash result of the fetch address of the reference instruction. In this case, the instruction prediction unit 11 can obtain the identifier obtained by hashing the fetch address, or it can first obtain the fetch address of the reference instruction, and then hash the fetch address to obtain the identifier of the reference instruction.

[0125] See Figure 5 During the instruction fetching phase, the address control unit 12 sends the fetch address of the reference instruction to the fetch bus 14 to fetch the reference instruction. While sending the fetch address of the reference instruction to the fetch bus 14, the address control unit 12 also sends the fetch address of the reference instruction to the instruction prediction unit 11. Figure 5The slash arrow indicates that a multi-bit signal is transmitted based on this connection, meaning the fetch address of the reference instruction is a multi-bit signal with a bit width of 32 bits. After receiving the fetch address of the reference instruction, the instruction prediction unit 11 hashes the fetch address to obtain the identifier of the reference instruction.

[0126] Optionally, the process of obtaining the prediction result based on the identifier of the reference instruction can be referred to in step 201. The instruction prediction unit 11 can also use the BTB corresponding to the RET instruction to perform prediction. The BTB is used to store the identifiers of executed RET instructions, i.e., historical instructions. If the identifier of the reference instruction matches an entry in the BTB, the prediction result indicates that the instruction type of the reference instruction is RET instruction.

[0127] In one possible scenario, after obtaining the prediction result, the instruction prediction unit 11 may predict the first return address of the reference instruction if the prediction result indicates that the instruction type of the reference instruction is a RET instruction. The first return address includes the first jump address corresponding to the first call instruction, where the first call instruction is the call instruction corresponding to the reference instruction during the instruction fetch stage.

[0128] Since the BTB does not store the jump address, in some cases the jump address can be stored in the stack. See also... Figure 5 The processing module also includes a stack unit 17, which is connected to the instruction prediction unit 11. The stack unit 17 performs the stack operations in step 202 to count the jump addresses corresponding to call instructions. In this case, the call instruction corresponding to the reference instruction during the fetch phase refers to the call instruction corresponding to the latest jump address pushed onto the stack by the stack unit 17 during the fetch phase.

[0129] Optionally, the process of the instruction prediction unit 11 predicting the first return address is as follows: when the prediction result indicates that the instruction type of the reference instruction is a RET instruction, the instruction prediction unit 11 sends a pop command to the stack unit 17. The stack unit 17 pops the latest first jump address based on the received pop command. The instruction prediction unit 11 receives the first jump address popped by the stack unit 17 and uses the received first jump address as the first return address for instruction fetching.

[0130] In one possible scenario, the address control unit 12 included in the processing module is used for queuing instruction fetching. After obtaining the first return address, the instruction prediction unit 11 sends the first return address to the address control unit 12, and the address control unit 12 queues instruction fetching according to the first return address. Figure 5 In the table, predict_addr corresponds to the first return address.

[0131] Optionally, the address control unit 12 is configured to write the first return address into an address queue, so as to retrieve the instruction indicated by the first return address according to the queuing order of the first return address in the address queue. See also Figure 5 The processing module also includes an instruction fetch bus 14, which is connected to the address control unit 12. After receiving the first return address from the instruction prediction unit 11, the address control unit 12 sends the first return address to the instruction fetch bus 14. Upon receiving the first return address, the instruction fetch bus 14 writes it into the address queue and retrieves the instruction indicated by the first return address according to its queuing order in the address queue. A description of the instruction fetch queuing process on the instruction fetch bus 14 can be found in step 202, and will not be repeated here.

[0132] In one possible scenario, besides queuing for instruction fetching based on the first return address during the reference instruction fetch phase, the processing module may also verify the predicted first return address during the reference instruction pre-decoding phase. For example... Figure 4 and Figure 5 As shown, the processing module also includes a verification unit 13, which is connected to the instruction prediction unit 11 and the address control unit 12. Figure 5 The verification unit 13 in the diagram belongs to a combinational logic circuit, which includes a comparator and a selector. The comparator corresponds to... Figure 5 The equals sign circle in the text indicates the comparison logic of whether items are equal, and the selector corresponds to this. Figure 5 In the case of a trapezoidal selector, the selector is, for example, MUX (Multiplexer).

[0133] In one possible implementation, the verification unit 13 is used to obtain the second return address predicted during the pre-decoding stage of the reference instruction, verify the first return address based on the second return address, and obtain the verification result. The verification result is used to control whether to continue queuing for instruction fetching based on the first return address.

[0134] Continue with Figure 5 For example, after the fetch bus 14 fetches the reference instruction according to the fetch address of the reference instruction, it sends the fetched reference instruction to the pre-decoding unit 15. When the pre-decoding unit 15 starts pre-decoding the received reference instruction, other units in the processing module will receive a signal indicating that the reference instruction has entered the pre-decoding stage, thereby determining that the pre-decoding stage of the reference instruction has been reached and starting to verify the first return address.

[0135] In one possible scenario, the second return address refers to the second jump address corresponding to the second call instruction. The second call instruction is the call instruction corresponding to the reference instruction during the pre-decoding phase. The second call instruction is the most recently submitted call instruction during the pre-decoding phase of the reference instruction. The second jump address refers to the PC of the instruction following the second call instruction. For a detailed description of the second call instruction and the second jump address, please refer to [link to relevant documentation]. Figure 2 The illustrated embodiment describes the second call instruction and the second jump address. Exemplarily, the process of stack unit 17 and verification unit 13 interactively predicting the second return address of a reference instruction includes: when stack unit 17 receives a signal and determines that the reference instruction has entered the pre-decoding stage, it pops the latest second jump address currently pushed onto the stack and sends the popped second jump address to verification unit 13. Verification unit 13 uses the received second jump address as the predicted second return address.

[0136] In addition to obtaining the second return address, the verification unit 13 also receives the first return address to be verified sent by the instruction prediction unit 11. Optionally, the processing module further includes a prediction information unit 16, which is connected to both the verification unit 13 and the instruction prediction unit 11. That is, the connection between the verification unit 13 and the instruction prediction unit 11 is an indirect connection achieved through the prediction information unit 16.

[0137] Optionally, the instruction prediction unit 11 sends a first return address to the prediction information unit 16. The prediction information unit 16 stores the first return address and sends it to the verification unit 13 during the pre-decoding phase of the reference instruction. In one possible scenario, the prediction information unit 16 may receive return addresses predicted by different instructions during the instruction fetch phase. The prediction information unit 16 will search for the first return address among multiple return addresses. If the reference instruction is not predicted as a RET instruction during the instruction fetch phase, the instruction prediction unit 11 will not predict the first return address during the instruction fetch phase, meaning the first return address does not exist, and the prediction information unit 16 will not find the first return address among the stored return addresses.

[0138] If the reference instruction is predicted as a RET instruction during the instruction fetch stage, and this reference instruction has a first return address, the prediction information unit 16 can find the first return address and send it to the verification unit 13. In addition to storing the first return address, the prediction information unit 16 can also store the prediction result of the reference instruction. In this case, the prediction information unit 16 can first determine whether a first return address exists based on the prediction result, and then, if a first return address exists, send the stored first return address to the verification unit 13.

[0139] For example, after receiving the second return address and the first return address, the verification unit 13 can compare whether the second return address and the first return address are the same. If the second return address and the first return address are the same, the verification result is determined to be that the first return address verification is successful; or, if the second return address is different, the verification result is determined to be that the first return address verification is unsuccessful. For a detailed description of the verification of the first return address, please refer to the process of verifying the first return address in step 203, which will not be repeated here.

[0140] After determining the verification result, the verification unit 13 can control the address control unit 12 to continue queuing for instruction fetching based on the first return address. Figure 5 Taking the verification unit 13 shown, which includes a comparator and a selector, as an example, the process of verifying the first return address and the second return address, and controlling the process based on the verification result, is explained. The stack unit 17 sends the second return address to both the comparator and the selector, and the prediction information unit 16 sends the first return address to both the comparator and the selector. The comparator determines whether the received first and second return addresses are the same, obtains the verification result, and sends the verification result to the selector. The selector selects the output address from the first and second return addresses based on the verification result.

[0141] For example, if the comparator outputs a verification result indicating that the first return address and the second return address are different, meaning the verification of the first return address failed, the selector selects the second return address as the output address. If the comparator outputs a verification result indicating that the first return address and the second return address are the same, meaning the verification of the first return address passed, the selector selects the first return address as the output address. The selector sends the selected output address to the address control unit 12 to control whether the address control unit 12 continues to queue for instruction fetching based on the first return address.

[0142] In one possible scenario, after pre-decoding the reference instruction and obtaining the pre-decoding result, the pre-decoding unit 15 will further determine the instruction type of the reference instruction based on the pre-decoding result, obtain a second determination result, and send the second determination result to the address control unit 12. The second determination result is, for example,... Figure 5 The instr_is_ret shown indicates that the instruction type is RET instruction.

[0143] After receiving the second determination result, the address control unit 12 can determine whether to send the output address to the instruction fetch bus 14 based on the second determination result and the received output address, so as to adjust the instruction fetching process queuing according to the first return address. The address control unit 12 adjusts the instruction fetching process queuing according to the first return address based on the second determination result and the output address. Figure 2The process of adjusting the first return address queue for instruction fetching based on the second determination result and the verification result in the embodiment shown is similar. Please refer to the process of adjusting the queue for instruction fetching in step 203. It will not be repeated here.

[0144] In one possible scenario, the instruction prediction unit 11 may further restrict the prediction of the first return address of the reference instruction if the prediction result does not indicate that the instruction type of the reference instruction is RET. In this case, although the instruction prediction unit 11 does not predict the return address of the reference instruction during the instruction fetch stage, the stack unit 17 will still determine the return address of the reference instruction during the pre-decoding stage, thus obtaining the third return address. In this case, since the first return address does not exist, the verification unit 13 only receives the third return address and does not receive the first return address to be verified. Therefore, the verification unit 13 does not need to compare and select again, but directly sends the received third return address to the address control unit 12, thereby obtaining the third return address predicted by the reference instruction during the pre-decoding stage.

[0145] Optionally, during the pre-decoding stage, the pre-decoding unit 15 also pre-decodes the reference instruction, determines the instruction type of the reference instruction based on the pre-decoding result, and obtains a first determination result. The address control unit 12 is used to queue and fetch instructions according to the third return address if the first determination result indicates that the instruction type is a RET instruction. That is... Figure 5 The fetch_addr (fetch address) sent by the address control unit 12 to the fetch bus 13 can be understood as the first return address of the fetch stage, and the second or third return address of the pre-decoding stage.

[0146] The embodiments in this application are intended to illustrate the various units that may be included in the processing module and the functions of each unit, rather than to limit the shape, name, or location of each unit in the processing module. In some cases, the instruction prediction unit 11 may be called a prediction unit, the address control unit 12 may be called a fetch address control, the instruction fetch bus 14 may be called a BUS, the pre-decode unit 15 may be called a predecode, the prediction information unit 16 may be called a prediction information queue, and the stack unit 17 may be called a RAS (return address stack).

[0147] Figure 6 This application provides a processing module for predicting the return address of a reference instruction only during the pre-decoding stage. Figure 6In this application, the processing module only includes predecode, RAS, BUS, and fetch address control. After the reference instruction (instr_rdata) is retrieved, predecode is used to pre-decode the reference instruction to determine if it is a RET instruction. If it is a RET instruction, the latest address pushed onto the stack in RAS is sent to the fetch address control. The fetch address control then updates the BUS with the received address in the next clock cycle and discards all instructions prefetched by the BUS, waiting for the instruction updated to the BUS address to be retrieved before continuing with the instruction process. This reference instruction processing can also be called a first-level prediction process. Compared to other applications, the processing module provided in this application... Figure 6 The instruction processing module can predict the first return address in advance during the instruction fetch stage and fetch the instruction in advance, resulting in high instruction processing efficiency.

[0148] In summary, the processing module provided in this application predicts the instruction type of the reference instruction during the instruction fetch stage. Based on the prediction result of the instruction type, it begins to predict the first return address of the reference instruction. The first return address indicates the next instruction that may be executed after the reference instruction. By fetching the instruction in advance based on the first return address, the processing time of the next instruction following the reference instruction is advanced, ensuring timely processing of the next instruction, effectively eliminating the processor's idle period, making instruction fetching continuous, and improving processing efficiency. Subsequently, in the pre-decoding stage, a second return address is predicted to verify the first return address, ensuring the accuracy of the predicted first return address. Compared to... Figure 6 The processing module shown eliminates cavitation during the first-level prediction of the reference instruction using only a small amount of logic, thus improving the performance of the processing module.

[0149] Figure 7 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. The computing device corresponds to... Figure 1 The computer device 01 shown can be a server, a terminal, or a SoC (System on Chip) chip. Optionally, the computing device can vary significantly due to different configurations or performance, and may include one or more processors (Central Processing Units, CPUs) 701 and one or more memories 702, wherein the one or more memories 702 store at least one instruction, which is loaded and executed by the one or more processors 701 using the instruction processing method provided in the embodiments of this application. Of course, the computing device may also have wired or wireless network interfaces, keyboards, and input / output interfaces for input and output. The computing device may also include other components for implementing device functions, which will not be elaborated here.

[0150] See Figure 8 The diagram illustrates the structure of a computer device according to an embodiment of this application. This computer device may be... Figure 1 The computer device 01 shown is... Figure 8 In the above embodiment, the computer device 800 includes a processing device 801, which may be the processing device provided above. The processing device 801 includes, for example, the processing device 801. Figure 4 The instruction prediction unit 11, verification unit 12, and address control unit 13 are shown. Figure 8 In this process, the processing device 801 is coupled to the memory 802, and it should be understood that the computer device 800 also supports other memory configurations known in the art.

[0151] The memory 802 may include one or more computer-readable storage media, which may be non-transitory, and the computer-readable storage media stores at least one computer program, which is loaded and executed by the processing device 801 to enable the computer device 800 to implement any of the above-described instruction processing methods.

[0152] The memory 802 may further include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 802 is used to store at least one instruction, which is executed by the processing device 801 to cause the computer device 800 to implement the instruction processing method provided in the above method embodiments.

[0153] In one possible implementation, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, and the like.

[0154] Figure 8 A wireless controller 805 coupled to the processing device 801 is also shown. In some cases, the computer device 800 can be used for wireless communication. Figure 8 Also shown are a speaker 809 and a microphone 810 coupled to the processing device 801 via an encoder / decoder 811; and a wireless antenna 808 coupled to the wireless controller 805.

[0155] Display 806 is used to display a UI (User Interface). This UI may include graphics, text, icons, video, and any combination thereof. When display 806 is a touch screen, it also has the ability to collect touch signals on or above its surface. In this case, display 806 can also provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display 806, located on the front panel of the terminal; in other embodiments, there may be at least two displays 806, located on different surfaces of the terminal or in a folded design; in still other embodiments, display 806 may be a flexible display, located on a curved or folded surface of the terminal. Furthermore, display 806 may be configured as a non-rectangular, irregular shape, i.e., a non-rectangular screen. Display 806 may be made of materials such as LCD (Liquid Crystal Display) or OLED (Organic Light-Emitting Diode).

[0156] Microphone 810 is used to collect sound waves from the user and the environment, and input the sound waves to processing device 801 for processing. Multiple microphones 810 can be used for stereo sound acquisition or noise reduction, each positioned at a different location on the terminal. Microphone 810 can also be an array microphone or an omnidirectional microphone. Speaker 809 is used to convert electrical signals from processing device 801 into sound waves. Speaker 809 can be a traditional thin-film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement.

[0157] The processing device 801 and the memory 802 may be contained in a system-in-package or system-on-a-chip device.

[0158] Input device 807 and power supply 803 are coupled to system-on-chip device 812. Optionally, such as Figure 8 As shown, when one or more optional boxes are present, the display 806, input device 807, speaker 809, microphone 810, wireless antenna 808, and power supply 803 are external to the system-on-chip device 812. However, each of the display 806, input device 807, speaker 809, microphone 810, wireless antenna 808, and power supply 803 can be coupled to components of the system-on-chip device 812, such as interfaces or controllers.

[0159] Power supply 803 is used to power the various components in the terminal. Power supply 803 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 803 includes a rechargeable battery, the rechargeable battery can support wired or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0160] In one possible implementation, the processing device 801 and the memory 802 may be integrated into a set-top box, server, music player, video player, entertainment unit, navigation device, personal digital assistant (PDA), fixed location data unit, computer, laptop computer, tablet computer, communication device, mobile phone or other similar device.

[0161] The methods described in conjunction with the embodiments of this application can be implemented directly in software modules executed by the processing device. The software modules can reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, compact disc read-only memory (CDROM), or any other form of storage media known in the art. The storage media is coupled to the processing device, thereby enabling the processing device to read information from and write information to the storage media. Optionally, the storage media can be integrated with the processing device.

[0162] Those skilled in the art will understand that Figure 8 The structures shown do not constitute a limitation on computer devices. Computer devices may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0163] In an exemplary embodiment, a computer device is also provided, the computer device including a processor for implementing Figure 2 The instruction processing method shown.

[0164] In an exemplary embodiment, a chip system is also provided, the chip system including a processing module for implementing... Figure 2 The instruction processing method shown.

[0165] It should be noted that all information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application have been authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the prediction results involved in this application were obtained with full authorization.

[0166] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0167] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A processing module, characterized in that, The processing module includes: The instruction prediction unit is used to predict the instruction type of the reference instruction during the instruction fetching stage; if the prediction result indicates that the instruction type of the reference instruction is a RET instruction, the jump address located at the top of the stack during the instruction fetching stage is used as the first return address of the reference instruction, and the first return address is sent to the address control unit and the verification unit. The RET instruction is used to return when the called program ends the call. The address control unit is used to receive the first return address and queue up to fetch instructions according to the first return address; The verification unit is configured to receive the first return address, take the jump address located at the top of the stack in the pre-decoding stage of the reference instruction as the second return address, verify the first return address according to the second return address, and obtain a verification result. The verification result is used to control whether the address control unit continues to queue for instruction fetching according to the first return address.

2. The module according to claim 1, characterized in that, The instruction prediction unit is configured to acquire the identifier of at least one historical instruction, wherein the historical instruction is an executed RET instruction; if the identifier of the at least one historical instruction includes the identifier of the reference instruction, the unit determines that the instruction type of the reference instruction is the RET instruction; or, if the identifier of the at least one historical instruction does not include the identifier of the reference instruction, the unit determines that the instruction type of the reference instruction is not the RET instruction.

3. The module according to claim 2, characterized in that, The identifier of the reference instruction includes the hash result of the fetch address of the reference instruction, and the identifier of the historical instruction includes the hash result of the fetch address of the historical instruction.

4. The module according to any one of claims 1-3, characterized in that, The address control unit is configured to write the first return address into an address queue, so as to retrieve the instruction indicated by the first return address according to the queuing order of the first return address in the address queue.

5. The module according to claim 4, characterized in that, The processing module also includes an instruction fetch bus; The address control unit is used to send the first return address to the instruction fetch bus; The instruction fetch bus is used to receive the first return address, write the first return address into the address queue on the instruction fetch bus, and fetch the instruction indicated by the first return address according to the queuing order of the first return address in the address queue.

6. The module according to any one of claims 1-3, characterized in that, The verification unit is configured to determine that the verification result is that the first return address verification is successful when the second return address and the first return address are the same; or, if the second return address and the first return address are different, determine that the verification result is that the first return address verification is unsuccessful.

7. The module according to any one of claims 1-3, characterized in that, The verification unit is further configured to send the second return address to the address control unit if the verification result is that the first return address verification fails. The address control unit is further configured to receive the second return address, replace the first return address used for queuing for instruction fetching with the second return address, and continue queuing for instruction fetching according to the second return address.

8. The module according to any one of claims 1-3, characterized in that, The processing module also includes a pre-decoding unit; The instruction prediction unit is further configured to restrict the prediction of the first return address of the reference instruction when the prediction result indicates that the instruction type of the reference instruction is not the RET instruction; The pre-decoding unit is used to pre-decode the reference instruction, determine the instruction type of the reference instruction based on the pre-decoding result, obtain a first determination result, and send the first determination result to the address control unit. The address control unit is further configured to receive the first determination result, and when the first determination result indicates that the instruction type is the RET instruction, queue up for instruction fetching according to the third return address, which is predicted during the pre-decoding stage of the reference instruction.

9. The module according to any one of claims 1-3, characterized in that, The processing module also includes a prediction information unit; The instruction prediction unit is used to send the first return address to the prediction information unit; The prediction information unit is used to store the first return address and send the first return address to the verification unit during the pre-decoding stage of the reference instruction.

10. An instruction processing method, characterized in that, The method includes: During the instruction fetching phase of the reference instruction, the instruction type of the reference instruction is predicted; If the prediction result indicates that the instruction type of the reference instruction is a RET instruction, the jump address located at the top of the stack during the instruction fetch stage is used as the first return address of the reference instruction, and the instruction is fetched in a queue according to the first return address. The RET instruction is used to return when the called program ends the call. The jump address located at the top of the stack during the pre-decoding phase of the reference instruction is used as the second return address. The first return address is verified based on the second return address to obtain a verification result. The verification result is used to control whether to continue queuing for instruction fetching based on the first return address.

11. The method according to claim 10, characterized in that, The instruction type for predicting the reference instruction includes: Obtain the identifier of at least one historical instruction, wherein the historical instruction is an executed RET instruction; If the identifier of at least one historical instruction includes the identifier of the reference instruction, the instruction type of the reference instruction is determined to be the RET instruction; or, if the identifier of at least one historical instruction does not include the identifier of the reference instruction, the instruction type of the reference instruction is determined not to be the RET instruction.

12. The method according to claim 11, characterized in that The identifier of the reference instruction includes the hash result of the fetch address of the reference instruction, and the identifier of the historical instruction includes the hash result of the fetch address of the historical instruction.

13. The method according to any one of claims 10-12, characterized in that, The step of queuing for instruction fetching based on the first return address includes: Write the first return address into the address queue to retrieve the instruction indicated by the first return address according to the queuing order of the first return address in the address queue.

14. The method according to any one of claims 10-12, characterized in that, The step of verifying the first return address based on the second return address to obtain the verification result includes: If the second return address and the first return address are the same, the verification result is determined to be that the first return address has passed verification; Alternatively, if the second return address and the first return address are different, the verification result is determined to be that the verification of the first return address failed.

15. The method according to any one of claims 10-12, characterized in that, After verifying the first return address based on the second return address and obtaining the verification result, the method further includes: If the verification result is that the first return address fails to be verified, the first return address used for queuing for instruction fetching is replaced with the second return address, so that instruction fetching can continue to be queued according to the second return address.

16. The method according to any one of claims 10-12, characterized in that, After predicting the instruction type of the reference instruction, the method further includes: If the prediction result indicates that the instruction type of the reference instruction is not the RET instruction, the prediction of the first return address of the reference instruction is restricted. The reference instruction is pre-decoded. If the pre-decoding result indicates that the instruction type is the RET instruction, the instruction is fetched in a queue according to the third return address, which is predicted during the pre-decoding stage of the reference instruction.

17. A chip system, characterized in that, The chip system includes the processing module as described in any one of claims 1 to 9.

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