Data conversion method, device, system, electronic equipment and storage medium

Abstract

This invention relates to the field of data security technology and discloses a data transformation method, apparatus, system, electronic device, and storage medium, comprising: obtaining several batches of ciphertext polynomials corresponding to the original ciphertext of a homomorphic encryption algorithm; allocating computing resources to each batch of ciphertext polynomials according to the ciphertext modular decomposition length of each batch of ciphertext polynomials; the computing resources including multiple key transformation computing operators, with different key transformation computing operators having the same throughput; based on the allocated computing resources, performing parallel pipelined operation of different key transformation computing operators on the ciphertext polynomials to obtain the key transformation calculation result of the ciphertext polynomials; and determining the target key transformation result of the original ciphertext based on the key transformation calculation result of the ciphertext polynomials. The method provided by the above scheme solves the data dependency problem in the key transformation calculation process, realizes the parallel pipelined operation of different key transformation computing operators, reduces the key transformation time consumption, and thus improves the versatility of homomorphic encryption.

Description

Technical Field

[0001] This application relates to the field of data security technology, and in particular to a data transformation method, apparatus, system, electronic device and storage medium. Background Technology

[0002] Homomorphic encryption, as a crucial technique for protecting data privacy and security, allows direct computation on ciphertext, and the decrypted result is identical to the result obtained by directly performing the corresponding computation on the plaintext. Therefore, homomorphic encryption can decouple communication volume and number of interaction rounds from computational tasks, making it suitable for long-distance, two-way secure computation scenarios with limited communication.

[0003] In related technologies, homomorphic encryption algorithms are several orders of magnitude slower in computation for ciphertext than for plaintext, and this huge computational overhead has become a bottleneck restricting the widespread deployment of homomorphic encryption. In particular, key transformation is the most time-consuming module in implementing ciphertext multiplication, rotation, and conjugation operations in algebraic homomorphic encryption schemes. Therefore, there is an urgent need for a data transformation method that can reduce the time consumption of key transformation, which is of great significance for improving the versatility of homomorphic encryption. Summary of the Invention

[0004] This application provides a data transformation method, apparatus, system, electronic device, and storage medium to address the shortcomings of related technologies, such as increased key transformation time and reduced versatility of homomorphic encryption.

[0005] The first aspect of this application provides a data transformation method, including:

[0006] Obtain several batches of ciphertext polynomials corresponding to the original ciphertext of the homomorphic encryption algorithm;

[0007] Based on the ciphertext modular decomposition length of each batch of ciphertext polynomials, computing resources are allocated sequentially to each batch of ciphertext polynomials; wherein, the computing resources include multiple key transformation computing operators, and the throughput of different key transformation computing operators is consistent;

[0008] Based on the allocated computing resources, the ciphertext polynomial is subjected to parallel pipelined operation of different key transformation calculation operators to obtain the key transformation calculation result of the ciphertext polynomial.

[0009] Based on the key transformation calculation result of the ciphertext polynomial, the target key transformation result of the original ciphertext is determined.

[0010] In one optional implementation, the step of allocating computational resources to each batch of ciphertext polynomials sequentially based on the ciphertext modular decomposition length of each batch of ciphertext polynomials includes:

[0011] Based on the ciphertext modular decomposition length of each batch of ciphertext polynomials, determine the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations; wherein, the first group of modular multiplication units and the second group of modular multiplication units include multiple modular multiplication operators;

[0012] Obtain the butterfly unit type and the number of parallel butterfly units for the inverse number theory transformation operator;

[0013] The number of computation cycles of the inverse number theory transformation operator is determined based on the butterfly unit type and the number of parallel butterfly units of the inverse number theory transformation operator.

[0014] Computational resources are allocated to each batch of encrypted polynomials based on the number of computation cycles of the inverse number theory transformation operator, the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations.

[0015] In one optional implementation, the allocation of computational resources to each batch of ciphertext polynomials based on the number of computation cycles of the inverse number theory transformation operator, the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations, includes:

[0016] Based on the number of calculation cycles of the inverse number theory transformation operator and the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations, determine the modular multiplication quantity information for each calculation cycle of the second group of modular multiplication units;

[0017] Based on the modular multiplication count information of each computation cycle of the second group of modular multiplication units, determine the number of parallel number theory transformations of each batch of encrypted polynomials;

[0018] Based on the number of parallel number-theoretical transformations for each batch of ciphertext polynomials, a corresponding number of parallel number-theoretical transformation operators are assigned to each batch of ciphertext polynomials.

[0019] In one optional implementation, determining the number of modular multiplications per calculation cycle of the second group of modular multiplication units based on the number of calculation cycles of the inverse number theory transformation operator and the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations includes:

[0020] Based on the number of calculation cycles of the inverse number theory transformation operator and the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations, determine the multiple of the number of modular multiplications in each calculation cycle of the second group of modular multiplication units relative to the number of modular multiplications in each calculation cycle of the first group of modular multiplication units;

[0021] The modular multiplication quantity information for each calculation cycle of the second group of modular multiplication units includes the multiplier.

[0022] In one optional implementation, the multiple of the number of modular multiplications in each calculation cycle of the second group of modular multiplication units relative to the number of modular multiplications in each calculation cycle of the first group of modular multiplication units satisfies the following expression:

[0023]

[0024] in, Indicating the multiple, the first group of modular multiplication units performs the polynomial scalar modular multiplication calculation 1 time. This indicates the number of times the second group of modular multiplication units performs polynomial-scalar modular multiplication calculations. This indicates the number of expanding elements in the expanded modulus of the original ciphertext. This indicates the number of ciphertext elements in the ciphertext pattern of the original ciphertext. This indicates the length of the ciphertext modular decomposition of each batch of ciphertext polynomials. This represents the number of computational cycles for the inverse number theory transformation operator. This represents the key parameters of the homomorphic encryption algorithm. This represents the number of parallel butterfly units of the inverse number-theoretic transformation operator. The butterfly unit cardinality represents the butterfly unit type characterization of the inverse number theory transformation operator.

[0025] In one optional implementation, the parallel pipelined execution of different key transformation computation operators on the ciphertext polynomial based on allocated computing resources to obtain the key transformation computation result of the ciphertext polynomial includes:

[0026] Each ciphertext polynomial and its corresponding rotation factor are sequentially obtained from the off-chip storage module, and the obtained ciphertext polynomial and its corresponding rotation factor are cached in the on-chip storage module.

[0027] Based on the allocated computing resources, and according to the rotation factor, the ciphertext polynomial is subjected to parallel pipelined operation of different key transformation calculation operators to obtain the key transformation calculation result of the ciphertext polynomial.

[0028] In one optional implementation, the step of sequentially obtaining each ciphertext polynomial and its corresponding twitch factor from the off-chip storage module, and caching the obtained ciphertext polynomial and its corresponding twitch factor to the on-chip storage module, includes:

[0029] Obtain the frequency of the off-chip storage module and the data bit width of each memory channel;

[0030] The bandwidth of each memory channel is determined based on the frequency of the off-chip storage module and the data bit width of each memory channel;

[0031] The throughput of the inverse number theory transformation operator is determined based on the frequency of the computing module and the data bit width of each prime number in the ciphertext polynomial; wherein, the computing module includes the computing resources;

[0032] The number of memory channels for parallel transmission between the off-chip storage module and the on-chip storage module is determined based on the bandwidth of each memory channel, the throughput of the inverse number theory transform operator, the butterfly unit type of the inverse number theory transform operator, and the number of parallel butterfly units.

[0033] Based on the number of memory channels that are transmitted in parallel between the off-chip storage module and the on-chip storage module, each ciphertext polynomial and its corresponding rotation factor are sequentially obtained from the off-chip storage module, and the obtained ciphertext polynomial and its corresponding rotation factor are cached in the on-chip storage module.

[0034] In one optional implementation, determining the number of memory channels for parallel transmission between the off-chip storage module and the on-chip storage module based on the bandwidth of each memory channel, the throughput of the inverse number theory transform operator, the butterfly unit type of the inverse number theory transform operator, and the number of parallel butterfly units includes:

[0035] The number of first memory channels for parallel transmission of ciphertext polynomials between the off-chip storage module and the on-chip storage module is determined based on the bandwidth of each memory channel and the throughput of the inverse number theory transformation operator.

[0036] The number of second memory channels for parallel transmission of rotation factors between the off-chip storage module and the on-chip storage module is determined based on the bandwidth of each memory channel, the throughput of the inverse number theory transform operator, the butterfly unit type of the inverse number theory transform operator, and the number of parallel butterfly units.

[0037] In one optional implementation, determining the number of first memory channels for parallel transmission of ciphertext polynomials between the off-chip storage module and the on-chip storage module based on the bandwidth of each memory channel and the throughput of the inverse number theory transformation operator includes:

[0038] The number of the first memory channels is determined based on the following expression:

[0039]

[0040] in, This indicates the number of the first memory channels. This represents the bandwidth of each of the aforementioned memory channels. This indicates the frequency of the off-chip storage module. This indicates the data bit width of each memory channel. This represents the throughput of the inverse number theory transformation operator. This represents the data bit width of each prime number in the ciphertext polynomial. Indicates the frequency of the computing module. This represents the key parameters of the homomorphic encryption algorithm. This represents the number of parallel butterfly units of the inverse number-theoretic transformation operator. The butterfly unit cardinality represents the butterfly unit type characterization of the inverse number theory transformation operator.

[0041] In one optional implementation, determining the number of second memory channels for parallel transmission of rotation factors between the off-chip storage module and the on-chip storage module based on the bandwidth of each memory channel, the throughput of the inverse number theory transform operator, the butterfly unit type of the inverse number theory transform operator, and the number of parallel butterfly units includes:

[0042] The number of the second memory channels is determined based on the following expression:

[0043]

[0044] in, Indicates the number of the second memory channels. This represents the bandwidth of each of the aforementioned memory channels. This indicates the frequency of the off-chip storage module. This indicates the data bit width of each memory channel. This represents the throughput of the inverse number theory transformation operator. This represents the data bit width of each prime number in the ciphertext polynomial. Indicates the frequency of the computing module. This represents the key parameters of the homomorphic encryption algorithm. This represents the number of parallel butterfly units of the inverse number-theoretic transformation operator. The butterfly unit cardinality represents the butterfly unit type characterization of the inverse number-theoretic transformation operator. This indicates the number of rotation factors required for each of the butterfly units.

[0045] In one optional implementation, the step of sequentially obtaining each ciphertext polynomial and its corresponding twitch factor from the off-chip storage module based on the number of memory channels used for parallel transmission between the off-chip storage module and the on-chip storage module, and then caching the obtained ciphertext polynomial and its corresponding twitch factor in the on-chip storage module, includes:

[0046] Based on the number of memory channels that are transmitted in parallel between the off-chip storage module and the on-chip storage module, each ciphertext polynomial and its corresponding twitch factor are sequentially obtained from the off-chip storage module.

[0047] The first target cache of the ciphertext polynomial and the second target cache of the twitch factor are respectively located on the on-chip storage module;

[0048] According to the first data transmission mode corresponding to the first target cache, the obtained ciphertext polynomial is cached in the first target cache;

[0049] According to the second data transmission mode corresponding to the second target buffer, the obtained rotation factor is cached in the second target buffer;

[0050] Among them, the data transmission mode is divided into at least two types: transmission after buffering through a first-in-first-out queue and transmission without buffering through a first-in-first-out queue.

[0051] In one optional implementation, the parallel pipelined execution of different key transformation computation operators on the ciphertext polynomial based on the allocated computing resources and according to the rotation factor to obtain the key transformation computation result of the ciphertext polynomial includes:

[0052] The transformation key polynomial pair and intermediate calculation results are obtained from the off-chip storage module and cached in the on-chip storage module.

[0053] After performing inverse number theory transformation operations and modular multiplication operations on the ciphertext polynomial based on inverse number theory transformation operators and modular multiplication operators, the target polynomial is obtained.

[0054] The rotation factor is read alternately and continuously from two copies of memory on the on-chip storage module;

[0055] Based on the number theory transformation operator, the target polynomial is subjected to number theory transformation operation according to the rotation factor read alternately, and the result of the number theory transformation operation of the ciphertext polynomial is obtained.

[0056] The inner product operation is performed on the number theory transformation result of the ciphertext polynomial and the transformation key polynomial pair to obtain the inner product operation result;

[0057] The inner product operation result and the intermediate calculation result are summed to obtain the summed result;

[0058] When the ciphertext polynomial is the last batch of ciphertext polynomials, the accumulation result is used as the key transformation calculation result of the ciphertext polynomial;

[0059] If the ciphertext polynomial is not the last batch of ciphertext polynomials, the accumulated result is used as the new intermediate calculation result to update the intermediate calculation result stored in the off-chip storage module.

[0060] In one optional implementation, the step of obtaining the transform key polynomial pair and intermediate calculation results from the off-chip storage module, and caching the obtained transform key polynomial pair and intermediate calculation results to the on-chip storage module, includes:

[0061] Intermediate calculation results are continuously and alternately acquired on two memory channels of the off-chip storage module, and the alternately acquired intermediate calculation results are alternately stored on two memories of the on-chip storage module, so that the accumulation operation runs alternately on different memories without interruption.

[0062] In one optional implementation, the step of performing a number-theoretical transformation operation on the target polynomial based on the alternately read rotation factors, to obtain the number-theoretical transformation operation result of the ciphertext polynomial, includes:

[0063] Based on the number of parallel runs of the number theory transformation operator, the target polynomial is split and written into a corresponding number of memories;

[0064] Based on the number theory transformation operator, the number theory transformation operation is performed alternately on the target polynomial stored in the memory according to the alternately read rotation factor, until the number theory transformation operation of all target polynomials is completed, and the number theory transformation operation result of the ciphertext polynomial is obtained.

[0065] In one optional implementation, determining the target key transformation result of the original ciphertext based on the key transformation calculation result of the ciphertext polynomial includes:

[0066] The key transformation calculation result of the ciphertext polynomial is subjected to a modular reduction operation to obtain the target key transformation result of the original ciphertext.

[0067] A second aspect of this application provides a data conversion apparatus, comprising:

[0068] The acquisition module is used to acquire several batches of ciphertext polynomials corresponding to the original ciphertext of the homomorphic encryption algorithm.

[0069] The allocation module is used to allocate computing resources to each batch of ciphertext polynomials according to the length of the ciphertext modular decomposition of each batch of ciphertext polynomials; wherein, the computing resources include a variety of key transformation computing operators, and the throughput of different key transformation computing operators is consistent;

[0070] The computation module is used to perform parallel pipelined operation of different key transformation computation operators on the ciphertext polynomial based on the allocated computing resources, so as to obtain the key transformation computation result of the ciphertext polynomial.

[0071] The transformation module is used to determine the target key transformation result of the original ciphertext based on the key transformation calculation result of the ciphertext polynomial.

[0072] A third aspect of this application provides a data transformation system, comprising: an off-chip storage module, an on-chip storage module, a control module, and a computing module;

[0073] The off-chip storage module is used to store several batches of ciphertext polynomials and rotation factors corresponding to the original ciphertext of the homomorphic encryption algorithm.

[0074] The control module is used to store the encrypted polynomial and twitch factor stored in the off-chip storage module to the on-chip storage module for the calculation module to read and use.

[0075] The computing module includes various computing resources; wherein, the computing resources include various key transformation computing operators, and the throughput of different key transformation computing operators is consistent;

[0076] The control module is also used to allocate computing resources to each batch of ciphertext polynomials according to the length of the ciphertext modular decomposition of each batch of ciphertext polynomials.

[0077] The computing resources are used to perform parallel pipelined operation of different key transformation calculation operators on the ciphertext polynomial to obtain the key transformation calculation result of the ciphertext polynomial; based on the key transformation calculation result of the ciphertext polynomial, the target key transformation result of the original ciphertext is determined.

[0078] A fourth aspect of this application provides an electronic device, comprising: at least one processor and a memory;

[0079] The memory stores computer-executable instructions;

[0080] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the method described in the first aspect above and various possible designs of the first aspect.

[0081] The fifth aspect of this application provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the method described in the first aspect above and various possible designs of the first aspect.

[0082] The sixth aspect of this application provides a computer program product including computer instructions for causing a computer to perform the methods described in the first aspect above and various possible designs of the first aspect.

[0083] The technical solution of this application has the following advantages:

[0084] This application provides a data transformation method, apparatus, system, electronic device, and storage medium. The method includes: obtaining several batches of ciphertext polynomials corresponding to the original ciphertext of a homomorphic encryption algorithm; allocating computational resources to each batch of ciphertext polynomials according to the ciphertext modular decomposition length of each batch; wherein the computational resources include multiple key transformation computation operators, and the throughput of different key transformation computation operators is consistent; based on the allocated computational resources, performing parallel pipelined operation of different key transformation computation operators on the ciphertext polynomials to obtain the key transformation computation result of the ciphertext polynomials; and determining the target key transformation result of the original ciphertext based on the key transformation computation result of the ciphertext polynomials. The method provided above solves the data dependency problem in the key transformation computation process by allocating parallel-runnable computational resources to the ciphertext polynomials and ensuring that the throughput of different key transformation computation operators is consistent, thereby realizing the parallel pipelined operation of different key transformation computation operators, reducing the key transformation time consumption, and thus improving the versatility of homomorphic encryption. Attached Figure Description

[0085] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0086] Figure 1 A flowchart illustrating the data transformation method provided in this application embodiment;

[0087] Figure 2 A schematic diagram of the parallel pipelined operation of an exemplary key transformation computation operator provided in the embodiments of this application;

[0088] Figure 3 This is a schematic diagram of the structure of the data transformation system provided in the embodiments of this application;

[0089] Figure 4 A schematic diagram illustrating an exemplary data transmission process for inverse number theory transformation operations provided in this application embodiment;

[0090] Figure 5 A schematic diagram showing the storage order of intermediate calculation results in the memory channel for embodiments of this application;

[0091] Figure 6 This is a schematic diagram illustrating data transfer between internal storage units of the computing module provided in an embodiment of this application.

[0092] Figure 7 This is a schematic diagram of the structure of the data conversion device provided in the embodiments of this application;

[0093] Figure 8This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0094] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0095] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0096] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. In the following descriptions of embodiments, "a plurality of" means two or more, unless otherwise explicitly defined.

[0097] With the development of artificial intelligence and cloud computing, the strategic value of data is increasingly valued. Due to the intangible and reproducible nature of data, privacy breaches are rampant. Protecting data security and privacy while promoting data applications has become a crucial research objective. As a key technology for protecting data privacy, homomorphic encryption allows direct computation on ciphertext, and the decrypted result is identical to the result obtained by directly computation on plaintext. Therefore, homomorphic encryption can decouple communication volume and number of interaction rounds from computational tasks, making it suitable for long-distance, secure two-way computation scenarios with limited communication. However, computation on ciphertext is four to five orders of magnitude slower than computation on plaintext, and this significant computational overhead is a bottleneck restricting the widespread deployment of homomorphic encryption. In particular, key transformation is the most time-consuming module in implementing ciphertext multiplication, rotation, and conjugation operations in algebraic homomorphic encryption schemes. Accelerating the key transformation module is crucial for promoting the practical application of homomorphic encryption and protecting data privacy.

[0098] On the other hand, the ciphertext of an algebraic homomorphic encryption scheme based on the RLWE (Ring Learning With Errors) problem is a pair of large-coefficient polynomials over a ring of integers in the circumscribed field. Homomorphic computation involves large integer operations, resulting in high computational complexity. Using the remainder theorem, a large-coefficient polynomial can be represented as a linear combination of multiple small-coefficient polynomials; this representation is called the Residue Number System (RNS) representation. Under the RNS representation, each small-coefficient polynomial can participate in the computation independently, thus reducing the computational overhead of large integers and leveraging parallel computing to improve the speed of homomorphic computation. Under the RNS representation, the key transformation module includes computational units such as Inverse Number Theoretic Transform (INTT), modular upgrading, Number Theoretic Transform (NTT), modular descent, modular multiplication, and accumulation, leading to complex data dependencies. Furthermore, on computing platforms with limited storage resources, completing the key transformation requires frequent cross-platform data transfers. Therefore, fine-grained decomposition of the key transformation process to alleviate data dependencies, reduce cross-platform communication latency, and thereby improve the throughput of the key transformation module becomes a key challenge for accelerating homomorphic computation.

[0099] To address the aforementioned problems, this application provides a data transformation method, apparatus, system, electronic device, and storage medium. The method includes: obtaining several batches of ciphertext polynomials corresponding to the original ciphertext of a homomorphic encryption algorithm; allocating computational resources to each batch of ciphertext polynomials sequentially based on the ciphertext modular decomposition length of each batch; wherein the computational resources include multiple key transformation computation operators, with different key transformation computation operators having consistent throughput; performing parallel pipelined execution of different key transformation computation operators on the ciphertext polynomials based on the allocated computational resources to obtain the key transformation computation result of the ciphertext polynomials; and determining the target key transformation result of the original ciphertext based on the key transformation computation result of the ciphertext polynomials. The method provided above solves the data dependency problem in the key transformation computation process by allocating parallel-runnable computational resources to the ciphertext polynomials and ensuring consistent throughput of different key transformation computation operators, thereby achieving parallel pipelined execution of different key transformation computation operators, reducing key transformation time consumption, and improving the versatility of homomorphic encryption.

[0100] The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0101] This application provides a data transformation method for key transformation of homomorphically encrypted ciphertext. The execution subject of this application embodiment is an electronic device, such as a server, desktop computer, laptop computer, tablet computer, or other electronic devices capable of performing key transformation.

[0102] like Figure 1The diagram shown is a flowchart illustrating a data transformation method provided in an embodiment of this application. The method includes:

[0103] Step 101: Obtain several batches of ciphertext polynomials corresponding to the original ciphertext of the homomorphic encryption algorithm.

[0104] It should be noted that the original ciphertext is ciphertext represented by RNS. RNS is used to represent a large-coefficient polynomial of a homomorphic encryption algorithm as multiple small-coefficient polynomials. This application further decomposes the length according to the ciphertext modulus. The RNS representation (multiple small-coefficient polynomials) is processed in batches to obtain several batches of ciphertext polynomials, each batch of ciphertext polynomials including multiple small-coefficient polynomials.

[0105] The principle behind RNS is as follows: First, obtain the key parameters of the homomorphic encryption algorithm. , for powers of, for Secondary circular region for Integer ring, For model Remaining class ring. Ciphertext module is , extended modulus ,in , They are distinct prime numbers. Given the length of the ciphertext module decomposition, the corresponding ciphertext module... Prime numbers can be divided into Groups (batches), each group contains at most A prime number. That is, the original ciphertext is represented as... Batch ciphertext polynomials, the ciphertext modular decomposition length of each batch ciphertext polynomial is .

[0106] set up and Two private keys for homomorphic encryption, in Randomly and uniformly sampled And based on error distribution Sampling polynomial ,in .make:

[0107]

[0108] Then corresponding to and The transformation key is . Specifically:

[0109]

[0110] in, , , , , , , .

[0111] The ciphertext of homomorphic encryption is a polynomial pair ciphertext The representation is RNS-NTT, which is a polynomial. Decomposed into ,in and It is obtained by performing number-theoretic transformations on the polynomial in coefficient representation. The length is determined based on the ciphertext modular decomposition. For ciphertext polynomials Divide it. Specifically, let ,but The polynomials can be divided into Group:

[0112]

[0113] in, , .

[0114] Step 102: Allocate computing resources to each batch of ciphertext polynomials according to the length of the ciphertext modular decomposition of each batch of ciphertext polynomials.

[0115] The computing resources include various key transformation computing operators, and the throughput of different key transformation computing operators is consistent. Specifically, the computing resources include key transformation computing operators such as inverse number theory transformation operators, modular multiplication operators, and number theory transformation operators.

[0116] Specifically, based on the length of the ciphertext modular decomposition of each batch of ciphertext polynomials, a corresponding number of inverse number theory transformation operators, modular multiplication operators, and number theory transformation operators can be allocated to each batch of ciphertext polynomials in sequence, and the throughput of different key transformation computation operators is consistent, so that different key transformation computation operators can run in parallel pipeline.

[0117] Step 103: Based on the allocated computing resources, perform parallel pipelined operation of different key transformation calculation operators on the ciphertext polynomial to obtain the key transformation calculation result of the ciphertext polynomial.

[0118] It should be noted that in the key transformation calculation, in order to control noise growth, it is necessary to perform a modulus upscaling calculation on the ciphertext polynomial, that is, to change the modulus of the ciphertext polynomial from... Transform into ,in and All are large integers. In RNS representation, let... , ,in and If the prime numbers are distinct, then the maximum depth of homomorphic computation is Given the security level and the polynomial degree, The upper limit is thus determined. If prime numbers and If the bit width is determined, then The upper limit is thus determined. Generally, and Must meet ,at this time, If based on the decomposition length For ciphertext To decompose, that is, to let ,in , ,but satisfy That's it. At this point, the maximum depth of homomorphic computation... However, this approach increases the data dependency in the key transformation calculation process, making hardware implementation more difficult.

[0119] Specifically, to address the data dependency problem in the key transformation computation process, this application, based on allocated computing resources, performs parallel pipelined execution of different key transformation computation operators on the ciphertext polynomial, such as... Figure 2 The diagram illustrates the parallel pipelined operation of an exemplary key transformation computation operator provided in this application embodiment. After each data transmission, the ciphertext polynomial is obtained, and an inverse number theory transformation operation is performed based on the inverse number theory transformation operator. For each inverse number theory transformation result, a modular multiplication operation is performed based on the modular multiplication operator. After obtaining the final modular multiplication result, further number theory transformation calculations are performed based on parallel number theory transformation operators. For each number theory transformation result, the modular multiplication operator can be reused for the final inner product operation. Figure 2 As can be seen, data transmission and inverse number theory transformation calculations and modular multiplication calculations have achieved a certain degree of parallel operation, as have number theory transformation calculations and inner product operations. This reduces the data dependency in the key transformation calculation process, thereby reducing the time consumption of key transformation.

[0120] Step 104: Determine the target key transformation result of the original ciphertext based on the key transformation calculation result of the ciphertext polynomial.

[0121] Specifically, the aforementioned computing resources can be reused to perform a modular reduction operation on the key transformation calculation result of the ciphertext polynomial, thereby obtaining the target key transformation result of the original ciphertext.

[0122] Based on the above embodiments, as an implementable approach, computational resources are allocated sequentially to each batch of ciphertext polynomials according to the length of the ciphertext modular decomposition of each batch, including:

[0123] Step 1021: Based on the ciphertext modular decomposition length of each batch of ciphertext polynomials, determine the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations; the first group of modular multiplication units and the second group of modular multiplication units include multiple modular multiplication operators;

[0124] Step 1022: Obtain the butterfly unit type and the number of parallel butterfly units for the inverse number theory transformation operator;

[0125] Step 1023: Determine the number of computation cycles of the inverse number theory transformation operator based on the butterfly unit type and the number of parallel butterfly units of the inverse number theory transformation operator;

[0126] Step 1024: Based on the number of computation cycles of the inverse number theory transformation operator and the number of times the first group of modular multiplication units and the second group of modular multiplication units performed polynomial scalar modular multiplication calculations, computational resources are allocated to each batch of ciphertext polynomials in sequence.

[0127] It should be noted that in the first In the key transformation calculation of the ciphertext polynomial, the following steps must be performed sequentially. The following calculations are performed: Sub-inverse number theory transformation and Sub-module upgrade calculation. This module upgrade calculation includes... Modular multiplication unit, the first modular multiplication unit is executed The second group of modular multiplication units performs polynomial scalar modular multiplication calculations. Scalar modular multiplication of polynomials of degree n. Let the inverse number-theoretic transformation operator be derived from... If radix-m butterfly units are computed in parallel, then the number of computation cycles for the inverse number-theoretic transformation is: In the final round of the inverse number theory transform iterative calculation, the output is [output value] per clock cycle. Each coefficient.

[0128] Specifically, in one embodiment, the number of modular multiplications per calculation cycle of the second group of modular multiplication units can be determined based on the number of calculation cycles of the inverse number theory transformation operator and the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations; the number of parallel number theory transformations of each batch of ciphertext polynomials can be determined based on the number of calculation cycles of the second group of modular multiplication units; and the corresponding number of parallel number theory transformation operators can be allocated to each batch of ciphertext polynomials in sequence based on the number of parallel number theory transformations of each batch of ciphertext polynomials.

[0129] In practical applications, if on-chip hardware resources are sufficient, several parallel inverse number theory transformation operators can be allocated to each batch of ciphertext polynomials to improve computational efficiency. Correspondingly, with multiple inverse number theory transformation operators running in parallel, the number of parallel modular multiplication units also increases adaptively.

[0130] Specifically, in order to achieve pipelined computation across different computing units and maintain consistent throughput across different operators, the module upgrade module... The modular multiplication unit calculates each clock cycle. Modular multiplication of the coefficients. The first coefficient in the modular multiplication module. The modular multiplication unit calculates each clock cycle. Modular multiplication of coefficients, This refers to the modular multiplication quantity information mentioned above.

[0131] Specifically, in one embodiment, the number of modular multiplications per calculation cycle of the second group of modular multiplication units relative to the number of modular multiplications per calculation cycle of the first group of modular multiplication units can be determined based on the number of calculation cycles of the inverse number theory transformation operator and the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations.

[0132] The modular multiplication quantity information for each calculation cycle of the second group of modular multiplication units includes the multiplier. The multiple of the number of modular multiplications per calculation cycle in the second group of modular multiplication units relative to the number of modular multiplications per calculation cycle in the first group of modular multiplication units satisfies the following expression:

[0133]

[0134] in, Indicating a multiple, the first group of modular multiplication units performs polynomial-scalar modular multiplication calculations 1 time. This indicates the number of times the second group of modular multiplication units performs polynomial-scalar modular multiplication calculations. This indicates the number of expanded elements in the expanded modulus of the original ciphertext. This represents the number of ciphertext elements in the ciphertext pattern of the original ciphertext. This indicates the length of the ciphertext modular decomposition of each batch of ciphertext polynomials. This represents the number of computational cycles for the inverse number theory transformation operator. This represents the key parameters of a homomorphic encryption algorithm. This represents the number of parallel butterfly units in the inverse number theory transformation operator. The butterfly unit cardinality represents the butterfly unit type characterization of the inverse number theory transformation operator.

[0135] Further, After the inverse number theory transformation and modular amplification are completed, the following steps need to be performed: The number-theoretic transformation is performed, and the result of the transformation is paired with the transformation key polynomial to perform a dot product operation (inner product operation). To reduce computational resource consumption, the dot product operation reuses the modular multiplication operator from the modular amplification module. Therefore, it must be executed in parallel. The number of number-theoretic transformations, i.e., the number of parallel number-theoretic transformations of each batch of ciphertext polynomials, is [number missing]. The number theory transformation module outputs each clock cycle. Each coefficient is calculated by the modular multiplication operator every clock cycle. Modular multiplication of coefficients.

[0136] Based on the above embodiments, as an implementable approach, the ciphertext polynomial is subjected to parallel pipelined execution of different key transformation computation operators based on allocated computing resources to obtain the key transformation computation result of the ciphertext polynomial, including:

[0137] Step 1031: Sequentially obtain each ciphertext polynomial and its corresponding rotation factor from the off-chip storage module, and cache the obtained ciphertext polynomial and its corresponding rotation factor in the on-chip storage module.

[0138] Step 1032: Based on the allocated computing resources, and according to the rotation factor, perform parallel pipelined operation of different key transformation calculation operators on the ciphertext polynomial to obtain the key transformation calculation result of the ciphertext polynomial.

[0139] Among them, the rotation factor is required in inverse number theory transformation operations and number theory transformation operations.

[0140] Specifically, in one embodiment, the frequency of the off-chip storage module and the data bit width of each memory channel can be obtained; the bandwidth of each memory channel can be determined based on the frequency of the off-chip storage module and the data bit width of each memory channel; the throughput of the inverse number theory transformation operator can be determined based on the frequency of the computation module and the data bit width of each prime number in the ciphertext polynomial; wherein, the computation module includes computational resources; the number of memory channels for parallel transmission between the off-chip storage module and the on-chip storage module can be determined based on the bandwidth of each memory channel, the throughput of the inverse number theory transformation operator, the butterfly unit type of the inverse number theory transformation operator, and the number of parallel butterfly units; based on the number of memory channels for parallel transmission between the off-chip storage module and the on-chip storage module, each ciphertext polynomial and its corresponding twiddle factor can be sequentially obtained from the off-chip storage module, and the obtained ciphertext polynomial and its corresponding twiddle factor can be cached in the on-chip storage module.

[0141] Specifically, during the key transformation calculation, each ciphertext polynomial and its rotation factor are sequentially transferred from the off-chip storage module to the on-chip storage module to participate in the inverse number theory transformation operation. Let the frequency of the off-chip storage module be... The off-chip storage module includes multiple memory channels, each with a data bit width of [missing information]. Then the bandwidth of the memory channel is The frequency of the design calculation module is... RNS represents the data width of each prime number as 1. The throughput of the inverse number theory transformation operator is In order to achieve Figure 2 The pipelined computation shown requires allocating the number of memory channels based on communication bandwidth and computing module throughput. This means determining the number of memory channels for parallel transmission between off-chip and on-chip storage modules, ensuring that data transmission time is comparable to the inverse number theory transformation computation time. Here, INTT represents the inverse number theory transformation operation, and NTT represents the number theory transformation operation.

[0142] Specifically, in one embodiment, the number of first memory channels for parallel transmission of ciphertext polynomials between the off-chip storage module and the on-chip storage module can be determined based on the bandwidth of each memory channel and the throughput of the inverse number theory transform operator; the number of second memory channels for parallel transmission of twitch factors between the off-chip storage module and the on-chip storage module can be determined based on the bandwidth of each memory channel, the throughput of the inverse number theory transform operator, the butterfly unit type of the inverse number theory transform operator, and the number of parallel butterfly units.

[0143] Specifically, since this application embodiment needs to obtain two types of data, the ciphertext polynomial and the rotation factor, from the off-chip storage module, the number of first memory channels for parallel transmission of the ciphertext polynomial between the off-chip storage module and the on-chip storage module and the number of second memory channels for parallel transmission of the rotation factor between the off-chip storage module and the on-chip storage module can be determined respectively. Then, according to the number of first memory channels, the ciphertext polynomial is transmitted to the on-chip storage module in parallel, and according to the number of second memory channels, the rotation factor is transmitted to the on-chip storage module in parallel, so as to ensure the normal operation of the inverse number theory transformation operator.

[0144] Specifically, in one embodiment, the number of first memory channels can be determined based on the following expression:

[0145]

[0146] in, Indicates the number of the first memory channels. This represents the bandwidth of each memory channel. Indicates the frequency of the off-chip storage module. This indicates the data bit width of each memory channel. This represents the throughput of the inverse number theory transformation operator. This represents the data bit width of each prime number in the ciphertext polynomial. Indicates the frequency of the computing module. This represents the key parameters of a homomorphic encryption algorithm. This represents the number of parallel butterfly units in the inverse number theory transformation operator. The butterfly unit cardinality represents the butterfly unit type characterization of the inverse number theory transformation operator.

[0147] Accordingly, in one embodiment, the number of second memory channels can be determined based on the following expression:

[0148]

[0149] in, Indicates the number of second memory channels. This represents the bandwidth of each memory channel. Indicates the frequency of the off-chip storage module. This indicates the data bit width of each memory channel. This represents the throughput of the inverse number theory transformation operator. This represents the data bit width of each prime number in the ciphertext polynomial. Indicates the frequency of the computing module. This represents the key parameters of a homomorphic encryption algorithm. This represents the number of parallel butterfly units in the inverse number theory transformation operator. The butterfly unit cardinality represents the butterfly unit type characterization of the inverse number-theoretic transformation operator. This indicates the number of rotation factors required for each butterfly unit.

[0150] Further, in one embodiment, each ciphertext polynomial and its corresponding twitch factor can be sequentially obtained from the off-chip storage module based on the number of memory channels used for parallel transmission between the off-chip storage module and the on-chip storage module; a first target cache for the ciphertext polynomial and a second target cache for the twitch factor can be located on the on-chip storage module; the obtained ciphertext polynomial is cached in the first target cache according to the first data transmission mode corresponding to the first target cache; and the obtained twitch factor is cached in the second target cache according to the second data transmission mode corresponding to the second target cache.

[0151] The data transmission mode is divided into at least two types: transmission after buffering via a first-in-first-out (FIFO) queue and transmission without buffering via a FIFO queue. The determination of the data transmission mode also includes the determination of the memory port frequency.

[0152] Specifically, such as Figure 3 The diagram shown is a structural schematic of the data transformation system provided in this embodiment. Since the encrypted polynomial must undergo an inverse number theory transformation locally after being input into the BRAM① in the on-chip storage module, the frequencies of both ports of BRAM① are... Therefore, a FIFO (First-In-First-Out) queue must be used to buffer the data. The rotation factor is passed to the URAM in the on-chip storage module, and the frequency of the URAM port is... Therefore, a FIFO buffer must be used to cache the data. Both BRAM and URAM are storage resources within the FPGA.

[0153] Further, in one embodiment, the transformation key polynomial pair and intermediate calculation results can be obtained from the off-chip storage module, and the obtained transformation key polynomial pair and intermediate calculation results can be cached in the on-chip storage module; after performing inverse number theory transformation and modular multiplication operations on the ciphertext polynomial based on inverse number theory transformation operators and modular multiplication operators, the target polynomial is obtained; the twiddle factor is continuously and alternately read from two copies of memory on the on-chip storage module; based on the number theory transformation operator, according to the alternately read twiddle factor, the target polynomial is subjected to number theory transformation operation, and the number theory transformation operation result of the ciphertext polynomial is obtained; the number theory transformation operation result of the ciphertext polynomial and the transformation key polynomial pair are subjected to inner product operation, and the inner product operation result is obtained; the inner product operation result and the intermediate calculation result are accumulated to obtain the accumulated result; if the ciphertext polynomial is the last batch of ciphertext polynomials, the accumulated result is used as the key transformation calculation result of the ciphertext polynomial; if the ciphertext polynomial is not the last batch of ciphertext polynomials, the accumulated result is used as the new intermediate calculation result to update the intermediate calculation result stored in the off-chip storage module.

[0154] For example, such as Figure 4 The diagram illustrates an exemplary data transmission process for inverse number theory transformation operations provided in this application embodiment. The external storage module is an off-chip storage module. While performing the first round of iterative calculation of the inverse number theory transformation on the ciphertext polynomial, it also performs an inner product operation between the ciphertext polynomial and the corresponding transformation key polynomial pair. The result of the inner product operation is accumulated with the intermediate calculation result. Therefore, the off-chip storage module transmits the transformation key polynomial pair and the intermediate calculation result polynomial pair simultaneously with the ciphertext polynomial to the on-chip storage module. The transmission of both the transformation key polynomial pair and the intermediate calculation result polynomial pair occupies [data / time / percentage]. One memory channel. After the transformation key is passed to BRAM② in the on-chip storage module, BRAM② only needs to perform read data operations, so the write and read port frequencies of BRAM② can be set to... and No FIFO buffer is needed. After the intermediate calculation result polynomial is passed to the BRAM③ in the on-chip storage module, BRAM③ must perform read and write operations. Therefore, the frequency of both ports of BRAM③ is... Therefore, intermediate results must be buffered using a FIFO buffer before being passed to BRAM③. After the accumulation calculation is completed, the intermediate results must be transferred from the on-chip storage module to the off-chip storage module, hence the need for a FIFO buffer. During data transfer, when the frequency of the memory channel of the off-chip storage module differs from the frequency of the read port of the memory unit of the on-chip storage module, a FIFO buffer is used.

[0155] in, After the inverse number theory transformation and modular amplification are completed, The number of polynomials performing number theory transformations is [number], and the number of number theory transformations performed in parallel is [number]. The corresponding rotation factor occupies The memory channels of the off-chip storage module. Since number theory transformations are performed continuously, two copies of URAM are allocated to store the rotation factor. The rotation factor is continuously transferred from the off-chip storage module to the on-chip storage module, and the control module controls the rotation factor to be alternately written into the two copies of URAM.

[0156] Accordingly, in one embodiment, intermediate calculation results are continuously and alternately acquired on two memory channels of the off-chip storage module, and the alternately acquired intermediate calculation results are alternately stored on two memories of the on-chip storage module, so that the accumulation operation can be continuously and alternately run on different memories.

[0157] Specifically, the output of the final iteration of the number-theoretic transformation is compared with the transformation key polynomial execution. The inner product operation is performed, and the result of the inner product operation is added to the intermediate calculation results. Therefore, the transmission of the transformation key polynomial occupies a certain amount of space. Each memory channel, such as Figure 4 As shown, The transformation key memory channel is contained in this In one memory channel. Because the intermediate result memory channel performs simultaneous read and write transfers and different batches of calculations need to access the same off-chip storage module address space, the transfer of the intermediate result polynomial occupies... Each memory channel, such as Figure 4 As shown, The intermediate result memory channel is contained in this In a memory channel. Specifically, this Each memory channel is divided into two parts, corresponding to the same group. The intermediate result polynomials for the prime numbers are stored in two separate memory channels. Two BRAMs are allocated to store the intermediate results, which are continuously transferred from the off-chip storage module to the on-chip storage module. The control module controls the alternating reading of data from the two memory channels and the alternating writing of the intermediate calculation results into the two BRAMs (two memories).

[0158] For example, such as Figure 5 The diagram shown illustrates the storage order of intermediate calculation results in the memory channel according to an embodiment of this application. , , , , For example, the off-chip storage module first stores the first copy of the memory channel... and The corresponding intermediate result polynomial is written into the first BRAM of the on-chip storage module, and then into the second memory channel. and The corresponding intermediate result polynomial is written into the second BRAM of the on-chip storage module. After the intermediate results are accumulated and calculated, they are written back to the original address of the off-chip storage module.

[0159] Furthermore, in one embodiment, the target polynomial can be split and written into a corresponding number of memories based on the number of parallel runs of the number-theoretical transformation operators; based on the number-theoretical transformation operators, the target polynomials stored in the memories are alternately subjected to number-theoretical transformation operations according to the alternately read rotation factors, until the number-theoretical transformation operations of all target polynomials are completed, and the number-theoretical transformation operation results of the ciphertext polynomial are obtained.

[0160] Specifically, on a hardware acceleration platform, a polynomial is stored in parallel across multiple BRAMs. Several BRAMs storing a polynomial are called a BRAM group, and an equal number of URAMs are called a URAM group. That is, a URAM group contains the same number of URAMs as a BRAM group contains the same number of BRAMs. Since the capacity of URAMs is greater than that of BRAMs, a URAM group can store multiple polynomials. The calculation result of the inverse number-theoretic transform is written into one of the BRAM groups in the computation module for subsequent modular transform calculations.

[0161] For example, Figure 6 The diagram shown is a schematic of data transfer between internal storage units of the computing module provided in an embodiment of this application. , , , Taking a URAM group storing 8 polynomials as an example, in order to perform number theory transformations continuously, the result of the modular transformation calculation (the target polynomial) is written to... Among one BRAM group and several URAM groups. Each BRAM component is divided into two parts, each containing One BRAM group is used for sequential parallel execution. Number theory transformation operations are performed. After the number theory transformation calculation corresponding to the first BRAM group is completed, the number theory transformation is immediately performed on the polynomial in the second BRAM group, while the control module controls the data in the URAM group to be transferred to the first BRAM group. After the number theory transformation calculation corresponding to the second BRAM group is completed, the number theory transformation is immediately performed on the polynomial in the first BRAM group, while the data in the URAM group is transferred to the second BRAM group. The above process is repeated alternately until all number theory transformation calculations are completed.

[0162] This application proposes a multi-channel cross-platform data transmission method. Data is distributed and stored across multiple memory channels according to the data volume required by the computing unit and the communication bandwidth. Data transmission is performed in parallel across multiple channels, and different cross-platform data transmission methods are selected based on the data processing method to reduce communication latency. Furthermore, this application allocates different on-chip memory to different computing units according to the computing type and improves memory utilization by transferring data between on-chip memory channels.

[0163] Specifically, The execution process of batch key transformation operations is the same, with each batch occupying the same on-chip storage and computing resources. The control module controls the read and write addresses of the ciphertext polynomial, transformation key, twiddle factor, and intermediate calculation results in the off-chip storage module during different batch operations. After obtaining the key transformation calculation result of the last batch of ciphertext polynomials, a modular reduction operation is performed on the key transformation calculation result of the ciphertext polynomials. The modular reduction operation reuses the on-chip storage and computing resources from the batch operations, sequentially performing inverse number theory transformation, modular transformation, number theory transformation, modular subtraction, and modular multiplication operations. The control module controls the read and write addresses of the intermediate calculation results and twiddle factor in the off-chip storage module to obtain the target key transformation result of the original ciphertext.

[0164] The data transformation method provided in this application involves obtaining several batches of ciphertext polynomials corresponding to the original ciphertext of a homomorphic encryption algorithm; allocating computational resources to each batch of ciphertext polynomials according to their ciphertext modular decomposition length; wherein the computational resources include multiple key transformation computation operators with consistent throughput across different key transformation computation operators; based on the allocated computational resources, performing parallel pipelined execution of different key transformation computation operators on the ciphertext polynomials to obtain the key transformation computation result of the ciphertext polynomials; and determining the target key transformation result of the original ciphertext based on the key transformation computation result of the ciphertext polynomials. The method provided above solves the data dependency problem in the key transformation computation process by allocating parallel-runnable computational resources to the ciphertext polynomials and ensuring consistent throughput across different key transformation computation operators, thereby achieving parallel pipelined execution of different key transformation computation operators, reducing key transformation time consumption, and improving the versatility of homomorphic encryption. Furthermore, key transformation computations in different batches can reuse on-chip storage and computational resources, alleviating the problem of limited on-chip resources. Data is distributed across multiple memory channels according to the ratio between the amount of data required by the computing unit and the communication bandwidth. Parallel data transmission across multiple channels reduces communication latency. Furthermore, fine-grained matching of cross-platform data transfer methods reduces on-chip resource consumption. Different types of on-chip memory units are fully utilized, and data can be transferred on demand according to the characteristics of the computing unit, improving on-chip memory utilization.

[0165] This application provides a data transformation apparatus for performing the data transformation method provided in the above embodiments.

[0166] like Figure 7 The diagram shown is a structural schematic of a data transformation device provided in an embodiment of this application. The data transformation device 70 includes: an acquisition module 701, an allocation module 702, a calculation module 703, and a transformation module 704.

[0167] The algorithm comprises the following modules: an acquisition module for acquiring several batches of ciphertext polynomials corresponding to the original ciphertext of the homomorphic encryption algorithm; an allocation module for allocating computational resources to each batch of ciphertext polynomials according to the length of the ciphertext modular decomposition; wherein the computational resources include various key transformation computation operators with consistent throughput across different key transformation computation operators; a computation module for performing parallel pipelined execution of different key transformation computation operators on the ciphertext polynomials based on the allocated computational resources to obtain the key transformation computation results of the ciphertext polynomials; and a transformation module for determining the target key transformation result of the original ciphertext based on the key transformation computation results of the ciphertext polynomials.

[0168] Regarding the data transformation device in this embodiment, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0169] The data transformation device provided in this application embodiment is used to execute the data transformation method provided in the above embodiment. Its implementation method and principle are the same, and will not be described again.

[0170] This application provides a data transformation system for performing the data transformation method provided in the above embodiments.

[0171] like Figure 3 As shown, the system includes an off-chip storage module, an on-chip storage module, a control module, and a computing module.

[0172] The system comprises the following components: an off-chip storage module for storing several batches of ciphertext polynomials and rotation factors corresponding to the original ciphertext of the homomorphic encryption algorithm; a control module for storing the ciphertext polynomials and rotation factors stored in the off-chip storage module to the on-chip storage module for the computation module to read and use; a computation module including various computational resources, including multiple key transformation operators with consistent throughput; a control module for allocating computational resources to each batch of ciphertext polynomials according to the length of the ciphertext modular decomposition; computational resources for parallel pipelined execution of different key transformation operators on the ciphertext polynomials to obtain the key transformation calculation results of the ciphertext polynomials; and a determination of the target key transformation result of the original ciphertext based on the key transformation calculation results of the ciphertext polynomials.

[0173] Specifically, the control module determines the on-chip and off-chip data transmission channels, transmission modes, number of burst transmissions, and read / write addresses. It also determines the order in which pre-calculated parameters are arranged in different batches of computation. The off-chip storage module stores the ciphertext polynomial, transformation key, intermediate calculation results, and twiddle factors, with different data stored in different memory channels. The on-chip storage module includes BRAM and URAM, serving as a bridge between the off-chip storage module and the computation module. The computation module includes computational units for inverse number theory transformation, modular transformation, number theory transformation, modular multiplication, and modular addition. Each computational unit achieves parallel computation by instantiating multiple operators. Notably, the computation module also internally includes BRAM and URAM for caching intermediate results of modular transformation calculations and for performing on-site number theory transformation calculations. Unlike the BRAM and URAM in the on-chip storage module, the BRAM and URAM in the computation module do not communicate with the off-chip storage module.

[0174] Regarding the data transformation system in this embodiment, the specific methods by which each module performs its operations have been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0175] The data transformation system provided in this application embodiment is used to execute the data transformation method provided in the above embodiment. Its implementation method and principle are the same, and will not be described again.

[0176] This application provides an electronic device for performing the data transformation method provided in the above embodiments.

[0177] like Figure 8 The diagram shown is a structural schematic of an electronic device provided in an embodiment of this application. The electronic device 80 includes at least one processor 81 and a memory 82.

[0178] The memory stores computer-executable instructions; at least one processor executes the computer-executable instructions stored in the memory, causing the at least one processor to perform the data transformation method provided in the above embodiments.

[0179] The electronic device provided in this application embodiment is used to execute the data transformation method provided in the above embodiment. Its implementation method and principle are the same, and will not be described again.

[0180] This application provides a computer-readable storage medium storing computer-executable instructions. When a processor executes the computer-executable instructions, it implements the data transformation method provided in any of the above embodiments.

[0181] The storage medium containing computer-executable instructions provided in this application embodiment can be used to store computer-executable instructions for the data transformation method provided in the foregoing embodiments. Its implementation method and principle are the same, and will not be described again.

[0182] This application provides a computer program product, including computer instructions, which are used to cause a computer to execute the data transformation method provided in the foregoing embodiments.

[0183] The computer program product provided in this application embodiment can be used to execute the computer instructions of the data transformation method provided in the foregoing embodiment. Its implementation method and principle are the same, and will not be described again.

[0184] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0185] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0186] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.

[0187] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0188] A portion of this application can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the present invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0189] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional modules is merely an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0190] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data transformation method, characterized in that: include: Obtain several batches of ciphertext polynomials corresponding to the original ciphertext of the homomorphic encryption algorithm; Allocating computing resources to each batch of ciphertext polynomials in turn according to the ciphertext modulus decomposition length of each batch of ciphertext polynomials; wherein the computing resources include multiple key transformation computing operators, and the throughput of different key transformation computing operators is consistent; Based on the allocated computing resources, performing parallel pipeline operation of different key transformation calculation operators on the ciphertext polynomial to obtain a key transformation calculation result of the ciphertext polynomial; Determining a target key transformation result of the original ciphertext according to a key transformation calculation result of the ciphertext polynomial; The allocating computing resources to each batch of ciphertext polynomials in turn according to the ciphertext modulus decomposition length of each batch of ciphertext polynomials includes: Determining the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations according to the length of the ciphertext modular decomposition of each batch of ciphertext polynomials; wherein the first group of modular multiplication units and the second group of modular multiplication units include a plurality of modular multiplication operators; Get the butterfly unit type and the number of butterfly units in parallel of the inverse number theory transform operator; Determining the number of calculation cycles of the inverse number theoretic transformation operator according to the butterfly unit type and the number of parallel butterfly units of the inverse number theoretic transformation operator; Allocating computing resources for each batch of ciphertext polynomials in turn according to the number of computing cycles of the inverse number theory transformation operator and the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations; The step of performing parallel pipeline operation of different key transformation calculation operators on the ciphertext polynomial based on the allocated computing resources to obtain a key transformation calculation result of the ciphertext polynomial includes: Obtain each ciphertext polynomial and the corresponding rotation factor from the off-chip storage module in turn, and cache the obtained ciphertext polynomial and the corresponding rotation factor to the on-chip storage module; Based on the allocated computing resources and according to the rotation factors, performing parallel pipeline operation of different key transformation calculation operators on the ciphertext polynomial to obtain a key transformation calculation result of the ciphertext polynomial; The determining, according to the key transformation calculation result of the ciphertext polynomial, a target key transformation result of the original ciphertext includes: A modular reduction operation is performed on the key transformation calculation result of the ciphertext polynomial to obtain a target key transformation result of the original ciphertext.

2. The method according to claim 1, characterized in that The method sequentially allocating computing resources to each batch of ciphertext polynomials according to the number of computing cycles of the inverse number theory transformation operator and the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations includes: Determine the number of modular multiplications of each calculation cycle of the second group of modular multiplication units according to the number of calculation cycles of the inverse number theory transformation operator and the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations; Determining the number of parallel number-theoretic transformations of each batch of ciphertext polynomials according to the number of modular multiplications of each calculation cycle of the second group of modular multiplication units; According to the number of parallel number-theoretic transformations of each batch of ciphertext polynomials, a corresponding number of parallel number-theoretic transformation operators are allocated to each batch of ciphertext polynomials in turn.

3. The method according to claim 1, characterized in that: The method of determining the number of modular multiplications of each calculation cycle of the second group of modular multiplication units according to the number of calculation cycles of the inverse number theory transformation operator and the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations comprises: Determine, according to the number of calculation cycles of the inverse number theory transform operator and the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations, a multiple of the number of modular multiplications per calculation cycle of the second group of modular multiplication units relative to the number of modular multiplications per calculation cycle of the first group of modular multiplication units; The modular multiplication quantity information of each calculation cycle of the second group of modular multiplication units includes the multiple.

4. The method according to claim 2, characterized in that: The multiple of the number of modular multiplications per computing cycle of the second group of modular multiplication units relative to the number of modular multiplications per computing cycle of the first group of modular multiplication units satisfies the following expression: in, represents the multiple, the number of times the first group of modular multiplication units performs polynomial scalar modular multiplication calculations is 1, Indicates the number of times the second group of modular multiplication units performs polynomial scalar modular multiplication calculations, represents the number of extended elements in the extended modulus of the original ciphertext, represents the number of ciphertext primes in the ciphertext modulus of the original ciphertext, represents the length of the ciphertext modular decomposition of each batch of ciphertext polynomials, represents the number of computational cycles of the inverse number-theoretic transformation operator, represents the key parameter of the homomorphic encryption algorithm, represents the number of parallel butterfly units of the inverse number theoretic transformation operator, A butterfly unit cardinality representing a butterfly unit type representation of the inverse number theoretic transform operator.

5. The method according to claim 1, characterized in that The method sequentially obtains each ciphertext polynomial and the corresponding rotation factor from the off-chip storage module, and caches the obtained ciphertext polynomial and the corresponding rotation factor to the on-chip storage module, including: Obtaining the frequency of the off-chip storage module and the data bit width of each memory channel; Determining the bandwidth of each memory channel according to the frequency of the off-chip storage module and the data bit width of each memory channel; Determining the throughput of the inverse number theory transformation operator according to the frequency of the computing module and the data bit width of each prime number in the ciphertext polynomial; wherein the computing module includes the computing resource; Determine the number of memory channels for parallel transmission between the off-chip storage module and the on-chip storage module according to the bandwidth of each of the memory channels, the throughput of the inverse number theoretic transformation operator, the butterfly unit type of the inverse number theoretic transformation operator, and the number of parallel butterfly units; According to the number of memory channels transmitted in parallel between the off-chip storage module and the on-chip storage module, each ciphertext polynomial and the corresponding rotation factor are obtained from the off-chip storage module in turn, and the obtained ciphertext polynomial and the corresponding rotation factor are cached in the on-chip storage module.

6. The method according to claim 5, characterized in that Determining the number of memory channels for parallel transmission between the off-chip storage module and the on-chip storage module according to the bandwidth of each memory channel, the throughput of the inverse number theory transform operator, the butterfly unit type of the inverse number theory transform operator, and the number of parallel butterfly units includes: Determine the number of first memory channels for parallel transmission of ciphertext polynomials between the off-chip storage module and the on-chip storage module according to the bandwidth of each of the memory channels and the throughput of the inverse number theory transformation operator; The number of second memory channels for parallel transmission of rotation factors between the off-chip storage module and the on-chip storage module is determined according to the bandwidth of each memory channel, the throughput of the inverse numerology transform operator, the butterfly unit type of the inverse numerology transform operator, and the number of parallel butterfly units.

7. The method according to claim 6, characterized in that The method of determining the number of first memory channels for parallel transmission of ciphertext polynomials between the off-chip storage module and the on-chip storage module according to the bandwidth of each memory channel and the throughput of the inverse number theory transformation operator comprises: The number of the first memory channels is determined based on the following expression: in, Indicates the number of the first memory channel, represents the bandwidth of each of the memory channels, represents the frequency of the off-chip storage module, Indicates the data bit width of each memory channel, represents the throughput of the inverse number-theoretic transformation operator, represents the data bit width of each prime number in the ciphertext polynomial, represents the frequency of the computation module, represents the key parameter of the homomorphic encryption algorithm, represents the number of parallel butterfly units of the inverse number theoretic transformation operator, A butterfly unit cardinality representing a butterfly unit type representation of the inverse number theoretic transform operator.

8. The method according to claim 6, characterized in that The method of determining the number of second memory channels for parallel transmission of rotation factors between the off-chip storage module and the on-chip storage module according to the bandwidth of each memory channel, the throughput of the inverse number theory transform operator, the butterfly unit type of the inverse number theory transform operator, and the number of parallel butterfly units includes: The number of the second memory channels is determined based on the following expression: in, Indicates the number of the second memory channel, represents the bandwidth of each of the memory channels, represents the frequency of the off-chip storage module, Indicates the data bit width of each memory channel, represents the throughput of the inverse number-theoretic transformation operator, represents the data bit width of each prime number in the ciphertext polynomial, represents the frequency of the computation module, represents the key parameter of the homomorphic encryption algorithm, represents the number of parallel butterfly units of the inverse number theoretic transformation operator, a butterfly unit cardinality representing a butterfly unit type representation of the inverse number theoretic transform operator, represents the number of rotation factors required by each of the butterfly units.

9. The method according to claim 5, characterized in that The method sequentially obtains each ciphertext polynomial and the corresponding rotation factor from the off-chip storage module according to the number of memory channels transmitted in parallel between the off-chip storage module and the on-chip storage module, and caches the obtained ciphertext polynomial and the corresponding rotation factor to the on-chip storage module, including: According to the number of memory channels transmitted in parallel between the off-chip storage module and the on-chip storage module, sequentially obtain each ciphertext polynomial and the corresponding rotation factor from the off-chip storage module; Locating a first target buffer for the ciphertext polynomial and a second target buffer for the twiddle factor on the on-chip storage module, respectively; caching the acquired ciphertext polynomial into the first target buffer according to the first data transmission mode corresponding to the first target buffer; Cache the acquired rotation factors into the second target buffer according to the second data transmission mode corresponding to the second target buffer; The data transmission mode is divided into at least two types: transmission after caching through a first-in-first-out queue and transmission after not caching through a first-in-first-out queue.

10. The method according to claim 1, characterized in that The step of performing parallel pipeline operation of different key transformation calculation operators on the ciphertext polynomial based on the allocated computing resources and according to the rotation factor to obtain a key transformation calculation result of the ciphertext polynomial includes: Obtaining a transformation key polynomial pair and an intermediate calculation result from an off-chip storage module, and caching the obtained transformation key polynomial pair and the intermediate calculation result to an on-chip storage module; After performing inverse number theory transformation operation and modular multiplication operation on the ciphertext polynomial based on the inverse number theory transformation operator and the modular multiplication operator, a target polynomial is obtained; Reading the rotation factors alternately and continuously from two memories on the on-chip storage module; Based on a number-theoretic transformation operator, according to the rotation factors read alternately, a number-theoretic transformation operation is performed on the target polynomial to obtain a number-theoretic transformation operation result of the ciphertext polynomial; Performing an inner product operation on the number theory transformation operation result of the ciphertext polynomial and the transformation key polynomial to obtain an inner product operation result; Accumulating the inner product operation result and the intermediate calculation result to obtain an accumulation result; In the case where the ciphertext polynomial is the last batch of ciphertext polynomials, using the accumulated result as the key transformation calculation result of the ciphertext polynomial; In the case that the ciphertext polynomial is not the last batch of ciphertext polynomials, the accumulated result is used as a new intermediate calculation result to update the intermediate calculation result stored in the off-chip storage module.

11. The method according to claim 10, characterized in that The step of acquiring the transformed key polynomial pair and the intermediate calculation result from the off-chip storage module and caching the acquired transformed key polynomial pair and the intermediate calculation result to the on-chip storage module includes: The intermediate calculation results are continuously and alternately obtained on the two memory channels of the off-chip storage module, and the alternately obtained intermediate calculation results are alternately stored in the two memories of the on-chip storage module, so that the accumulation operation can be continuously and alternately run on different memories.

12. The method according to claim 10, characterized in that The method of performing a number-theoretic transformation operation on the target polynomial based on the number-theoretic transformation operator according to the rotation factors read alternately to obtain a number-theoretic transformation operation result of the ciphertext polynomial includes: According to the number of parallel operations of the number theory transformation operator, splitting the target polynomial and writing it into a corresponding number of memories; Based on the number theoretic transformation operator, according to the rotation factors read alternately, number theoretic transformation operations are alternately performed on the target polynomials stored in the memory until the number theoretic transformation operations of all target polynomials are completed, thereby obtaining the number theoretic transformation operation results of the ciphertext polynomials.

13. A data conversion device, characterized in that: include: An acquisition module, used to obtain several batches of ciphertext polynomials corresponding to the original ciphertext of the homomorphic encryption algorithm; An allocation module, used to allocate computing resources to each batch of ciphertext polynomials in turn according to the ciphertext modulus decomposition length of each batch of ciphertext polynomials; wherein the computing resources include multiple key transformation computing operators, and the throughputs of different key transformation computing operators are consistent; A computing module, configured to perform parallel pipeline operation of different key transformation computing operators on the ciphertext polynomial based on the allocated computing resources, so as to obtain a key transformation computing result of the ciphertext polynomial; A transformation module, used to determine a target key transformation result of the original ciphertext according to a key transformation calculation result of the ciphertext polynomial; The allocation module is specifically used for: Determining the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations according to the length of the ciphertext modular decomposition of each batch of ciphertext polynomials; wherein the first group of modular multiplication units and the second group of modular multiplication units include a plurality of modular multiplication operators; Get the butterfly unit type and the number of butterfly units in parallel of the inverse number theory transform operator; Determining the number of calculation cycles of the inverse number theoretic transformation operator according to the butterfly unit type and the number of parallel butterfly units of the inverse number theoretic transformation operator; Allocating computing resources for each batch of ciphertext polynomials in turn according to the number of computing cycles of the inverse number theory transformation operator and the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations; The computing module is specifically used for: Obtain each ciphertext polynomial and the corresponding rotation factor from the off-chip storage module in turn, and cache the obtained ciphertext polynomial and the corresponding rotation factor to the on-chip storage module; Based on the allocated computing resources and according to the rotation factors, performing parallel pipeline operation of different key transformation calculation operators on the ciphertext polynomial to obtain a key transformation calculation result of the ciphertext polynomial; The computing module is specifically used for: Obtaining the frequency of the off-chip storage module and the data bit width of each memory channel; Determining the bandwidth of each memory channel according to the frequency of the off-chip storage module and the data bit width of each memory channel; Determining the throughput of the inverse number theory transformation operator according to the frequency of the computing module and the data bit width of each prime number in the ciphertext polynomial; wherein the computing module includes the computing resource; Determine the number of memory channels for parallel transmission between the off-chip storage module and the on-chip storage module according to the bandwidth of each of the memory channels, the throughput of the inverse number theoretic transformation operator, the butterfly unit type of the inverse number theoretic transformation operator, and the number of parallel butterfly units; According to the number of memory channels transmitted in parallel between the off-chip storage module and the on-chip storage module, each ciphertext polynomial and the corresponding rotation factor are obtained from the off-chip storage module in turn, and the obtained ciphertext polynomial and the corresponding rotation factor are cached in the on-chip storage module; The transformation module is specifically used for: A modular reduction operation is performed on the key transformation calculation result of the ciphertext polynomial to obtain a target key transformation result of the original ciphertext.

14. A data conversion system, characterized in that: include: An off-chip storage module, an on-chip storage module, a control module, and a computing module; The off-chip storage module is used to store several batches of ciphertext polynomials and rotation factors corresponding to the original ciphertext of the homomorphic encryption algorithm; The control module is used to store the ciphertext polynomial and the rotation factor stored in the off-chip storage module to the on-chip storage module for reading and use by the computing module; The computing module includes multiple computing resources; wherein the computing resources include multiple key transformation computing operators, and the throughput of different key transformation computing operators is consistent; The control module is also used to allocate computing resources to each batch of ciphertext polynomials in turn according to the ciphertext modulus decomposition length of each batch of ciphertext polynomials; The computing resource is used to perform parallel pipeline operation of different key transformation calculation operators on the ciphertext polynomial to obtain a key transformation calculation result of the ciphertext polynomial; and determine a target key transformation result of the original ciphertext according to the key transformation calculation result of the ciphertext polynomial; The control module is specifically used for: Determining the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations according to the length of the ciphertext modular decomposition of each batch of ciphertext polynomials; wherein the first group of modular multiplication units and the second group of modular multiplication units include a plurality of modular multiplication operators; Get the butterfly unit type and the number of butterfly units in parallel of the inverse number theory transform operator; Determining the number of calculation cycles of the inverse number theoretic transformation operator according to the butterfly unit type and the number of parallel butterfly units of the inverse number theoretic transformation operator; Allocating computing resources for each batch of ciphertext polynomials in turn according to the number of computing cycles of the inverse number theory transformation operator and the number of times the first group of modular multiplication units and the second group of modular multiplication units perform polynomial scalar modular multiplication calculations; The control module is specifically used to: sequentially obtain each ciphertext polynomial and the corresponding rotation factor from the off-chip storage module, and cache the obtained ciphertext polynomial and the corresponding rotation factor to the on-chip storage module; Based on the allocated computing resources and according to the rotation factors, performing parallel pipeline operation of different key transformation calculation operators on the ciphertext polynomial to obtain a key transformation calculation result of the ciphertext polynomial; The control module is specifically used for: Obtaining the frequency of the off-chip storage module and the data bit width of each memory channel; Determining the bandwidth of each memory channel according to the frequency of the off-chip storage module and the data bit width of each memory channel; Determining the throughput of the inverse number theory transformation operator according to the frequency of the computing module and the data bit width of each prime number in the ciphertext polynomial; wherein the computing module includes the computing resource; Determine the number of memory channels for parallel transmission between the off-chip storage module and the on-chip storage module according to the bandwidth of each of the memory channels, the throughput of the inverse number theoretic transformation operator, the butterfly unit type of the inverse number theoretic transformation operator, and the number of parallel butterfly units; According to the number of memory channels transmitted in parallel between the off-chip storage module and the on-chip storage module, each ciphertext polynomial and the corresponding rotation factor are sequentially obtained from the off-chip storage module, and the obtained ciphertext polynomial and the corresponding rotation factor are cached in the on-chip storage module; The control module is specifically used for: A modular reduction operation is performed on the key transformation calculation result of the ciphertext polynomial to obtain a target key transformation result of the original ciphertext.

15. An electronic device, characterized in that: include: at least one processor and memory; The memory stores computer-executable instructions; The at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor performs the method according to any one of claims 1 to 12.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when a processor executes the computer-executable instructions, the method according to any one of claims 1 to 12 is implemented.

17. A computer program product, characterized in that The method comprises computer instructions for causing a computer to execute the method according to any one of claims 1 to 12.

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