A Dual-Antenna Clock Synchronization and Time-Synchronization Method, System, Device, and Medium Based on UWB Technology

Abstract

The present invention discloses a dual-antenna clock synchronization and time transfer method, system, device and medium based on UWB technology, which relates to the field of wireless clock synchronization technology. The method includes: using a master base station to receive GPS second pulse signals, sending UWB synchronization signals to slave base stations, and using dual UWB communication chips for clock synchronization, that is, receiving the UWB synchronization signals sent by the master base station and forwarding the UWB synchronization signals to indoor terminal devices, and using the UWB communication chips to obtain the timestamps at the moments of receiving and sending the UWB synchronization signals, and calculating the difference between the two timestamps; determining the phase difference of the UWB synchronization signals forwarded by the slave base station based on the time difference, converting the phase difference into voltage information through a DAC, and performing frequency regulation on a temperature-compensated crystal oscillator, thereby adjusting the phase of the sent UWB synchronization signals. The present invention can utilize UWB base stations to complete the wireless transmission of second pulse time references and improve the synchronization accuracy of receiving and sending clocks.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless clock synchronization, and particularly to a dual-antenna clock synchronization and timing method, system, device and medium based on UWB technology. Background Art

[0002] With the rapid development of 5G and Internet of Things (IoT) technologies, the application of indoor base stations has become increasingly widespread. These base stations are widely deployed in indoor environments such as shopping malls, office buildings, subway stations, airports, etc. to provide high-quality wireless communication services. To ensure the coordinated operation between multiple base stations, the accuracy of data transmission, and the reliability of real-time applications, accurate timing of each base station is particularly important.

[0003] In a complex indoor environment, the coordinated operation between multiple base stations requires precise timing between the base stations. The timing scheme must have high stability and reliability and be able to work properly under various interference conditions. Real-time positioning, synchronous transmission, and high-quality services require the timing accuracy between base stations to reach the microsecond level or even the sub-microsecond level to reduce data latency and errors. An ideal timing scheme should also be able to adapt to various indoor environments, including high-rise buildings, underground facilities, etc., and be flexibly configured according to specific application scenarios.

[0004] In existing indoor base station timing technologies, solutions such as Global Positioning System (GPS) timing, fiber optic transmission timing, shortwave timing, longwave timing, and low-frequency time code timing are mainly adopted. GPS timing synchronizes the clocks of ground devices by receiving time signals from GPS satellites. The time signals provided by GPS have high precision and can reach the nanosecond level. However, in an indoor environment, GPS signals are blocked by buildings, resulting in a significant reduction in signal strength or even complete loss, thus unable to guarantee the reliability and precision of timing. Therefore, GPS timing is restricted in indoor applications. Fiber optic transmission timing utilizes the low-latency characteristics of fiber optic media to achieve timing between base stations by transmitting high-precision time signals through optical fibers. This method can provide high-precision timing and is usually used in high-end applications that require strict synchronization. However, fiber optic transmission timing requires a large amount of physical wiring, which involves a large amount of work, high cost, and is difficult to wire and maintain in a complex indoor environment. In addition, the laying and maintenance of optical fibers will increase the complexity of the system. Shortwave timing uses shortwave radio with wavelengths ranging from 100 meters to 10 meters (frequency: 3 MHz to 30 MHz) for timing. In China, the shortwave radio station of the National Time Service Center (call sign BPM) uses frequencies of 2.5 MHz, 5 MHz, 10 MHz, and 15 MHz to continuously broadcast Chinese shortwave radio time signals throughout the day. The disadvantage is that shortwave signals are easily interfered by the ionosphere and environmental noise, and the accuracy and stability decrease in a complex environment. Longwave timing uses longwave radio with wavelengths ranging from 10 kilometers to 1 kilometer (frequency: 30 KHz to 300 KHz) for timing. The longwave radio station of the National Time Service Center (call sign BPL) transmits at a frequency of 100 KHz. The ground wave action distance of the timing signal is 1000 - 2000 kilometers, and the sky wave signal covers 3000 kilometers, basically covering inland China and coastal waters. The timing accuracy is at the microsecond level. The disadvantage is that longwave signals have poor penetrability, are greatly affected by geography and buildings, and have limited indoor coverage. Low-frequency time code timing belongs to a special type of longwave timing and is suitable for regional standard time and frequency transmission. The National Time Service Center adopts a continuous wave time code timing system technology with a carrier frequency of 68.5 KHz. The accuracy can reach an error of no more than 1 second in 300,000 years. However, the transmission distance of low-frequency time code signals is limited, the signal strength is weak in areas far from the transmitting station, and it is easily interfered by the environment. Traditional local clock timekeeping design schemes often use digital phase-locked loops, which often have problems such as low accuracy and complex structures. Therefore, it is difficult for existing traditional schemes to balance the portability and reliability of implementing timing schemes.

[0005] Therefore, the following problems currently exist:

[0006] (1) The problem that GPS signals are weak and have low accuracy in an indoor environment, making it impossible to directly perform GPS timing;

[0007] (2) The problem that fiber optic transmission clock synchronization requires a large amount of physical wiring, involving a large amount of work and high cost. Summary of the Invention

[0008] The object of the present invention is to provide a dual-antenna clock synchronization and time service method, system, device and medium based on UWB technology, which can complete the wireless transmission of the second pulse time reference by using a UWB base station and improve the synchronization accuracy of the transceiver clocks.

[0009] To achieve the above object, the present invention provides the following solutions:

[0010] A dual-antenna clock synchronization and time service method based on UWB technology, comprising:

[0011] Using the master base station to receive the GPS second pulse signal and send a UWB synchronization signal to the slave base station;

[0012] Using the dual UWB communication chips in the slave base station for clock synchronization, that is, receiving the UWB synchronization signal sent by the master base station, forwarding the UWB synchronization signal to the indoor terminal device, and using the UWB communication chips to obtain the timestamps of the moments when the UWB synchronization signals are received and sent, and calculating the difference between the timestamps to obtain the time difference;

[0013] Based on the time difference, determining the phase information of the delay or lag of the UWB synchronization signal forwarded by the slave base station, converting the phase information into voltage information through DAC, regulating the frequency of the temperature-compensated crystal oscillator, and adjusting the phase of the UWB synchronization signal sent through frequency transformation, so as to form a feedback and control the phase difference between the forwarded and received UWB synchronization signals within the error setting range.

[0014] Optionally, the step of using the master base station to receive the GPS second pulse signal and send a UWB synchronization signal to the slave base station specifically includes:

[0015] Using the main control chip of the master base station to receive the GPS second pulse signal. After the main control chip detects the rising edge of the GPS second pulse signal, controlling the DW1000 chip to start the UWB sending function and send a UWB synchronization signal with a period of 1 second for the slave base station to receive; the DW1000 chip sets the delay sending value to the timestamp value of each send plus 1 second by configuring the delay transceiver register value, so as to achieve the function of sending a pulse signal once per second.

[0016] Optionally, the method for obtaining the time difference is:

[0017] Reset the slave base station, and actively receive the UWB synchronization signal sent by the master base station through the DW1000-A chip after reset; when the DW1000-A chip receives the UWB synchronization signal each time, immediately obtain the current time, and make the DW1000-B chip send and forward the UWB synchronization signal every 1 second while recording the current timestamp and generating an interruption as the local clock synchronization pulse; make the DW1000-B chip actively send the forwarded UWB synchronization signal with a period of 1 second, and its delay sending configuration method is the same as that of the DW1000 chip of the master base station; use the main control chip to calculate the difference between the latest obtained timestamps of the two DW1000 chips to obtain the time difference.

[0018] Optionally, the frequency regulation includes system feedback coarse tuning and system feedback fine tuning;

[0019] The process of the system feedback coarse tuning is as follows:

[0020] When the difference between the timestamps is greater than or equal to 1 millisecond, perform count value compensation on the internal delay transceiver register of the DW1000 chip of the slave base station, and the formula for compensating the counter value is as follows:

[0021] ΔC = f(t)·Δt - C

[0022] The process of the system feedback fine tuning is as follows:

[0023] When the difference between the timestamps is less than 1 millisecond, adjust the external crystal oscillator frequency, and the calculation formula for adjustment is as follows:

[0024] Δt_a = C·Δf(t)

[0025] Wherein, f(t) is the current working frequency of the DW1000 chip, Δt is the time difference, C is the original counter count value, and Δt_a is the time difference between receiving the UWB synchronization signal and forwarding the UWB synchronization signal.

[0026] Optionally, the feedback control adopts PID feedback control, and the output of the PID feedback control is expressed as:

[0027]

[0028] Wherein, u(t) is the control signal, e(t) is the error of the system, which is used to represent the difference between the set value and the actual value, K p 、K i 、K d are the proportional, integral and differential coefficients respectively, and t is the moment.

[0029] The present invention also provides a dual-antenna clock synchronization and time service system based on UWB technology, including:

[0030] A signal synchronization module, configured to receive GPS second pulse signals by using a master base station and send UWB synchronization signals to slave base stations;

[0031] A time difference acquisition module, configured to perform clock synchronization by using a dual-UWB communication chip in a slave base station, that is, receive UWB synchronization signals sent by the master base station, forward UWB synchronization signals to indoor terminal devices, and obtain timestamps of the moments when the UWB synchronization signals are received and sent by using the UWB communication chip, and calculate the difference between the timestamps to obtain a time difference;

[0032] A system regulation module, configured to determine phase information of the delay or lag of the UWB synchronization signal forwarded by the slave base station based on the time difference, convert the phase information into voltage information through a DAC, perform frequency regulation on a temperature-compensated crystal oscillator, and adjust the phase of the sent UWB synchronization signal through frequency conversion, so as to form a feedback and control the phase difference between the forwarded and received UWB synchronization signals within an error setting range.

[0033] The present invention further provides an electronic device, including a memory and a processor, where the memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to execute the dual-antenna clock synchronization and timing method based on UWB technology as described above.

[0034] The present invention further provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the dual-antenna clock synchronization and timing method based on UWB technology as described above is implemented.

[0035] According to the specific embodiments provided by the present invention, the following technical effects are disclosed by the present invention:

[0036] The present invention discloses a dual-antenna clock synchronization and timing method, system, device and medium based on UWB technology. The method includes receiving GPS second pulse signals by using a master base station, sending UWB synchronization signals to slave base stations, performing clock synchronization by using a dual-UWB communication chip, that is, receiving UWB synchronization signals sent by the master base station, forwarding UWB synchronization signals to indoor terminal devices, and obtaining timestamps of the moments when the UWB synchronization signals are received and sent by using the UWB communication chip, and calculating the difference between the two timestamps; determining the phase difference of the UWB synchronization signal forwarded by the slave base station based on the time difference, and converting the phase difference into voltage information through a DAC, performing frequency regulation on a temperature-compensated crystal oscillator, and further adjusting the phase of the sent UWB synchronization signal. The present invention can complete the wireless transmission of the second pulse time reference by using a UWB base station and improve the synchronization accuracy of the transceiver clocks. Description of the Drawings

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0038] Figure 1 It is a schematic diagram of the dual-antenna clock synchronization and time transfer logic based on UWB technology of the present invention;

[0039] Figure 2 It is a schematic diagram of the difference between the timestamps of the two time transfer signals in this embodiment. Detailed implementation manners

[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0041] The object of the present invention is to provide a dual-antenna clock synchronization and time transfer method, system, device and medium based on UWB technology, which can use a UWB base station to complete the wireless transmission of the second pulse time reference and improve the synchronization accuracy of the transceiver clocks.

[0042] To make the above objects, features and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0043] As Figure 1 shown, the present invention provides a dual-antenna clock synchronization and time transfer method based on UWB technology, including:

[0044] Step 100: Use the master base station to receive the GPS second pulse signal and send a UWB synchronization signal to the slave base station;

[0045] Step 200: Use the dual-UWB communication chips in the slave base station for clock synchronization, that is, receive the UWB synchronization signal sent by the master base station, forward the UWB synchronization signal to the indoor terminal device, and use the UWB communication chips to obtain the timestamps of the moments when the UWB synchronization signals are received and sent, and calculate the difference between the timestamps to obtain the time difference;

[0046] Step 300: Determine the phase information of the UWB synchronization signal delayed or lagged from the base station based on the time difference, convert the phase information into voltage information through a DAC, regulate the frequency of the temperature-compensated crystal oscillator, and adjust the phase of the transmitted UWB synchronization signal through frequency conversion, so as to form a feedback and control the phase difference between the forwarded and received UWB synchronization signals within the error setting range.

[0047] Based on the above technical solution, the following embodiments are provided.

[0048] In this embodiment, first, taking advantage of the characteristics of low power consumption, strong indoor multipath interference resistance, and high time measurement resolution of UWB technology, a UWB base station is used to complete the wireless transmission of the second pulse time reference. Secondly, the traditional local clock timekeeping design scheme requires a phase detector, a DAC, and a voltage-controlled oscillator to form a phase-locked loop. Among them, the phase detector can use a TDC and adopt a digital phase-locked loop mode. In this design scheme, a 38.4M voltage-controlled temperature-compensated crystal oscillator drives the DW1000 to generate a local second pulse. The DW1000 itself has the high-precision time measurement function of a TDC, and the measurement resolution reaches 15.65 ps, which is better than the current mainstream TDC chips. This design scheme uses the signal transceiver time measurement function of the DW1000 to achieve digital phase detection, and forms a low-cost digital phase-locked loop with a DAC and a temperature-compensated crystal oscillator, which can make the synchronization accuracy of the transceiver clocks reach within 50 nanoseconds.

[0049] The specific content includes: The master base station receives the GPS second pulse signal and simultaneously transmits UWB synchronization signals with a time interval of 1 second. The slave base station uses a dual-UWB communication chip for clock synchronization, receives the UWB synchronization signals sent by the master base station, forwards the synchronization signals to the indoor terminal device, and uses the UWB communication chip to obtain the timestamps of the moments when the UWB signals are sent and received. The difference between the two timestamps is the time difference, which can be reflected as a phase difference in a square wave. The timestamp information is sent to the main control chip (STM32H750) for comparison. The phase information of the slave base station forwarding the synchronization signal delayed or lagged is converted into voltage information through a DAC. The voltage can regulate the frequency of the temperature-compensated crystal oscillator. Through the change of frequency, the phase of the transmitted signal can be adjusted, so as to form a feedback, and gradually make the phase difference between the forwarded synchronization signal and the received synchronization signal approach and converge within the error tolerance range.

[0050] Based on previous research on UWB technology, this dual-antenna clock synchronization and time dissemination scheme based on UWB technology was designed and developed. The scheme mainly consists of a master base station and a slave base station. The master base station is mainly used for satellite standard signal reception and time dissemination synchronization signal transmission. The overall hardware of the slave base station is a UWB wireless transceiver base station. Two UWB communication chips in the slave base station use the same voltage-controlled crystal oscillator as the frequency source and can receive the wireless time dissemination synchronization signal sent by the master base station. While receiving the synchronization signal, the slave base station transmits and forwards the synchronization signal. According to the timestamp information of the received and forwarded synchronization signals, the slave base station regulates the forwarded synchronization signal to make the phase of the forwarded synchronization signal consistent with that of the received synchronization signal, achieving the effects of clock synchronization and synchronization signal forwarding. While transmitting and forwarding the synchronization signal, the slave base station outputs a local synchronization second pulse. The main components of the base station hardware are as follows:

[0051] (1) Main control chip;

[0052] (2) UWB communication chip;

[0053] (3) 38.4MHz temperature-compensated crystal oscillator;

[0054] (4) Digital-to-analog converter (DAC);

[0055] The main control chips of both the master base station and the slave base station adopt the STM32H750 chip. STM32H750 is a high-performance microcontroller (MCU) produced by STMicroelectronics (ST). It belongs to the STM32H7 series and uses a 32-bit ARM Cortex-M7 core with a working frequency of up to 480MHz. The processing power and working frequency of this chip can meet the requirements of the nanosecond-level clock synchronization working environment.

[0056] The master base station uses one UWB communication chip to send UWB synchronization signals. The slave base station uses one UWB communication chip to receive the UWB synchronization signals sent by the master base station and then uses another identical UWB communication chip to send the forwarded UWB synchronization signals for synchronizing other terminal devices. The UWB communication chips in this scheme all adopt the DW1000 model chip. DW1000 is a UWB wireless transceiver chip launched by Decawave and is widely used in fields such as high-precision position location. The clock generated by the 38.4MHz crystal oscillator in the slave base station is frequency-multiplied to 124.8MHz through an internal phase-locked loop to be used as the working clock of DW1000, and its internal timestamp accuracy can reach up to 15.65ps at most. The main control chip communicates with the UWB communication chip through the SPI communication protocol to control it to realize the functions of wireless signal transceiver and timestamp acquisition.

[0057] The working principle is as follows:

[0058] After the master base station receives the rising edge of the GPS second pulse signal, i.e., GPS_1PPS, it immediately activates the UWB transmission function and transmits the UWB synchronization signal.

[0059] After the slave base station is reset and started, the DW1000 timestamp information is the count value of the system clock counter register (Register file: 0x06 – System Time Counter) after reset. Its maximum counting time reaches about 17 seconds and then resets to zero for counting again. Therefore, the same external clock crystal oscillator is used to drive two DW1000s and the SYNC function of the two DW1000s is used to reset their clocks simultaneously, so that the system clock counter registers of the two DW1000s count synchronously. For the two DW1000 chips of the slave base station, DW1000-A is responsible for receiving the UWB synchronization signal from the master base station, and DW1000-B is responsible for forwarding the UWB synchronization signal at 1-second intervals.

[0060] After DW1000-B is reset, it actively sends a forwarded UWB synchronization signal with a period of 1 second. Each time a UWB signal is sent, the timestamp at the time of sending is recorded. DW1000-A receives the synchronization signal sent by the master base station and records the timestamp at the time of reception. The pulse periods of both receiving the UWB synchronization signal and forwarding the UWB synchronization signal are 1 second. The difference between the latest two timestamps is the time difference between receiving the UWB synchronization signal and forwarding the UWB synchronization signal. While DW1000-B forwards the UWB synchronization signal and records the timestamp, it can also generate an interrupt event. The content of the event is to raise the level and then lower it, so that the overall function of the interrupt is to generate a standard local second pulse, and the generation of the interrupt event occurs simultaneously with the transmission of forwarding the UWB synchronization signal.

[0061] The main control chip obtains the timestamp information of DW1000-A and DW1000-B and gets their difference. The main control chip gives feedback according to the time difference between the two signals. The feedback signal is input into the DAC to be converted into an analog voltage value. The 38.4MHz temperature-compensated crystal oscillator is regulated by the voltage. The change of the externally applied voltage will change the output frequency of the crystal oscillator. The two DW1000s receive the crystal oscillator pulses as the clock source. The change of the crystal oscillator frequency affects the period of the UWB forwarded synchronization signal generated by DW1000-B and the generated local second pulse, and ultimately affects the signal output, forming a closed-loop feedback to achieve the result of frequency modulation and phase modulation.

[0062] The logic of this solution is based on the UWB synchronization signal received from the master base station at the slave base station. Eventually, the forwarded UWB synchronization signal and the local second pulse will reach phase and frequency synchronization with the UWB synchronization signal received from the master base station after multiple adjustment feedbacks. The forwarded UWB synchronization signal generated by the slave base station of this solution can synchronize other indoor terminal IoT devices. When the slave base station of this solution is used as an IoT terminal solution, the locally generated second pulse can be used as a standard timing signal to synchronize the local terminal.

[0063] As a specific implementation method, the specific working processes of each part are as follows:

[0064] (1) The master base station sends a synchronization signal

[0065] The master control chip of the master base station receives the GPS second pulse signal. After the master control chip detects the rising edge of the GPS second pulse signal, it controls the DW1000 chip to start the UWB sending function and send a UWB synchronization signal with a period of 1 second for the slave base station to receive. The DW1000 chip sets the delayed send value to the timestamp value of each send plus 1 second by configuring the Delayed Send or Receive Time register (Register file: 0x0A), achieving the function of sending a pulse signal once per second.

[0066] (2) The slave base station system resets

[0067] The master control chip of the slave base station sends a reset signal to the SYNC pins of the two DW1000 chips simultaneously, resetting the two DW1000 chips simultaneously. When the two DW1000 chips are reset simultaneously and use the same clock source, the system clock counting registers count simultaneously, and the clock period is 1 second for both, which can make the subsequent obtained timestamp difference be the phase difference between the two signals.

[0068] (3) Obtaining the time difference

[0069] After the slave base station is reset, DW1000-A actively receives the UWB synchronization signal sent by the master base station. Each time DW1000-A receives the UWB synchronization signal, it immediately obtains the current timestamp. While DW1000-B sends the forwarded UWB synchronization signal every 1 second, it records the current timestamp and generates an interrupt as the local clock synchronization pulse. DW1000-B actively sends a forwarded UWB synchronization signal with a period of 1 second, and its delayed send configuration method is the same as that of the DW1000 chip of the master base station. The master control chip subtracts the timestamps newly obtained by the two DW1000s to obtain the time difference, which is the phase difference difference information.

[0070] As Figure 2 shown in the figure, Δt1 and Δt2 in the figure are the time differences obtained by the master control chip by subtracting the timestamps of the two timing signals.

[0071] Δt_a = Δt2 - Δt1

[0072] Δt_a is the difference between the interpolation of two adjacent time difference values. After the main control chip obtains its value, it performs preprocessing on it. First, it judges and eliminates outliers for this information.

[0073] First, the time differences obtained by the main control chip are grouped according to the acquisition time sequence. Within each group, outliers are judged and eliminated according to the Rheinmetall (3s) criterion. The criterion is based on the following algorithm rules:

[0074] There are a total of n Δt_a measurement values in each group, which are Δt_1, Δt_2... Δt_n respectively. If the residual error of a certain measured value is considered to be greater than three times the standard deviation, then this outlier is identified and eliminated. For example:

[0075]

[0076]

[0077] If: Then the b-th data is an outlier and needs to be eliminated.

[0078] After eliminating outliers using the Rheinmetall criterion, the moving average filtering algorithm is used to further filter the data. The filtering window adopted in this scheme is 8, that is, the first data output by the filter is after 8 sampling periods. That is, first, the 8 input data are averaged to obtain the average value After 8 periods, the sliding input of the data can be realized.

[0079] After the 8th sampling value, the c-th time difference Δt_c is:

[0080]

[0081] where d = c - k.

[0082] The filtered time difference information can be used for subsequent feedback control.

[0083] (4) System feedback coarse adjustment

[0084] Since the signal clock cycles involved are all 1 second, when the time stamp differences are all less than 1 second. When the time stamp difference is greater than or equal to 1 millisecond, a timing synchronization signal is sent for coarse adjustment.

[0085] The principle of coarse adjustment is to adjust the count value by compensating the internal delay transceiver register of DW1000 according to the phase difference, that is, the difference, so as to change the counting time and further change the phase of the transmitted synchronization timing pulse. The compensation value is calculated according to the following formula:

[0086]

[0087] It can be rewritten according to the formula: ΔC = f(t)·Δt - C.

[0088] Among them, since the timing signals involved are all pulse signals with a period of 1 second, the time difference Δt at the rising edge of the time is the phase difference Δθ. C is the original counter value, ΔC is the compensation counter value, and f(t) is the current working frequency of DW1000.

[0089] (5) System feedback fine-tuning

[0090] When the time stamp difference is less than 1 millisecond, fine-tuning is performed on the transmitted timing synchronization signal, that is, the external crystal oscillator frequency is adjusted. If the phase of the standard clock is faster than the local timing clock, it is necessary to speed up the generation time of the timing pulse, that is, at the same count value, increase the counting frequency. Vice versa. The specific formula is as follows:

[0091] Δt_a = C·Δf(t)

[0092] Among them, Δt_a is the phase difference between the received UWB synchronization signal and the forwarded UWB synchronization signal, Δf(t) is the required change in the system main frequency, and C is the count value of the delay transceiver register.

[0093] (6) PID feedback control

[0094] During the system fine-tuning process, converting the phase difference into the voltage value required to change the crystal oscillator pulse frequency is achieved through the PID feedback control process. PID control is a widely used adjustment method in automatic control systems. By setting appropriate proportional (P), integral (I), and derivative (D) parameters, it can accurately control the output and make the system reach a stable state.

[0095] Proportional control multiplies the current error by a proportional coefficient and directly outputs the control signal. The role of proportional control is to quickly respond to the error, but it is prone to causing a steady-state error in the system. Integral control accumulates past errors and multiplies by an integral coefficient to output the control signal. The role of integral control is to eliminate the steady-state error, but it may introduce system oscillations. Derivative control calculates the rate of change of the error and multiplies by a derivative coefficient to output the control signal. The role of derivative control is to predict the error trend and improve the system response speed, but it is sensitive to noise.

[0096] The output of PID control can be expressed as:

[0097]

[0098] Among them, u(t) is the control signal, e(t) is the error of the system, that is, the difference between the set value and the actual value. K p 、K i 、Kd They are the proportional, integral, and derivative coefficients respectively.

[0099] In this embodiment, PID control is used to adjust the external crystal oscillator frequency. By adjusting the voltage, the frequency of the crystal oscillator is controlled, thereby achieving precise synchronization of the system. Specifically, the phase difference information obtained by the master control chip is converted into a control voltage through a PID controller, and the externally applied voltage of the 38.4 MHz temperature-compensated crystal oscillator is adjusted, causing the crystal oscillator frequency to change accordingly, and then adjusting the system clock frequency to achieve synchronization of the pulse signal.

[0100] Therefore, it has the following beneficial effects:

[0101] The dual-antenna clock synchronization and timekeeping scheme based on UWB technology proposed by the present invention; designs a high-performance UWB communication chip based on the UWB communication principle. Compared with the traditional synchronization and timekeeping scheme, taking advantage of the characteristics of strong indoor multipath interference resistance and high time resolution of UWB technology, a new indoor timekeeping scheme is designed. The PID closed-loop feedback is used to adjust the system clock, and algorithms are used to eliminate and filter the errors that may be encountered in practice, and finally a synchronous timekeeping signal with high resolution and strong multipath interference resistance is generated. This scheme can not only enable the terminal Internet of Things devices to quickly synchronize with the received timekeeping signal, but also stably send the standard external GPS or Beidou satellite signals to each terminal Internet of Things device indoors.

[0102] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0103] Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the core idea of the present invention; at the same time, for those of ordinary skill in the art, based on the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A dual-antenna clock synchronization timing method based on UWB technology, characterized in that: include: The master base station receives the GPS pulse-per-second signal and sends the UWB synchronization signal to the slave base station. The dual UWB communication chips in the slave base station are used for clock synchronization, which not only receives the UWB synchronization signal sent by the master base station, but also forwards the UWB synchronization signal to the indoor terminal device, and uses the UWB communication chip to obtain the timestamp of the moment of sending and receiving the UWB synchronization signal, and calculates the difference between the timestamps to obtain the time difference; Based on the time difference, the phase information of the delay or lag of the forwarded UWB synchronization signal from the base station is determined, and the phase information is converted into voltage information through a DAC, and the temperature compensated crystal oscillator is frequency-controlled, and the phase of the sent UWB synchronization signal is adjusted through frequency conversion, thereby forming feedback, and controlling the phase difference between the forwarded and received UWB synchronization signals to be within the error setting range; The frequency control includes system feedback coarse adjustment and system feedback fine adjustment; The process of system feedback coarse adjustment is as follows: When the difference in timestamps is greater than or equal to 1 millisecond, the count value of the delayed transceiver register inside the DW1000 chip of the slave base station is compensated. The formula for compensating the counter value is as follows: ΔC=f(t)·Δt-C The process of system feedback fine-tuning is as follows: When the timestamp difference is less than 1 millisecond, the external crystal frequency is adjusted. The adjustment calculation formula is as follows: Δt_a=C·Δf(t) Among them, f(t) is the current operating frequency of the DW1000 chip, Δt is the time difference, C is the count value of the original counter, and Δt_a is the time difference between receiving the UWB synchronization signal and forwarding the UWB synchronization signal.

2. The dual-antenna clock synchronization timing method based on UWB technology according to claim 1, characterized in that: The method of receiving the GPS pulse-per-second signal by the master base station and sending the UWB synchronization signal to the slave base station specifically includes: The main control chip of the main base station is used to receive the GPS second pulse signal. After the main control chip detects the rising edge of the GPS second pulse signal, the DW1000 chip is controlled to start the UWB sending function and send a UWB synchronization signal with a period of 1 second for reception from the slave base station; the DW1000 chip configures the delayed sending and receiving register value and sets the delayed sending value to the timestamp value of each sending plus 1 second, thereby achieving the function of sending a pulse signal once per second.

3. The dual-antenna clock synchronization timing method based on UWB technology according to claim 1, characterized in that: The method for obtaining the time difference is: Reset the slave base station, and after the reset, actively receive the UWB synchronization signal sent by the master base station through the DW1000-A chip; every time the DW1000-A chip receives the UWB synchronization signal, it immediately obtains the current time, so that the DW1000-B chip sends the forwarded UWB synchronization signal every 1 second, records the current timestamp and generates an interrupt as a local clock synchronization pulse; the DW1000-B chip actively sends the forwarded UWB synchronization signal with a period of 1 second, and its delayed sending configuration method is the same as the DW1000 chip configuration method of the master base station; the time difference is obtained by subtracting the latest timestamps obtained by the two DW1000 chips through the main control chip.

4. The dual-antenna clock synchronization timing method based on UWB technology according to claim 1, characterized in that: The feedback control of the system feedback fine adjustment adopts PID feedback control, and the output of PID feedback control is expressed as: Where u(t) is the control signal, e(t) is the system error, which is used to represent the difference between the set value and the actual value, and K p , K i , K d are the proportional, integral and differential coefficients respectively, and t is the time.

5. A dual-antenna clock synchronization timing system based on UWB technology, based on the method according to any one of claims 1 to 4, characterized in that: include: A signal synchronization module is used to receive the GPS pulse-per-second signal using the master base station and send a UWB synchronization signal to the slave base station; The time difference acquisition module is used to use the dual UWB communication chips in the slave base station for clock synchronization, to receive the UWB synchronization signal sent by the master base station, to forward the UWB synchronization signal to the indoor terminal device, and to use the UWB communication chip to obtain the timestamp of the moment of sending and receiving the UWB synchronization signal, and to calculate the difference between the timestamps to obtain the time difference; The system control module is used to determine the phase information of the delay or lag of the UWB synchronization signal forwarded from the base station based on the time difference, and convert the phase information into voltage information through a DAC, perform frequency control on the temperature compensated crystal oscillator, and adjust the phase of the sent UWB synchronization signal through frequency conversion, thereby forming feedback and controlling the phase difference between the forwarded and received UWB synchronization signals to be within the error setting range.

6. An electronic device, characterized in that: It comprises a memory and a processor, the memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to execute the dual-antenna clock synchronization timing method based on UWB technology according to any one of claims 1-4.

7. A computer-readable storage medium, characterized in that: The device stores a computer program, which, when executed by a processor, implements a dual-antenna clock synchronization timing method based on UWB technology as described in any one of claims 1 to 4.

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