Pointer updating method and device based on FPGA

Abstract

The present application discloses an FPGA-based pointer update method, which includes: setting a pointer pool, wherein the pointers in the pointer pool point to the addresses of the memory; setting a dynamic pointer chain, wherein the dynamic pointer chain includes a head pointer and a tail pointer, wherein the head pointer and the tail pointer are continuous pointers, and the tail pointer is a moving pointer, and the tail pointer is moved based on a preset time interval to update the dynamic pointer chain, wherein the pointers in the dynamic pointer chain point to the addresses of the memory; responding to a new pointer request instruction, determining whether there is an idle pointer in the pointer pool, and if so, outputting an idle pointer as a new pointer; if not, using the head pointer in the dynamic pointer chain as the new pointer, and adding 1 to the head pointer; responding to a pointer recovery instruction, determining whether the recovered pointer is in the dynamic pointer chain, and if so, discarding the recovered pointer, otherwise pushing the recovered pointer into the pointer pool. The present application can improve the utilization rate of the memory.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a pointer updating method, apparatus, network device, and computer-readable storage medium based on FPGA. Background Art

[0002] A Field-Programmable Gate Array (FPGA) chip is a commonly used digital communication baseband chip. During FPGA design, pointers are often used to improve the utilization rate of the FPGA's random-access memory (RAM).

[0003] In a related technical solution, a pointer pool is set up with an initial number of m pointers in the pointer pool. When the FPGA writes data to the RAM, it extracts a pointer value from the pointer pool and obtains the RAM write address based on the pointer value to complete the RAM write operation. When the FPGA completes reading data from the RAM, it performs a pointer recovery operation and pushes the corresponding read address back into the pointer pool. In actual use, pointers may be lost or not effectively recovered. For example, when a service is deleted, the data in the RAM address corresponding to the service is no longer needed, that is, the data will not be read out later, resulting in the RAM address being occupied, and the pointer cannot be recovered. Alternatively, when the FPGA executes a read RAM command, the read command is lost due to a bug, resulting in the inability to read the corresponding data, resulting in the pointer being unable to be recovered. Or, the RAM data is read, but the pointer is not pushed back into the pointer pool due to a program bug, resulting in the pointer being lost. In these situations, the pointer is lost, making it impossible to effectively recover the pointer, thereby reducing the utilization rate of the RAM and even potentially causing all the pointers in the pointer pool to be lost, causing the entire system design to freeze. Summary of the Invention

[0004] The purpose of this application is to provide a pointer updating method based on FPGA, which can effectively recycle pointers and improve memory utilization.

[0005] Based on the above objectives, the present application provides a pointer updating method based on FPGA, which includes:

[0006] Set up a pointer pool, where the pointers in the pointer pool point to the addresses of the memory;

[0007] Setting a dynamic pointer chain, the dynamic pointer chain including a head pointer and a tail pointer, the head pointer and the tail pointer being continuous pointers, the tail pointer being a moving pointer, the tail pointer being moved based on a preset time interval to update the dynamic pointer chain, the pointers in the dynamic pointer chain pointing to addresses of the memory;

[0008] In response to a new pointer request instruction, determine whether there is an idle pointer in the pointer pool. If so, output a free pointer as a new pointer; if not, use the head pointer in the dynamic pointer chain as the new pointer and increment the head pointer by 1.

[0009] In response to a pointer recycling instruction, it is determined whether the recycled pointer is in the dynamic pointer chain. If so, the recycled pointer is discarded; otherwise, the recycled pointer is pushed into the pointer pool.

[0010] Furthermore, the number of addresses in the memory is m, the initial value of the number of pointers in the dynamic pointer chain is n, the number of pointers in the pointer pool is mn, the pointers in the pointer pool are 0 to mn-1, where n is less than or equal to m, the head pointer of the dynamic pointer chain is mn, and the tail pointer of the dynamic pointer chain is m-1.

[0011] Furthermore, when n is less than m, after the system is powered on, dynamic adjustment is performed on the dynamic pointer chain. The steps of dynamic adjustment include:

[0012] In the first clock cycle, the tail pointer is incremented by 1 and becomes 0;

[0013] Every x clock cycles, the tail pointer is incremented from 0 to 1 until the tail pointer is mn-1.

[0014] Furthermore, in response to a new pointer request instruction, the method includes:

[0015] In response to a write data instruction of the memory, output a new pointer request instruction;

[0016] After obtaining the new pointer, the memory write operation is performed using the new pointer.

[0017] Furthermore, in response to a pointer reclaim instruction, the method includes:

[0018] In response to a data read instruction of the memory, performing a read operation on the memory;

[0019] When the read operation is completed, a pointer recovery instruction is output, and the pointer recovery instruction includes the read address of the read operation.

[0020] Furthermore, the method further comprises:

[0021] At every preset first clock cycle, it is determined whether the tail pointer in the dynamic pointer chain is incremented by 1. The determination steps are as follows:

[0022] If the tail pointer is less than the head pointer, the tail pointer is increased by 1, otherwise the tail pointer remains unchanged.

[0023] Furthermore, the method further comprises:

[0024] A new pointer request instruction is output every preset second clock cycle, and the first clock cycle is greater than the second clock cycle.

[0025] Based on the above objectives, the present application provides an FPGA-based pointer updating device, which includes:

[0026] The storage module is used to set a pointer pool, wherein the pointers in the pointer pool point to the addresses of the memory;

[0027] A dynamic pointer module is used to set up a dynamic pointer chain, the dynamic pointer chain includes a head pointer and a tail pointer, the head pointer and the tail pointer are continuous pointers, the tail pointer is a moving pointer, the tail pointer is moved based on a preset time interval to update the dynamic pointer chain, and the pointers in the dynamic pointer chain point to the addresses of the memory;

[0028] An update module is configured to respond to a new pointer request instruction, determine whether there is an idle pointer in the pointer pool, and if so, output an idle pointer as a new pointer; if not, use the head pointer in the dynamic pointer chain as the new pointer and increment the head pointer by 1;

[0029] The recycling module is used to respond to a pointer recycling instruction, determine whether the recycled pointer is in the dynamic pointer chain, if so, discard the recycled pointer, otherwise push the recycled pointer into the pointer pool.

[0030] Based on the above purpose, the present application provides a network device, including the FPGA-based pointer updating device as described above.

[0031] Based on the above purpose, the present application provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0032] The present application sets up a pointer pool and a dynamic pointer chain, and dynamically updates the dynamic pointer chain. When all pointers in the pointer pool are occupied or a pointer is lost, a new pointer is taken from the dynamic pointer chain. The dynamic pointer chain can replenish the pointer. When the pointer is recycled, the pointer is pushed back into the pointer pool. This cycle allows the pointers in the pointer pool to be updated and replaced at a certain speed. Even if the pointer is lost, it can be replenished, thereby solving the technical problem that the pointer cannot be recycled after being lost, and improving the resource utilization of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 1 is a schematic diagram of a first flow chart of a pointer updating method based on FPGA provided in an embodiment of the present application;

[0034] Figure 2 2 is a schematic diagram of a second flow chart of an FPGA-based pointer updating method provided in an embodiment of the present application;

[0035] Figure 3 3 is a schematic diagram of a third flow chart of an FPGA-based pointer updating method provided in an embodiment of the present application;

[0036] Figure 4 This is a system block diagram of an FPGA-based pointer updating device provided in an embodiment of the present application;

[0037] Figure 5 This is a system block diagram of a network device provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] The present application will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings, but these embodiments do not limit the present application. Structural, methodological, or functional changes made by ordinary technicians in this field based on these embodiments are included in the scope of protection of the present application.

[0039] Please refer to Figure 1 , an embodiment of the present application provides a pointer update method based on FPGA, the method comprising the steps of:

[0040] Step S101: Set a pointer pool, where pointers in the pointer pool point to addresses of memory.

[0041] Exemplarily, the pointer pool may be a FIFO, the memory may be a RAM, and the pointers in the pointer pool point to addresses of the memory, that is, the pointer values ​​in the pointer pool correspond to respective storage addresses of the memory.

[0042] Step S102: Set a dynamic pointer chain, which includes a head pointer and a tail pointer. The head pointer and the tail pointer are continuous pointers, and the tail pointer is a moving pointer. The tail pointer is moved based on a preset time interval to update the dynamic pointer chain. The pointers in the dynamic pointer chain point to the addresses of the memory.

[0043] A dynamic pointer chain is constructed. The dynamic pointer chain includes a head pointer and a tail pointer. The pointers in the dynamic pointer chain point to memory addresses. The head pointer and the tail pointer are continuous pointers, and the tail pointer is a movable pointer. Dynamic adjustment of the tail pointer causes dynamic adjustment of the pointers in the dynamic pointer chain. The system adjusts the tail pointer based on a preset time interval to dynamically update the dynamic pointer chain.

[0044] For example, an initial dynamic pointer chain is set, with the head pointer of the initial dynamic pointer chain pointing to a memory address. This address can be set according to actual needs. Based on the initial head pointer and the number of pointers in the dynamic pointer chain, a tail pointer is set. The system updates the tail pointer at regular intervals. Because the pointers in the dynamic pointer chain are continuous, the tail pointer is incremented by 1, increasing the number of pointers in the dynamic pointer chain. This dynamically updates the pointers in the dynamic pointer chain so that all pointers in the dynamic pointer chain point to memory addresses.

[0045] For example, a dynamic pointer chain can be designed using registers. Because the pointer values ​​in a dynamic pointer chain are continuous, only registers for the head pointer and the tail pointer are designed. Specifically, the first register stores the head pointer, and the second register stores the tail pointer. For pointers between the head and tail pointers, the corresponding pointers can be identified sequentially based on the head pointer. For example, the first pointer after the head pointer is the head pointer plus 1, the second pointer is the head pointer plus 2, and so on. Based on this implementation, the register approach is adopted instead of the FIFO approach, saving storage space during the FPGA design process.

[0046] Step S103: In response to a new pointer request instruction, determine whether there is an idle pointer in the pointer pool. If so, output an idle pointer as a new pointer; if not, use the head pointer in the dynamic pointer chain as the new pointer, and increase the head pointer by 1.

[0047] After receiving the new pointer request instruction, it is determined whether there is an idle pointer in the pointer pool. If there is an idle pointer in the pointer pool, an idle pointer is popped out from the pointer pool and used as a new pointer, and the new pointer serves as the address of the memory. It is understandable that when there are multiple idle pointers in the pointer pool, any idle pointer can be popped out from the pointer pool and used as a new pointer. If there are no idle pointers in the pointer pool, that is, all the pointers in the pointer pool are occupied, it is necessary to obtain a new pointer from the dynamic pointer chain. As can be seen from the above, the pointers in the dynamic pointer chain also point to the address of the memory, that is, the pointers in the dynamic pointer chain can be used as the address of the memory, and after the pointers in the dynamic pointer chain are frequently dynamically updated, their pointers all point to the address of the memory, so a new pointer value can be obtained from the dynamic pointer chain. Therefore, if there is no idle pointer in the pointer pool, the head pointer in the dynamic pointer chain is used as the new pointer. After the head pointer is taken out, the head pointer is used, so it is necessary to update the head pointer in the dynamic pointer chain, that is, to increase the head pointer by 1.

[0048] Step S104: In response to a pointer recycling instruction, determine whether the recycled pointer is in the dynamic pointer chain; if so, discard the recycled pointer; otherwise, push the recycled pointer into the pointer pool.

[0049] Upon receiving a pointer recycling instruction, the pointer to be recycled is determined based on the pointer recycling instruction, and whether the recycled pointer is in the dynamic pointer chain is judged. If it is in the dynamic pointer chain, the recycled pointer is discarded. If it is not in the dynamic pointer chain, the recycled pointer is pushed back into the pointer pool, and the corresponding pointer is released back into the pointer pool.

[0050] In this embodiment, by setting up a pointer pool and a dynamic pointer chain, and dynamically updating the dynamic pointer chain, when all pointers in the pointer pool are occupied or a pointer is lost, because the pointer also exists in the dynamic pointer chain, a new pointer is taken from the dynamic pointer chain, and the dynamic pointer chain can replenish the pointer. When the pointer is recycled, the pointer is pushed back into the pointer pool. This cycle allows the pointers in the pointer pool to be updated and replaced at a certain speed, and even if the pointer is lost, it can be replenished, thereby solving the technical problem that the pointer cannot be recycled after being lost, and improving the resource utilization of RAM.

[0051] As an optional implementation, the number of memory addresses is m, the initial value of the number of pointers in the dynamic pointer chain is n, the number of pointers in the pointer pool is mn, and the pointers in the pointer pool range from 0 to mn-1, where n is less than or equal to m. The head pointer of the dynamic pointer chain is mn, and the tail pointer of the dynamic pointer chain is m-1. In the design of the dynamic pointer chain, the number of pointers in the dynamic pointer chain can be set to be consistent with the number of pointers in the pointer pool, that is, consistent with the number of memory addresses, and all pointers in the dynamic pointer chain also point to memory addresses. For example, the number of memory addresses is 1024, the number of pointers in the pointer pool is 1024, and the number of pointers in the dynamic pointer chain is 1024. The pointers in the pointer pool point to memory addresses, and the pointers in the dynamic pointer chain point to memory addresses.

[0052] As an optional implementation, the number of pointers in the dynamic pointer chain can be set to be inconsistent with the number of pointers in the pointer pool. That is, the initial value n of the dynamic pointer chain's pointer count is less than m. After the system is powered on, the dynamic pointer chain needs to be dynamically adjusted so that the pointers in the dynamic pointer chain point to the memory addresses. This dynamic adjustment step includes: in the first clock cycle, incrementing the tail pointer by 1, causing the tail pointer to become 0. Every x clock cycles, the tail pointer is incremented from 0 by 1 until the tail pointer reaches mn-1. For example, the system is initially configured as follows: the number of memory addresses is 1024. Assuming the addresses are set from 0 to 1023, the number of pointers in the pointer pool is 1008, and the corresponding pointers are 0 to 1007. The initial value of the dynamic pointer chain's pointer count is 16, and the corresponding pointers in the dynamic pointer chain are 1008 to 1023, i.e., the head pointer is 1008 and the tail pointer is 1023. After the system is powered on, the dynamic pointer chain is dynamically adjusted. The adjustment process is as follows: in the first clock cycle, the tail pointer is incremented by 1, updating the tail pointer to 0. In the second clock cycle, the tail pointer is incremented by 1, updating the tail pointer to 1. This continues for several clock cycles. After several clock cycles, the tail pointer is updated to 1007. In other words, the pointers in the dynamic pointer chain change from 1008 to 1023 to 0 to 1007. The pointers between 1008 and 1023 are continuous, and the pointers between 0 and 1007 are continuous. Therefore, after dynamic adjustment, all pointers in the dynamic pointer chain can execute memory addresses. It can be understood that using the FPGA system clock as the clock during the dynamic adjustment process makes the dynamic adjustment process relatively quick.

[0053] As an optional implementation, such as Figure 2 As shown, in response to a new pointer request instruction, it is determined whether there is an idle pointer in the pointer pool. If so, an idle pointer is output as a new pointer; if not, the head pointer in the dynamic pointer chain is used as the new pointer, and the head pointer is incremented by 1, including:

[0054] Step S201: In response to a write data instruction from the memory, output a new pointer request instruction;

[0055] Step S202: After obtaining the new pointer, perform a write operation on the memory using the new pointer.

[0056] When data needs to be written to memory, the FPGA executes the write operation, outputting a write instruction to the memory. Writing data to the memory requires obtaining a pointer, so a new pointer request instruction is output based on the write instruction. Based on this new pointer request instruction, the FPGA determines whether there is a free pointer in the pointer pool. If so, it outputs a free pointer as the new pointer. If not, the head pointer in the dynamic pointer chain is used as the new pointer, and the head pointer is incremented by 1. After obtaining the new pointer, the memory write operation is executed with the new pointer, completing the memory write function.

[0057] As an optional implementation, such as Figure 3 As shown, in response to a pointer recovery instruction, the method includes:

[0058] Step S301: In response to a read data instruction of a memory, a read operation is performed on the memory;

[0059] Step S302: After the read operation is completed, a pointer recovery instruction is output, where the pointer recovery instruction includes the read address of the read operation.

[0060] When data needs to be read from memory, the FPGA executes a memory read operation, outputting a memory read instruction to retrieve the data. Once the read operation is complete, it outputs a pointer recovery instruction, which includes the read address of the read operation. Based on the read address of the pointer recovery instruction, the FPGA determines the pointer to be recovered and checks whether the recovered pointer is in the dynamic pointer chain. If so, the recovered pointer is discarded; otherwise, it is pushed into the pointer pool.

[0061] As an optional implementation, if not, the head pointer in the dynamic pointer chain is used as the new pointer, and the head pointer is incremented by 1. This includes: at every preset first clock cycle, determining whether the tail pointer in the dynamic pointer chain is incremented by 1, the determination step being: if the tail pointer is less than the head pointer, the tail pointer is incremented by 1; otherwise, the tail pointer remains unchanged. A new pointer request instruction is output every preset second clock cycle, where the first clock cycle is greater than the second clock cycle. After the head pointer in the dynamic pointer chain is updated, it is necessary to determine whether the tail pointer in the dynamic pointer chain is updated. At every first clock cycle, the tail pointer update is determined; if the tail pointer is less than the head pointer, the tail pointer is incremented by 1; otherwise, the tail pointer remains unchanged. For example, if the second clock cycle is set to 2 system clock cycles, the second clock cycle is set to 4 system clock cycles. A new pointer retrieval rate is also set, with a new pointer request instruction output every preset second clock cycle, where the first clock cycle is greater than the second clock cycle. In this embodiment, the dynamic pointer chain update rate is less than the new pointer retrieval rate, so that the pointer flow rate is greater than the pointer replacement rate, thereby ensuring that pointers in the pointer pool are replaced at a certain rate.

[0062] like Figure 4 As shown, the present application provides a pointer updating device based on FPGA, which includes:

[0063] The storage module 401 is used to set a pointer pool, wherein the pointers in the pointer pool point to the addresses of the memory;

[0064] A dynamic pointer module 402 is configured to set up a dynamic pointer chain, wherein the dynamic pointer chain includes a head pointer and a tail pointer, wherein the head pointer and the tail pointer are continuous pointers, and the tail pointer is a moving pointer. The tail pointer is moved based on a preset time interval to update the dynamic pointer chain, and the pointers in the dynamic pointer chain point to addresses in the memory;

[0065] The pointer request module 403 is used to respond to a new pointer request instruction, determine whether there is an idle pointer in the pointer pool, and if so, output an idle pointer as a new pointer; if not, use the head pointer in the dynamic pointer chain as the new pointer and increment the head pointer by 1;

[0066] The pointer recycling module 404 is used to respond to a pointer recycling instruction and determine whether the recycled pointer is in the dynamic pointer chain. If so, the recycled pointer is discarded; otherwise, the recycled pointer is pushed into the pointer pool.

[0067] Optionally, the number of memory addresses is m, the initial value of the number of pointers in the dynamic pointer chain is n, the number of pointers in the pointer pool is mn, and the pointers in the pointer pool range from 0 to mn-1, where n is less than or equal to m. The head pointer of the dynamic pointer chain is mn, and the tail pointer of the dynamic pointer chain is m-1. When n is less than m, after the system is powered on, the dynamic pointer module 402 dynamically adjusts the dynamic pointer chain, including: in the first clock cycle, incrementing the tail pointer by 1, so that the tail pointer becomes 0; and every x clock cycles, incrementing the tail pointer from 0 by 1 until the tail pointer reaches mn-1.

[0068] Optionally, the pointer request module 403 is specifically configured to:

[0069] In response to a write data instruction of the memory, output a new pointer request instruction;

[0070] After obtaining the new pointer, the memory write operation is performed using the new pointer.

[0071] Optionally, the pointer recovery module 404 is specifically configured to:

[0072] In response to a data read instruction of the memory, performing a read operation on the memory;

[0073] When the read operation is completed, a pointer recovery instruction is output, and the pointer recovery instruction includes the read address of the read operation.

[0074] Optionally, the pointer recovery module 404 is specifically configured to:

[0075] At every preset first clock cycle, it is determined whether the tail pointer in the dynamic pointer chain is incremented by 1. The determination step is: if the tail pointer is smaller than the head pointer, the tail pointer is incremented by 1; otherwise, the tail pointer remains unchanged.

[0076] Optionally, the pointer request module 403 is specifically configured to:

[0077] A new pointer request instruction is output every second preset clock cycle, and the first clock cycle is greater than the second clock cycle.

[0078] The embodiment of the present application further provides a network device, which includes the above-mentioned FPGA-based pointer updating device, for example, the network device includes Figure 4 The FPGA-based pointer update device shown. The network device can be any network device used for service forwarding in a communication network. For example, based on device type, the network device can be a switch, router, etc. Based on device deployment location, the network device can be an edge network device, a core network device, or a network device in a data center.

[0079] As an example, see Figure 5 , which shows a schematic diagram of the structure of a network device provided by an embodiment of the present application. The network device includes an FPGA-based pointer update device 501, a communication interface 502, a processor 503, a memory 504, and a bus 505. The processor 503, the memory 504, the communication interface 502, and the FPGA-based pointer update device 501 are connected to each other through the bus 505. Figure 5 The connection method between the processor 503, memory 504, communication interface 502 and FPGA-based pointer update device 501 shown is merely exemplary. During implementation, the processor 503, memory 504, communication interface 502 and FPGA-based pointer update device 501 may also be connected to each other in communication using other connection methods besides the bus 505.

[0080] The memory 504 can be used to store computer programs, which may include instructions and data. In embodiments of the present application, the memory 504 may be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, optical storage, and registers. The memory 504 may include a hard disk and / or memory.

[0081] Processor 503 may be a general-purpose processor. A general-purpose processor may be a processor that performs specific steps and / or operations by reading and executing a computer program stored in a memory (e.g., memory 504). The general-purpose processor may use data stored in the memory (e.g., memory 504) during the execution of the steps and / or operations. A general-purpose processor may be, for example, but not limited to, a central processing unit (CPU). In addition, processor 503 may also be a special-purpose processor. A special-purpose processor may be a processor specially designed to perform specific steps and / or operations. A special-purpose processor may be, for example, but not limited to, an ASIC and an FPGA. In addition, processor 503 may also be a combination of multiple processors, such as a multi-core processor.

[0082] The communication interface 502 may include input / output (I / O) interfaces, physical interfaces, and logical interfaces, etc., for interconnecting components within the network device, as well as interfaces for interconnecting the network device with other devices (e.g., network devices). A physical interface may be a Gigabit Ethernet (GE) interface, which can be used to interconnect the network device with other devices. A logical interface is an interface within the network device, which can be used to interconnect components within the network device. It is easy to understand that the communication interface 502 can be used for communication between the network device and other devices. For example, the communication interface 802 is used to send and receive messages between the network device and other devices.

[0083] The bus 505 may be any type of communication bus for interconnecting the processor 503 , the memory 504 , the communication interface 502 and the FPGA-based pointer updating device 501 , such as a system bus.

[0084] The pointer updating device 501 based on FPGA can be any possible chip such as ASIC chip, FPGA chip, etc. The structure of the pointer updating device 501 based on FPGA can refer to Figure 1 The illustrated embodiments are not described here in detail. The interconnection between any one of the processor 503, memory 504 and communication interface 502 and the FPGA-based pointer update device 501 may specifically refer to the interconnection between any one of the devices and the device in the FPGA-based pointer update device 501. In some embodiments, the above-mentioned processor 503, memory 504 and communication interface 502 may all be integrated on the FPGA-based pointer update device 501, or the above-mentioned processor 503, memory 504 and communication interface 502 may be respectively arranged on chips independent of each other, or may be at least partially or completely arranged on the same chip. Whether each device is independently arranged on different chips or integrated on one or more chips often depends on the needs of product design. This application does not limit the specific implementation form of the above-mentioned devices.

[0085] Figure 5 The network device shown is merely exemplary. During implementation, the network device may further include other components, which are not listed here one by one.

[0086] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product, and the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, a computer, a server or a data center to another website, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrations. Available media can be magnetic media (e.g., floppy disk, hard disk, tape), optical media, or semiconductor media (e.g., solid-state hard disk), etc.

[0087] The embodiments disclosed in the present application further provide a computer-readable storage medium, which stores instructions. When the computer-readable storage medium is run on a computer, the computer executes the FPGA-based pointer update method described in any one of the above embodiments.

[0088] Although the preferred embodiments of the present application have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the application as disclosed in the accompanying claims.

Claims

1. A pointer update method based on FPGA, characterized in that: The method comprises: Setting a pointer pool, wherein the pointers in the pointer pool point to addresses of the memory; Setting a dynamic pointer chain, the dynamic pointer chain including a head pointer and a tail pointer, the head pointer and the tail pointer being continuous pointers, the tail pointer being a moving pointer, the tail pointer being moved based on a preset time interval to update the dynamic pointer chain, the pointers in the dynamic pointer chain pointing to the addresses of the memory; In response to a new pointer request instruction, determine whether there is an idle pointer in the pointer pool, and if so, output a free pointer as a new pointer; if not, use the head pointer in the dynamic pointer chain as the new pointer, and increment the head pointer by 1; In response to a pointer recycling instruction, it is determined whether the recycled pointer is in the dynamic pointer chain. If so, the recycled pointer is discarded; otherwise, the recycled pointer is pushed into the pointer pool.

2. The pointer updating method based on FPGA according to claim 1, characterized in that: The number of addresses of the memory is m, the initial value of the number of pointers in the dynamic pointer chain is n, the number of pointers in the pointer pool is mn, the pointers in the pointer pool are 0 to mn-1, where n is less than or equal to m, the head pointer of the dynamic pointer chain is mn, and the tail pointer of the dynamic pointer chain is m-1.

3. The pointer updating method based on FPGA according to claim 2, characterized in that: When n is less than m, after the system is powered on, dynamic adjustment is performed on the dynamic pointer chain, and the steps of dynamic adjustment include: In the first clock cycle, the tail pointer is incremented by 1, and the tail pointer becomes 0; Every x clock cycles, the tail pointer is incremented from 0 by 1 until the tail pointer reaches mn-1.

4. The pointer updating method based on FPGA according to claim 1, wherein: The step of responding to a new pointer request instruction includes: In response to a write data instruction from the memory, output the new pointer request instruction; After obtaining the new pointer, a write operation of the memory is performed using the new pointer.

5. The pointer updating method based on FPGA according to claim 4, characterized in that: The step of responding to a pointer recovery instruction includes: In response to a data read instruction of the memory, performing a read operation on the memory; When the read operation is completed, a pointer recovery instruction is output, where the pointer recovery instruction includes the read address of the read operation.

6. The pointer updating method based on FPGA according to claim 1, wherein: The method further comprises: At every preset first clock cycle, it is determined whether the tail pointer in the dynamic pointer chain is incremented by 1, wherein the determination step is as follows: If the tail pointer is smaller than the head pointer, the tail pointer is incremented by 1; otherwise, the tail pointer remains unchanged.

7. The pointer updating method based on FPGA according to claim 6, characterized in that: The method further comprises: The new pointer request instruction is output every preset second clock cycle, and the first clock cycle is greater than the second clock cycle.

8. A pointer updating device based on FPGA, characterized in that: The device comprises: A storage module is used to set a pointer pool, wherein the pointers in the pointer pool point to the addresses of the memory; a dynamic pointer module, configured to set a dynamic pointer chain, the dynamic pointer chain including a head pointer and a tail pointer, the head pointer and the tail pointer being continuous pointers, the tail pointer being a moving pointer, the tail pointer being moved based on a preset time interval to update the dynamic pointer chain, the pointers in the dynamic pointer chain pointing to addresses of the memory; an update module, configured to, in response to a new pointer request instruction, determine whether there is an idle pointer in the pointer pool, and if so, output an idle pointer as a new pointer; if not, use the head pointer in the dynamic pointer chain as the new pointer, and increment the head pointer by 1; The recycling module is used to respond to a pointer recycling instruction, determine whether the recycled pointer is in the dynamic pointer chain, and if so, discard the recycled pointer; otherwise, push the recycled pointer into the pointer pool.

9. A network device, characterized in that: It includes the FPGA-based pointer updating device as described in claim 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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