A method for scheduling a flash queue and related apparatus

Abstract

The embodiment of the application provides a method for scheduling a flash queue, which is used for improving the efficiency of a coprocessor in analyzing message instructions and the efficiency of scheduling the flash queue. The method comprises the following steps: obtaining a target hardware processing queue and a target flash queue module which are in communication connection with a target coprocessor; if the usage rate of the storage space of any hardware processing queue in the target hardware processing queue reaches a preset threshold, determining whether all the schedulable flash queues in the target flash queue module are in a working state; if yes, determining whether there is an unanalyzed message instruction in the message queue of the target coprocessor; if there is an unanalyzed message instruction in the message queue of the target coprocessor, performing an analysis operation on the unanalyzed message instruction to obtain an analyzed message instruction; and storing the analyzed message instruction in a preset position.

Description

Technical Field

[0001] This invention relates to the field of hard disk data processing technology, and in particular to a method and related apparatus for scheduling flash queues. Background Technology

[0002] Nand Flash (hereinafter referred to as NAND) is a non-volatile semiconductor storage medium. Its basic storage unit is a double-layer floating-gate MOSFET similar to NMOS. Solid-state drives (SSDs) are storage devices that use NAND as the storage medium. Their main components include NAND, a controller chip, and DRAM. An important function of the controller chip is to act as a driver for the NAND chip to perform storage operations, including erasing, writing, and reading.

[0003] To improve the overall write and read speeds of solid-state drives (SSDs), multiple channels typically run in parallel under the controller. Each channel carries multiple die regions, and these die regions share a common control bus. When a die region finishes sending commands / data, it enters a Busy state and cannot execute any more commands. However, it can still send commands / data to other die regions via the bus. Once all other die regions have finished sending commands, the system can check the previously Busy die region to confirm its completion. If it has, it can continue sending subsequent commands to that die region. This fully utilizes the parallelism of die regions to increase bus bandwidth and improve overall performance.

[0004] To improve the overall write / read speed of NAND flash memory, blocks within NAND flash are typically distributed across multiple planes. Currently, mainstream NAND flash memory typically uses 2, 4, 6, or 8 planes. Taking a 4-plane NAND flash memory as an example, blocks 0 / 4 / 8 / 12… are in plane0, blocks 1 / 5 / 9 / 13… are in plane1, blocks 2 / 6 / 10 / 14… are in plane2, and blocks 3 / 7 / 11 / 15… are in plane3. NAND flash memory supports parallel operations across multiple planes; for example, blocks 0, 1, 6, and 11 can simultaneously perform erase, write, or read operations.

[0005] For batch / sequential reads, multiple planes can typically be sent in parallel to improve read bandwidth. For random reads, however, because the time of receiving the read command and the plane position are random, it's usually impossible to concatenate multiple planes for parallel read commands. To improve random read bandwidth, more and more Nand arrays support asynchronous plane read parallel operations: for example, when Plane A issues a Read command and the Nand array begins its Read operation, Plane A cannot continue executing other commands, but other Planes can continue issuing Read commands, and Read command operations from different Planes can be executed in parallel.

[0006] As NAND flash memory performance improves and its functionality becomes more powerful and complex, fixed controller chips are finding it increasingly difficult to meet the flexible control requirements of NAND. Some controllers are beginning to add coprocessor CPUs (S-CPUs) to optimize the flexibility of NAND operation through a combination of hardware and software. Controllers typically add several S-CPUs, each responsible for processing commands from one or more processing nodes (CHs). The upper-layer driver sends commands (SQs) to the S-CPUs, which further parse the commands into a sequence of hardware instructions and send them to the hardware processing queue (JOB FIFO) for sequential execution.

[0007] For ease of understanding, Figure 1 A schematic diagram of a solid-state drive (SSD) including a coprocessor S-CPU is given. Figure 1 In this context, the main processor (CPU) and the coprocessor (S-CPU) belong to different systems. The SQ (Signal Query) cannot be directly transmitted; it needs to be sent through a hardware module. For ease of understanding, Figure 2 A schematic diagram is given illustrating the process of SQ being transferred and parsed between the main processor and the coprocessor. However, in a continuous read scenario... Figure 3 A schematic diagram of the S-CPU parsing SQ process is given, in which, Figure 3 The green area represents the time taken by the coprocessor S-CPU to perform other operations when the hardware processing queue JOB FIFO space is insufficient. Therefore, according to... Figure 2 As shown in the parsing flowchart, the space of the JOB FIFO is insufficient, which means that the computing power of the S-CPU cannot be fully used to parse the SQ, thus reducing the data processing performance of the solid-state drive. Summary of the Invention

[0008] This invention provides a method for scheduling a flash queue. In a solid-state drive (SSD), when the storage space of the hardware processing queue communicating with the target coprocessor is less than the storage space of the flash queue module communicating with the target processor, the coprocessor pre-parses the unparsed message instructions in the coprocessor message queue to obtain a parsed hardware instruction sequence. The parsed message instructions are then stored at a preset location. This allows the coprocessor to directly read the parsed message instructions from the preset location when the JOB FIFO space is sufficient. Compared to existing technologies, this saves the time required to parse message instructions in the coprocessor message queue when the JOB FIFO space is sufficient, thereby improving the efficiency of the coprocessor in parsing message instructions and correspondingly improving the data processing performance of the SSD.

[0009] A first aspect of this application provides a method for scheduling a flash queue, applied to a coprocessor in a solid-state drive (SSD). The SSD includes at least one coprocessor, a hardware processing queue and a flash queue module communicatively connected to the coprocessor, wherein the flash queue module includes at least one flash queue, and the storage space of the hardware processing queue communicatively connected to a target coprocessor is smaller than the storage space of the flash queue module communicatively connected to the target coprocessor. The target coprocessor is any one of the at least one coprocessor. The method includes:

[0010] Acquire the target hardware processing queue and target flash queue module that are communicatively connected to the target coprocessor;

[0011] If the storage space utilization rate of any hardware processing queue in the target hardware processing queue reaches a preset threshold, then it is determined whether all schedulable flash queues in the target flash queue module are in working state.

[0012] If all schedulable flash queues in the target flash queue module are in a working state, then determine whether there are any unparsed message instructions in the message queue of the target coprocessor.

[0013] If there are unparsed message instructions in the message queue of the target coprocessor, then a parsing operation is performed on the unparsed message instructions to obtain parsed message instructions;

[0014] The parsed message instruction is stored in a preset location.

[0015] Preferably, the solid-state drive further includes a main processor, and the method further includes:

[0016] If the target flash queue module has an idle flash queue, and the idle flash queue contains a message instruction sent by the main processor, the message instruction is stored in the message queue of the target coprocessor, and the idle flash queue is updated to be in a working state.

[0017] Preferably, the solid-state drive further includes a hardware processing module communicatively connected to the hardware processing queue, and the method further includes:

[0018] If the utilization rate of the storage space of any hardware processing queue in the target hardware processing queue does not reach the preset threshold, then it is determined whether there is a parsed message instruction at the preset position.

[0019] If a parsed message instruction is present at the preset location, then the parsed message instruction is retrieved from the preset location.

[0020] The parsed message instruction is sent to the corresponding target hardware processing queue, so that the target hardware processing queue sends the parsed message instruction to the corresponding hardware processing module for processing.

[0021] Preferably, the method further includes:

[0022] If no parsed message instruction is found at the preset position, it is determined whether there is an unparsed message instruction in the message queue of the target coprocessor.

[0023] If there are unparsed message instructions in the message queue of the target coprocessor, then the unparsed message instructions are parsed to obtain the parsed message instructions;

[0024] The parsed message instruction is sent to the corresponding hardware processing queue, so that the hardware processing queue sends the parsed message instruction to the corresponding hardware processing module for processing.

[0025] Preferably, the target coprocessor is provided with multiple message queues with priorities;

[0026] The step of determining whether there are unparsed message instructions in the message queue of the target coprocessor includes:

[0027] Based on the priority of multiple message queues, determine whether there are any unparsed message instructions in each of the multiple message queues;

[0028] If there are unparsed message instructions in the message queue of the target coprocessor, then a parsing operation is performed on the unparsed message instructions to obtain parsed message instructions, including:

[0029] If there are unparsed message instructions in multiple message queues of the target coprocessor, then the unparsed message instructions are parsed according to the priority of the message queues to obtain the parsed message instructions.

[0030] Preferably, the solid-state drive further includes multiple NandFlash, a message queue interface, and a hardware scheduling module. The hardware scheduling module includes at least one scheduling channel. The main processor communicates with the scheduling channel through the message queue interface. Each scheduling channel communicates with a flash queue module. One or more flash queue modules communicate with one of the coprocessors. Each coprocessor communicates with one or more hardware processing queues. One or more hardware processing queues communicate with a hardware processing module.

[0031] The message instruction is used to instruct interactive operations with the plurality of NandFlashes, and the interactive operations include at least one of read operations, write operations, delete operations, and query operations.

[0032] Preferably, the NandFlash includes multiple Die regions, each Die region includes multiple Plane surfaces, each Plane surface includes multiple Blocks, and each Block includes one or more Pages;

[0033] If the NandFlash supports asynchronous plane read operations, then the read operation message instruction received by each flash queue from the main processor corresponds to the read operation instruction in each plane.

[0034] If the NandFlash does not support asynchronous plane read operations, then the read operation message instruction received by each flash queue from the main processor corresponds to the read operation instruction in each Die region.

[0035] A second aspect of this application provides a solid-state drive, comprising:

[0036] At least one coprocessor, a hardware processing queue and a flash queue module communicatively connected to the coprocessor, wherein the flash queue module includes at least one flash queue, the storage space of the hardware processing queue communicatively connected to the target coprocessor is smaller than the storage space of the flash queue module communicatively connected to the target coprocessor, and the target coprocessor is any one of the at least one coprocessor, the coprocessor comprising:

[0037] The acquisition unit is used to acquire the target hardware processing queue and the target flash queue module that are communicatively connected to the coprocessor;

[0038] The judgment unit is used to determine whether all schedulable flash queues in the target flash queue module are in working state when the utilization rate of the storage space of any hardware processing queue in the target hardware processing queue reaches a preset threshold.

[0039] The judgment unit is also used to determine whether there are unparsed message instructions in the message queue of the coprocessor when all schedulable flash queues in the target flash queue module are in working state.

[0040] The parsing unit is used to perform a parsing operation on the unparsed message instructions when there are unparsed message instructions in the message queue of the coprocessor, so as to obtain the parsed message instructions;

[0041] A storage unit is used to store the parsed message instructions at a preset location.

[0042] Preferably, the solid-state drive further includes a main processor, and the storage unit is further used for:

[0043] If the target flash queue module has an idle flash queue, and the idle flash queue contains a message instruction sent by the main processor, the message instruction is stored in the message queue of the target coprocessor, and the idle flash queue is updated to be in a working state.

[0044] Preferably, the solid-state drive further includes a hardware processing module communicatively connected to the hardware processing queue, and the judgment unit is further configured to:

[0045] If the utilization rate of the storage space of any hardware processing queue in the target hardware processing queue does not reach the preset threshold, then it is determined whether there is a parsed message instruction at the preset position.

[0046] The acquisition unit is further configured to:

[0047] If a parsed message instruction is present at the preset location, then the parsed message instruction is retrieved from the preset location.

[0048] The coprocessor also includes:

[0049] The sending unit is used to send the parsed message instruction to the corresponding target hardware processing queue, so that the target hardware processing queue sends the parsed message instruction to the corresponding hardware processing module for processing.

[0050] Preferably, the determining unit is further configured to:

[0051] If no parsed message instruction is found at the preset position, it is determined whether there is an unparsed message instruction in the message queue of the target coprocessor.

[0052] The parsing unit is also used for:

[0053] If there are unparsed message instructions in the message queue of the target coprocessor, then the unparsed message instructions are parsed to obtain the parsed message instructions;

[0054] The transmitting unit is further configured to:

[0055] The parsed message instruction is sent to the corresponding hardware processing queue, so that the hardware processing queue sends the parsed message instruction to the corresponding hardware processing module for processing.

[0056] Preferably, the target coprocessor is provided with multiple message queues with priorities;

[0057] The judgment unit is specifically used for:

[0058] Based on the priority of multiple message queues, determine whether there are any unparsed message instructions in each of the multiple message queues;

[0059] The parsing unit is specifically used for:

[0060] If there are unparsed message instructions in multiple message queues of the target coprocessor, then the unparsed message instructions are parsed according to the priority of the message queues to obtain the parsed message instructions.

[0061] Preferably, the solid-state drive further includes multiple NandFlash, a message queue interface, and a hardware scheduling module. The hardware scheduling module includes at least one scheduling channel. The main processor communicates with the scheduling channel through the message queue interface. Each scheduling channel communicates with a flash queue module. One or more flash queue modules communicate with one of the coprocessors. Each coprocessor communicates with one or more hardware processing queues. One or more hardware processing queues communicate with a hardware processing module.

[0062] The message instruction is used to instruct interactive operations with the plurality of NandFlashes, and the interactive operations include at least one of read operations, write operations, delete operations, and query operations.

[0063] Preferably, the NandFlash includes multiple Die regions, each Die region includes multiple Plane surfaces, each Plane surface includes multiple Blocks, and each Block includes one or more Pages;

[0064] If the NandFlash supports asynchronous plane read operations, then the read operation message instruction received by each flash queue from the main processor corresponds to the read operation instruction in each plane.

[0065] If the NandFlash does not support asynchronous plane read operations, then the read operation message instruction received by each flash queue from the main processor corresponds to the read operation instruction in each Die region.

[0066] A third aspect of this application provides a readable computer storage medium having a computer program stored thereon, wherein the computer program, when executed by a coprocessor, is used to implement the method for scheduling flash queues provided in the first aspect of this application.

[0067] A fourth aspect of this application provides a computer program product having a computer program stored thereon. When the computer program is executed by a coprocessor, it is used to implement the method for scheduling flash queues provided in the first aspect of this application.

[0068] As can be seen from the above technical solutions, the embodiments of the present invention have the following advantages:

[0069] In this embodiment of the application, if the utilization rate of the storage space of any hardware processing queue in the target hardware processing queue reaches a preset threshold, and all schedulable flash queues in the target flash queue module are in working state, it is determined whether there are unparsed message instructions in the message queue of the coprocessor. If there are unparsed message instructions in the message queue of the coprocessor, the unparsed message instructions are parsed in advance, and the parsed message instructions are stored in a preset location, thereby providing a technical basis for the coprocessor to quickly obtain the parsed message instructions from the preset location.

[0070] Therefore, compared with the prior art, the embodiments of this application reduce the parsing time of the coprocessor for unparsed message instructions when the utilization rate of the storage space of any hardware processing queue in the target hardware processing queue does not reach a preset threshold, thereby improving the parsing efficiency of the coprocessor for message instructions and the scheduling efficiency of the flash queue, and also improving the data processing performance of the solid-state drive. Attached Figure Description

[0071] Figure 1 This is a schematic diagram of the solid-state drive architecture in an embodiment of this application;

[0072] Figure 2 A schematic diagram illustrating the process of scheduling flash queues by coprocessors in existing technologies;

[0073] Figure 3A schematic diagram illustrating the time allocation for coprocessor scheduling flash queues in existing technologies;

[0074] Figure 4 This is a schematic diagram of one embodiment of the method for scheduling flash queues in this application;

[0075] Figure 5 This is a schematic diagram of another embodiment of the method for scheduling flash queues in this application;

[0076] Figure 6 This is a schematic diagram illustrating the time allocation for coprocessor scheduling of flash queues in an embodiment of this application;

[0077] Figure 7 This is a schematic diagram of one embodiment of the coprocessor of the solid-state drive in this application. Detailed Implementation

[0078] This invention provides a method for scheduling flash queues. In a solid-state drive (SSD), when the storage space of a hardware processing queue communicating with a target coprocessor is less than the storage space of a flash queue module communicating with the target processor, the method acquires the target hardware queue and the target flash queue module communicating with the target coprocessor. When the storage space utilization rate of any hardware queue in the target hardware queue reaches a preset threshold, and all schedulable flash queues in the target flash queue module are in a working state, the method determines whether there are unparsed message instructions in the coprocessor's message queue. If there are unparsed message instructions in the coprocessor's message queue, the coprocessor pre-parses the message instructions in the coprocessor's message queue and stores the parsed message instructions at a preset location. This ensures that when the storage space utilization rate in the hardware queue is less than the preset threshold, the pre-parsed message instructions can be directly retrieved from the preset location and sent to the hardware processing module for processing. This improves the efficiency of the coprocessor in parsing message instructions and scheduling flash queues in the SSD, thereby also improving the data processing performance of the SSD.

[0079] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0080] The terms "first," "second," "third," "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0081] Figure 1 This is a schematic diagram of the structure of a solid-state drive including an S-CPU, as provided in the background section of this application. Figure 1 In the process, the main processor CPU sends message instructions SQ through the message queue interface, and then the message instructions SQ are sent down to the flash queue module through different message channels CH in the hardware scheduling module. The flash queue module contains multiple flash queues FQ (FQ stands for Flash Queue, which is an independent execution unit queue). In the diagram, one message channel CH communicates with one flash queue module, and due to hardware resource limitations, the number of flash queues FQ in the same message channel is usually 32.

[0082] exist Figure 1 In this context, one end of the S-CPU coprocessor can communicate with one or more message channels (CH), while the other end of the S-CPU can communicate with one or more hardware queues (JOB FIFO). Figure 1 The diagram shows a JOB FIFO, which corresponds to a communication connection to a hardware processing module. The JOB FIFO stores the message instructions (SQs) parsed by the coprocessor S-CPU. The parsed SQs are then sent to the corresponding hardware processing module for processing. When parsing a message instruction (SQ), the S-CPU parses it into a sequence of hardware instructions. These parsed hardware instructions include START, DELAY, CMD, ADDR, TIME, INFO, CE_SEL, FRDATA, FWDATA, DWDATA, DRDATA, CHK, and END. Each sequence of hardware instructions parsed from an SQ begins with a START instruction and ends with an END instruction; no other SQ hardware instructions can be inserted in between.

[0083] To make it easier to understand, the following will be combined with Figure 1The process of issuing and parsing message instructions (SQ) is described. Generally, message instructions (SQ) contain CH and FQ information. Therefore, the main processor (CPU) can route message instructions (SQ) to different flash queues (FQ) in different flash queue modules through different message channels (CH). The software resources of FQ are represented by status bits to indicate the current running state. When FQ is parsing SQ, FQ is set to busy (working state). When SQ is completed, FQ is set to idle (idle state), which facilitates the coprocessor (S-CPU) to schedule the next SQ in the flash queue.

[0084] The coprocessor S-CPU has a message queue. When there is a message instruction SQ to be parsed in the flash queue and the flash queue FQ is in an idle state, the coprocessor S-CPU stores the message instruction to be parsed in the message queue and sets the idle FQ to a busy state. Then, the S-CPU parses the message instruction to be parsed into a hardware instruction sequence and stores it in the hardware queue JOB FIFO. The JOB FIFO further sends the hardware instruction sequence to the hardware processing module for processing.

[0085] Figure 2 The diagram provided in the background of this application illustrates the process of a coprocessor S-CPU scheduling a flash queue to parse message instructions SQ. Figure 2 In this process, the coprocessor S-CPU schedules the flash queue to parse the message instruction SQ as follows:

[0086] Step 1: Determine if there is an empty flash queue FQ in the flash queue of the flash module;

[0087] Step 2: If there is an idle flash queue FQ in the flash module, and there is a message instruction sent by the main processor in the idle flash queue, then the message instruction is stored in the message queue, and then the idle flash queue FQ is updated to the working state.

[0088] Step 3: If there is no free flash queue FQ in the flash queue, then further determine whether there is a message instruction SQ to be executed in the coprocessor's message queue. If there is no message instruction SQ to be executed in the coprocessor's message queue, then determine whether a message instruction in the coprocessor's message queue has been executed by the flash queue FQ. If a message instruction has been executed by the flash queue FQ, then update the status of the flash queue FQ from the working state to the idle state and return to step 1. If no message instruction in the coprocessor has been executed by the flash queue FQ, then further return to step 1.

[0089] Step 4: If there is a message instruction SQ to be executed in the coprocessor's message queue, then it is further determined whether the storage space utilization rate of the hardware queue JOB FIFO has reached a preset threshold. If the storage space utilization rate of JOB FIFO has reached the preset threshold, then it is determined whether there is a message instruction in the flash queue that has been executed. If a message instruction has been executed, then the status of the corresponding flash queue is updated to idle.

[0090] Step 5: If the storage space utilization of JOB FIFO does not reach the preset threshold, the message instruction SQ in the message queue is parsed into a hardware instruction sequence and placed into the hardware processing queue JOB FIFO.

[0091] Step 6: If no message instructions in the flash queue have been executed, return to step 1.

[0092] according to Figure 2 The diagram shown illustrates the SQ parsing process. Figure 3 A schematic diagram illustrating the S-CPU's scheduling of flash queues in a continuous read scenario is provided. Figure 3 The text omits the time spent checking the FQ status in the flash queue, whether there are pending message instructions in the message queue, the usage status of space in the JOB FIFO, and whether the message instructions SQ in the message queue have been completed. Green represents the time spent by the coprocessor S-CPU performing other operations when the JOB FIFO space is insufficient. It clearly shows that when the JOB FIFO space is insufficient, the S-CPU's computing power cannot be fully utilized to parse message instructions SQ. It should be noted that... Figure 3 The colors in the image are merely an indication of the time each part occupies, not a limitation.

[0093] Based on the problems described in the background section, the method for scheduling flash queues by a coprocessor in this application is now described. Please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is a schematic diagram of an embodiment of the method for coprocessor scheduling flash queues in this application:

[0094] Specifically, in this embodiment, the protocol processor is located in a solid-state drive (SSD). The SSD includes at least one coprocessor, and a hardware processing queue and a flash queue module communicatively connected to the coprocessor. The flash queue module includes at least one flash queue. In this embodiment, the storage space of the hardware processing queue communicatively connected to the target coprocessor is smaller than the storage space of the flash queue module communicatively connected to the target coprocessor. The target coprocessor is any one of the at least one coprocessor. Unlike existing technologies, when the coprocessor begins executing program instructions, existing technologies first execute… Figure 2Step 1 in the previous step (determining whether there is an empty flash queue FQ in the flash queue of the flash module) is executed by the coprocessor in this application according to the following process:

[0095] 401. Obtain the target hardware processing queue and target flash queue modules that are connected to the target coprocessor;

[0096] To make it easier to understand, the following will be combined with Figure 1 Explanation: In Figure 1 The application sets up multiple coprocessors (S-CPUs), and the target coprocessor in this application is any one of the multiple S-CPUs. Figure 1 In the S-CPU, there is one communication channel CH for each communication connection. However, in actual application scenarios, there can be multiple communication channels CH for each S-CPU, and one S-CPU can have multiple flash queue modules for each communication connection. However, it should be noted that the number of FQs in the same communication channel is usually limited to a maximum of 32 due to hardware limitations.

[0097] Specifically, in this embodiment of the application, it is assumed that the target protocol processor is Figure 1 S-CPU0 in this context refers to the target flash queue module and the target hardware processing queue that are connected to S-CPU0. Since the specific hardware connection relationship is recorded in the software program during the hardware connection process, the coprocessor S-CPU0 in this embodiment can read the target flash queue module and the target hardware processing queue that are connected to S-CPU0 from the software program.

[0098] 402. If the storage space utilization rate of any hardware processing queue in the target hardware processing queue reaches a preset threshold, then determine whether all schedulable flash queues in the target flash queue module are in working state. If so, then execute step 403.

[0099] If the storage space utilization rate of any hardware queue in the target hardware queue exceeds a preset threshold, it is determined whether all schedulable flash queues in the target flash queue module are in a working state.

[0100] Corresponding to step 401, if the storage space utilization rate of the JOB FIFO connected to S-CPU0 is greater than a preset threshold (assuming it is 80%, but it can also be other values), then it is determined whether the flash queues connected to S-CPU0 are all in working state.

[0101] Because the parallelism of internal operations in Nand is highest only when all schedulable flash queues in all target flash queue modules are in a working state. This allows for accurate determination of whether there are unparsed message instructions in the message queue of the target coprocessor. If there are unparsed message instructions in the message queue, they are parsed, thereby improving the efficiency of parsing unparsed message instructions in the message queue and further enhancing the data processing performance of the solid-state drive.

[0102] Specifically, when a flash queue FQ in the flash queue module receives a message instruction SQ dispatched by the main CPU, it sends the message instruction SQ to the message queue of the coprocessor S-CPU. Since each message instruction SQ carries message channel CH and flash queue FQ identification information, when the message instruction SQ is sent to the message queue of the S-CPU, the state of the FQ identified by the message instruction SQ is changed from idle to working. Only after the FQ corresponding to the message instruction has been executed can the flash queue FQ be released and its state updated from working to idle. Here, when determining whether all flash queues in the target flash queue module are in a working state, it can be determined by the corresponding flash queue status flag bit in the software program.

[0103] 403. If all schedulable flash queues in the target flash queue module are in working state, determine whether there are unparsed message instructions in the message queue of the target coprocessor. If so, execute step 404.

[0104] If all schedulable flash queues in the target flash queue module are in a working state, then it is further determined whether there are any unparsed message instructions in the coprocessor's message queue.

[0105] Specifically, corresponding to steps 401 and 402, when all schedulable flash queues in the target flash queue module connected to S-CPU0 are in working state, it is further determined whether there are unparsed message instructions in the message queue of S-CPU0. If there are unparsed message instructions in the message queue of S-CPU0, step 404 is executed.

[0106] 404. If there are unparsed message instructions in the message queue of the target coprocessor, then perform a parsing operation on the unparsed message instructions to obtain parsed message instructions;

[0107] If there are unparsed message instructions in the message queue of the target coprocessor, then a parsing operation is performed on the unparsed message instructions to obtain the parsed message instructions.

[0108] Specifically, steps 401-403 involve parsing unparsed message instructions in the message queue of S-CPU0 to obtain parsed message instructions.

[0109] Generally, when parsing message instructions, the target coprocessor parses the message instruction (SQ) into a sequence of hardware instructions. This sequence includes instructions such as START, DELAY, CMD, ADDR, TIME, INFO, CE_SEL, FRDATA, FWDATA, DWDATA, DRDATA, CHK, and END. Each SQ's resulting hardware instruction sequence begins with a START instruction and ends with an END instruction; no other SQ hardware instructions can be inserted in between.

[0110] 405. Store the parsed message instruction in a preset location.

[0111] Once the target coprocessor has parsed the unparsed message instructions in the message queue, it stores the parsed message instructions in a preset location. This ensures that when the utilization rate of the JOB FIFO, which is connected to the target coprocessor, is less than a preset threshold, the parsed message instructions are read directly from the preset location. Compared to existing technologies, this directly saves the time spent interpreting message instructions in the message queue of the target coprocessor when the utilization rate of the JOB FIFO is less than the preset threshold, thereby further improving the efficiency of the coprocessor in parsing message instructions and making full use of the computing power of the coprocessor S-CPU. In this embodiment, the preset location is the memory space of the software program, such as SRAM, DRAM, or set as a global variable.

[0112] Specifically, corresponding to steps 401-404, when S-CPU0 stores the parsed message instructions at a preset location, thereby reducing the storage space utilization of the JOB FIFO connected to S-CPU0 to a preset threshold, the coprocessor can directly read the parsed message instructions from the preset location, that is, directly read the parsed hardware instruction sequence from the preset location, and send the read hardware instruction sequence to the JOB FIFO connected to S-CPU0, so that the JOB FIFO can send the hardware instruction sequence to the hardware processing module for processing.

[0113] In this embodiment of the application, if the utilization rate of the storage space of any hardware processing queue in the target hardware processing queue reaches a preset threshold, it is determined whether all schedulable flash queues in the target flash queue module are in a working state. If all schedulable flash queues in the target flash queue module are in a working state, it is determined whether there are unparsed message instructions in the message queue of the coprocessor, and the unparsed message instructions are parsed in advance so as to store the parsed message instructions in a preset location, thereby providing a technical basis for the coprocessor to quickly obtain the parsed message instructions from the preset location.

[0114] Therefore, compared with the prior art, the embodiments of this application reduce the parsing time of the coprocessor for unparsed message instructions when the utilization rate of the storage space of any hardware processing queue in the target hardware processing queue does not reach a preset threshold. This improves the parsing efficiency of the coprocessor for message instructions and the efficiency of scheduling flash queues, and also improves the data processing performance of the solid-state drive.

[0115] based on Figure 4 In the embodiments described above, it is easy to understand that, in addition to a coprocessor and hardware processing queue and flash queue modules that are communicatively connected to the coprocessor, the solid-state drive also includes: multiple NandFlash, a main processor, a message queue interface, a hardware scheduling module and a hardware processing module, wherein the hardware scheduling module includes at least one scheduling channel.

[0116] As a specific connection relationship, in this embodiment of the application, the solid-state drive can be a main processor communicating with a scheduling channel via a message queue interface, and each scheduling channel communicating with a flash queue module, and one or more flash queue modules communicating with a coprocessor (wherein, in Figure 1 In the solid-state drive shown, a flash queue module is connected to a coprocessor. Each coprocessor is connected to one or more hardware processing queues. One or more hardware processing queues are connected to a hardware processing module. The message instructions in this embodiment are used to instruct interactive operations with multiple NandFlashes. The interactive operations include at least one of read, write, delete, and query operations.

[0117] For example, if the message instruction is a read operation instruction, it can be an instruction to read the relevant content in page 1 of NandFlash1. If the message instruction is a write operation instruction, it can be an instruction to write the relevant content in page 2 of NandFlash2. There are no specific restrictions on the relevant content here.

[0118] Furthermore, the NandFlash in this embodiment includes multiple Die regions, each Die region includes multiple Plane surfaces, each Plane surface includes multiple Block blocks, and each Block block includes one or more Pages;

[0119] When the NandFlash supports asynchronous plane read operations, the read operation message instruction received by each flash queue from the main processor corresponds to the read operation instruction in each plane; when the NandFlash does not support asynchronous plane read operations, the read operation message instruction received by each flash queue from the main processor corresponds to the read operation instruction in each die region.

[0120] This application provides a detailed description of the structure and connection relationships of the solid-state drive (SSD). The NandFlash in this application includes two modes: one that supports asynchronous Plane surface read operations and the other that does not support asynchronous Plane surface read operations, thereby improving the flexibility of the SSD read mode in this application.

[0121] Based on the solid-state drive structure described in the above embodiments, the method for coprocessor scheduling flash queues in this application embodiment will be described next. Please refer to [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic diagram of an embodiment of the method for coprocessor scheduling flash queues in this application:

[0122] 501. Obtain the target hardware processing queue and target flash queue module that are connected to the target coprocessor;

[0123] 502. If the storage space utilization rate of any hardware processing queue in the target hardware processing queue reaches a preset threshold, determine whether all schedulable flash queues in the target flash queue module are in working state. If yes, proceed to step 503; otherwise, proceed to step 506.

[0124] 503. If all schedulable flash queues in the target flash queue module are in a working state, determine whether there are any unparsed message instructions in the message queue of the target coprocessor. If yes, proceed to step 504; otherwise, return to step 501.

[0125] 504. If there are unparsed message instructions in the message queue of the coprocessor, then a parsing operation is performed on the unparsed message instructions to obtain parsed message instructions;

[0126] 505. Store the parsed message instruction in a preset location.

[0127] It should be noted that steps 501 to 505 are related to... Figure 4The examples described are similar and will not be repeated here.

[0128] 506. If there is an idle flash queue in the target flash queue module, and the idle flash queue contains a message instruction sent by the main processor, the received message instruction is stored in the message queue of the target coprocessor, and the idle flash queue is updated to the working state.

[0129] Based on step 502, if the schedulable flash queue in the target flash queue module is in an idle state, and there is a message instruction sent by the main processor in the idle flash queue, then the received message instruction is stored in the message queue of the target coprocessor, and the idle flash queue is updated to a working state.

[0130] Corresponding to the example in step 402, when the schedulable flash queue in the target flash queue module that is connected to the coprocessor S-CPU0 is in an idle state, and there is a message instruction sent by the main processor in the flash queue in the idle state, the received message instruction is stored in the message queue of S-CPU0, and the flash queue in the idle state is updated to the working state.

[0131] Furthermore, generally speaking, NandFlash consists of multiple die areas, which in turn consist of multiple planes, which in turn consist of multiple blocks, which in turn consist of one or more pages.

[0132] In batch / continuous read scenarios, multi-plane parallel read commands are usually sent to improve read bandwidth. However, for random reads, since the time of the obtained read command is random and the plane position is random, it is impossible to form a multi-plane parallel read command to be issued.

[0133] For random read scenarios, in order to improve the bandwidth of random reads, more and more NandFlash supports asynchronous plane parallel read operations. For example, when PlaneA issues a Read command and the NandFlash starts the Read operation, PlaneA cannot continue to execute other commands, but other planes can continue to issue Read commands, and the Read command operations of different planes can be executed in parallel.

[0134] When NandFlash supports asynchronous plane read operations, the read operation message instructions received by each flash queue from the main processor correspond to the read operation instructions in each plane.

[0135] When NandFlash does not support asynchronous plane read operations, the read operation message instructions received by each flash queue from the main processor correspond to the read operation instructions in each die region.

[0136] 507. If the utilization rate of the storage space of any hardware processing queue in the target hardware processing queue does not reach the preset threshold, then determine whether there is a parsed message instruction at the preset position. If yes, then execute step 508; otherwise, execute step 510.

[0137] If the storage space utilization rate of any hardware processing queue in the target hardware processing queue does not reach the preset threshold, then it is determined whether there is a parsed message instruction at the preset position.

[0138] Specifically, corresponding to Figure 4 For example, when the storage space utilization rate of the target hardware processing queue JOB FIFO connected to S-CPU0 does not reach a preset threshold, it is determined whether there is a parsed message instruction at a preset position, that is, whether there is a parsed hardware instruction sequence. If there is a parsed message instruction at the preset position, step 508 is executed.

[0139] 508. If a parsed message instruction is present at the preset location, then retrieve the parsed message instruction from the preset location.

[0140] Specifically, if a parsed message instruction is found at a preset location, the parsed message instruction is retrieved from the preset location, and step 509 is executed.

[0141] 509. Send the parsed message instruction to the corresponding target hardware processing queue, so that the target hardware processing queue will send the parsed message instruction to the corresponding hardware processing module for processing.

[0142] After the target coprocessor receives the parsed message instruction, it sends the parsed message instruction to the corresponding target hardware processing queue, so that the target hardware processing queue sends the parsed message instruction to the corresponding hardware processing module for processing.

[0143] For Figure 4 For example, after S-CPU0 receives the parsed message instruction, it sends the parsed message instruction to the hardware processing queue JOB FIFO that is connected to S-CPU0, so that the JOB FIFO sends the parsed message instruction to the corresponding hardware processing module for processing.

[0144] 510. If no parsed message instruction is found at the preset position, determine whether there is an unparsed message instruction in the message queue of the target coprocessor. If yes, proceed to step 511; otherwise, return to step 501.

[0145] If no parsed message instruction is found at the preset location, the target coprocessor further determines whether there is an unparsed message instruction in its own message queue. If there is an unparsed message instruction in the message queue, step 511 is executed; if there is no unparsed message instruction in the message queue, the process returns to step 501.

[0146] 511. If there are unparsed message instructions in the message queue of the target coprocessor, then the unparsed message instructions are parsed to obtain parsed message instructions;

[0147] If there are unparsed message instructions in the message queue of the target coprocessor, then the unparsed message instructions are parsed to obtain the parsed message instructions.

[0148] correspond Figure 4 For example, if there is an unparsed message instruction in the message queue of S-CPU0, the unparsed message instruction is parsed to obtain the parsed message instruction.

[0149] 512. Send the parsed message instruction to the corresponding target hardware processing queue, so that the target hardware processing queue sends the parsed message instruction to the corresponding hardware processing module for processing.

[0150] Once the target coprocessor receives the parsed message instruction, it sends the parsed message instruction to the corresponding target hardware processing queue, so that the target hardware processor queue sends the parsed message instruction to the corresponding hardware processing module for processing.

[0151] correspond Figure 4 For example, when S-CPU0 receives the parsed message instruction, it sends the parsed message instruction to the hardware processing queue that is connected to S-CPU0, so that the hardware processing queue sends the parsed message instruction to the corresponding hardware processing module for processing.

[0152] In this embodiment of the application, when the storage space utilization rate of any hardware processing queue in the target hardware processing queue does not reach a preset threshold, and there is a parsed message instruction at a preset position, the parsed message instruction can be directly obtained from the preset position, thereby improving the parsing efficiency of the coprocessor for message instructions and correspondingly improving the data processing performance of the solid-state drive.

[0153] To verify the utilization rate of coprocessor computing power in the embodiments of this application Figure 6 According to Figure 5 The S-CPU scheduling process in this embodiment, when the storage space of the JOB FIFO hardware resource is smaller than the storage space of the FQ hardware resource, illustrates the time allocation diagram for S-CPU scheduling of the flash queue, compared to... Figure 3 In this regard, the computing resources of the S-CPU can be maximized for processing message instructions (SQ), thereby improving the scheduling efficiency of message instructions (FQ). It should be noted that... Figure 6 The colors in the text are meant to indicate the time each part occupies, rather than to define it.

[0154] Furthermore, based on Figure 4 and Figure 5 In the aforementioned embodiment, the message queues in the target coprocessor can be multiple message queues with priorities. When the target coprocessor has multiple message queues with priorities, the target coprocessor determines whether there are unparsed message instructions in the message queues according to the priorities of the multiple message queues. When there are unparsed message instructions in multiple message queues, the target coprocessor performs parsing operations on the unparsed message instructions according to the priorities of the message queues to obtain the parsed message instructions.

[0155] In other words, when the target coprocessor's message queue consists of multiple message queues with different priorities, the target coprocessor will judge and parse the message instructions in the corresponding message queue according to their priority levels when executing judgment instructions and parsing instructions.

[0156] In this embodiment, a priority level is set in the message queue of the target coprocessor, so that message queues of different levels can store message instructions of different priority levels, thereby meeting the processing of message instructions of different priority levels in different application scenarios and improving the user's experience of using solid-state drives.

[0157] It is understood that, in various embodiments of the present invention, the order of the steps does not imply the order of execution. The execution order of each step should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0158] The method for scheduling flash queues in the embodiments of this application has been described in detail above. The solid-state drive in the embodiments of this application will be described below. Please refer to [link / reference]. Figure 7 :

[0159] The solid-state drive in this embodiment includes at least one coprocessor, a hardware processing queue and a flash queue module communicatively connected to the coprocessor, wherein the flash queue module includes at least one flash queue, and the storage space of the hardware processing queue communicatively connected to the target coprocessor is smaller than the storage space of the flash queue module communicatively connected to the target coprocessor. The target coprocessor is any one of the at least one coprocessor, and the coprocessor includes:

[0160] Acquisition unit 701 is used to acquire the target hardware processing queue and the target flash queue module that are communicatively connected to the coprocessor;

[0161] The judgment unit 702 is used to determine whether all schedulable flash queues in the target flash queue module are in working state when the utilization rate of the storage space of any hardware processing queue in the target hardware processing queue reaches a preset threshold.

[0162] The judgment unit 702 is also used to determine whether there are unparsed message instructions in the message queue of the coprocessor when all schedulable flash queues in the target flash queue module are in working state.

[0163] The parsing unit 703 is used to perform a parsing operation on the unparsed message instructions when there are unparsed message instructions in the message queue of the coprocessor, so as to obtain the parsed message instructions;

[0164] Storage unit 704 is used to store the parsed message instruction to a preset location.

[0165] Preferably, the solid-state drive further includes a main processor, and the storage unit 704 is further used for:

[0166] If the target flash queue module has an idle flash queue, and the idle flash queue contains a message instruction sent by the main processor, the message instruction is stored in the message queue of the target coprocessor, and the idle flash queue is updated to be in a working state.

[0167] Preferably, the solid-state drive further includes a hardware processing module communicatively connected to the hardware processing queue, and the judgment unit 702 is further configured to:

[0168] If the utilization rate of the storage space of any hardware processing queue in the target hardware processing queue does not reach the preset threshold, then it is determined whether there is a parsed message instruction at the preset position.

[0169] The acquisition unit 701 is further configured to:

[0170] If a parsed message instruction is present at the preset location, then the parsed message instruction is retrieved from the preset location.

[0171] The coprocessor also includes:

[0172] The sending unit 705 is used to send the parsed message instruction to the corresponding target hardware processing queue, so that the target hardware processing queue sends the parsed message instruction to the corresponding hardware processing module for processing.

[0173] Preferably, the determining unit 702 is further configured to:

[0174] If no parsed message instruction is found at the preset position, it is determined whether there is an unparsed message instruction in the message queue of the target coprocessor.

[0175] The parsing unit 703 is also used for:

[0176] If there are unparsed message instructions in the message queue of the target coprocessor, then the unparsed message instructions are parsed to obtain the parsed message instructions;

[0177] The transmitting unit 705 is further configured to:

[0178] The parsed message instruction is sent to the corresponding hardware processing queue, so that the hardware processing queue sends the parsed message instruction to the corresponding hardware processing module for processing.

[0179] Preferably, the target coprocessor is provided with multiple message queues with priorities;

[0180] The judgment unit 702 is specifically used for:

[0181] Based on the priority of multiple message queues, determine whether there are any unparsed message instructions in each of the multiple message queues;

[0182] The parsing unit 703 is specifically used for:

[0183] If there are unparsed message instructions in multiple message queues of the target coprocessor, then the unparsed message instructions are parsed according to the priority of the message queues to obtain the parsed message instructions.

[0184] Preferably, the solid-state drive further includes multiple NandFlash, a message queue interface, and a hardware scheduling module. The hardware scheduling module includes at least one scheduling channel. The main processor communicates with the scheduling channel through the message queue interface. Each scheduling channel communicates with a flash queue module. One or more flash queue modules communicate with one of the coprocessors. Each coprocessor communicates with one or more hardware processing queues. One or more hardware processing queues communicate with a hardware processing module.

[0185] The message instruction is used to instruct interactive operations with the plurality of NandFlashes, and the interactive operations include at least one of read operations, write operations, delete operations, and query operations.

[0186] Preferably, the NandFlash includes multiple Die regions, each Die region includes multiple Plane surfaces, each Plane surface includes multiple Blocks, and each Block includes one or more Pages;

[0187] If the NandFlash supports asynchronous plane read operations, then the read operation message instruction received by each flash queue from the main processor corresponds to the read operation instruction in each plane.

[0188] If the NandFlash does not support asynchronous plane read operations, then the read operation message instruction received by each flash queue from the main processor corresponds to the read operation instruction in each Die region.

[0189] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of each unit described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0190] Compared with the prior art, the embodiments of this application reduce the parsing time of the coprocessor for unparsed message instructions when the utilization rate of the storage space of any hardware processing queue in the target hardware processing queue does not reach a preset threshold. This improves the parsing efficiency of the coprocessor for message instructions and the efficiency of the coprocessor in scheduling flash queues, and also improves the data processing performance of the solid-state drive.

[0191] This application also provides a computer program product, on which a computer program is stored, which, when executed by a processor, is used to implement, for example... Figure 4 and Figure 5 The method for scheduling flash queues described in the method embodiments.

[0192] The present invention also provides another computer-readable storage medium for implementing the functions of a coprocessor, wherein a computer program is stored thereon, and when the computer program is executed by a processor, the processor can use it to perform... Figure 4 and Figure 5 Steps in the method embodiments.

[0193] It is understood that if the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a corresponding computer-readable storage medium. Based on this understanding, all or part of the processes in the above-described embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the above-described method embodiments. The computer program includes computer program code, which can be in the form of source code, object code, executable file, or some intermediate form. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0194] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0195] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0196] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0197] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for scheduling a flash queue, characterized in that, A coprocessor applied in a solid-state drive (SSD), the SSD including at least one coprocessor, a hardware processing queue and a flash queue module communicatively connected to the coprocessor, wherein the flash queue module includes at least one flash queue, the storage space of the hardware processing queue communicatively connected to a target coprocessor is smaller than the storage space of the flash queue module communicatively connected to the target coprocessor, and the target coprocessor is any one of the at least one coprocessor, the method comprising: Acquire the target hardware processing queue and target flash queue module that are communicating with the target coprocessor; If the storage space utilization rate of any hardware processing queue in the target hardware processing queue reaches a preset threshold, then it is determined whether all schedulable flash queues in the target flash queue module are in working state. If all schedulable flash queues in the target flash queue module are in a working state, then determine whether there are any unparsed message instructions in the message queue of the target coprocessor. If there are unparsed message instructions in the message queue of the target coprocessor, then a parsing operation is performed on the unparsed message instructions to obtain the parsed message instructions; The parsed message instruction is stored in a preset location.

2. The method according to claim 1, characterized in that, The solid-state drive also includes a main processor, and the method further includes: If the target flash queue module has an idle flash queue, and the idle flash queue contains a message instruction sent by the main processor, the message instruction is stored in the message queue of the target coprocessor, and the idle flash queue is updated to be in a working state.

3. The method according to claim 1, characterized in that, The solid-state drive further includes a hardware processing module communicatively connected to the hardware processing queue, and the method further includes: If the utilization rate of the storage space of any hardware processing queue in the target hardware processing queue does not reach the preset threshold, then it is determined whether there is a parsed message instruction at the preset position. If a parsed message instruction is present at the preset location, then the parsed message instruction is retrieved from the preset location. The parsed message instruction is sent to the corresponding target hardware processing queue, so that the target hardware processing queue sends the parsed message instruction to the corresponding hardware processing module for processing.

4. The method according to claim 3, characterized in that, The method further includes: If no parsed message instruction is found at the preset position, it is determined whether there is an unparsed message instruction in the message queue of the target coprocessor. If there are unparsed message instructions in the message queue of the target coprocessor, then the unparsed message instructions are parsed to obtain the parsed message instructions; The parsed message instruction is sent to the corresponding hardware processing queue, so that the hardware processing queue sends the parsed message instruction to the corresponding hardware processing module for processing.

5. The method according to claim 1, characterized in that, The target coprocessor is equipped with multiple message queues with priorities; The step of determining whether there are unparsed message instructions in the message queue of the target coprocessor includes: Based on the priority of multiple message queues, determine whether there are any unparsed message instructions in each of the multiple message queues; If there are unparsed message instructions in the message queue of the target coprocessor, then a parsing operation is performed on the unparsed message instructions to obtain parsed message instructions, including: If there are unparsed message instructions in multiple message queues of the target coprocessor, then the unparsed message instructions are parsed according to the priority of the message queues to obtain the parsed message instructions.

6. The method according to claim 1, characterized in that, The solid-state drive also includes multiple NandFlash, a message queue interface, and a hardware scheduling module. The hardware scheduling module includes at least one scheduling channel. The main processor communicates with the scheduling channel through the message queue interface. Each scheduling channel communicates with a flash queue module. One or more flash queue modules communicate with one of the coprocessors. Each coprocessor communicates with one or more hardware processing queues. One or more hardware processing queues communicate with a hardware processing module. The message instruction is used to instruct interactive operations with the plurality of NandFlashes, and the interactive operations include at least one of read operations, write operations, delete operations, and query operations.

7. The method according to claim 6, characterized in that, The NandFlash includes multiple Die regions, each Die region includes multiple Planes, each Plane includes multiple Blocks, and each Block includes one or more Pages. If the NandFlash supports asynchronous plane read operations, then the read operation message instruction received by each flash queue from the main processor corresponds to the read operation instruction in each plane. If the NandFlash does not support asynchronous plane read operations, then the read operation message instruction received by each flash queue from the main processor corresponds to the read operation instruction in each Die region.

8. A solid-state drive, characterized in that, At least including: At least one coprocessor, a hardware processing queue and a flash queue module communicatively connected to the coprocessor, wherein the flash queue module includes at least one flash queue, the storage space of the hardware processing queue communicatively connected to the target coprocessor is smaller than the storage space of the flash queue module communicatively connected to the target coprocessor, and the target coprocessor is any one of the at least one coprocessor, the coprocessor comprising: The acquisition unit is used to acquire the target hardware processing queue and the target flash queue module that are communicatively connected to the coprocessor; The judgment unit is used to determine whether all schedulable flash queues in the target flash queue module are in working state when the utilization rate of the storage space of any hardware processing queue in the target hardware processing queue reaches a preset threshold. The judgment unit is also used to determine whether there are unparsed message instructions in the message queue of the coprocessor when all schedulable flash queues in the target flash queue module are in working state. The parsing unit is used to perform a parsing operation on the unparsed message instructions when there are unparsed message instructions in the message queue of the coprocessor, so as to obtain the parsed message instructions; A storage unit is used to store the parsed message instructions at a preset location.

9. A readable computer storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the coprocessor, it is used to implement the method for scheduling flash queues as described in any one of claims 1 to 6.

10. A computer program product having a computer program stored thereon, characterized in that, When the computer program is executed by the coprocessor, it is used to implement the method for scheduling flash queues as described in any one of claims 1 to 6.

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