Method, system and terminal for fast dynamic allocation and release of non-cache memory based on high-performance MCU

Abstract

The present invention provides a method, system and terminal for fast dynamic allocation and release of non-cache memory based on high-performance MCU, by accessing linked list data for describing the allocation state of non-cache memory in a cacheable area, allocating and releasing the memory of the non-cache memory, and updating the linked list data. The present invention improves the allocation speed of non-cache memory by storing a memory block management data structure in a cacheable area, and allocates non-cache memory compared to a traditional memory allocation algorithm. This method hardly accesses non-cache memory when executing memory allocation and release, so the speed is greatly improved. At the same time, the allocation algorithm is simple and easy to implement, and the data structure occupies little memory, which is very suitable for high-performance MCU embedded platforms with CACHE with tight resources.

Description

Technical Field

[0001] The present invention relates to the field of MCU technology, and in particular to a method, system and terminal for fast dynamic allocation and release of non-cache area memory based on a high-performance MCU. Background Art

[0002] As the performance of MCU becomes increasingly powerful, many high-performance MCUs use a CACHE system to increase the CPU's operating speed compared to traditional MCUs. When the CPU is executing, it will load the code and data in the main memory into the cache memory (CACHE). Since the speed of CAHCE is much faster than the speed of the main memory, the CPU's performance will be significantly improved. Currently, common high-performance MCUs on the market all have a CACHE system. MCU is a system on a chip, which generally integrates a rich set of peripherals, and data will also be exchanged between the peripherals and the CPU.

[0003] In traditional MCUs without a CACHE system, there is no cache consistency problem when the peripherals and CPU interact with each other. However, on high-performance MCUs with a CACHE system, there will be cache consistency problems when the CPU and peripherals interact, so in general, the memory for data interaction between the CPU and peripherals will be placed in the non-cacheable area (NONCHAHEABLE). For example, the ADC collects data and writes the data to the RAM (random access memory) through direct memory access (DMA). After the ADC is collected, the CPU will read and process the data collected by the ADC. If the RAM storing the data is a cacheable area (CACHEABLE), then when the CPU reads it, it may not read the real data in the RAM, but the data cached in the CACHE, which will cause cache inconsistency problems. If the RAM storing the data is a non-cacheable (NONCACHE) area, there will be no consistency problems when the CPU reads the data. Therefore, in general, the memory of high-performance MCUs is divided into two types: CACHEABLE and NONCACHEABLE. The NONCACHEABLE area is mainly used for data interaction between peripherals and CPUs and data interaction between CPUs.

[0004] In order to fully utilize the memory utilization of the NONCAHEABLE area, the NONCAHEABLE area will usually introduce a dynamic memory allocation algorithm for management. Existing memory allocation algorithms all place data structures and data areas in the NONCACHEABLE area. For the CPU, the access speed of the memory in the NONCAHEABLE area is much lower than the access speed of the CACHEABLE area. Therefore, when executing the memory allocation algorithm, a lot of CPU memory access time will be wasted, which greatly reduces the speed of memory allocation. Therefore, the existing memory algorithm is not suitable for memory allocation in the NONCACHEABLE area. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method, system and terminal for fast dynamic allocation and release of non-cache area memory based on a high-performance MCU, which is used to solve the technical problems of low efficiency and speed of existing memory allocation algorithms in the prior art in allocating in the NONCACHEABLE area.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for fast dynamic allocation and release of non-cache area memory based on a high-performance MCU, which is applied to the MCU and includes a cacheable area and a non-cache area. The method includes: constructing linked list data stored in the cacheable area for describing the memory allocation status of the non-cache area; by accessing the linked list data in the cacheable area, allocating and releasing the memory of the non-cache area, and updating the linked list data.

[0007] In one embodiment of the present invention, the linked list data includes: an unused linked list, used to place blk_info that is not associated with a non-cache memory block; a free linked list, used to place blk_info that is respectively associated with a non-cache memory block in an unallocated state; and an allocated linked list, used to place blk_info that is respectively associated with a non-cache memory block in an allocated state.

[0008] In one embodiment of the present invention, the data structure of blk_info includes: a linked list node, a pointer to the previous adjacent blk_info, a pointer to the next adjacent blk_info, the first address of the associated non-cache memory block, the data length of the associated non-cache memory block, and an allocation status mark.

[0009] In one embodiment of the present invention, the method for allocating memory in the non-cache area includes: finding the blk_info associated with the non-cache area memory block that is not smaller than the memory to be allocated from the free linked list, and obtaining the target blk_info that matches the memory to be allocated, and attaching the target blk_info to the allocated linked list; storing the storage address of the target blk_info to the first 4 bytes of the corresponding non-cache area memory block.

[0010] In one embodiment of the present invention, finding the blk_info associated with the non-cache memory block that is not less than the memory to be allocated from the free linked list, obtaining the target blk_info that matches the memory to be allocated, and attaching the target blk_info to the allocated linked list includes: if the blk_info associated with the non-cache memory block whose memory is equal to the memory to be allocated is found from the free linked list, attaching the blk_info as the target blk_info to the allocated linked list; if the blk_info associated with the non-cache memory block whose memory is greater than the memory to be allocated is found from the free linked list, using the blk_info as the blk_info associated with the memory block to be split, obtaining the blk_info associated with the non-cache memory block whose memory is equal to the memory to be allocated cut from the memory block to be split, attaching the blk_info as the target blk_info to the allocated linked list, and updating the blk_info of the memory block to be split based on the remaining memory after the cutting.

[0011] In one embodiment of the present invention, obtaining blk_info associated with a non-cache memory block that is equal to the memory to be allocated and is cut from the memory block to be split includes: based on the memory head address of the non-cache memory block cut from the memory block to be split, the data length of the memory block, and the adjacent blk_info, filling in a blk_info obtained from the unused linked list to obtain a target blk_info.

[0012] In one embodiment of the present invention, a method for releasing memory in a non-cache area includes: based on the first four bytes of a non-cache memory block to be released, searching the allocated linked list for blk_info associated with the non-cache memory block to be released as the current blk_info, and searching the blk_info adjacent to the current blk_info; determining whether the blk_info adjacent to the current blk_info is in an allocated state; if it is in an unallocated state, merging the current blk_info with the adjacent unallocated blk_info; if both are in an allocated state, directly deleting the current blk_info from the allocated linked list and adding it to the unused linked list.

[0013] In one embodiment of the present invention, merging the current blk_info with the adjacent unallocated blk_info includes: if only the previous adjacent blk_info is in the unallocated state, updating the data length recorded in the previous adjacent blk_info to the sum of the data length recorded in the current blk_info and the data length recorded in the previous adjacent blk_info, and deleting the current blk_info from the allocated list and adding it to the unused list; if only the next adjacent blk_info is in the unallocated state, updating the data length recorded in the current blk_info to the sum of the data length recorded in the current blk_info and the data length recorded in the next adjacent blk_info, and deleting the updated current blk_info from the allocated list and adding it to the free list, and adding the next adjacent blk_info to the free list. info is deleted from the free list and added to the unused list; if the previous adjacent blk_info and the next adjacent blk_info are both in the unallocated state, the data length recorded in the current blk_info is first updated to the sum of the data length recorded in the current blk_info and the data length recorded in the next adjacent blk_info, and the updated current blk_info is deleted from the allocated list and added to the free list, and the next adjacent blk_info is deleted from the free list and added to the unused list; the data length recorded in the previous adjacent blk_info is modified to the sum of the data length recorded in the updated current blk_info and the data length recorded in the previous adjacent blk_info, and the updated current blk_info is deleted from the free list and added to the unused list.

[0014] To achieve the above-mentioned purpose and other related purposes, the present invention provides a non-cache area memory fast dynamic allocation and release system based on a high-performance MCU, which is applied to the MCU and includes a cacheable area and a non-cache area. The system includes: a linked list data construction module, which is used to construct linked list data stored in the cacheable area for describing the memory allocation status of the non-cache area; a memory allocation and release module, which is connected to the linked list data construction module, and is used to allocate and release the memory of the non-cache area by accessing the linked list data of the cacheable area, and update the linked list data.

[0015] To achieve the above-mentioned purpose and other related purposes, the present invention provides an electronic terminal, comprising: one or more memories and one or more processors; the one or more memories are used to store computer programs; the one or more processors are connected to the memories and are used to run the computer program to execute the non-cache area memory fast dynamic allocation and release method based on high-performance MCU.

[0016] As described above, the present invention is a method, system and terminal for fast dynamic allocation and release of non-cache memory based on high-performance MCU, which has the following beneficial effects: the present invention allocates and releases the memory of the non-cache memory by accessing the linked list data for describing the allocation status of the non-cache memory in the cacheable area, and updates the linked list data. The present invention improves the allocation speed of the non-cache memory by storing the memory block management data structure in the cacheable area. Compared with the traditional memory allocation algorithm for allocating non-cache memory, this method hardly accesses the non-cache memory when executing memory allocation and release, so the speed is greatly improved. At the same time, the allocation algorithm is simple and easy to implement, and the data structure occupies little memory, which is very suitable for high-performance MCU embedded platforms with CACHE with tight resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Shown is a flow chart of a method for fast dynamic allocation and release of non-cache memory based on a high-performance MCU in one embodiment of the present invention.

[0018] Figure 2 Shown is a schematic diagram of linked list data in an initial state in one embodiment of the present invention.

[0019] Figure 3 Shown is a schematic diagram of a memory allocation process for allocating one memory block in an embodiment of the present invention.

[0020] Figure 4 Shown is a schematic diagram of a memory release process in which two memory blocks have been allocated in an embodiment of the present invention.

[0021] Figure 5 Shown is a schematic diagram of the structure of a non-cache memory fast dynamic allocation and release system based on a high-performance MCU in one embodiment of the present invention.

[0022] Figure 6 Shown is a schematic structural diagram of an electronic terminal in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0024] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present invention. It should be understood that other embodiments may also be used, and that mechanical composition, structural, electrical and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present invention is limited only by the claims of the published patents. The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0025] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a part is said to "include" a certain constituent element, unless otherwise stated, it does not exclude other constituent elements, but means that other constituent elements may be included.

[0026] The terms first, second and third mentioned herein are used to describe various parts, components, regions, layers and / or segments, but are not limited thereto. These terms are only used to distinguish a certain part, component, region, layer or segment from other parts, components, regions, layers or segments. Therefore, the first part, component, region, layer or segment described below may refer to the second part, component, region, layer or segment within the scope of the present invention.

[0027] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0028] The present invention provides a non-cache area memory fast dynamic allocation and release method based on high-performance MCU, by accessing the linked list data for describing the non-cache area memory allocation state in the cacheable area, the memory of the non-cache area is allocated and released, and the linked list data is updated. The present invention improves the allocation speed of the non-cache area memory by storing the memory block management data structure in the cacheable area, and allocates the non-cache area memory compared with the traditional memory allocation algorithm. This method hardly accesses the non-cache area memory when executing memory allocation and release, so the speed is greatly improved. At the same time, the allocation algorithm is simple and easy to implement, and the data structure occupies little memory, which is very suitable for high-performance MCU embedded platform with CACHE with tight resources.

[0029] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0030] like Figure 1 A flowchart showing a method for fast dynamic allocation and release of non-cache memory based on a high-performance MCU in an embodiment of the present invention is shown.

[0031] The method comprises:

[0032] Step S1: constructing linked list data stored in the cacheable area for describing the memory allocation status of the non-cacheable area.

[0033] Specifically, when executing memory allocation, the CPU manages the memory in the NONCACHEABLE area through a series of data structures, such as linked lists, and the speed of accessing these data structures of the CPU determines the speed of memory allocation and recycling. In order to improve the speed of the NONCACHEABLE allocation algorithm, the main idea of ​​the present invention is to place the structure for managing the NONCACHEABLE area data in the CACHEABLE area.

[0034] In one embodiment, the managed non-cache memory block is described by a blk_info data structure, and the blk_info data structure is stored in the RAM in the cacheable area, and has a fast access speed; the linked list data includes:

[0035] The unused linked list is used to place multiple blk_infos that are not associated with non-cache memory blocks; the number of blk_infos is set according to demand. Each blk_info does not contain memory block information.

[0036] The free list is used to store blk_info associated with unallocated non-cache memory blocks; each unallocated non-cache memory block is associated with a blk_info;

[0037] The allocated linked list is used to store blk_info associated with non-buffered memory blocks in the allocated state; each allocated non-buffered memory block is associated with one blk_info.

[0038] In a specific embodiment, the data structure of blk_info includes:

[0039] 1. Linked list node (list);

[0040] 2. A pointer (pre) pointing to the previous adjacent blk_info, through which the previous adjacent blk_info can be found; the memory block associated with the previous adjacent blk_info is the previous adjacent memory block of the currently associated memory block.

[0041] 3. A pointer (nxt) pointing to the next adjacent blk_info, through which the next adjacent blk_info can be found; the memory block associated with the next adjacent blk_info is the next adjacent memory block of the currently associated memory block.

[0042] 4. The starting address (start) of the associated non-cache memory block. This address is the starting address of the non-cache memory block. The data in the memory block can be accessed or operated through this address.

[0043] 5. The data length (len) of the associated non-buffered memory block;

[0044] 6. Allocation status flag. In the blk_info of the free list, the memory block is in the unallocated state and is marked with the allocation status. In the blk_info of the allocated list, the memory block is in the allocated state and is marked with the unallocated status.

[0045] In one embodiment, if Figure 2 As shown, the initial state of the linked list data is:

[0046] The initial state does not contain any allocated non-buffered memory blocks, so there is no blk_info in the allocated list; the initial state has only one unallocated non-buffered memory block, so it is associated with a blk_info, which records the basic information of the non-buffered memory block and is stored in the free list. The initial state contains N unused blk_infos, and all blk_infos are not associated with any non-buffered memory blocks.

[0047] Step S2: by accessing the linked list data in the cacheable area, the memory in the non-cacheable area is allocated and released, and the linked list data is updated.

[0048] In one embodiment, the method of allocating memory in the non-cache area includes:

[0049] Find the blk_info associated with the non-cache memory block that is not smaller than the memory to be allocated from the free linked list, obtain the target blk_info that matches the memory to be allocated, and attach the target blk_info to the allocated linked list;

[0050] The storage address of the target blk_info is stored in the first 4 bytes of the corresponding non-cache memory block, and the address obtained by subtracting 4 from the first address of the non-cache memory block is used as the first address of the allocated memory for the system to use.

[0051] In a specific embodiment, if Figure 3 , taking the allocation of a memory block from the initial state as an example, the specific process of allocating a memory block is explained. The methods for allocating memory in the non-cache area include:

[0052] First, find a blk_info associated with a non-cache memory block whose memory size is not less than the memory to be allocated from the free list;

[0053] If a blk_info associated with a non-cache memory block whose memory is equal to the memory to be allocated is found from the free linked list, the blk_info is attached to the allocated linked list as the target blk_info;

[0054] If the blk_info associated with the non-cache memory block whose memory is larger than the memory to be allocated is found from the free linked list, memory segmentation is required. First, the blk_info is regarded as the blk_info of the memory block to be segmented, and then a part equal to the size of the memory to be allocated is cut out from the memory block to be segmented, and a new blk_info is obtained from the unused linked list to manage the newly cut memory block (i.e., the target blk_info), and it is attached to the allocated linked list. At the same time, the original blk_info is updated to reflect the remaining memory block information after the cutting (e.g., the linked list node, the pointer to the previous adjacent blk_info, the pointer to the next adjacent blk_info, the first address of the remaining non-cache memory block, and the data length of the remaining non-cache memory block), and it is put back into the free linked list.

[0055] In one embodiment, obtaining the blk_info associated with the non-cache memory block of the memory cut from the memory block to be divided that is equal to the memory to be allocated includes: filling in a blk_info obtained from the unused linked list based on the memory first address of the non-cache memory block cut from the memory block to be divided, the data length of the memory block, and the adjacent blk_info to obtain the target blk_info. Specifically, the blk_info obtained from the unused linked list is filled in with the memory first address of the non-cache memory block cut from the memory block to be divided as the first address of the associated non-cache memory block, and the data length of the memory block is used as the data length of the associated non-cache memory block to fill in the blk_info, and the adjacent blk_info is used to obtain a pointer to the previous adjacent blk_info and a pointer to the next adjacent blk_info to fill in the blk_info, and the target blk_info is obtained after filling in.

[0056] In one embodiment, if Figure 4 , taking 2 memory blocks allocated as an example, combined with Figure 4 Status changed to Figure 3 The status describes the process of memory release.

[0057] The ways to release the non-cache memory include:

[0058] Obtain the first address of the blk_info stored in the first four bytes of the non-cache memory block to be released, search the blk_info associated with the non-cache memory block to be released in the allocated linked list as the current blk_info, and search the blk_info adjacent to the current blk_info through the pointer pointing to the previous adjacent blk_info and the pointer pointing to the next adjacent blk_info in the current blk_info;

[0059] Determine whether the blk_info adjacent to the current blk_info is in an allocated state; specifically, determine whether it is in an allocated state using an allocation state flag in the blk_info adjacent to the current blk_info.

[0060] If it is in the unallocated state, merge the current blk_info with the adjacent unallocated blk_info;

[0061] If they are all in the allocated state, the current blk_info is directly deleted from the allocated linked list and added to the unused linked list.

[0062] In one embodiment, merging the current blk_info with the adjacent unallocated blk_info includes:

[0063] If only the previous adjacent blk_info is in the unallocated state, the data length recorded in the previous adjacent blk_info is updated to the sum of the data length recorded in the current blk_info and the data length recorded in the previous adjacent blk_info. At the same time, the current blk_info is deleted from the allocated list and added to the unused list.

[0064] If only the next adjacent blk_info is in the unallocated state, the data length recorded in the current blk_info is updated to the sum of the data length recorded in the current blk_info and the data length recorded in the next adjacent blk_info. At the same time, the updated current blk_info is deleted from the allocated list and added to the free list, and the next adjacent blk_info is deleted from the free list and added to the unused list.

[0065] If the previous adjacent blk_info and the next adjacent blk_info are both in the unallocated state, first update the data length recorded in the current blk_info to the sum of the data length recorded in the current blk_info and the data length recorded in the next adjacent blk_info, and delete the updated current blk_info from the allocated list and add it to the free list, and delete the next adjacent blk_info from the free list and add it to the unused list; modify the data length recorded in the previous adjacent blk_info to the sum of the data length recorded in the updated current blk_info and the data length recorded in the previous adjacent blk_info, and delete the updated current blk_info from the free list and add it to the unused list.

[0066] It should be noted that when blk_info is updated, the pointer pointing to the previous adjacent blk_info and the first address information do not need to be modified, and only the data length and the pointer pointing to the next adjacent blk_info need to be updated.

[0067] The main advantage of this design is that it can effectively merge adjacent unallocated memory blocks and only update the data length and the pointer to the next adjacent blk_info without moving the memory block itself or modifying its physical address. By simply updating the metadata of blk_info and adjusting the linked list structure, the system can manage memory more efficiently, reduce memory fragmentation, and improve memory utilization.

[0068] Similar to the principle of the above-mentioned embodiment, the present invention provides a non-cache memory fast dynamic allocation and release system based on a high-performance MCU.

[0069] The following provides specific embodiments in conjunction with the accompanying drawings:

[0070] like Figure 5 A structural schematic diagram showing a non-cache memory fast dynamic allocation and release system based on a high-performance MCU in an embodiment of the present invention.

[0071] Applied to MCU, including a cacheable area and a non-cacheable area, the system includes:

[0072] A linked list data construction module 1 is used to construct linked list data stored in the cacheable area for describing the memory allocation state of the non-cache area;

[0073] The memory allocation and release module 2 is connected to the linked list data construction module and is used to allocate and release the memory of the non-cache area by accessing the linked list data of the cacheable area, and to update the linked list data.

[0074] Since the implementation principle of the non-cache memory fast dynamic allocation and release system based on the high-performance MCU has been described in the above embodiments, it will not be repeated here.

[0075] The non-cache memory fast dynamic allocation and release method based on high-performance MCU provided in the embodiment of the present invention can be implemented on the terminal side or the server side. As for the hardware structure of the electronic terminal, please refer to Figure 6 , is an optional hardware structure diagram of an electronic terminal 1000 provided in an embodiment of the present invention. The terminal 1000 may be a mobile phone, a computer device, a tablet device, a personal digital processing device, a factory background processing device, etc. The terminal 1000 includes: at least one processor 1001, a memory 1002, at least one network interface 10010 and a user interface 1009. The various components in the device are coupled together through a bus system 1005. It can be understood that the bus system 1005 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 1005 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, in Figure 6 In the specification, various buses are labeled as bus systems.

[0076] The user interface 1009 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0077] It is understood that the memory 1002 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of exemplary but not limiting explanation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable categories of memory.

[0078] The memory 1002 in the embodiment of the present invention is used to store various categories of data to support the operation of the terminal 1000. Examples of these data include: any executable program used to operate on the terminal 1000, such as an operating system 10021 and an application 10022; the operating system 10021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 10022 can include various applications, such as a media player (MediaPlayer), a browser (Browser), etc., for implementing various application services. The method for fast dynamic allocation and release of non-cache area memory based on a high-performance MCU provided in the embodiment of the present invention can be included in the application 10022.

[0079] The method disclosed in the above embodiment of the present invention can be applied to the processor 1001, or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 1001 or the instruction in the form of software. The above processor 1001 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 1001 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiment of the present invention. The general processor 1001 can be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present invention, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0080] In an exemplary embodiment, the terminal 1000 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

[0081] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

[0082] In the embodiments provided in the present application, the computer readable and writable storage medium may include a read-only memory, a random access memory, an EEPROM, a CD-ROM or other optical disk storage device, a disk storage device or other magnetic storage device, a flash memory, a USB flash drive, a mobile hard disk, or any other medium that can be used to store a desired program code in the form of an instruction or data structure and can be accessed by a computer. In addition, any connection can be appropriately referred to as a computer-readable medium. For example, if the instruction is sent from a website, a server or other remote source using a coaxial cable, an optical fiber cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, optical fiber cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. However, it should be understood that computer readable and writable storage media and data storage media do not include connections, carriers, signals, or other temporary media, but are intended to be non-temporary, tangible storage media. Disk and disc, as used in this application, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

[0083] In summary, the non-cache area memory fast dynamic allocation and release method, system and terminal based on high-performance MCU of the present invention allocates and releases the memory of the non-cache area by accessing the linked list data for describing the allocation state of the non-cache area memory in the cacheable area, and updates the linked list data. The present invention improves the allocation speed of the non-cache area memory by storing the memory block management data structure in the cacheable area. Compared with the traditional memory allocation algorithm to allocate the non-cache area memory, this method hardly accesses the non-cache area memory when executing memory allocation and release, so the speed is greatly improved. At the same time, the allocation algorithm is simple and easy to implement, and the data structure occupies little memory, which is very suitable for high-performance MCU embedded platforms with CACHE with tight resources. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0084] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for fast dynamic allocation and release of non-cache memory based on high-performance MCU, characterized in that: Applied to MCU, including a cacheable area and a non-cacheable area, the method comprises: Constructing linked list data for describing the non-cache memory allocation state stored in the cacheable area, wherein the linked list data includes: an unused linked list for placing blk_info of non-cache memory blocks not associated; a free linked list for placing blk_info of non-cache memory blocks respectively associated with an unallocated state; and an allocated linked list for placing blk_info of non-cache memory blocks respectively associated with an allocated state; By accessing the linked list data in the cacheable area, the memory in the non-cacheable area is allocated and released, and the linked list data is updated.

2. According to the method for fast dynamic allocation and release of non-cache memory based on high-performance MCU described in claim 1, it is characterized in that: The data structure of blk_info includes: a linked list node, a pointer to the previous adjacent blk_info, a pointer to the next adjacent blk_info, the first address of the associated non-cache memory block, the data length of the associated non-cache memory block, and an allocation status flag.

3. According to the method for fast dynamic allocation and release of non-cache memory based on high-performance MCU described in claim 2, it is characterized in that: The ways to allocate non-cache memory include: Find the blk_info associated with the non-cache memory block that is not smaller than the memory to be allocated from the free linked list, obtain the target blk_info that matches the memory to be allocated, and attach the target blk_info to the allocated linked list; The storage address of the target blk_info is stored in the first 4 bytes of the corresponding non-buffered memory block.

4. According to the method for fast dynamic allocation and release of non-cache memory based on high-performance MCU described in claim 3, it is characterized in that: Finding the blk_info associated with the non-cache memory block that is not smaller than the memory to be allocated from the free linked list, obtaining the target blk_info that matches the memory to be allocated, and attaching the target blk_info to the allocated linked list includes: If a blk_info associated with a non-cache memory block whose memory is equal to the memory to be allocated is found from the free linked list, the blk_info is attached to the allocated linked list as the target blk_info; If the blk_info associated with the non-cache memory block whose memory is larger than the memory to be allocated is found from the free linked list, the blk_info is used as the blk_info associated with the memory block to be split, and the blk_info associated with the non-cache memory block whose memory is equal to the memory to be allocated and cut from the memory block to be split is obtained, and the blk_info is attached to the allocated linked list as the target blk_info, and the blk_info of the memory block to be split is updated based on the remaining memory after cutting.

5. The method for fast dynamic allocation and release of non-cache memory based on high-performance MCU according to claim 4, characterized in that: Obtaining the blk_info associated with the non-buffered memory block that is equal to the memory to be allocated and cut from the memory block to be split includes: Based on the memory head address of the non-cache memory block cut from the memory block to be split, the data length of the memory block, and the adjacent blk_info, fill in a blk_info obtained from the unused linked list to obtain the target blk_info.

6. The method for fast dynamic allocation and release of non-cache memory based on high-performance MCU according to claim 3, characterized in that: The ways to release the non-cache memory include: Based on the first four bytes of the non-cache memory block to be released, searching the allocated linked list for the blk_info associated with the non-cache memory block to be released as the current blk_info, and searching for the blk_info adjacent to the current blk_info; Determine whether the blk_info adjacent to the current blk_info is in the allocated state; If it is in the unallocated state, merge the current blk_info with the adjacent unallocated blk_info; If they are all in the allocated state, the current blk_info is directly deleted from the allocated linked list and added to the unused linked list.

7. The method for fast dynamic allocation and release of non-cache memory based on high-performance MCU according to claim 6, characterized in that: Merging the current blk_info with the adjacent unallocated blk_info includes: If only the previous adjacent blk_info is in the unallocated state, the data length recorded in the previous adjacent blk_info is updated to the sum of the data length recorded in the current blk_info and the data length recorded in the previous adjacent blk_info. At the same time, the current blk_info is deleted from the allocated list and added to the unused list. If only the next adjacent blk_info is in the unallocated state, the data length recorded in the current blk_info is updated to the sum of the data length recorded in the current blk_info and the data length recorded in the next adjacent blk_info. At the same time, the updated current blk_info is deleted from the allocated list and added to the free list, and the next adjacent blk_info is deleted from the free list and added to the unused list. If the previous adjacent blk_info and the next adjacent blk_info are both in the unallocated state, first update the data length recorded in the current blk_info to the sum of the data length recorded in the current blk_info and the data length recorded in the next adjacent blk_info, and delete the updated current blk_info from the allocated list and add it to the free list, and delete the next adjacent blk_info from the free list and add it to the unused list; modify the data length recorded in the previous adjacent blk_info to the sum of the data length recorded in the updated current blk_info and the data length recorded in the previous adjacent blk_info, and delete the updated current blk_info from the free list and add it to the unused list.

8. A non-cache memory fast dynamic allocation and release system based on high-performance MCU, characterized in that: Applied to MCU, including a cacheable area and a non-cacheable area, the system includes: A linked list data construction module is used to construct linked list data stored in the cacheable area for describing the memory allocation state of the non-cache area, wherein the linked list data includes: an unused linked list for placing blk_info of non-cache area memory blocks that are not associated; a free linked list for placing blk_info of non-cache area memory blocks that are respectively associated with an unallocated state; and an allocated linked list for placing blk_info of non-cache area memory blocks that are respectively associated with an allocated state. The memory allocation and release module is connected to the linked list data construction module and is used to allocate and release the memory of the non-cache area by accessing the linked list data of the cacheable area, and to update the linked list data.

9. An electronic terminal, characterized in that: include: one or more memories and one or more processors; The one or more memories are used to store computer programs; The one or more processors, connected to the memory, are configured to run the computer program to perform the method according to any one of claims 1 to 7.

Images