A control method and system of a four-level inverter

Abstract

The application discloses a control method and system of a four-level inverter, and comprises the following steps: acquiring an actual output current value of the four-level inverter; determining an actual output voltage at the next moment according to the actual output current value; performing coordinate transformation on the actual output voltage at the next moment to obtain a reference voltage vector; determining a vector in a space vector diagram of the four-level inverter that is closest to the reference voltage vector, and determining a sector in which the vector is located as two-level hexagonal sectors in which the reference voltage vector is located; determining a wave emission mode according to the parity of the two-level hexagonal sector in which the reference voltage vector is located; determining a switching sequence according to the wave emission mode; and controlling the four-level inverter through the determined switching sequence. The four-level inverter has the characteristics of fast response speed, low common-mode voltage and realization of flying capacitor voltage balance.

Description

Technical Field

[0001] The present invention relates to the technical field of inverters, and in particular to a control method and system for a four-level inverter. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] like Figure 1 As shown in Figure 1, the four-level nested neutral point clamped (4L-NNPC) inverter is a creative combination of neutral point clamped (NPC) and flying capacitor (FC) inverters, which fully utilizes the advantages of NPC and FC. The 4L-NNPC generates four levels of output voltage in each phase, and each phase has six power switches, two diodes and two flying capacitors C a1 、C a2 In order to ensure the normal operation of the inverter, the flying capacitor voltage must be adjusted to the input DC power supply voltage (V dc ) of 1 / 3.

[0004] In actual operation, multi-level inverters can generate high-frequency leakage currents due to common-mode voltage (CMV), causing electromagnetic interference and impacting the operation of communication equipment. Therefore, it is necessary to suppress CMV in four-level inverters. Related technologies mention the use of isolation transformers, common-mode filters, and modulation techniques to reduce common-mode voltage.

[0005] However, both the isolation transformer and the common-mode filter are heavy, costly, and reduce system efficiency. A virtual vector is used to modulate the common-mode voltage to obtain smaller neutral-point voltage fluctuations and output current harmonics, but this requires a lot of calculation. Summary of the Invention

[0006] In order to solve the above problems, the present invention proposes a control method and system for a four-level inverter, which has the characteristics of fast response speed, low common-mode voltage and achieving flying capacitor voltage balance.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] In a first aspect, a control method for a four-level inverter is proposed, comprising:

[0009] Get the actual output current value of the four-level inverter;

[0010] According to the actual output current value, determine the actual output voltage at the next moment;

[0011] Perform coordinate transformation on the actual output voltage at the next moment to obtain a reference voltage vector;

[0012] determine a fixed vector closest to the reference voltage vector in a space vector diagram of the four-level inverter;

[0013] determine a two-level hexagon sector centered on the determined fixed vector as a two-level hexagon sector in which the reference voltage vector is located;

[0014] determine a firing mode according to parity of the two-level hexagon sector in which the reference voltage vector is located;

[0015] determine a switching sequence according to the firing mode;

[0016] control the four-level inverter through the determined switching sequence.

[0017] Further, the space vector diagram of the four-level inverter includes 13 two-level hexagon sectors, and a construction process of the space vector diagram of the four-level inverter is as follows:

[0018] construct a four-level space vector diagram of the four-level inverter;

[0019] cut the four-level space vector diagram to obtain six large sectors with the range of -30°—30° as a reference;

[0020] determine four fixed vectors of each large sector;

[0021] determine a two-level hexagon sector centered on each fixed vector.

[0022] Further, all voltage vectors of the four-level inverter are determined according to a topology structure of the four-level inverter;

[0023] determine a common-mode voltage generated by each voltage vector;

[0024] select a voltage vector generating a common-mode voltage less than or equal to V dc / 6, to construct a four-level space vector diagram of the four-level inverter, wherein V dc is an input voltage of the inverter.

[0025] Further, a process of determining a two-level hexagon sector in which the reference voltage vector is located is as follows:

[0026] determine a large sector in which the reference voltage vector is located according to a three-phase voltage polarity;

[0027] calculate distances between the reference voltage vector and each fixed vector in the large sector;

[0028] select a two-level hexagon sector centered on a fixed vector closest to the reference voltage vector as the two-level hexagon sector in which the reference voltage vector is located.

[0029] Further, when the two-level hexagon sector where the reference voltage vector is located is even, a seven-segment wave mode is adopted;

[0030] When the two-level hexagon sector where the reference voltage vector is located is odd, a five-segment wave mode is adopted.

[0031] Further, the reference voltage vector is also decomposed into the two-level hexagon sector where the reference voltage vector is located;

[0032] According to the decomposed vectors, the action time of each decomposed vector is determined;

[0033] According to the switch sequence and the action time, the four-level inverter is controlled.

[0034] Further, the determined switch sequence is a switch sequence for balancing the voltage across the flying capacitor.

[0035] In a second aspect, a control system of a four-level inverter is provided, comprising:

[0036] An acquisition unit is configured to acquire an actual output current value of the four-level inverter;

[0037] A voltage prediction unit is configured to determine an actual output voltage at a next moment according to the actual output current value;

[0038] A reference voltage vector determination unit is configured to perform coordinate transformation on the actual output voltage at the next moment to obtain a reference voltage vector;

[0039] A sector determination unit is configured to determine a fixed vector closest to the reference voltage vector in a space vector diagram of the four-level inverter, and determine a two-level hexagon sector centered on the determined fixed vector as a two-level hexagon sector where the reference voltage vector is located;

[0040] A wave mode determination unit is configured to determine a wave mode according to the parity of the two-level hexagon sector where the reference voltage vector is located;

[0041] A switch sequence determination unit is configured to determine a switch sequence according to the wave mode;

[0042] A four-level inverter control unit is configured to control the four-level inverter through the determined switch sequence.

[0043] In a third aspect, a computer device is provided, comprising:

[0044] A processor is adapted to execute a computer program;

[0045] A computer readable storage medium, wherein a computer program is stored in the computer readable storage medium, and the computer program, when executed by the processor, implements the control method of the four-level inverter according to the first aspect.

[0046] In a fourth aspect, a computer readable storage medium is provided, wherein a computer program is stored in the computer readable storage medium, and the computer program is adapted to be loaded and executed by a processor to implement the control method of the four-level inverter according to the first aspect.

[0047] In a fifth aspect, a computer program product is provided, wherein the computer program product comprises a computer program, and the computer program, when executed by a processor, implements the control method of the four-level inverter according to the first aspect.

[0048] Compared with the prior art, the present application has the following beneficial effects:

[0049] The present application can quickly locate the two-level hexagonal sector where the reference voltage vector is located by calculating the distance between each fixed vector and the reference voltage vector in the space vector diagram, reduces the calculation amount and complexity, and the determined switching sequence satisfies the balance of the voltage across the flying capacitor. In addition, the wave emission mode is determined according to the parity of the two-level hexagonal sector where the reference voltage vector is located. The wave emission mode includes seven-segment and five-segment, and the switching sequence combining seven-segment and five-segment realizes comprehensive control of the flying capacitor voltage and common-mode voltage, balances and symmetrizes the output AC voltage, and makes the four-level inverter have the characteristics of fast response speed, low common-mode voltage and balanced flying capacitor voltage.

[0050] The advantages of the additional aspects of the present application will be partially given in the following description, partially become obvious from the following description, or be known by the practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0051] The drawings accompanying the specification of this application form a part thereof, serve to provide further understanding of the application, and together with the description of the exemplary embodiments of the application given below, serve to explain the application, and do not constitute an improper limitation on the application.

[0052] Figure 1 A structural schematic diagram of the 4L-NNPC inverter mentioned in the background art;

[0053] Figure 2 A vector label diagram of all sectors in the space vector diagram of the four-level inverter disclosed in the embodiments;

[0054] Figure 3 A vector label diagram of each small sector in the S0 large sector in the space vector diagram of the four-level inverter disclosed in the embodiments;

[0055] Figure 4 Space vector diagram of the four-level inverter disclosed in the embodiment for the remaining small common-mode voltage vector;

[0056] Figure 5 Flow chart of the control method (FCS-MPC method) of the four-level inverter disclosed in the embodiment;

[0057] Figure 6 Simulation result diagram disclosed in the embodiment, Figure 6 (a) is a three-phase current, Figure 6 (b) is a line current, Figure 6 (c) is a flying capacitor voltage;

[0058] Figure 7 THD result of the FCS-MPC method disclosed in the embodiment;

[0059] Figure 8 Common-mode voltage comparison result of the FCS-MPC method disclosed in the embodiment and the common-mode voltage control without adding common-mode voltage; Figure 8 (a) is a result diagram of the FCS-MPC method, Figure 8 (b) is a result diagram of the common-mode voltage control method without adding common-mode voltage;

[0060] Figure 9 Four-level space vector diagram of the four-level inverter disclosed in the embodiment. DETAILED DESCRIPTION

[0061] The application will be further described below in conjunction with the drawings and embodiments.

[0062] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0063] It should be noted that the terms used herein are only for the purpose of describing the specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise, and it should be further understood that when the terms "comprise" and / or "include" are used in the specification, there is a presence of the features, steps, operations, devices, components and / or combinations thereof.

[0064] The embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0065] Embodiment 1

[0066] Multi-level inverters (MLI) are mainly classified into neutral point clamped (NPC), flying capacitor (FC), cascaded H-bridge (CHB) and modular multilevel converter (MMC). Compared with two-level inverters, they have low output current and voltage harmonic content, high voltage withstand level, high cost performance, low dv / dt value, etc. They are mainly used in variable speed wind energy conversion systems as part of their power converters. Compared with three-level NPC inverters, four-level inverters have lower device stress and higher equivalent switching frequency when working, and are widely used in medium voltage (MV) applications at present. In recent years, there are many research papers on the control and modulation of multi-level inverters. However, these methods are proposed for three-level and five-level inverters, and due to the differences in circuit structure and number of DC capacitors, these control methods cannot be directly applied to four-level inverters.

[0067] Recently, a MLI topology called four-level nested neutral point clamped (4L-NNPC) was introduced into MV drive applications. The 4L-NNPC inverter is an important topology to fill the gap between three-level and five-level inverters. Compared with three-level inverters, the 4L-NNPC inverter can provide an additional voltage level without increasing the number of power devices, resulting in smaller output current harmonic content, and in addition, the 4L-NNPC inverter also effectively reduces the off-state voltage rise rate of the active switches in the circuit; compared with five-level inverters, the 4L-NNPC inverter requires fewer switching elements, reducing the complexity of control.

[0068] As shown in Figure 1 , the 4L-NNPC inverter is an innovative combination of neutral point clamped (NPC) and flying capacitor (FC) inverters, which fully utilizes the advantages of NPC and FC. The 4L-NNPC inverter outputs four voltage levels in each phase, and each phase has six power switches, two diodes and two flying capacitors. The six power switches are S a1 , S a2 , S a3 , S a4 , S a5 and S a6 , the two flying capacitors are C a1 and Ca2, and the two diodes are connected between the connection lines of S a2 and S a3 and the connection lines of C a1 and C a2 , and the connection lines of S a4 and S a5 and the connection lines of C a1 and C a2Between the connection lines, four output levels are achieved with six different switching combinations. The list of switching combinations is shown in Table 4. It should be noted that all the switching devices have a rating of one third of the DC side voltage. Another advantage of the proposed converter is that there are redundant states in the switching combinations for the same output level. For example, there are two redundant switching states when generating voltage levels of 1 / 6V dc and -1 / 6V dc . Each redundant state provides a specific charging and discharging current path for each flying capacitor. This is a specific feature of the redundant switching states that can be used to achieve voltage balancing of the capacitors. To ensure proper operation of the inverter, the flying capacitor voltage must be regulated to 1 / 3 of the input voltage V dc of the inverter. Compared to 4L-NPC and 4L-FC, the 4L-NNPC inverter has fewer diodes and flying capacitors. In addition, the 4L-NNPC inverter does not require series connection of power switches in the range of AC side RMS voltage, and compared to the NNPC inverter with higher output voltage level (such as 5L-NNPC), the 4L-NNPC inverter can operate in a larger range (2.4 - 7.2 kV). Despite the above advantages, 4L-NNPC faces technical challenges in industrial applications, especially in motor drive applications. The main technical challenges include reducing common-mode voltage, flying capacitor voltage balancing control, and reducing output current harmonics.

[0069] In actual operation, multi-level inverters will generate high-frequency leakage current due to common-mode voltage (CMV), which will cause electromagnetic interference and affect the operation of communication equipment. Therefore, it is necessary to suppress CMV in four-level inverters. Various methods have been proposed in the literature to address the problem related to common-mode voltage. These methods include the use of isolation transformers, CMV filters, and modulation techniques. Isolation transformers are a simple and reliable solution to solve machine insulation faults, but they are heavy, costly, and reduce system efficiency. Many scholars have developed transformerless solutions, such as using common-mode filters to bear the main common-mode voltage stress. However, CMV filters are usually large, costly, and inefficient. Some literature constructs virtual vectors to replace vectors that generate larger CMV to obtain smaller neutral point voltage fluctuations and output current harmonics, but the computational load is large.

[0070] To solve the above technical problems, in this embodiment, a control method for a four-level inverter is disclosed, as shown in Figures 2-8 , comprising:

[0071] obtaining an actual output current value of the four-level inverter;

[0072] determining an actual output voltage at the next moment according to the actual output current value;

[0073] The actual output voltage of the next moment is coordinate-transformed to obtain a reference voltage vector;

[0074] A fixed vector closest to the reference voltage vector in a space vector diagram of the four-level inverter is determined;

[0075] A two-level hexagonal sector centered on the determined fixed vector is taken as a two-level hexagonal sector where the reference voltage vector is located;

[0076] A wave emission mode is determined according to the parity of the two-level hexagonal sector where the reference voltage vector is located;

[0077] A switch sequence is determined according to the wave emission mode;

[0078] The four-level inverter is controlled through the determined switch sequence.

[0079] The actual output voltage of the next moment is determined according to an actual output current value and a discrete mathematical model of phase voltage of the four-level inverter, wherein the discrete mathematical model of phase voltage of the four-level inverter is obtained according to a mathematical model of the four-level inverter.

[0080] The mathematical model of the four-level inverter is established according to a topological structure of the four-level inverter by using Kirchhoff's voltage law, and a specific mathematical model of the four-level inverter is as follows:

[0081]

[0082] wherein, v xN is the voltage of each phase of the 4L-NNPC inverter to the N-point ground, i x is the three-phase alternating current output by the inverter, v nN is the voltage of the midpoint of the alternating side and the midpoint of the direct current side, L and R represent the inductance and equivalent resistance of the alternating side respectively, v aN , v bN , and v cN are the phase voltages of the a-phase, b-phase, and c-phase of the inverter respectively.

[0083] The discrete mathematical model of the phase voltage of the four-level inverter is as follows:

[0084]

[0085] wherein, T s is a control period; x=a, b, c, i x (k) is the three-phase actual output current of the 4L-NNPC at the k moment, i* x (k+1) is the three-phase ideal output current value at the k+1 moment, and V xn(k) is the k time output point to the load side of the common point between the x-phase prediction voltage, namely the k+1 time x-phase actual output voltage.

[0086] According to the Lagrange post method, the k+1 time three-phase ideal output current value can be calculated by the following formula:

[0087]

[0088] Therefore, according to the k time ideal output current value, the k-1 time ideal output current value, the k-2 time ideal output current value and formula (3), the k+1 time ideal output current value is calculated and obtained; according to the k+1 time ideal output current value, the k time actual output current value and formula (2), the k+1 time actual output voltage is calculated and obtained.

[0089] In this embodiment, the actual output voltage is transformed from the abc rectangular coordinate system to the gh 60° coordinate system to obtain the reference voltage vector, and the transformation formula is:

[0090]

[0091] Where, V a , V b , V c are the coordinates of the voltage vector in the abc coordinate system, and V g , V h are the coordinates of the voltage vector in the gh coordinate system.

[0092] As shown in Figure 2 , the space vector diagram of the four-level inverter constructed in this embodiment contains 13 two-level hexagonal sectors, and the 13 two-level hexagonal sectors are all centered on the vector position in the circle, such as the center vector of the two-level hexagonal sector S0 is 111, and the center vector of the other even two-level hexagonal sector is the one with the smallest sum of vector numbers, and the odd two-level hexagonal sector refers to Figure 4 .

[0093] The construction process of the space vector diagram of the four-level inverter is as follows:

[0094] Constructing a four-level space vector diagram of a four-level inverter;

[0095] Rotating the average cutting of the four-level space vector diagram in the range of-30°-30° as the reference angle to obtain six large sectors;

[0096] Determine four fixed vectors of each large sector;

[0097] Determine the two-level hexagonal sector centered on each fixed vector.

[0098] The embodiment determines four fixed vectors of each large sector, takes each fixed vector as a generalized zero vector, determines two-level hexagonal sectors centered by each generalized zero vector, and obtains a space vector diagram of the four-level inverter. For the four-level inverter, the positions of all generalized zero vectors are as shown in Figure 2 It can be seen that there are 13 generalized zero vectors in the four-level inverter, that is, the four-level space vector diagram can be divided into 13 two-level small hexagonal sectors, respectively S0-S 12 .

[0099] The process of constructing the four-level space vector diagram of the four-level inverter is as follows:

[0100] According to the topology structure of the four-level inverter, all voltage vectors of the four-level inverter are determined.

[0101] The common-mode voltage generated by each voltage vector is determined.

[0102] The voltage vector whose generated common-mode voltage is less than or equal to V dc / 6 is selected, and the four-level space vector diagram of the four-level inverter is constructed, wherein V dc is the input voltage of the inverter.

[0103] The common-mode voltage U cm can be calculated as:

[0104]

[0105] In the formula, U an , U bn and U cn represent the voltage vectors of phase a, phase b and phase c respectively; L x represents the voltage level generated by phase x, and L sum represents the sum of the three-phase output voltage levels. The vector whose absolute value of common-mode voltage (CMV) is less than or equal to V dc / 6, that is, 3≤L sum ≤6, is selected, and the vectors whose absolute values of CMV are V dc / 2, 7V dc / 18 and 5V dc / 18 are removed.

[0106] After screening, there are 44 voltage vectors meeting the condition, and 20 voltage vectors with high CMV are eliminated. The screened space vector diagram is as shown in Figure 4 .

[0107] The process of determining the two-level hexagonal sector where the reference voltage vector is located is as follows:

[0108] According to the polarity of the three-phase voltage, the large sector where the reference voltage vector is located is determined.

[0109] The distance between the reference voltage vector and each fixed vector in the large sector where the reference voltage vector is located is calculated.

[0110] A two-level hexagonal sector centered on the closest fixed vector is selected as the two-level hexagonal sector where the reference voltage vector is located.

[0111] In this embodiment, the distance between the reference voltage vector and each fixed vector in the large sector where the reference voltage vector is located is calculated by a target function, which is:

[0112]

[0113] or

[0114] F = (V gref -V g ) 2 +(V href -V h ) 2

[0115] In the formula, V greg , V href are the coordinates of the reference voltage vector in the gh coordinate system, and V g , V h are the coordinates in the space vector diagram.

[0116] The determination process of the target function is as follows:

[0117] The current dynamic equation can be obtained by transforming formula (1):

[0118]

[0119] The backward Euler discretization method is adopted, and the following definitions are made:

[0120]

[0121] According to the switching state in Table 4, the four-level NNPC output voltage can be written as:

[0122]

[0123] where S x1 , S x2 , S x3 are the x-phase power switch states (S xi |i→1, 2, 3={0, 1}), and V cx1 and V cx2 are the voltages of the x-phase flying capacitor.

[0124] The total voltage output of the three phases can be expressed as

[0125]

[0126] where, a = e j2π / 3

[0127] where i x (k) and u xn (k) are the actual output current and voltage of the xth phase at kth time, (k+1) time (x = a, b, c), T s is the sampling time.

[0128] It can be obtained by Lagrange extrapolation and Clarke transformation at k, k-1 and k-2 time, and the extrapolation formula is:

[0129]

[0130] where, and are the output current references at (k-2), (k-1) and k time. Under the action of any space voltage vector, the predicted value of the output current i x at k+1 time can be calculated at k time.

[0131] To achieve the predicted current of the four-level NNPC inverter that can track the given value well, the square sum of the difference between the predicted current value and the given value in the g-h 60° coordinate system can be taken as the objective function. That is

[0132] After determining the two-level hexagonal sector where the reference voltage vector is located, the reference voltage vector is decomposed into the two-level hexagonal sector where it is located, and the position of the small sector where the decomposed vector is located is found in the hexagonal sector, and the duty ratio of the decomposed vector is calculated, as shown in Tables 6 and 7. According to the duty ratio of the decomposed vector, the action time of the decomposed vector is determined, which is used for PWM wave generation. As shown in Table 8, the two-level hexagonal sector includes six small sectors, and the six small sectors are ss1-ss6. Figure 3

[0133] When the two-level hexagonal sector where the reference voltage vector is located is even, a seven-segment wave generation mode is adopted;

[0134] When the two-level hexagonal sector where the reference voltage vector is located is odd, a five-segment wave generation mode is adopted.

[0135] That is: even sectors S0, S2, S4, S6, S8, S 10 and S 12 adopt seven-segment wave, odd large sectors S1, S3, S5, S7, S9 and S 11 ​The five-segment wave is adopted.

[0136] Each large sector contains four two-level hexagonal sectors, one of which is an odd two-level hexagonal sector adopting the five-segment wave and three of which are even two-level hexagonal sectors adopting the seven-segment wave, and all the wave modes suppress the common-mode voltage, such as the -30°-30° large sector containing the odd hexagonal sector S1 and the even hexagonal sectors S0, S2, S 12 .

[0137] In the even sector, it is assumed that the basic vectors to be used are Vx, Vy, Vz, Vt in the fixed sequence, Vx is the first vector in the switching sequence, Vy is the second vector in the switching sequence, Vz is the third vector in the switching sequence, and Vt is the fourth vector in the switching sequence.

[0138] Vx and Vt are both zero vectors or generalized zero vectors, and the sequence of actions is as follows:

[0139] Vx→Vy→Vz→Vt→Vz→Vy→Vx, which is performed in the descending symmetric seven-segment mode.

[0140] According to the volt-second balance principle, the action times Tx, Ty, Tz, Tt of the unit vectors Vx, Vy, Vz, Vt are calculated. Taking the ss1 small sector of the S0 sector as an example, as shown in FIG. 1, in one switching period Ts, the vector switching sequence is V0→V1→V2→V0→V2→V1→V0, the switching sequence is (1, 1, 1)→(2, 1, 1)→(2, 2, 1)→(2, 2, 2)→(2, 2, 1)→(2, 1, 1)→(1, 1, 1), and the corresponding seven-segment basic vector action times are 0.25T1-0.5T2-0.5T3-0.5T1-0.5T3-0.5T2-0.25T1 in turn. Figure 3 The sequence starting vector in each even two-level hexagonal sector is

[0141] The selected sector center point is taken as an example, and each sequence starting vector is abc, A=a+1, B=b+1, and C=c+1. The capital letters ABC represent the numbers, and the previous combination of letters represents the numbers plus one. Taking the ss1 small sector of the S0 sector as an example, abc is 111, Abc is 211, aBc is 221, and abC is 222. Figure 2 The sequence order in each small sector is shown in Table 1.

[0142] Table 1 Sequence order in each small sector in the hexagonal two-level large sector

[0143]

[0144]

[0145] ​The odd two-level hexagonal sectors use a five-segment wavelet generation. Let each sequence start vector be abc, A = a - 1, B = b - 1, C = c - 1, D = a + 1, E = b + 1, F = c + 1. The upper case letters A, B, C represent the number minus one, the upper case letters D, E, F represent the number plus one.

[0146] In the sectors S1, S5 and S9, the direction of the vector movement is opposite to the even sectors, i.e. clockwise. In contrast, in the sectors S3, S7 and S11, the direction of the vector rotation is the same as in the even sectors, i.e. counter-clockwise. The sequence order in each sub-sector is shown in Tables 2, 3.

[0147] Table 2 Sequence order in each sub-sector in the two-level large sectors S1, S5 and S9

[0148]

[0149] Table 3 Sequence order in each sub-sector in the two-level large sectors S3, S7 and S11

[0150]

[0151]

[0152] The embodiment also considers balancing the voltage across the flying capacitor when determining the switching sequence, and the final switching sequence is the switching sequence that balances the voltage across the flying capacitor; balancing the voltage across the flying capacitor means that the deviation between the capacitor voltage and the expected voltage is less than or equal to a set deviation.

[0153] In a specific implementation, the embodiment also acquires the capacitor voltage, and determines whether the voltage across the flying capacitor is balanced according to the capacitor voltage; when the voltage across the flying capacitor is not balanced, the embodiment determines the positive or negative nature of the deviation between the capacitor voltage and the expected voltage, and determines the switching sequence that balances the voltage across the flying capacitor according to the positive or negative nature of the deviation between the capacitor voltage and the expected voltage and the influence of the switching state on the deviation between the capacitor voltage and the expected voltage.

[0154] The flying capacitor balancing mode is shown in Table 5. As shown in Table 4, the switching states 0 and 3 (corresponding to levels 0 and 3, respectively) have no influence on the capacitor voltage because no current flows through the capacitor. Levels 1 and 2 always have an influence on the capacitor voltage. For different redundant switching states, the influence is different and also depends on the direction of the phase current. Also, due to the coupling, both capacitors can be charged and discharged at the same time. For level 1, if the redundant switching state 1a is used and i x > 0, then the capacitor C x2 is discharged and V Cx2 is reduced, if i x<0, capacitor C x2 is charged and V Cx2 increases, while capacitor C x1 is not affected, as shown in Table 1. If redundant switch state 1b is employed, when i x > 0, both capacitors C x1 and C x2 are charged, and capacitor voltages V Cx1 and V Cx2 increase, when i x < 0, C x1 and C x2 are discharged, and V Cx1 and V Cx2 decrease. For level 2, if redundant switch state 2a is employed and i x > 0, capacitor C x1 is charged and V Cx1 increases, if i x < 0, capacitor C x1 is discharged and V Cx1 decreases, while capacitor C x2 is not affected, if redundant switch state 2b is employed, when i x > 0, both capacitors C x1 and C x2 are discharged, and capacitor voltages V Cx1 and V Cx2 decrease, when i x < 0, C x1 and C x2 are charged, and V Cx1 and V Cx2 increase. If there is no control of the voltage of the FC in the NNPC converter, the FC voltage will deviate from its desired value because there is no control of the current into / out of the capacitors. The difference between the actual FC voltage (capacitor voltage) and the desired voltage (V dc / 3) can be defined as the voltage deviation of the FC, and can be expressed as:

[0155] AV Cxi = V Cxi - V dc / 3 (5)

[0156] where V Cxi is the capacitor voltage, V dc is the input voltage of the inverter, AV Cxi is the deviation of the capacitor voltage, x = a, b, c, i = 1, 2.

[0157] Table 4 Switching states of a four-level NNPC inverter and their effects on flying capacitor voltages

[0158]

[0159]

[0160] Table 5 flying capacitor balance mode

[0161]

[0162] Table 6 duty cycle of three vertex basic vectors in s3, s7, s11

[0163]

[0164] Table 7 duty cycle of three vertex basic vectors in s1, s5, s9

[0165]

[0166] By using the specific vector sequence selection method, combining the influence of the redundant vector state at different levels on the common-mode voltage, the basic voltage vector is selected based on this to form a seven-segment or five-segment vector switching sequence.

[0167] The present embodiment will also refer to the voltage vector decomposition into the two-level hexagonal sector where it is located;

[0168] According to the decomposition vector, the action time of each decomposition vector is determined;

[0169] According to the switching sequence and the action time, the four-level inverter is controlled.

[0170] The method disclosed in the present embodiment transforms the reference voltage vector from the abc coordinate system to the gh60° coordinate system, and the coordinate values of each vector on the space vector diagram are all integers, so that the vector coordinates are more clear; the duty cycle is calculated by using the coordinates of the vector on the g and h coordinate axes and the sign of the sum of the two coordinates, and the duty cycle can be obtained after finding the vector closest to the reference vector (one of the four fixed vectors in the -30°—30° sector division method), which greatly shortens the duty cycle calculation time. In the case of a simple cost function without weight factors, good current and voltage waveforms are obtained. By dividing the appropriate control ratio in each cycle to track the reference voltage, the THD is small. The method disclosed in the present embodiment can control the phase current THD to 1.57%. However, single-vector FCS-MPC can only control it to 2.45%.

[0171] The parameters in Table 8 are used to verify the effect of the control method (FCS-MPC method) of the four-level inverter proposed in the present embodiment, and the results are shown in Figure 6 , Figure 7 and Figure 8 , Figure 6The middle (a) shows a sinusoidal waveform of three-phase current, Figure 6 The middle (b) shows that the line current has 7 voltage levels, Figure 6 The middle (c) is the flying capacitor voltage; Figure 7 For the harmonic simulation results of the FCS-MPC method disclosed in this embodiment, the FCS-MPC method disclosed in this embodiment can control the phase current THD to 1.86%, and the FCS-MPC method disclosed in this embodiment can track the reference voltage by dividing the appropriate control ratio in each cycle, so it has a smaller THD. Figure 8 The CMV of the 4L-NNPC is shown, wherein, Figure 8 The middle (a) is a control result graph of the FCS-MPC method; Figure 8 The middle (b) is a control method result graph without common mode voltage, and it can be verified that the method disclosed in this embodiment

[0172] Table 8 Simulation parameter table

[0173]

[0174] The control method of the four-level inverter disclosed in this embodiment can quickly locate the two-level hexagonal sector where the reference voltage vector is located by calculating the distance between each fixed vector in the space vector diagram and the reference voltage vector, thereby reducing the amount of calculation and the complexity of calculation; the determined switching sequence satisfies the balance of the flying capacitor voltage; in addition, the wave generation mode is determined according to the parity of the two-level hexagonal sector where the reference voltage vector is located; the wave generation mode includes seven-segment and five-segment, and the switching sequence combining seven-segment and five-segment realizes the comprehensive control of the flying capacitor voltage and the common mode voltage, so that the output alternating voltage is balanced and symmetrical; so that the four-level inverter has the characteristics of fast response speed, low common mode voltage and balanced flying capacitor voltage.

[0175] Embodiment 2

[0176] In this embodiment, a control system of a four-level inverter is proposed, comprising:

[0177] The acquisition unit is configured to acquire an actual output current value of the four-level inverter.

[0178] The voltage prediction unit is configured to determine an actual output voltage at a next moment according to the actual output current value.

[0179] The reference voltage vector determination unit is configured to perform coordinate transformation on the actual output voltage at the next moment to obtain a reference voltage vector.

[0180] The sector in which the reference voltage vector is located is determined by a sector determining unit, which is configured to determine a fixed vector closest to the reference voltage vector in a space vector diagram of the four-level inverter; and take two-level hexagon sectors centered on the determined fixed vector as the two-level hexagon sectors in which the reference voltage vector is located.

[0181] The wave emission mode is determined by a wave emission mode determining unit according to the parity of the two-level hexagon sector in which the reference voltage vector is located.

[0182] The switch sequence is determined by a switch sequence determining unit according to the wave emission mode.

[0183] The four-level inverter is controlled by a four-level inverter control unit through the determined switch sequence.

[0184] The application further discloses a computer device, which comprises:

[0185] A processor is adapted to execute a computer program.

[0186] A computer readable storage medium stores the computer program, and the computer program is executed by the processor to implement the control method of the four-level inverter.

[0187] The application further discloses a computer readable storage medium, which stores a computer program, and the computer program is adapted to be loaded and executed by a processor to implement the control method of the four-level inverter.

[0188] The application further discloses a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the control method of the four-level inverter.

[0189] The method disclosed in Embodiment 1 can be directly embodied by a hardware processor or a combination of hardware and software modules in the processor. The software module can be located in a storage medium mature in the art, such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and a processor reads information in the memory and combines hardware to complete the steps of the above method. To avoid repetition, no further description is given here.

[0190] Those skilled in the art can understand that the units and algorithm steps of each example described in combination with the present embodiment can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software manner depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0191] Although the specific embodiments of the present application are described above in combination with the drawings, it is not a limitation on the scope of protection of the present application. Those skilled in the art should understand that various modifications or variations made by those skilled in the art on the basis of the technical solutions of the present application without creative labor are still within the scope of protection of the present application.

Claims

1. A control method for a four-level inverter, characterized in that: include: Get the actual output current value of the four-level inverter; According to the actual output current value, determine the actual output voltage at the next moment; Perform coordinate transformation on the actual output voltage at the next moment to obtain a reference voltage vector; According to the topology of the four-level inverter, all voltage vectors of the four-level inverter are determined; Determine the common-mode voltage produced by each voltage vector; Select the voltage vector whose common-mode voltage is less than or equal to Vdc / 6 to construct a four-level space vector diagram of the four-level inverter, where Vdc is the input voltage of the inverter; Determine the large sector where the reference voltage vector is located according to the polarity of the three-phase voltage; Calculate the distance between the reference voltage vector and each fixed vector in the large sector; A two-level hexagonal sector centered on the nearest fixed vector is selected as the two-level hexagonal sector where the reference voltage vector is located; When the number of two-level hexagonal sectors where the reference voltage vector is located is even, the seven-segment wave generation mode is adopted; When the two-level hexagonal sector where the reference voltage vector is located is an odd number, the five-segment wave generation mode is adopted; Determine the switching sequence according to the wave pattern; The four-level inverter is controlled through a determined switching sequence.

2. The control method of a four-level inverter according to claim 1, wherein: The space vector diagram of the four-level inverter contains 13 two-level hexagonal sectors. The construction process of the four-level space vector diagram of the four-level inverter is as follows: Construct a four-level space vector diagram of a four-level inverter; The four-level space vector diagram is rotated and averaged based on the angle range of -30° to 30° to obtain six large sectors; Determine four fixed vectors for each large sector; A two-level hexagonal sector centered around each fixed vector is determined.

3. The control method of a four-level inverter according to claim 1, wherein: The determined switching sequence is a switching sequence that balances the voltages across the flying capacitor.

4. A control system for a four-level inverter, characterized in that: include: An acquisition unit, used to acquire an actual output current value of the four-level inverter; A voltage prediction unit, used to determine the actual output voltage at the next moment based on the actual output current value; a reference voltage vector determination unit, configured to perform coordinate transformation on the actual output voltage at the next moment to obtain a reference voltage vector; The reference voltage vector sector determination unit is used to determine all voltage vectors of the four-level inverter according to the topology of the four-level inverter; and determine the common mode voltage generated by each voltage vector; Select voltage vectors with a common-mode voltage less than or equal to Vdc / 6 to construct a four-level space vector diagram for the four-level inverter, where Vdc is the input voltage of the inverter. Determine the large sector where the reference voltage vector is located based on the polarity of the three-phase voltages. Calculate the distance between the reference voltage vector and each fixed vector in the large sector. Select the two-level hexagonal sector centered on the closest fixed vector as the two-level hexagonal sector where the reference voltage vector is located. a wave transmission mode determining unit, configured to adopt a seven-segment wave transmission mode when the two-level hexagonal sector where the reference voltage vector is located is an even number; and adopt a five-segment wave transmission mode when the two-level hexagonal sector where the reference voltage vector is located is an odd number; A switch sequence determination unit, configured to determine a switch sequence according to a wave transmission mode; The four-level inverter control unit is used to control the four-level inverter through a determined switching sequence.

5. An electronic device, characterized in that: The device comprises: a processor adapted to execute a computer program; A computer-readable storage medium having a computer program stored therein, wherein when the computer program is executed by the processor, the control method of the four-level inverter according to any one of claims 1 to 3 is implemented.

6. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program is suitable for being loaded by a processor and executing the control method of a four-level inverter according to any one of claims 1 to 3.

7. A computer program product, characterized in that The computer program product includes a computer program, and when the computer program is executed by a processor, the computer program implements the control method of a four-level inverter according to any one of claims 1 to 3.

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