Method and circuit for data signal processing

Abstract

The present disclosure provides a method and circuit for data signal processing. The method for data signal processing provided by an embodiment of the present disclosure includes: obtaining frequency information of a channel used to transmit the data signal; determining the frequency category of the channel based on the frequency information; when the frequency category is determined to be a first category, obtaining a first clock signal from a first clock source, and performing analog-to-digital conversion sampling and digital baseband signal processing on the data signal based on the first clock signal; and when the frequency category is determined to be a second category, obtaining a second clock signal from a mixing signal used for mixing with the data signal, and performing analog-to-digital conversion sampling and digital baseband signal processing on the data signal based on the second clock signal.

Description

Technical Field

[0001] The present disclosure relates to the field of wireless communication technology, and in particular to a method and circuit for data signal processing in the field of wireless communication chips. Background Art

[0002] In the field of communications equipment, wireless communication systems, due to their open environment, are subject to far more complex interference than wired communication systems. This includes interference from out-of-band signals and noise in the air, various types of electromagnetic interference caused by poor circuit board design, and harmonics and noise interference caused by internal chip design issues. Currently, there is no effective solution to the aforementioned problem of interference caused by high-order clock harmonics within the chip. Many existing methods for reducing harmonic interference target the board-level system, employing shielding, isolation, filtering, and other methods to enhance electromagnetic compatibility. However, there is no particularly effective method for addressing the interference caused by high-order clock harmonics within the chip. Therefore, a method that can effectively eliminate internal chip clock harmonics is needed. Summary of the Invention

[0003] An embodiment of the present disclosure provides a method for data signal processing, comprising: obtaining frequency information of a channel used to transmit the data signal; determining the frequency category of the channel based on the frequency information; when the frequency category is determined to be a first category, obtaining a first clock signal from a first clock source, and performing analog-to-digital conversion sampling and digital baseband signal processing of the data signal based on the first clock signal; and when the frequency category is determined to be a second category, obtaining a second clock signal from a mixing signal used for mixing with the data signal, and performing analog-to-digital conversion sampling and digital baseband signal processing of the data signal based on the second clock signal.

[0004] In some embodiments, obtaining a first clock signal from a first clock source includes: obtaining a third clock signal from the first clock source; and using the third clock signal as the first clock signal, or dividing the third clock signal based on a first division coefficient to obtain the first clock signal, wherein the first division coefficient is a multiple of the frequency of the third clock signal relative to the frequency of the first clock signal.

[0005] In some embodiments, obtaining a second clock signal from a mixing signal used to mix with the data signal includes: dividing the mixing signal based on a second division coefficient to obtain the second clock signal, wherein the second division coefficient is the harmonic order of the harmonic of the first clock signal falling into the channel.

[0006] In some embodiments, the frequency information includes one or more of the following: the center frequency and / or bandwidth of the channel; the number of the channel; the frequency category of the channel, wherein the frequency category includes the first category and the second category.

[0007] In some embodiments, determining the frequency category of the channel based on the frequency information includes: determining whether the harmonics of the first clock signal fall into the channel based on the frequency information; in the case of determining that the harmonics of the first clock signal do not fall into the channel, determining the frequency category as the first category; and in the case of determining that the harmonics of the first clock signal fall into the channel, determining the frequency category as the second category.

[0008] In some embodiments, the frequency of the second clock signal is lower or higher than the frequency of the first clock signal.

[0009] In some embodiments, the first clock source is a crystal oscillator clock source.

[0010] In some embodiments, the frequency of the mixing signal is lower than a center frequency of the channel by a first frequency, wherein the first frequency is determined based on a data rate mode used to transmit the data signal.

[0011] In some embodiments, the mixed signal is generated by a phase-locked loop of a low-IF architecture receiver.

[0012] In some embodiments, when the frequency point category is determined to be the second category, the digital baseband signal processing further includes: compensating for the sampling rate deviation of analog-to-digital conversion sampling of the data signal based on a first compensation amount, wherein the first compensation amount is determined based on the frequency of the mixing signal and the center frequency of the channel.

[0013] An embodiment of the present disclosure provides a circuit for data signal processing, comprising: a digital clock generating unit; an analog-to-digital converter; a digital baseband signal processing unit; and a control unit, wherein the control unit is configured to: obtain frequency information of a channel used to transmit the data signal; determine the frequency category of the channel based on the frequency information; when the frequency category is determined to be a first category, control the digital clock generating unit to obtain a first clock signal from a first clock source, and respectively control the analog-to-digital converter and the digital baseband signal processing unit to perform analog-to-digital conversion sampling and digital baseband signal processing on the data signal based on the first clock signal; and when the frequency category is determined to be a second category, control the digital clock generating unit to obtain a second clock signal from a mixing signal used for mixing with the data signal, and respectively control the analog-to-digital converter and the digital baseband signal processing unit to perform analog-to-digital conversion sampling and digital baseband signal processing on the data signal based on the second clock signal.

[0014] In some embodiments, the circuit further includes a first frequency division circuit, and wherein controlling the digital clock generation unit to obtain the first clock signal from the first clock source includes: controlling the digital clock generation unit to obtain a third clock signal from the first clock source; and controlling the digital clock generation unit to use the third clock signal as the first clock signal, or to divide the third clock signal based on a first frequency division coefficient by the first frequency division circuit to obtain the first clock signal.

[0015] The first frequency division coefficient is a multiple of the frequency of the third clock signal relative to the frequency of the first clock signal.

[0016] In some embodiments, the circuit further includes a second frequency division circuit, and wherein controlling the digital clock generation unit to obtain a second clock signal from a mixing signal for mixing with the data signal includes: controlling the digital clock generation unit to divide the mixing signal based on a second frequency division coefficient through the second frequency division circuit to obtain the second clock signal, wherein the second frequency division coefficient is the harmonic order of the harmonic of the first clock signal falling into the channel.

[0017] In some embodiments, the frequency information includes one or more of the following: the center frequency and / or bandwidth of the channel; the number of the channel; the frequency category of the channel, wherein the frequency category includes the first category and the second category.

[0018] In some embodiments, determining the frequency category of the channel based on the frequency information includes: determining whether the harmonics of the first clock signal fall into the channel based on the frequency information; in the case of determining that the harmonics of the first clock signal do not fall into the channel, determining the frequency category as the first category; and in the case of determining that the harmonics of the first clock signal fall into the channel, determining the frequency category as the second category.

[0019] In some embodiments, the frequency of the second clock signal is lower or higher than the frequency of the first clock signal.

[0020] In some embodiments, the first clock source is a crystal oscillator clock source.

[0021] In some embodiments, the frequency of the mixing signal is lower than a center frequency of the channel by a first frequency, wherein the first frequency is determined based on a data rate mode used to transmit the data signal.

[0022] In some embodiments, the circuit further comprises a phase-locked loop of a low intermediate frequency architecture receiver, wherein the mixing signal is generated by the phase-locked loop.

[0023] In some embodiments, the digital baseband signal processing unit further includes a compensation circuit, wherein, when the frequency point category is determined to be the second category, the digital baseband signal processing further includes: compensating for the sampling rate deviation of the analog-to-digital conversion sampling of the data signal based on a first compensation amount through the compensation circuit, wherein the first compensation amount is determined based on the frequency of the mixing signal and the center frequency of the channel.

[0024] The method disclosed in the present invention can solve the sensitivity deterioration problem caused by ADC sampling and digital clock harmonics. The solution has low hardware resource cost and stable and reliable performance, and can fundamentally eliminate the sensitivity deterioration problem caused by ADC sampling and digital clock harmonics. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings are not necessarily drawn to scale, and for illustrative purposes, elements of similar structure or function may generally be represented by the same reference numerals or portions thereof throughout the drawings. The drawings are merely for the convenience of describing the various embodiments described herein. The drawings do not describe every aspect of the teachings disclosed herein and do not limit the scope of the claims. To prevent the drawings from becoming obscure, not all components, connections, etc. are shown, and not all components have reference numerals. However, the pattern of component configuration can be easily seen from the drawings. The drawings, together with the specification, illustrate example embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the drawings, in which:

[0026] Figure 1 A schematic diagram illustrating a situation where clock harmonic interference is mixed into a band according to an embodiment of the present disclosure;

[0027] Figure 2 A schematic diagram of a system for eliminating clock harmonics of an ADC sampling clock and a digital baseband signal processing unit clock according to an embodiment of the present disclosure is shown;

[0028] Figure 3 An example flow chart of digital baseband signal processing according to an embodiment of the present disclosure is shown;

[0029] Figure 4 It further shows a schematic diagram of spectrum shifting of signals and harmonics under a 1 MHz low intermediate frequency architecture according to an embodiment of the present disclosure;

[0030] Figure 5 A schematic diagram of a sampling rate deviation calibration circuit according to an embodiment of the present disclosure is shown;

[0031] Figure 6 A corresponding exemplary control flow diagram of a state machine of a chip digital circuit according to an embodiment of the present disclosure is shown;

[0032] Figure 7 A schematic flow chart of a method for data signal processing according to an embodiment of the present disclosure is shown; and

[0033] Figure 8 FIG. 8 is a schematic block diagram of a circuit 800 for data signal processing according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] Before proceeding with the detailed description below, it may be helpful to set forth the definitions of certain words and phrases used throughout this patent document. The terms "couple," "connect," and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are in physical contact with each other. The terms "transmit," "receive," and "communicate," and their derivatives, encompass both direct and indirect communication. The terms "include," "comprise," and their derivatives, mean including, but not limited to. The term "or" is inclusive, meaning and / or. The phrases "associated with," "corresponding to," and their derivatives, mean including, included within, interconnected, containing, contained within, connected or connected with, coupled or coupled with, communicate with, cooperate with, intertwine, juxtapose, approach, bound or bound with, have, have an attribute of, have a relationship with, or have a relationship with, etc. The term "controller" refers to any device, system, or portion thereof that controls at least one operation. Such a controller may be implemented using hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, whether local or remote. The phrase "at least one of," when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one of the items in the list may be needed. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A, B, and C.

[0035] Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0036] In this patent document, the application combination of modules and the division level of submodules are only for illustration. Without departing from the scope of the present disclosure, the application combination of modules and the division level of submodules can be different. The embodiments of the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make this disclosure thorough and complete and to fully convey exemplary implementation methods to those skilled in the art. The embodiments of the present disclosure can be arbitrarily combined to form additional embodiments.

[0037] In this disclosure, the sampling rate may refer to the frequency of a sampling clock.

[0038] In this disclosure, the clock signal may also be simply referred to as a clock.

[0039] In the present disclosure, frequency or frequency information may also include or refer to a channel, a center frequency and / or bandwidth of a channel.

[0040] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0041] In the field of communications equipment, wireless communication systems, due to their open environment, are subject to far more complex interference than wired communication systems. This includes interference from out-of-band signals and noise in the air, various electromagnetic interferences caused by improper circuit board design, and harmonics and noise interference caused by internal chip design issues.

[0042] For wireless communication chip receivers, if the digital-to-analog circuit design is unreasonable or the signal isolation is not done well, some digital signals, especially the harmonics generated by the digital clock signal (including the analog-to-digital converter (ADC) sampling clock and the digital circuit clock), will be coupled into the RF receiving path, causing a significant drop in the receiver's sensitivity at specific frequencies, also known as desense.

[0043] Desensitization is a common phenomenon in some communication systems operating in the common 2.4 GHz ISM band, particularly narrowband systems such as Bluetooth. It's present in chips from virtually every mainstream manufacturer, both domestically and internationally. The primary cause of this desensitization is that harmonics of the ADC sampling clock and demodulator clock enter the RF path through power / ground coupling, ultimately falling within a specific physical channel within the 2.4 GHz band. In this context, "in-band" refers to the physical channel of a certain width occupied by the wireless signal in the frequency domain.

[0044] For single-carrier communication systems like Bluetooth, in-band harmonics significantly impact the signal-to-noise ratio (SNR), significantly reducing the chip's sensitivity at these frequencies. This results in inconsistent sensitivity across the entire 2.4GHz band, creating a limited number of "pitfalls." While Bluetooth's frequency hopping mechanism can mitigate the impact of these "pitfalls" on communication, their presence still reduces the connection performance of Bluetooth devices, especially in complex environments with congested traffic and limited available frequencies. Most importantly, some device manufacturers utilize fixed-frequency communication mechanisms in the 2.4GHz band. These sensitivity "pitfalls" significantly degrade system communication performance, resulting in inconsistent device connectivity and a communication "shortcoming."

[0045] Taking Bluetooth chips as an example, they typically use an external crystal (crystal oscillator) as their clock source. The chip's internal components are divided into two parts: analog and digital circuits. For example, the digital circuit portion may include an ADC and a digital baseband signal processing unit, and the clock for the ADC and / or digital baseband signal processing unit is typically provided by an external crystal (e.g., a crystal oscillator). The RF signal (e.g., data signal) received by the Bluetooth chip is amplified, mixed (e.g., to a low intermediate frequency or zero intermediate frequency), and filtered before being converted to a digital signal by the ADC. This signal is then processed by circuits such as a digital demodulator and a symbol detector.

[0046] When the chip is operating, higher-order harmonics of the ADC sampling clock and the digital baseband clock can couple into the RF path and enter the signal band, causing single-frequency interference within the digital baseband signal. When the RX (receiver) receives weak signals (for example, near the sensitivity level), the received signal quality may deteriorate, significantly reducing the chip's reception performance. The most obvious indicator is that the chip's sensitivity at these harmonic frequencies deteriorates, significantly lower than the reception sensitivity at the frequencies to the left and right, with a difference of 7 to 8 dB or more. This difference is more pronounced for more sensitive communication system chips. Figure 1 A schematic diagram illustrating a situation where clock harmonic interference is mixed into a band according to an embodiment of the present disclosure is shown.

[0047] Bluetooth systems operate in the ISM (Industrial Scientific and Medical) band, for example, 2402-2480 MHz. Assuming a 32 MHz clock source and a 16 MHz ADC sampling clock, the 151st to 155th harmonics of this clock frequency will fall in the 2416, 2432, 2448, 2464, and 2480 MHz bands, respectively, causing sensitivity degradation at these integer frequencies. Consequently, the chip will experience sensitivity dips at 16 MHz intervals across the entire 2.4 GHz band, degrading communication quality in frequency-hopping systems. This is unacceptable to most customers.

[0048] Currently, there's no effective solution to the aforementioned problem of internal chip clock harmonics interfering with signals. Many existing methods for reducing harmonic interference target board-level systems, employing shielding, isolation, filtering, and other methods to enhance electromagnetic compatibility. However, there's no particularly effective solution for internal chip clock harmonic interference.

[0049] In practice, the ADC sampling clock generally contributes significantly to sensitivity degradation, yet current harmonic elimination methods fail to fundamentally address this issue. To address the sensitivity degradation caused by ADC sampling and digital clock harmonics, the present disclosure employs a spectrum shifting method. This shifts the higher-order harmonics of the ADC sampling clock and digital clock (e.g., harmonics that interfere with the receive channel or fall within the receive channel range) away from their original locations, thereby eliminating the impact of the original harmonic interference on signal sensitivity.

[0050] The disclosed method solves the sensitivity degradation problem caused by ADC sampling and digital clock harmonics. This solution requires minimal hardware resources and offers stable and reliable performance, fundamentally eliminating the sensitivity degradation caused by ADC sampling and digital clock harmonics. The wireless receiver chip's sensitivity no longer differs between normal and harmonic frequencies, maintaining the same optimal performance across the entire available frequency band.

[0051] Next, Figure 2 A schematic diagram of a system for eliminating clock harmonics of an ADC sampling clock and a digital baseband signal processing unit clock according to an embodiment of the present disclosure is shown.

[0052] like Figure 2 As shown, the harmonic cancellation circuit for the ADC sampling clock and baseband clock according to an embodiment of the present disclosure may include three parts: a fractional-frequency phase-locked loop (PFL) of a receiver, a digital clock generation circuit, an analog-to-digital converter (ADC), and a digital baseband signal processing unit (or simply referred to as a digital baseband (BB)). The PFL is responsible for generating and receiving a clock signal for signal mixing (e.g., the output of a voltage-controlled oscillator (VCO), also referred to herein as a mixing signal); the digital clock generation circuit is responsible for generating the ADC sampling clock and the digital baseband clock signal; the ADC and the digital baseband signal processing unit are used to convert analog signals to digital signals at a specific sampling rate, and to demodulate and detect the digital signals.

[0053] In wireless communication chip systems, a fractional-N phase-locked loop (PLL) is a commonly used PLL. Its structure can include a phase detector (PD), a charge pump (CP), a loop filter (LF), a voltage-controlled oscillator (VCO), and a multi-mode divider (MMD). The receiver receives an over-the-air wireless signal (e.g., a data signal) through an antenna and a matching network. After passing through a low-noise amplifier (LNA), it is mixed with the output of the VCO of the PLL (e.g., a mixing signal) to generate a low-intermediate-frequency (LIF) signal. This signal then passes through a filter circuit and is input into an analog-to-digital converter (ADC), ultimately converting it into a digital signal at a specific sampling rate. The digital signal then passes through digital circuits such as synchronization, demodulation, and detection to ultimately obtain the information bits sent by the transmitter.

[0054] The present disclosure proposes a new technical solution, namely, by changing (fine-tuning) the sampling clock of the ADC and the clock frequency of the digital baseband, the harmonic components of the interference source can be transferred from the signal band to the outside of the band and filtered out, thereby eliminating the impact of the harmonic components on the interfered frequency of the receiver, that is, eliminating the deterioration of the receiver's sensitivity.

[0055] Figure 2 The digital clock generation circuit portion may include two frequency divider circuits and a clock selection circuit. Frequency divider circuit 1 (also referred to herein as the first frequency divider circuit) can be used to generate a clock for a common frequency (i.e., a frequency not interfered with by clock harmonic components). In this case, the clock source for the analog-to-digital converter and digital baseband is a crystal oscillator (also referred to herein as the first clock source) that passes through the clock output of frequency divider circuit 1 (e.g., clock 1, also referred to herein as the first clock signal). For example, if a 32MHz crystal oscillator is used and the ADC and digital baseband use a 16MHz clock frequency, frequency divider circuit 1 can be a simple divide-by-2 circuit. The frequency division coefficient of frequency divider circuit 1 can be determined by the multiple of the crystal oscillator's clock frequency relative to the clock frequency used by the ADC and / or digital baseband. In another embodiment, if the ADC and digital baseband use a 32MHz clock frequency, frequency divider circuit 1 may not be required to divide the crystal oscillator clock output from the first clock source (also referred to herein as the third clock signal). It should be understood that the specific values ​​of the signal frequencies described in the embodiments of the present disclosure (eg, 32 MHz, 16 MHz, etc.) are merely examples, and the embodiments of the present disclosure may also adopt signal frequencies of any other values, and the present disclosure does not impose any limitation thereto.

[0056] Frequency divider circuit 2 (also referred to herein as the second frequency divider circuit) can be used to generate a clock for a disturbed frequency (i.e., a frequency affected by harmonic interference). In this case, the analog-to-digital converter (ADC) and digital baseband clocks are derived from the fractional-frequency phase-locked loop (FNPL) voltage-controlled oscillator (VCO) output, which is the mixing signal from the low-IF receiver. The voltage-controlled oscillator (VCO) output passes through frequency divider circuit 2 to generate an ADC sampling clock and a digital baseband clock (e.g., clock 2, also referred to herein as the second clock signal) approximately 16 MHz. Clocks 1 and 2 can be selected by a clock selector circuit based on the channel frequency to generate the clocks ultimately used for ADC sampling and digital baseband signal processing. The ADC sampling clock and the digital baseband signal processing clock can be of the same frequency or / and can be simply divided by integers (e.g., an integer multiple of each other). After passing the ADC, the digital baseband signal processing unit can demodulate and detect information bits. The clock harmonics referred to herein generally refer to harmonics generated by the clocks used for ADC sampling or digital baseband processing.

[0057] Figure 3An example flow chart of digital baseband signal processing according to an embodiment of the present disclosure is shown.

[0058] like Figure 3 As shown, the received data signal is converted to a digital signal via an analog-to-digital converter (ADC) with a sampling rate slightly less than 16 MHz (for example, in a low local oscillator architecture, which will be described in further detail below). The clock harmonic frequency (after mixing in the low local oscillator structure) is at the direct current (DC) frequency of the digital signal (i.e., at zero frequency). A high-pass filter (HPF) can be used to filter out these clock harmonics, thereby eliminating interference from the clock harmonics in the receiver.

[0059] The signal is then downconverted to baseband via a downconversion module and then filtered through a channel filter to remove out-of-band noise and interference. Because the entire digital baseband sampling clock is slightly less than 16 MHz, this is equivalent to an additional sampling rate deviation between the transceiver and the receiver. This deviation can then be compensated for by subsequent circuit modules. Figure 3 The sampling rate compensation module in can achieve this function. The sampling rate compensation can utilize any known symbol synchronization estimation and compensation algorithm, such as early-late-gate, Gardner algorithm, etc. Usually, such estimation and compensation circuits already exist in most receivers (e.g., Bluetooth receivers) (for example, used to compensate for the sampling rate deviation caused by the crystal deviation between transceivers). Therefore, it is only necessary to slightly modify the existing estimation and compensation circuit and add an additional compensation amount for the sampling rate deviation introduced by the embodiment of the present disclosure to eliminate clock harmonics. After the sampling rate is restored, the data is processed by the synchronization module, demodulation module, symbol detection module, etc., and the bit information in the data packet can be restored. In this article, for the convenience of description, the signals used to carry data transmission can be collectively referred to as data signals from the RF signal stage received by the antenna to the digital signal stage after ADC sampling.

[0060] In the following, a Bluetooth low intermediate frequency (BIF) receiver is used as an example for further exemplary description.

[0061] A low-IF architecture refers to an architecture in which wireless signals received by a receiver are mixed down to a low-IF frequency. A Bluetooth receiver (RX) employs a low-IF architecture, assuming a low-IF (IF) of 1MHz or 2MHz. Whether the IF is 1MHz or 2MHz depends on the Bluetooth data rate mode. The receiver typically employs a low-LO architecture: a fractional-N phase-locked loop (FNPL) generates a local oscillator (LO) clock (e.g., the mixing signal described above) at a frequency lower than the RF signal frequency (e.g., the center frequency of the data channel) by one IF.

[0062] According to an embodiment of the present disclosure, Figure 2 In the frequency division circuit 2 shown, the harmonic order (also called the harmonic order) of the clock harmonics that fall within the signal band (i.e., the data channel) can be used as the frequency division coefficient: for the 1Mbps mode of the BLE (Bluetooth Low Energy) system standard (taking this mode as an example, the frequency ranges from 2402MHz to 2480MHz, with a frequency interval of 2MHz, and a total of 40 channels), as described above, the sensitivity deterioration frequencies (harmonic frequencies) are 2416MHz, 2432MHz, 2448MHz, 2464MHz, and 2480MHz, respectively, corresponding to the 151st, 152nd, 153rd, 154th, and 155th harmonics of the 16MHz clock (still assuming the ADC sampling clock is 16MHz). At these five sensitivity-deteriorating frequency points, assuming the system uses a low local oscillator architecture with a 1MHz intermediate frequency, the VCO clock outputs are 2415MHz, 2431MHz, 2447MHz, 2463MHz, and 2479MHz, respectively. By dividing each VCO clock output by 151, 152, 153, 154, and 155 times, we can obtain ADC sampling clock frequencies and digital baseband clock frequencies of 15.993377MHz, 15.993421MHz, 15.993464MHz, 15.993506MHz, and 15.993548MHz, respectively.

[0063] As a result, the harmonics of the ADC sampling clock and digital baseband clock at these sensitivity-degrading frequencies (the 151st, 152nd, 153rd, 154th, and 155th harmonics) fall at 2415MHz, 2431MHz, 2447MHz, 2463MHz, and 2479MHz, respectively. These frequencies are exactly 1MHz lower than the in-band signal frequencies (for example, 2416MHz, 2432MHz, 2448MHz, 2464MHz, and 2480MHz) (consistent with the used IF frequency). This prevents interference with the in-band signal and makes it possible to resolve the sensitivity degradation issue at the clock harmonic frequencies.

[0064] Figure 4 The schematic diagram of spectrum shifting of signals and harmonics under a 1 MHz low intermediate frequency architecture according to an embodiment of the present disclosure is further shown. Specifically, Figure 4 The upper middle portion shows a situation where a crystal oscillator is used as the clock source to generate a 16 MHz clock, which is used as the ADC sampling clock and the digital baseband clock, and its harmonics fall within the Bluetooth band (e.g., one or more channels); Figure 4The lower middle section shows the relative positions of the harmonics and Bluetooth signal on the frequency axis, using the VCO as the clock source, to generate a clock slightly below 16MHz. This is used as the ADC sampling clock and the digital baseband clock. As can be seen, by using the VCO's mixed signal as the clock source, the harmonics that affect the system's receiver sensitivity are moved out of band, effectively resolving the sensitivity degradation issue.

[0065] from Figure 4 As can be seen, the clock harmonics are downconverted to a DC frequency after RF mixing (for example, the 2399 MHz harmonics are mixed with the 2399 MHz VCO mixing signal and then converted to a zero frequency). This can be eliminated using a simple high-pass filter (HPF). Due to the ADC sampling rate variation, a sampling rate deviation occurs between the receiver and transmitter. Subsequent circuit modules can compensate for this sampling rate deviation using any known symbol synchronization estimation and compensation algorithm, such as the early-late-gate algorithm or the Gardner algorithm. The data with the recovered sampling rate passes through the synchronization module, demodulation module, and symbol detection module to recover the bit information in the data packet.

[0066] Some system parameters involved in this disclosure are described below.

[0067] The sampling rate deviation can be calculated using the following sampling rate deviation formula:

[0068] (Formula 1)

[0069] in, is the RF signal frequency (for example, the center frequency of the corresponding channel), is the VCO output frequency of the fractional-frequency phase-locked loop (for example, the frequency of the mixing signal). Indicates the sampling rate deviation of the receiver. A negative number means that the receiver ADC sampling rate is smaller than the normal ADC sampling rate (for example, the ADC sampling rate of the normal frequency point).

[0070] Bluetooth Low Energy (BLE) systems are categorized by symbol rate: 1Msps (Mega symbols per second) and 2Msps, with physical bandwidths of 1MHz and 2MHz, respectively. Generally, for 1Msps BLE mode, the receiver uses a low-IF architecture with a 1MHz intermediate frequency (IF); for 2Msps BLE mode, the receiver uses a low-IF architecture with a 2MHz intermediate frequency (IF).

[0071] The sampling clock (or sampling rate) of the ADC can be expressed as:

[0072] (Formula 2)

[0073] in, Indicates the sampling rate of the ADC, Indicates the frequency of the RF signal. Indicates the frequency of the intermediate frequency signal used, and n indicates the harmonic order of the clock harmonic corresponding to the frequency point.

[0074] Tables 1 and 2 below show the example correspondence between the RF frequency, VCO frequency, harmonic order, ADC sampling rate, and receiver sampling rate deviation RXppm at typical sensitivity degradation frequencies:

[0075] Table 1 BLE 1Msps mode

[0076]

[0077] Table 2 BLE 2Msps mode

[0078]

[0079] Take the harmonic frequency of 2480MHz as an example:

[0080] If the system uses a 1MHz IF architecture (corresponding to BLE's 1Msps mode), the voltage-controlled oscillator (VCO) output is 2479MHz. The 155th harmonic of the original 16MHz clock (2480MHz) will fall within the 2480MHz frequency band. However, using 2479MHz divided by 155 as the ADC sampling clock, the 155th harmonic is at 2479MHz, which is out of band. Therefore, it can be filtered out by the high-pass filter module (this circuit originally exists to filter out the receiver DC).

[0081] If the system uses a 2MHz IF architecture (corresponding to BLE's 2Msps mode), the voltage-controlled oscillator (VCO) output is 2478MHz. The 155th harmonic of the original 16MHz clock (2480MHz) will fall within the 2480MHz frequency band. However, using 2478MHz divided by 155 as the ADC sampling clock, the 155th harmonic is at 2478MHz, which is out of band. Therefore, it can be filtered out by the high-pass filter module (this circuit originally exists to filter out the receiver DC).

[0082] The following describes the processing flow for common frequencies (eg, frequencies or channels not interfered by clock harmonics of the ADC and digital circuits) and frequencies with degraded sensitivity.

[0083] like Figure 2As shown in the figure, as previously described, clocks 1 and 2 can be used to generate the clocks ultimately used for ADC sampling and digital baseband signal processing through a clock selector circuit, based on channel frequency categories (e.g., normal frequencies (also referred to as the first category) and harmonic frequencies (also referred to as the second category)). Channel frequencies can be categorized as normal frequencies and harmonic frequencies (sensitivity-degraded frequencies). At normal frequencies, clock 1 can be used as the ADC sampling clock and digital baseband signal processing clock; at harmonic frequencies, clock 2 can be used as the ADC sampling clock and digital baseband signal processing clock.

[0084] After the receiver is powered on, it receives the receiving frequency transmitted from the link layer. The digital-analog interface circuit can control the clock selector according to the type of the receiving frequency (for example, Figure 2 The selector in the output is divided into two categories as described above, namely, the common frequency and the harmonic frequency, and the corresponding processing is carried out respectively. If the current frequency is the common frequency, the data is received according to the common Bluetooth receiving circuit process, and the digital baseband does not need to be Do special sampling rate deviation compensation; if the current frequency point is a harmonic frequency point, you can wait for the fractional frequency phase-locked loop to stabilize, select clock 2 as the ADC sampling clock and the digital baseband clock, and the digital baseband can also be adjusted accordingly. Do additional sampling rate deviation compensation. For example, according to different symbol rates and different harmonic frequencies, select the corresponding The compensation amount is used to compensate for the sampling rate deviation. The compensation amount can be determined in advance and stored in the storage unit of the receiver. For a specific example control flow, please refer to Figure 6 .

[0085] Figure 5 FIG. 1 shows a schematic diagram of a sampling rate deviation calibration circuit according to an embodiment of the present disclosure. Figure 5 As shown, the sampling rate deviation calibration circuit according to an embodiment of the present disclosure may include two components: a timing error estimation and compensation circuit; and a sampling rate deviation compensation circuit for sampling rate deviation caused by harmonic cancellation. When the current frequency is a normal frequency, a selector may select a value of '0' and add it to the error accumulator. When the current frequency is a harmonic frequency, the selector may read a corresponding value (the aforementioned compensation amount) from a sampling rate deviation value storage unit based on the current frequency value and add it to the error accumulator (e.g., according to Table 1, Table 2, etc.). The storage unit may be in any form, such as a register, ROM, or RAM, and is not limited herein.

[0086] exist Figure 5In the embodiment, the timing error estimation and compensation circuit can be any existing general-purpose timing error estimation and compensation circuit in a receiver, and the sampling rate deviation compensation circuit can be a compensation circuit for the sampling rate deviation introduced by harmonic cancellation in the present disclosure. As described above, the data signal can be compensated simply by adding a compensation amount for the sampling rate deviation introduced by harmonic cancellation to any existing general-purpose timing error estimation and compensation circuit.

[0087] It should be understood that, depending on the signal processing capability range of the sampling rate estimation and compensation unit (also known as the clock timing recovery unit), the size of the introduced sampling rate deviation, the wireless protocol packet length and other factors, specific sampling rate deviation compensation introduced for harmonic elimination may not be performed, and this article does not impose any restrictions.

[0088] Figure 6 A corresponding exemplary control flow diagram of a state machine of a chip digital circuit according to an embodiment of the present disclosure is shown.

[0089] Referring to Tables 1 and 2, for common and harmonic frequencies, the ADC sampling rate difference is minimal, so no additional modifications are required to the ADC design. Simply switching the clock in the chip's state machine based on the channel type is sufficient. The digital baseband clock changes are also relatively small, and the clock period is slightly increased. Therefore, this does not increase the critical path in the digital circuit (due to the looser constraints). Overall, the only major circuits or modules added to the present invention compared to a general-purpose receiver are the frequency divider circuit for clock 2 and some control logic. Therefore, the present invention can address the sensitivity degradation caused by ADC sampling clock harmonics and digital baseband clock harmonics while significantly reducing circuit area.

[0090] The above description uses a low-IF Bluetooth receiver as an example to illustrate embodiments of the present disclosure. It should be understood that the circuit block diagrams, control flows, and the like shown above are merely examples, and that the present disclosure may incorporate any additions, deletions, substitutions, or combinations of these circuit block diagrams, control flows, and the like, without limitation. For example, the above description uses a fractional-frequency phase-locked loop as an example, but the present disclosure may employ any other type of phase-locked loop, without limitation.

[0091] Furthermore, while the above description uses a low local oscillator architecture as an example, it should be understood that in other embodiments, the receiver may also employ a high local oscillator architecture. Specifically, the frequency of the local oscillator clock (e.g., the mixing signal described above) generated by the fractional-frequency phase-locked loop is higher than the RF signal frequency (e.g., the center frequency of the data channel) by an intermediate frequency. In this case, the frequency of the second clock signal described above may be higher than the frequency of the first clock signal.

[0092] Next, more generally, Figure 7FIG. 7 is a schematic flow chart of a method 700 for data signal processing according to an embodiment of the present disclosure.

[0093] like Figure 7 As shown, the method 700 for data signal processing according to an embodiment of the present disclosure may include: in step S701, obtaining frequency information of a channel for transmitting a data signal; in step S702, determining the frequency category of the channel based on the frequency information; in step S703, when the frequency category is determined to be the first category, obtaining a first clock signal from a first clock source, and performing analog-to-digital conversion sampling and digital baseband signal processing of the data signal based on the first clock signal; and in step S704, when the frequency category is determined to be the second category, obtaining a second clock signal from a mixing signal for mixing with the data signal, and performing analog-to-digital conversion sampling and digital baseband signal processing of the data signal based on the second clock signal.

[0094] In some embodiments, obtaining the first clock signal from the first clock source may include obtaining, from the first clock source, a third clock signal output by the first clock source. In some embodiments, the third clock signal may be directly used as the first clock signal. In some embodiments, the third clock signal may be divided based on a first frequency division coefficient to obtain the first clock signal. In some embodiments, as described above, the first frequency division coefficient may be a multiple of the frequency of the third clock signal relative to the frequency of the first clock signal.

[0095] In some embodiments, obtaining the second clock signal from the mixing signal for mixing with the data signal may include dividing the mixing signal based on a second frequency division coefficient to obtain the second clock signal. In some embodiments, the second frequency division coefficient may be a harmonic order of the first clock signal falling into the harmonic of the data channel.

[0096] In some embodiments, the frequency information of the channel includes one or more of the following: a center frequency and / or bandwidth of the channel; a channel number; and a frequency category of the channel, wherein the frequency category may include a first category and a second category. For example, the first category may be a frequency category of a common frequency that is not interfered with by the clock harmonics of the first clock signal, and the second category may be a frequency category of a harmonic frequency that is interfered with by the clock harmonics of the first clock signal.

[0097] In some embodiments, determining the frequency category of a channel based on frequency information may include: determining whether the harmonics of the first clock signal fall into the channel based on the frequency information of the channel; in the case of determining that the harmonics of the first clock signal do not fall into the channel, determining the frequency category as the first category; and in the case of determining that the harmonics of the first clock signal fall into the channel, determining the frequency category as the second category.

[0098] For example, when the frequency information of the channel includes the center frequency and / or bandwidth of the channel, it is possible to directly determine whether the harmonics of the first clock signal fall within the channel range based on the center frequency and / or bandwidth of the channel and the harmonic frequency of the first clock signal, thereby further determining the frequency category of the channel.

[0099] When the channel frequency information includes the channel number, for example, in the 1 Mbps BLE system described above with a frequency range of 2402 MHz to 2480 MHz, a frequency interval of 2 MHz, and a total of 40 channels, the 40 channels can be pre-numbered, for example, from 0 to 39, and the numbers of the channels that are (and / or are not) affected by the clock harmonics of the first clock signal can be pre-determined. Based on this, after receiving the channel number information, it can be directly determined based on the channel number whether the harmonics of the first clock signal fall within the channel range, thereby further determining the channel's frequency category.

[0100] In addition, in the case where the frequency information of the channel already includes the frequency category of the channel, the control logic may also directly perform subsequent selection and processing based on the frequency category.

[0101] In some embodiments, as described above, the frequency of the second clock signal may be lower than the frequency of the first clock signal.

[0102] In some embodiments, the first clock source may be a crystal oscillator clock source.

[0103] In some embodiments, the frequency of the mixing signal may be a first frequency lower than the center frequency of the channel, wherein the first frequency may be determined based on a data rate mode used to transmit the data signal. In other embodiments, the first frequency may also be any other frequency value such that harmonics of the first clock signal do not fall within the range of the data channel.

[0104] In some embodiments, the mixing signal may be generated by a phase-locked loop of a low-IF architecture receiver.

[0105] In some embodiments, when the frequency point category of the channel is determined to be the second category, the digital baseband signal processing may also include sampling rate deviation compensation for analog-to-digital conversion sampling of the data signal based on a first compensation amount, wherein the first compensation amount may be determined based on the frequency of the mixing signal and the center frequency of the channel.

[0106] Figure 8 FIG. 8 is a schematic block diagram of a circuit 800 for data signal processing according to an embodiment of the present disclosure.

[0107] like Figure 8As shown, the circuit 800 for data signal processing according to an embodiment of the present disclosure may include: a digital clock generating unit 801 , an analog-to-digital converter 802 , a digital baseband signal processing unit 803 and a control unit 804 .

[0108] In some embodiments, the control unit 804 can be configured to: obtain frequency information of a channel used to transmit a data signal; determine the frequency category of the channel based on the frequency information; when the frequency category is determined to be the first category, control the digital clock generation unit 801 to obtain a first clock signal from a first clock source, and respectively control the analog-to-digital converter 802 and the digital baseband signal processing unit 803 to perform analog-to-digital conversion sampling and digital baseband signal processing of the data signal based on the first clock signal; and when the frequency category is determined to be the second category, control the digital clock generation unit 801 to obtain a second clock signal from a mixing signal used for mixing with the data signal, and respectively control the analog-to-digital converter 802 and the digital baseband signal processing unit 803 to perform analog-to-digital conversion sampling and digital baseband signal processing of the data signal based on the second clock signal.

[0109] In some embodiments, the circuit 800 may further include a first frequency dividing circuit.

[0110] In some embodiments, controlling the digital clock generation unit 801 to obtain the first clock signal from the first clock source may include controlling the digital clock generation unit 801 to obtain a third clock signal from the first clock source; and controlling the digital clock generation unit 801 to use the third clock signal as the first clock signal, or to divide the third clock signal based on a first frequency division coefficient using a first frequency division circuit to obtain the first clock signal. In some embodiments, as described above, the first frequency division coefficient may be a multiple of the frequency of the third clock signal relative to the frequency of the first clock signal.

[0111] In some embodiments, the circuit 800 may further include a second frequency dividing circuit.

[0112] In some embodiments, controlling the digital clock generation unit 801 to obtain the second clock signal from the mixed signal for mixing with the data signal may include controlling the digital clock generation unit 801 to divide the mixed signal based on a second frequency division coefficient using a second frequency division circuit to obtain the second clock signal. In some embodiments, the second frequency division coefficient may be a harmonic order of the harmonic of the first clock signal falling into the data channel.

[0113] In some embodiments, the frequency information of the channel includes one or more of the following: a center frequency and / or bandwidth of the channel; a channel number; and a frequency category of the channel, wherein the frequency category may include a first category and a second category. For example, the first category may be a frequency category of a common frequency that is not interfered with by the clock harmonics of the first clock signal, and the second category may be a frequency category of a harmonic frequency that is interfered with by the clock harmonics of the first clock signal.

[0114] In some embodiments, determining the frequency category of a channel based on frequency information may include: determining whether the harmonics of the first clock signal fall into the channel based on the frequency information of the channel; in the case of determining that the harmonics of the first clock signal do not fall into the channel, determining the frequency category as the first category; and in the case of determining that the harmonics of the first clock signal fall into the channel, determining the frequency category as the second category.

[0115] In some embodiments, as described above, the frequency of the second clock signal may be lower than the frequency of the first clock signal.

[0116] In some embodiments, the first clock source may be a crystal oscillator clock source.

[0117] In some embodiments, the frequency of the mixing signal may be lower than a center frequency of the channel by a first frequency, wherein the first frequency may be determined based on a data rate mode used to transmit the data signal.

[0118] In some embodiments, the circuit 800 may further include a phase-locked loop of a low-IF architecture receiver, wherein the mixing signal may be generated by the phase-locked loop.

[0119] In some embodiments, the digital baseband signal processing unit 803 may further include a compensation circuit. In some embodiments, when the frequency category of the channel is determined to be the second category, the digital baseband signal processing may further include compensating for sampling rate deviation of analog-to-digital conversion of the data signal by the compensation circuit based on a first compensation amount, wherein the first compensation amount may be determined based on the frequency of the mixing signal and the center frequency of the channel.

[0120] An embodiment of the present disclosure further provides a computer-readable medium having instructions stored thereon. When executed, the instructions may be used to implement the method 700 described above or any other method according to an embodiment of the present disclosure.

[0121] It should be understood that the methods described above in conjunction with various embodiments or drawings are merely examples. The embodiments of the present disclosure may also make any additions, deletions, replacements, or combinations of the steps or elements in the methods shown above. The steps in the methods in the embodiments of the present disclosure may be executed in parallel or in any other order not shown, and this document does not limit this. For example, the first clock signal and / or the second clock signal as described above may be acquired or generated before determining the frequency category of the channel. In this way, after determining the frequency category of the channel, it may be directly (for example, by Figure 2 The selector shown in FIG4 selects the corresponding clock signal for subsequent processing.

[0122] Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.

[0123] Nothing in this disclosure should be construed as implying that any particular element, step, or function is an essential element that must be included in the claims scope. The scope of the patented subject matter is defined solely by the claims.

[0124] Exemplary embodiments of the present disclosure have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise indicated. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made to the present disclosure without departing from the spirit and scope of the claims.

Claims

1. A method for data signal processing, comprising: Acquiring frequency information of a channel used to transmit the data signal; Determining a frequency category of the channel based on the frequency information; When the frequency point category is determined to be the first category, obtaining a first clock signal from a first clock source, and performing analog-to-digital conversion sampling and digital baseband signal processing on the data signal based on the first clock signal; as well as When the frequency point category is determined to be the second category, a second clock signal is obtained from a mixing signal for mixing with the data signal, and analog-to-digital conversion sampling and digital baseband signal processing of the data signal are performed based on the second clock signal. The step of obtaining the second clock signal from the mixing signal for mixing with the data signal comprises: Divide the mixed signal by a second frequency division coefficient to obtain the second clock signal, The second frequency division coefficient is the harmonic order of the first clock signal falling into the harmonic of the channel; The determining of the frequency category of the channel based on the frequency information includes: determining, based on the frequency information, whether harmonics of the first clock signal fall into the channel; In a case where it is determined that the harmonics of the first clock signal do not fall into the channel, determining the frequency point category as the first category; and In the case where it is determined that the harmonics of the first clock signal fall into the channel, the frequency point category is determined to be the second category.

2. The method according to claim 1, wherein Acquiring a first clock signal from a first clock source includes: Obtaining a third clock signal from the first clock source; and using the third clock signal as the first clock signal, or dividing the third clock signal based on a first frequency division coefficient to obtain the first clock signal, The first frequency division coefficient is a multiple of the frequency of the third clock signal relative to the frequency of the first clock signal.

3. The method according to claim 1, wherein The frequency information includes one or more of the following: The center frequency and / or bandwidth of the channel; the number of the channel; The frequency category of the channel, wherein the frequency category includes the first category and the second category.

4. The method according to claim 1, wherein The frequency of the second clock signal is lower or higher than the frequency of the first clock signal.

5. The method according to claim 1, wherein The first clock source is a crystal oscillator clock source.

6. The method according to claim 1, wherein The frequency of the mixing signal is lower than the center frequency of the channel by a first frequency, The first frequency is determined based on a data rate mode used to transmit the data signal.

7. The method according to claim 1, wherein The mixed signal is generated by a phase-locked loop of a low intermediate frequency architecture receiver.

8. The method according to claim 1, wherein When the frequency point category is determined to be the second category, the digital baseband signal processing further includes: Compensating for a sampling rate deviation of analog-to-digital conversion of the data signal based on a first compensation amount, The first compensation amount is determined based on the frequency of the mixing signal and the center frequency of the channel.

9. A circuit for data signal processing, comprising: Digital clock generation unit; analog-to-digital converters; Digital baseband signal processing unit; and A control unit, wherein the control unit is configured to: Acquiring frequency information of a channel used to transmit the data signal; Determining a frequency category of the channel based on the frequency information; When the frequency point category is determined to be the first category, controlling the digital clock generating unit to obtain a first clock signal from a first clock source, and controlling the analog-to-digital converter and the digital baseband signal processing unit to perform analog-to-digital conversion sampling and digital baseband signal processing on the data signal based on the first clock signal, respectively; and When the frequency point category is determined to be the second category, controlling the digital clock generating unit to obtain a second clock signal from a mixing signal for mixing with the data signal, and controlling the analog-to-digital converter and the digital baseband signal processing unit to perform analog-to-digital conversion sampling and digital baseband signal processing on the data signal based on the second clock signal, respectively; Wherein, the circuit further includes a second frequency dividing circuit, and The step of controlling the digital clock generating unit to obtain the second clock signal from the mixing signal for mixing with the data signal comprises: controlling the digital clock generating unit to divide the frequency of the mixed signal based on a second frequency division coefficient through the second frequency division circuit to obtain the second clock signal, The second frequency division coefficient is the harmonic order of the first clock signal falling into the harmonic of the channel; The determining of the frequency category of the channel based on the frequency information includes: determining, based on the frequency information, whether harmonics of the first clock signal fall into the channel; In a case where it is determined that the harmonics of the first clock signal do not fall into the channel, determining the frequency point category as the first category; and In the case where it is determined that the harmonics of the first clock signal fall into the channel, the frequency point category is determined to be the second category.

10. The circuit according to claim 9, wherein The circuit further includes a first frequency dividing circuit, and The step of controlling the digital clock generating unit to obtain the first clock signal from the first clock source includes: controlling the digital clock generating unit to obtain a third clock signal from the first clock source; and controlling the digital clock generating unit to use the third clock signal as the first clock signal, or dividing the third clock signal by the first frequency dividing circuit based on a first frequency dividing coefficient to obtain the first clock signal, The first frequency division coefficient is a multiple of the frequency of the third clock signal relative to the frequency of the first clock signal.

11. The circuit according to claim 9, wherein The frequency information includes one or more of the following: The center frequency and / or bandwidth of the channel; the number of the channel; The frequency category of the channel, wherein the frequency category includes the first category and the second category.

12. The circuit according to claim 9, wherein The frequency of the second clock signal is lower or higher than the frequency of the first clock signal.

13. The circuit according to claim 9, wherein The first clock source is a crystal oscillator clock source.

14. The circuit according to claim 9, wherein The frequency of the mixing signal is lower than the center frequency of the channel by a first frequency, The first frequency is determined based on a data rate mode used to transmit the data signal.

15. The circuit of claim 9, wherein: The circuit also includes a phase-locked loop of a low intermediate frequency architecture receiver, Wherein, the mixing signal is generated by the phase-locked loop.

16. The circuit of claim 9, wherein: The digital baseband signal processing unit further includes a compensation circuit, Wherein, when the frequency point category is determined to be the second category, the digital baseband signal processing further includes: Compensating for a sampling rate deviation of analog-to-digital conversion sampling of the data signal by the compensation circuit based on a first compensation amount, The first compensation amount is determined based on the frequency of the mixing signal and the center frequency of the channel.

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