A distributed chip backplane traffic load balancing method and device

Abstract

The present disclosure relates to the technical field of communication load balancing, and particularly relates to a distributed chip backplane traffic load balancing method and device. A service chip FAP is connected through a cross chip FE; the FAP and the FE periodically send control cells to adjacent chips, and update a routing table by recording the link of receiving the control cell and the content of the control cell; the FE dynamically adjusts the reachable link quantity according to the real-time link quantity of each FAP in the routing table. The present disclosure can effectively solve the traffic imbalance problem of inconsistent links on the backplane side of the entry disc and the exit disc for the distributed device. For the cross disc, the traffic borne by each link corresponding to the entry disc and the exit disc can be completely equal, the traffic is more balanced, and the exit congestion problem is effectively solved.

Description

Technical Field

[0001] This disclosure relates to the field of communication load balancing technology, and in particular to a distributed chip backplane traffic load balancing method and apparatus. Background Technology

[0002] In existing transmission networks, distributed devices are widely used. Service boards responsible for service forwarding and cross-connect boards responsible for traffic forwarding are connected through backplane connectors. Due to the insertion and removal of equipment and aging, the high-speed backplane connectors will inevitably become damaged and unusable. At this time, the service boards interconnected at both ends will be connected to the service boards, and the inlet and outlet links of the cross-connect boards will be unbalanced, resulting in uneven traffic on the backplane. In extreme cases, it will lead to outlet congestion.

[0003] In summary, there is an urgent need for a distributed chip backplane traffic load balancing solution. Summary of the Invention

[0004] To address the aforementioned issues, this disclosure provides a distributed chip backplane traffic load balancing method and apparatus, which solves the problems of imbalance between inlet and outlet boards caused by physical damage to the backplane connectors of distributed device boards, backplane traffic imbalance, and outlet congestion caused by the imbalance.

[0005] A first aspect includes a distributed chip backplane traffic load balancing method, the method comprising:

[0006] The service chip FAP is connected via the cross-connect chip FE;

[0007] FAP and FE periodically send control cells to adjacent chips and update their routing tables by recording the connection link that receives the control cells and the contents of the control cells; the link represents the connection between FAP and FE.

[0008] The FE dynamically adjusts the number of reachable links based on the real-time link count of each FAP in the routing table.

[0009] Furthermore, the routing table is located in the FAP chip and FE chip, and is used to record the connection links and reachable FAPs;

[0010] The routing table uses FAP_ID as the key and stores a bitmap, where each bit in the bitmap represents a link on the chip.

[0011] Furthermore, when the FAP goes online for the first time, the FE allocates the initial total number of reachable links by sending control cells and assigns the same initial score to each link;

[0012] The initial total number of reachable links includes: when the chip first comes online, it sends a control cell containing its own chip ID to each link; the control cell sent by the FAP; when the FE receives the control cell, it considers the link reachable; and finally, an initial total number of reachable links to the FAP is obtained.

[0013] Furthermore, the FE dynamically adjusts the number of reachable links based on the real-time link count of each FAP in the routing table, including:

[0014] The FE monitors the link status in real time and calculates the current number of reachable links.

[0015] The real-time reachable link count includes: the chip sending control cells containing its own chip ID to each link in real time, and the control cells sent by the FAP. If the FE receives the control cells, it considers the link reachable from the FAP. If it does not receive them, it considers the link unreachable from the FAP. Finally, the real-time reachable link count (active links) is obtained.

[0016] FE calculates the realtime score based on the number of real-time reachable links. The realtime score is calculated as: (Number of real-time reachable links / Initial total number of reachable links) * Total score.

[0017] The total score is the static configuration parameter of FE, which is set when the device is powered on for the first time;

[0018] During route forwarding, the FE removes links with link score > realtime score from the routing table, thereby achieving load balancing.

[0019] The link score is set as follows:

[0020] The step value is calculated using the number of parallel links connected on the FE and the total score;

[0021] Step value = Total score / Number of connections;

[0022] Choose a random order and set the link score for each link connection on the FE to 0, one step value, two step value, and so on, until all link connections are assigned a value.

[0023] Furthermore, the FE dynamically adjusts the number of reachable links based on the real-time link count of each FAP in the routing table, and also includes:

[0024] When a link of the target FAP becomes unreachable, the FE notifies all FAPs by sending control cells, proportionally reducing the number of reachable links from all source FAPs to the target FAP.

[0025] Secondly, a distributed chip backplane employs the aforementioned distributed chip backplane traffic load balancing method.

[0026] Thirdly, a distributed chip communication method employs the aforementioned distributed chip backplane traffic load balancing method.

[0027] Fourthly, a distributed chip backplane traffic load balancing device includes: a service chip FAP and a cross-connect chip FE; the service chip FAP is connected through the cross-connect chip FE.

[0028] FAP and FE periodically send control cells to adjacent chips and update the routing table by recording the connection link that receives the control cells and the contents of the control cells;

[0029] The FE dynamically adjusts the number of reachable links based on the real-time link count of each FAP in the routing table.

[0030] Fifthly, an electronic device includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus;

[0031] Memory, which stores computer programs;

[0032] When a processor executes a computer program stored in memory, it implements the aforementioned distributed chip backplane traffic load balancing method.

[0033] Sixthly, a computer-readable storage medium storing a computer program that, when executed by a processor, implements the aforementioned distributed chip backplane traffic load balancing method.

[0034] This disclosure has at least the following beneficial effects:

[0035] This disclosure addresses distributed devices and effectively resolves the traffic imbalance issue caused by inconsistent links on the backplane sides of the ingress and egress disks. For cross-connect disks, the traffic carried by each link corresponding to the ingress and egress disks can be completely equal, resulting in more balanced traffic and effectively resolving egress congestion issues.

[0036] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures pointed out in the description and the accompanying drawings. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the load balancing method according to an embodiment of the present disclosure;

[0039] Figure 2 A schematic diagram of the control cell communication mechanism and routing table design between distributed devices FE and FAP;

[0040] Figure 3 A schematic diagram illustrating the actual effect of the routing table generated between distributed devices FE and FAP;

[0041] Figure 4 A schematic diagram illustrating the actual connection effect during initialization between distributed devices FE and FAP;

[0042] Figure 5 A schematic diagram illustrating the data used to calculate the real-time score for a distributed device FE.

[0043] Figure 6 This diagram illustrates the effect of load balancing between distributed devices FE and FAP.

[0044] Figure 7 This is a schematic diagram of the electronic device structure. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0046] The load balancing methods disclosed herein can be widely used in products such as OTN and PTN.

[0047] like Figure 1 As shown, a distributed chip backplane traffic load balancing method is provided, the method comprising:

[0048] The service chip FAP is connected via the cross-connect chip FE;

[0049] S101, FAP and FE periodically send control cells to adjacent chips and update the routing table by recording the connection link that receives the control cells and the contents of the control cells;

[0050] S102, FE dynamically adjusts the number of reachable links based on the real-time number of links for each FAP in the routing table.

[0051] The specific implementation details are as follows:

[0052] A communication mechanism is established at the chip level, consisting of a service chip (hereinafter referred to as FAP) and a cross-connect chip (hereinafter referred to as FE). FAP and FE periodically send control cells to adjacent chips, and automatically calculate and update the routing table by recording the link of the received control cells and the content of the cells.

[0053] The FE dynamically adjusts reachability messages based on the actual number of links in each FAP, thereby regulating the number of reachable links. When a link to the target FAP fails and becomes unreachable, the FE notifies all FAPs through the control cell mechanism, proportionally reducing the number of reachable links from all source FAPs to the target FAP.

[0054] like Figure 2 As shown, FAP and FE periodically send control cells to adjacent chips, and automatically calculate and update the routing table by recording the link that receives the control cells and the content of the cells. The routing table is used in FAP and FE chips to record which FAPs can be reached through which links. The routing table usually stores a bitmap with FAP_ID as the key. Each bit in the bitmap represents a link on the chip.

[0055] The final generated routing table is as follows Figure 3 As shown, FAP_ID1 can be reached via link1 and link2, FAP_ID2 can be reached via link3 and link4, FAP_ID3 can be reached via link1, link2, link3, and link4, but FAP_ID4 is unreachable.

[0056] like Figure 4 As shown, to distinguish between the inlet and outlet, FIP0 and FOP0 are the input and output sides of FAP0, respectively:

[0057] FIP stands for FABRIC INPUT PLANE;

[0058] FOP stands for Fabric Output Plane;

[0059] As shown in the diagram, lines 0, 1, and 2 are connected to FAP0, while lines 3, 4, and 5 are connected to FAP1.

[0060] When a FAP first comes online, the FE will allocate a total number of reachable links to it through the control cell mechanism and assign one score to each link on average. Each FAP has a total score of 120 points (initial configuration), and there are 3 links between each FAP and the FE. Therefore, the scores for each link are as follows: link0: 40, link1: 80, link2: 120 (FAP0), link3: 40, link41: 80, link5: 120 (FAP1).

[0061] Specifically, when a chip first comes online, it sends a control cell containing its own chip ID to each link. The FAP sends this control cell, and the FE (Functional Equipment) considers the link reachable upon receiving it. Ultimately, a total number of links to that FAP is obtained. The reason for assigning scores is related to the subsequent total score; each link has its own score, and subsequent load balancing calculations are based on these scores.

[0062] The Front End (FE) monitors link status in real time and calculates the current number of reachable links (active links). Based on the number of active links, the FE calculates a real-time score: real-time score = actual number of links / total number of links * total score. During route forwarding, the FE removes links with a link score greater than the real-time score from its routing table, thus achieving load balancing.

[0063] Specifically, the number of reachable links (active links) is determined by the chip sending control cells containing its own chip ID to each link in real time. When the FAP sends control cells, the FE considers the link reachable from the FAP if it receives the control cells, and considers the link unreachable from the FAP if it does not receive the control cells.

[0064] The actual number of links is the active link count mentioned above, updated in real time. The total number of links is the total number calculated during the first online deployment. The total score is a static configuration, a fixed value of 120 written to the software during the device's first power-on.

[0065] The link score is assigned upon the first connection. For example, if the total score is 120, and there are 3 links in total, the step size is 40. There are 3 links between each FAP and FE, with a step size of 40. Therefore, the score for each link is as follows: link0: 40, link1: 80, link2: 120.

[0066] like Figure 5 As shown, assuming one outgoing link fails, the actual number of active links is 2. The real-time soreness calculated using the table is 80 points. The actual effect during routing and forwarding is illustrated in the diagram below. Figure 6 As shown, if link3 fails, the traffic to the ingress FAP1 will only flow in from links 0 and 1 during actual routing and forwarding, thus achieving load balancing between the ingress and egress.

[0067] Specifically, the number of reachable links from all source FAPs to the target FAP is reduced proportionally, as shown in the following example:

[0068] Assume that the FE and both FAPs are connected by 3 links, and the link distribution is as follows:

[0069] FAP1:link0:40,link1:80,link2:120;

[0070] FAP2:link3:40,link4:80,link5:120;

[0071] If link 2 of FAP1 is broken, then the realtime score = 2 / 3 * 120 = 80 points. When the FE calculates the route, it will cover the links that can reach FAP2 with a score greater than 80. Therefore, FAP2 will also have one less link.

[0072] Assuming there is another FAP3 that initially has 6 link connections, then the link score is as follows:

[0073] FAP3:link3:20,link4:40,link5:60;

[0074] link6:80,link7:100,link8:120;

[0075] When FE calculates the route to FAP3, FAP3 will simultaneously reduce two links.

[0076] A distributed chip backplane employs the aforementioned distributed chip backplane traffic load balancing method.

[0077] A distributed chip communication method employs the aforementioned distributed chip backplane traffic load balancing method.

[0078] like Figure 2 As shown, a distributed chip backplane traffic load balancing device includes: a service chip FAP and a cross-connect chip FE; the service chip FAP is connected through the cross-connect chip FE.

[0079] FAP and FE periodically send control cells to adjacent chips and update the routing table by recording the connection link that receives the control cells and the contents of the control cells;

[0080] The FE dynamically adjusts the number of reachable links based on the real-time link count of each FAP in the routing table.

[0081] like Figure 7 As shown, this disclosure provides an electronic device, including a processor 701, a communication interface 702, a memory 703, and a communication bus 704, wherein the processor 701, the communication interface 702, and the memory 703 communicate with each other through the communication bus 704;

[0082] Memory 703 stores computer programs;

[0083] The processor 701 implements the above method when executing a computer program stored in the memory 703.

[0084] This disclosure provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0085] The computer-readable storage medium may be included in the device / apparatus described in the above embodiments; or it may exist independently and not assembled into the device / apparatus. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of this disclosure.

[0086] According to embodiments of this disclosure, the computer-readable storage medium can be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0087] Although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A distributed chip backplane traffic load balancing method, characterized in that, The method includes: The service chip FAP is connected via the cross-connect chip FE; FAP and FE periodically send control cells to adjacent chips and update their routing tables by recording the connection link that receives the control cells and the contents of the control cells; the link represents the connection between FAP and FE. The FE dynamically adjusts the number of reachable links based on the real-time link count of each FAP in the routing table; When the FE first comes online at the FAP, it assigns an initial total number of reachable links to the FAP by sending control cells and assigns the same initial score to each link. The initial total number of reachable links includes: when the chip first comes online, it sends a control cell containing the chip ID to each link; the control cell sent by the FAP; when the FE receives the control cell, it considers the link reachable; and finally, an initial total number of reachable links to the FAP is obtained. The FE dynamically adjusts the number of reachable links based on the real-time link count for each FAP in the routing table, including: The FE monitors the link status in real time and calculates the current number of reachable links. The real-time reachable link count includes: the chip sending control cells containing its own chip ID to each link in real time, and the control cells sent by the FAP. If the FE receives the control cells, it considers the link reachable from the FAP. If it does not receive them, it considers the link unreachable from the FAP. Finally, the real-time reachable link count (active links) is obtained. FE calculates the realtime score based on the number of real-time reachable links: realtime score = number of real-time reachable links / initial total number of reachable links * total score; The total score is the static configuration parameter of FE, which is set when the device is powered on for the first time; During route forwarding, the FE removes links with link score > realtime score from the routing table, thereby achieving load balancing. The link score is set as follows: The step value is calculated using the number of parallel links connected on the FE and the total score; Step value = Total score / Number of connections; Choose a random order and set the link score to 0, then a single step value, then a double step value for each link connection on the FE, until all link connections are assigned a score.

2. The distributed chip backplane traffic load balancing method according to claim 1, characterized in that, The routing table is located in the FAP chip and FE chip and is used to record the connection links and reachable FAPs; The routing table uses FAP_ID as the key and stores a bitmap, where each bit in the bitmap represents a link on the chip.

3. The distributed chip backplane traffic load balancing method according to claim 1, characterized in that, The FE dynamically adjusts the number of reachable links based on the real-time link count for each FAP in the routing table, and also includes: When a link of the target FAP becomes unreachable, the FE notifies all FAPs by sending control cells, proportionally reducing the number of reachable links from all source FAPs to the target FAP.

4. A distributed chip backplane, characterized in that, The distributed chip backplane traffic load balancing method according to any one of claims 1-3 is adopted.

5. A distributed chip communication method, characterized in that, The distributed chip backplane traffic load balancing method according to any one of claims 1-3 is adopted.

6. A distributed chip backplane traffic load balancing device, characterized in that, include: Service chip FAP and cross-connect chip FE; Service chip FAP is connected via cross-connect chip FE; FAP and FE periodically send control cells to adjacent chips and update the routing table by recording the connection link that receives the control cells and the contents of the control cells; The FE dynamically adjusts the number of reachable links based on the real-time link count of each FAP in the routing table; When the FE first comes online at the FAP, it assigns an initial total number of reachable links to the FAP by sending control cells and assigns the same initial score to each link. The initial total number of reachable links includes: when the chip first comes online, it sends a control cell containing the chip ID to each link; the control cell sent by the FAP; when the FE receives the control cell, it considers the link reachable; and finally, an initial total number of reachable links to the FAP is obtained. The FE dynamically adjusts the number of reachable links based on the real-time link count for each FAP in the routing table, including: The FE monitors the link status in real time and calculates the current number of reachable links. The real-time reachable link count includes: the chip sending control cells containing its own chip ID to each link in real time, and the control cells sent by the FAP. If the FE receives the control cells, it considers the link reachable from the FAP. If it does not receive them, it considers the link unreachable from the FAP. Finally, the real-time reachable link count (active links) is obtained. FE calculates the realtime score based on the number of real-time reachable links: realtime score = number of real-time reachable links / initial total number of reachable links * total score; The total score is the static configuration parameter of FE, which is set when the device is powered on for the first time; During route forwarding, the FE removes links with link score > realtime score from the routing table, thereby achieving load balancing. The link score is set as follows: The step value is calculated using the number of parallel links connected on the FE and the total score; Step value = Total score / Number of connections; Choose a random order and set the link score to 0, then a single step value, then a double step value for each link connection on the FE, until all link connections are assigned a score.

7. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, which stores computer programs; A processor, when executing a computer program stored in memory, implements a distributed chip backplane traffic load balancing method according to any one of claims 1-3.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements a distributed chip backplane traffic load balancing method according to any one of claims 1-3.

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