Information processing method, parasitic parameter extraction method, device and medium

Abstract

The present application provides an information processing method, including determining grid information of at least one grid used to divide the chip circuit according to graphic information of multiple graphics in the chip circuit, wherein the graphic information includes position information of the graphic in the chip circuit, each of the grids includes multiple grid units, and the grid information of the grid includes position information of each grid unit in the grid; based on the grid information of the at least one grid, determining the graphics associated with each grid unit of the at least one grid. The present application also provides a parasitic parameter extraction method, device and medium. Therefore, the present application can confirm the grid information of at least one grid according to the graphic information of each graphic, thereby determining the graphics associated with the grid unit of the grid, and can quickly obtain the associated graphics according to the grid unit, thereby improving the search efficiency of the graphics, and then, for example, can improve the extraction efficiency of parasitic parameters.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an information processing method, a parasitic parameter extraction method, a device and a medium. Background Art

[0002] As the size of interconnects decreases and the operating frequency of chips increases, the impact of parasitic effects on the performance of integrated circuits becomes more and more significant. Therefore, the extraction of parasitic parameters has always been an important issue in the fields of electronic design automation (EDA). The accuracy and efficiency of graphic search are directly related to the accuracy and application scope of parasitic parameter extraction.

[0003] Currently, standard data structures such as octree (also known as octree) and kd-tree (also known as k-dimensional) are commonly used for graph search. However, standard data structures use the same processing strategy when processing various graphs, which prolongs the graph search time and is inefficient.

[0004] Therefore, it is necessary to provide an information processing method that can improve the search efficiency of graphics. Summary of the invention

[0005] In response to the above technical problems, the present application provides an information processing method to improve the search efficiency of graphics.

[0006] To solve the above technical problems, the present application provides an information processing method, 1. An information processing method, comprising: determining grid information of at least one grid used to divide the chip circuit according to graphic information of multiple graphics in the chip circuit, wherein the graphic information includes position information of the graphic in the chip circuit, each of the grids includes multiple grid units, and the grid information of the grid includes position information of each grid unit in the grid; based on the grid information of the at least one grid, determining the graphics associated with each grid unit of the at least one grid.

[0007] In one embodiment, the chip circuit includes multiple graphic layers in a first direction; wherein, the step of determining the grid information of at least one grid used to divide the chip circuit based on the graphic information of multiple graphics in the chip circuit of the chip includes: determining the grid information of the grid corresponding to each graphic layer based on the graphic information in each graphic layer, wherein each grid is used to divide at least one graphic layer.

[0008] In one embodiment, the at least one grid is a non-uniform grid.

[0009] In one embodiment, the lengths of the grid units in the same grid along the second direction are the same; and / or the lengths of the grid units in the same grid along the third direction are the same; the lengths of the grid units in the same grid along the second direction and along the third direction are different.

[0010] In one embodiment, the step of determining the grid information of the grid corresponding to each graphic layer according to the graphic information of multiple graphics in each graphic layer includes: obtaining the average length of the graphics of the first target graphic layer along the second direction and the average length along the third direction, wherein the first target graphic layer includes at least one graphic layer; obtaining the maximum bounding box of the first target graphic layer, wherein the maximum bounding box is an area that can accommodate all graphics of the first target graphic layer; determining the number of grid units of the first target graphic layer along the second direction and the length of each grid unit along the second direction according to the average length of all graphics of the first target graphic layer along the second direction and the corresponding length of the maximum bounding box along the second direction; determining the number of grid units of the first target graphic layer along the third direction and the length of each grid unit along the third direction according to the average length of all graphics of the first target graphic layer along the third direction and the corresponding length of the maximum bounding box along the third direction.

[0011] In one embodiment, based on the grid information of the at least one grid, obtaining the graphics associated with each grid cell of the at least one grid includes: determining a graphic layer corresponding to the position of each grid; determining a second independent memory array corresponding to each grid based on the graphic layer corresponding to each grid, and determining the graphics associated with the grid cells of each grid based on the graphic information of each graphic stored in the second independent memory array and the position information of the grid cells; and storing the graphic information of the graphics associated with each grid cell in a third independent memory array corresponding to each grid cell.

[0012] The present application also provides an information processing method, including: obtaining position information of a search graphic; determining a target grid unit whose position satisfies a preset condition with respect to the search graphic, wherein grid information of at least one grid is determined based on graphic information of multiple graphics in a chip circuit of a chip, and the at least one grid is used to divide the chip circuit, wherein the graphic information includes position information of the graphic in the chip circuit, and the grid information of the grid includes position information of each grid unit in the grid; and obtaining a target graphic associated with the target grid unit.

[0013] In one embodiment, the step of determining a target grid unit that satisfies a preset condition with a search graph includes: determining a search range corresponding to the search graph based on a preset field range; obtaining a grid that intersects with the search range, and determining the target grid unit that intersects with the search range from a plurality of grid units corresponding to the grid.

[0014] In one embodiment, the step of obtaining, from the multiple grid units, a grid unit intersecting with the search range to obtain the target grid unit includes: obtaining, based on the position range of the search range along a first direction and a first independent memory array, a second target graphic layer whose position range along the first direction intersects with the position range of the search range along the first direction, wherein the first independent memory array stores the position range of each graphic layer along the first direction; confirming the grid corresponding to the second target graphic layer, and obtaining from the grid a grid unit intersecting with the search range in the second direction and / or third direction to obtain the target grid unit.

[0015] In one embodiment, the step of obtaining a target graphic associated with the target grid unit includes: obtaining graphic information of the graphic associated with the target grid unit from a third independent memory array corresponding to the target grid unit, and screening out a graphic whose distance from the search graphic meets a preset requirement as the target graphic.

[0016] The present application also provides a parasitic parameter extraction method, which includes any one of the above methods.

[0017] The present application also provides a device, characterized in that the device includes a memory and a processor, and the processor is used to implement any one of the above methods when executing a computer program in the memory.

[0018] The present application also provides a medium, on which a computer program is stored, and when the computer program is executed by a processor, any of the above methods can be implemented.

[0019] The present application provides an information processing method, including determining grid information of at least one grid used to divide the chip circuit according to graphic information of multiple graphics in the chip circuit, wherein the graphic information includes position information of the graphic in the chip circuit, each of the grids includes multiple grid units, and the grid information of the grid includes position information of each grid unit in the grid; based on the grid information of the at least one grid, determining the graphics associated with each grid unit of the at least one grid. The present application also provides a parasitic parameter extraction method, device and medium. Therefore, the present application can confirm the grid information of at least one grid according to the graphic information of each graphic, thereby determining the graphics associated with the grid unit of the grid, and can quickly obtain the associated graphics according to the grid unit, thereby improving the search efficiency of the graphics, and then, for example, can improve the extraction efficiency of parasitic parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a flowchart of an information processing method according to an embodiment of the present application.

[0021] Figure 2 It is graphic information of a graphic according to an embodiment of the present application.

[0022] Figure 3 It is a schematic diagram of the cross-sectional structure of multiple graphic layers of a chip circuit according to the first embodiment of the present application.

[0023] Figure 4 According to an embodiment of the present application, Figure 3 Schematic diagram of the top view structure of the eighth graphic layer shown.

[0024] Figure 5 It is a flowchart of an information processing method according to another embodiment of the present application.

[0025] Figure 6 It is a cross-sectional schematic diagram of a chip circuit including a search point according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following is an explanation of the implementation of the present application by means of specific embodiments. People familiar with the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.

[0027] In the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It should be understood that other embodiments may also be used, and that mechanical composition, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present application is limited only by the claims of the published patents. The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0028] Although the terms first, second, etc. are used herein to describe various elements in some instances, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0029] Furthermore, as used in this article, the singular forms "one", "an" and "the" are intended to include plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.

[0030] First embodiment

[0031] Figure 1 FIG. 1 is a flow chart of an information processing method according to the first embodiment of the present application. Figure 1 As shown, an information processing method comprises the following steps:

[0032] S10, acquiring graphic information of multiple graphics in the chip circuit;

[0033] In one embodiment, the graphic information of multiple graphics of the layout of the chip circuit can be obtained through the chip design file. Specifically, the graphic information of multiple graphics can be obtained through the LEF (Library Exchange Format) file and / or the DEF (Design Exchange Format) file. Among them, the DEF file is used together with the LEF (Library Exchange Format) file to represent the complete layout of a complex IC design. Specifically, in one embodiment, the multiple graphics of the chip circuit layout can be, but are not limited to, multiple metal wire graphics.

[0034] The graphic information of the graphic includes the position information of the graphic in the chip circuit. The graphic in the general layout is represented by a rectangle. Specifically, in one embodiment, the graphic information of the graphic may include, but is not limited to, the coordinates of the vertices of the graphic and / or the coordinate range of the graphic in the first direction and other position information. Figure 2 As shown, the graphic may be a rectangle, and the graphic information of the graphic may include, for example, the coordinates of the two vertices of the graphic (X0, Y0, Z0), (X1, Y1, Z1). In other embodiments, the graphic information of the graphic may also include information such as the coordinates of the center point of the graphic, the size of the graphic, and the shape of the graphic. Specifically, the graphic information of the graphic may include, for example, at least one of the length of the graphic in the first direction, the length in the second direction, and the length in the third direction. The second direction and the third direction are the plane directions of each metal layer in the layout, i.e., the X-axis direction and the Y-axis direction in the coordinate system, and the first direction is the height direction of the chip, i.e., the Z-axis direction in the coordinate system. The plane coordinates can be stored in one array, and the height coordinates can be stored in another array.

[0035] S11, determining grid information of at least one grid used to divide the chip circuit according to the graphic information of the plurality of graphics;

[0036] Each grid includes a plurality of grid units, and the grid information of the grid includes position information of each grid unit in the grid.

[0037] In one embodiment, at least one grid is a non-uniform grid. Different grids may have different lengths in the first direction. A non-uniform grid refers to a grid in which at least two of the lengths in the first direction, the lengths in the second direction, and the lengths in the third direction of at least one grid unit in the grid are not equal. Compared with a uniform grid, a non-uniform grid can more appropriately associate a grid with a graphic based on graphic information. Specifically, in one embodiment, the lengths of the grid units in the same grid along the second direction are the same; and / or the lengths of the grid units in the same grid along the third direction are the same; the lengths of the grid units in the same grid along the second direction and along the third direction are different.

[0038] In one embodiment, the chip circuit includes a plurality of pattern layers in a first direction, such as Figure 3 As shown, the chip circuit may include the first to eighth graphic layers, each graphic layer represents a metal layer in the layout. Each graphic layer includes multiple graphics, but the present application is not limited thereto.

[0039] In one embodiment, step S11, determining the grid information of at least one grid used to divide the chip circuit according to the graphic information of multiple graphics in the chip circuit of the chip, includes: determining the grid information of the grid corresponding to each graphic layer according to the graphic information in each graphic layer, wherein each grid divides at least one graphic layer. Specifically, in one embodiment, when the grid divides the layout, each grid may include graphics of one graphic layer or more than two graphic layers. After determining the graphic layer of each grid, the grid information of each grid is determined by the graphic information in the graphic layer it divides. In other embodiments, at least one grid is used to divide multiple graphic layers. Specifically, when a grid is used to divide multiple graphic layers, the grid information of the grid can be determined by the graphic information of one graphic layer in the multiple graphic layers, or can be determined by all the graphic information of the multiple graphic layers. Specifically, for example, if the grid is used to divide the 1st to nth graphic layers, the grid information of this grid can be determined by the graphic information of the 1st to nth graphic layers, and n is an integer greater than 1.

[0040] In one embodiment, a graphic layer corresponding to a grid of grid units to be divided is used as a first target graphic layer. The length of the grid units in the grid of the first target graphic layer in the third direction may be determined, but not limited to, according to the length of the graphics of the first target graphic layer in the third direction, and / or the number of graphics of the first target graphic layer in the third direction, and / or the length of the maximum bounding box of the first target graphic layer in the third direction; the length of the grid units corresponding to the first target graphic layer in the second direction may be determined, but not limited to, according to the length of the graphics of the first target graphic layer in the second direction, and / or the number of graphics of the first target graphic layer in the second direction, and / or the length of the maximum bounding box of the first target graphic layer in the second direction; the length of the grid units corresponding to the first target graphic layer in the first direction may be determined, but not limited to, according to the length of the graphics of the first target graphic layer in the first direction, and / or the number of graphics of the first target graphic layer in the first direction, and / or the length of the maximum bounding box of the first target graphic layer in the first direction. Specifically, for example, the length of the grid units corresponding to the first target graphic layer in the second direction may be determined according to at least one of the average value of the lengths of at least two graphics in the first target graphic layer in the second direction, the median value in the second direction, and the longest length in the second direction. For example, the length of the corresponding grid unit in the third direction may be determined based on at least one of the average value of the length in the third direction, the median value of the length in the third direction, and the longest length in the third direction of at least two graphics in the first target graphic layer.

[0041] The first target graphic layer includes at least one graphic layer. The maximum bounding box of the first target graphic layer is the area that can include all graphics of the first target graphic layer. In one embodiment, the maximum bounding box of the first target graphic layer is the minimum area that can include all graphics of the first target graphic layer.

[0042] In one embodiment, step S11, based on the graphic information of multiple graphics in the chip circuit of the chip, determines the grid information of at least one grid used to divide the chip circuit, including: obtaining the average length of the graphics of the first target graphic layer along the second direction and the average length along the third direction; obtaining the maximum bounding box of the first target graphic layer; according to the average length of all graphics of the first target graphic layer along the second direction, and the corresponding length of the maximum bounding box along the second direction, determining the number of grid units of the first target graphic layer along the second direction, and the length of each grid unit along the second direction; according to the average length of all graphics of the first target graphic layer along the third direction, and the corresponding length of the maximum bounding box along the third direction, determining the number of grid units of the first target graphic layer along the third direction, and the length of each grid unit along the third direction.

[0043] In one embodiment, the step of obtaining the maximum bounding box of the first target graphics layer includes: obtaining the maximum coordinate value of the graphics in the first target graphics layer in the second direction, the minimum coordinate value in the second direction, the maximum coordinate value in the third direction, and the minimum coordinate value in the third direction; according to the maximum coordinate value of the graphics in the second direction, the minimum coordinate value in the second direction, the maximum coordinate value in the third direction, and the minimum coordinate value in the third direction, respectively determine the four vertices of the maximum bounding box of the first target graphics layer, so as to determine the coordinate values ​​of the four vertices of the maximum bounding box of the first target graphics layer in the second direction and the third direction. In other embodiments, the step of obtaining the maximum bounding box of the first target graphics layer may also include, but is not limited to: obtaining the maximum coordinate value of the graphics in the first direction and the minimum coordinate value in the first direction; according to the coordinate values ​​of the four vertices of the maximum bounding box and the maximum coordinate value of the graphics in the first direction and the minimum coordinate value in the first direction, determine the coordinate values ​​of the eight vertices of the maximum bounding box in the first direction, the second direction, and the third direction.

[0044] Specifically, in one embodiment, if the length of the maximum bounding box of the current layer in the second direction is Wg, and the length of the maximum bounding box in the third direction is Lg based on the coordinate values ​​of the four vertices of the maximum bounding box in the second direction and the third direction, the average length of the first target graphic layer in the second direction is Wm, and the average length of the first target graphic layer in the third direction is Lm, then the number of grids along the second direction of the current layer Nx=Wg / Wm, the number of grids along the third direction of the previous layer Ny=Lg / Lm, the length of the grid units corresponding to the first target graphic layer in the second direction is Wm, and the length of the grid units corresponding to the first target graphic layer in the third direction is Lm.

[0045] Please refer to Figure 4 , Figure 4 For Figure 3 The schematic diagram of the top view of the eighth graphic layer is shown in FIG. Figure 4 As shown, the maximum bounding box of the eighth graphic layer may be, for example, an area that can include all graphics of the eighth graphic layer (only five are shown in the figure, but the present application is not limited thereto). Specifically, in one embodiment, the third direction (for example, the Y-axis direction) is perpendicular to the second direction (for example, the X-axis direction) and the first direction (for example, the Z-axis direction). Specifically, as Figure 4 As shown, if the average length of the graphics of a certain graphic layer (for example, the eighth graphic layer) of the chip circuit in the second direction is greater than the average length of the graphics of this graphic layer in the third direction, then the length of the grid unit corresponding to this graphic layer in the second direction is also greater than the length of the grid unit corresponding to this graphic layer in the third direction.

[0046] S12. Determine a graphic associated with each grid unit of at least one grid based on grid information of at least one grid.

[0047] In one embodiment, the association between a graphic and a grid unit means that the graphic and the grid unit have overlapping parts, for example, the graphic and the grid unit intersect. In other embodiments, the association between a graphic and a grid unit may also be other relationships between the graphic and the grid unit defined by the user or the system, for example, the graphic is located within the grid unit. Specifically, a graphic may be associated with only one grid unit, or may be associated with multiple grid units at the same time. For example, Figure 4 As shown, each graphic of the eighth graphic layer is associated with two grid units.

[0048] In one embodiment, S12, based on the grid information of at least one grid, obtaining the graphics associated with each grid unit of the at least one grid, may include but is not limited to: determining the graphics layer corresponding to the position of each grid; determining the second independent memory array corresponding to each grid based on the graphics layer corresponding to each grid, and determining the graphics associated with the grid unit of each grid based on the graphics information of each graphics stored in the second independent memory array and the position information of the grid unit; storing the graphics information of the graphics associated with each grid unit in the third independent memory array corresponding to each grid unit. Specifically, each grid has a corresponding second independent memory array, and each grid unit has a corresponding third independent memory array. For each grid, determine the second independent memory array corresponding to the grid, and determine the graphics associated with each grid unit based on the graphics information of the graphics stored in the second independent memory array and the position information of the grid unit in the grid. For example, the second independent memory array corresponding to each grid can be traversed, and the position relationship between each graphics and the grid unit can be calculated in turn. If the graphics intersects with the grid unit, the graphics information of the graphics is stored in the third independent memory array corresponding to the grid unit, until all graphics are stored in the corresponding third independent memory array.

[0049] In one embodiment, the method may also include, but is not limited to: storing the position range of the graphics of each graphics layer along the first direction in a first independent memory array. Figure 3 As shown, the coordinate range (Z0, Z1) of the eighth graphic layer graphic along the first direction can be stored in the first independent memory array. The position range can be, for example, a coordinate range.

[0050] The present application provides an information processing method, including determining grid information of at least one grid used to divide the chip circuit according to the graphic information of multiple graphics in the chip circuit, wherein the graphic information includes the position information of the graphic in the chip circuit, each grid includes multiple grid units, and the grid information of the grid includes the position information of each grid unit in the grid; based on the grid information of at least one grid, determining the graphics associated with each grid unit of at least one grid. Therefore, the present application can confirm the grid information of at least one grid according to the graphic information of each graphic, thereby determining the graphics associated with the grid unit of the grid, and can quickly obtain the associated graphics according to the grid unit, thereby improving the search efficiency of the graphics, and further, for example, can improve the extraction efficiency of parasitic parameters.

[0051] The present application also provides an information processing method, such as Figure 5 As shown, the method comprises the following steps:

[0052] S20, obtaining the location information of the search graph;

[0053] In one implementation, the search graph may be any graph defined by a user or a system. Specifically, the search graph may be, but is not limited to, a search point.

[0054] S21, determining a target grid unit whose position meets a preset condition with the search graph;

[0055] The preset condition may be any condition defined by a user or a system. Specifically, in one embodiment, the step of determining a target grid unit that satisfies the preset condition with the search graph includes: determining a search range corresponding to the search graph according to a preset domain range; obtaining a grid that intersects with the search range, and determining a target grid unit that intersects with the search range from a plurality of grid units corresponding to the intersecting grids. In other embodiments, the target grid unit that satisfies the preset condition may be, for example, a grid unit that overlaps with the search graph, or a grid unit that is closest to the search graph.

[0056] In one embodiment, the step of obtaining a grid unit intersecting with a search range from a plurality of grid units to obtain a target grid unit includes: obtaining a second target graphic layer whose position or coordinate range along the first direction intersects with the position or coordinate range of the search range along the first direction based on the position or coordinate range of the search range along the first direction and a first independent memory array, wherein the position or coordinate range of each graphic layer along the first direction is stored in the first independent memory array; confirming a grid corresponding to the second target graphic layer, and determining a target grid unit in the grid intersecting with the search range in the second direction and / or third direction.

[0057] Specifically, Figure 6 As shown, Figure 6 It is a cross-sectional schematic diagram of a chip circuit including a search point P shown in an embodiment of the present application. If the coordinate value of the search point P is (Xp0, Yp0, Zp0), the neighborhood range of the search point along the second direction is adjLenX, the neighborhood range along the third direction is adjLenY, and the neighborhood range along the first direction is adjLenZ, then it can be first confirmed that the maximum coordinate value of the search range along the first direction is Zp0+adjLenZ, and the minimum coordinate value of the search range along the first direction is Zp0-adjLenZ. If it is determined that only the coordinate range of the seventh and eighth graphic layers along the first direction includes the maximum coordinate value Zp0+adjLenZ or the minimum coordinate value Zp0-adjLenZ according to the coordinate range of each graphic layer in the first independent memory array along the first direction, then the seventh and eighth graphic layers are confirmed as the second target graphic layers. Then, the grid cells corresponding to the graphics of the seventh and eighth graphic layers are confirmed to intersect with the search range along the second direction and / or the third direction to obtain the target grid cells.

[0058] S22. Obtain a target graphic associated with the target grid unit.

[0059] In one embodiment, S22, the step of obtaining a target graphic associated with the target grid unit, includes: obtaining graphic information of the graphic associated with the target grid unit from a third independent memory array corresponding to the target grid unit, and screening out a graphic whose distance from the search graphic meets a preset requirement as the target graphic. The graphic that meets the preset requirement may be, for example, a graphic that is closest to the search graphic, or may be a graphic that meets other requirements set by the user or the system. In other embodiments, all graphics associated with the target grid unit may also be used as the target graphic.

[0060] The information processing method of the present application obtains the position information of the search pattern; determines the target grid unit whose position satisfies the preset conditions with the search pattern, wherein the grid information of at least one grid is determined based on the graphic information of multiple graphics in the chip circuit of the chip, and the at least one grid is used to divide the chip circuit, wherein the graphic information includes the position information of the graphic in the chip circuit, and the grid information of the grid includes the position information of each grid unit in the grid; obtains the target graphic associated with the target grid unit. Therefore, the present application can confirm the grid information of at least one grid based on the graphic information of each graphic, and obtain the target grid unit that satisfies the preset conditions with the search pattern from the multiple grids to obtain the target graphic, which can improve the search efficiency, thereby improving the extraction efficiency of parasitic parameters.

[0061] An embodiment of the present application further provides a parasitic parameter extraction method, and the parasitic parameter extraction method includes any one of the above methods.

[0062] An embodiment of the present application also provides a device, including a memory and a processor, wherein the processor is configured to implement the above method when executing a computer program in the memory.

[0063] Specifically, the processor may include a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0064] Wherein, the memory may include a large capacity memory for data or instructions. By way of example and not limitation, the memory may include a hard disk drive (HDD), a floppy disk drive, a solid state drive (SSD), a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory may include a removable or non-removable (or fixed) medium. Where appropriate, the memory may be inside or outside the fault pattern generating device. In a specific embodiment, the memory is a non-volatile memory. In a specific embodiment, the memory includes a read-only memory (ROM) and a random access memory (RAM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (Programmable Read-Only Memory, PROM for short), an erasable PROM (Erasable ProgrammableRead-Only Memory, EPROM for short), an electrically erasable PROM (Electrically Erasable ProgrammableRead-Only Memory, EEPROM for short), an electrically alterable ROM (Electrically Alterable Read-Only Memory, EAROM for short) or a flash memory (FLASH) or a combination of two or more of these. Under appropriate circumstances, the RAM can be a static random access memory (SRAM) or a dynamic random access memory (DRAM), wherein the DRAM can be a fast page mode dynamic random access memory (FPMDRAM), an extended data output dynamic random access memory (EDODRAM), a synchronous dynamic random access memory (SDRAM), etc.

[0065] The memory may be used to store or cache various data files required for processing and / or communication, as well as possible computer program instructions executed by the processor.

[0066] The processor implements any one of the methods in the above embodiments by reading and executing computer program instructions stored in the memory.

[0067] Optionally, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0068] An embodiment of the present application further provides an intelligent terminal, comprising: a memory and a processor, wherein an operation program is stored in the memory, and when the operation program is executed by the processor, the steps of any of the above methods are implemented.

[0069] An embodiment of the present application further provides a computer-readable medium, wherein the medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0070] In the embodiments of the smart terminal and computer-readable storage medium provided in the present application, all technical features of any of the above embodiments may be included, and the expanded and explained contents of the specification are basically the same as those of the embodiments of the above methods, and will not be repeated here.

[0071] The embodiment of the present application further provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer executes the methods in the above various possible implementation modes.

[0072] The information processing method, parasitic parameter extraction method, device and medium of the present application determine the grid information of at least one grid used to divide the chip circuit according to the graphic information of multiple graphics in the chip circuit, wherein the graphic information includes the position information of the graphic in the chip circuit, each of the grids includes multiple grid units, and the grid information of the grid includes the position information of each grid unit in the grid; based on the grid information of the at least one grid, the graphics associated with each grid unit of the at least one grid are determined. Therefore, the present application can confirm the grid information of at least one grid according to the graphic information of each graphic, thereby determining the graphics associated with the grid unit of the grid, and can quickly obtain the associated graphics according to the grid unit, thereby improving the search efficiency of the graphics, and then, for example, improving the efficiency of extracting parasitic parameters.

[0073] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0074] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs.

[0075] The units in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0076] In the present application, the same or similar terminology concepts, technical solutions and / or application scenario descriptions are generally described in detail only the first time they appear. When they appear again later, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of the present application, for the same or similar terminology concepts, technical solutions and / or application scenario descriptions that are not described in detail later, reference can be made to the previous related detailed descriptions.

[0077] In the present application, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0078] The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0079] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. An information processing method, characterized in that: include: Determine, according to graphic information of a plurality of graphics in a chip circuit, grid information of at least one grid for dividing the chip circuit, wherein the graphic information includes position information of the graphics in the chip circuit, each of the grids includes a plurality of grid units, and the grid information of the grids includes position information of each grid unit in the grid; Based on the grid information of the at least one grid, a graphic associated with each grid unit of the at least one grid is determined.

2. The information processing method according to claim 1, characterized in that: The chip circuit includes a plurality of pattern layers in a first direction; The step of determining grid information of at least one grid for dividing the chip circuit according to the graphic information of a plurality of graphics in the chip circuit of the chip includes: According to the graphic information in each graphic layer, grid information of the grids corresponding to each graphic layer is determined, wherein each grid is used to divide at least one graphic layer.

3. The information processing method according to claim 1, wherein: The at least one grid is a non-uniform grid.

4. The information processing method according to claim 1, wherein: The lengths of the grid units in the same grid along the second direction are the same; and / or the lengths of the grid units in the same grid along the third direction are the same; the lengths of the grid units in the same grid along the second direction and along the third direction are different.

5. The information processing method according to claim 2, characterized in that: The step of determining the grid information of the grid corresponding to each graphic layer according to the graphic information of the multiple graphics in each graphic layer includes: Acquire an average length of a graphic of a first target graphic layer along a second direction and an average length of a graphic of a first target graphic layer along a third direction, wherein the first target graphic layer includes at least one graphic layer; Acquire a maximum bounding box of the first target graphic layer, wherein the maximum bounding box is an area that can accommodate all graphics of the first target graphic layer; Determine the number of grid units in the first target graphic layer along the second direction and the length of each grid unit along the second direction according to the average length of all graphics in the first target graphic layer along the second direction and the length of the corresponding maximum bounding box along the second direction; According to the average length of all graphics of the first target graphic layer along the third direction and the length of the corresponding maximum bounding box along the third direction, the number of grid units of the first target graphic layer along the third direction and the length of each grid unit along the third direction are determined.

6. The information processing method according to claim 2, characterized in that: Based on the grid information of the at least one grid, acquiring a graph associated with each grid unit of the at least one grid includes: Determine the graphic layer corresponding to the position of each grid; Determine a second independent memory array corresponding to each grid based on the graphic layer corresponding to each grid, and determine a graphic associated with the grid cell of each grid based on the graphic information of each graphic and the position information of the grid cell stored in the second independent memory array; The graphic information of the graphics associated with each grid unit is stored in a third independent memory array corresponding to each grid unit.

7. An information processing method, characterized in that: include: Get the location information of the search graph; Determine a target grid unit whose position with the search pattern satisfies a preset condition, wherein grid information of at least one grid is determined according to graphic information of a plurality of graphics in a chip circuit of a chip, and the at least one grid is used to divide the chip circuit, wherein the graphic information includes position information of the graphic in the chip circuit, and the grid information of the grid includes position information of each grid unit in the grid; Get the target graphic associated with the target grid cell.

8. The information processing method according to claim 7, characterized in that: The steps of determining and searching for target grid cells of a graph that meets preset conditions include: Determine the search scope corresponding to the search graph according to the preset domain scope; A grid intersecting with the search range is acquired, and the target grid unit intersecting with the search range is determined from a plurality of grid units corresponding to the grid.

9. The information processing method according to claim 8, characterized in that: The step of acquiring, from the plurality of grid units, a grid unit intersecting with the search range to acquire the target grid unit comprises: According to the position range of the search range along the first direction and the first independent memory array, obtaining a second target graphic layer whose position range along the first direction intersects with the position range of the search range along the first direction, wherein the first independent memory array stores the position range of each graphic layer along the first direction; A grid corresponding to the second target graphic layer is confirmed, and a grid unit intersecting with the search range in the second direction and / or the third direction is obtained from the grid to obtain the target grid unit.

10. The information processing method according to claim 7, characterized in that: The step of obtaining a target graphic associated with the target grid unit comprises: The graphic information of the graphic associated with the target grid unit is obtained from the third independent memory array corresponding to the target grid unit, and the graphic whose distance from the search graphic meets the preset requirement is screened out as the target graphic.

11. A parasitic parameter extraction method, characterized in that: The parasitic parameter extraction method comprises the method according to any one of claims 1-10.

12. A computer device, characterized in that: The computer device comprises a memory and a processor, and the processor is configured to implement the method according to any one of claims 1 to 11 when executing a computer program in the memory.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 11 is implemented.

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