Interconnection line graph processing method, computing device and computer readable storage medium

Abstract

The present application discloses a method for processing interconnection line graphics, a computing device and a computer-readable storage medium, comprising: obtaining at least one interconnection line overlapping graphic group in a chip design layout; determining a first segmentation direction corresponding to the interconnection line overlapping graphic group according to a first routing direction of the interconnection line overlapping graphic group; performing a segmentation and merging operation on the interconnection line overlapping graphic group along the first segmentation direction to obtain a first non-overlapping graphic set; obtaining a target graphic group in the first graphic set; the target graphic group includes graphics in the first graphic set that are sequentially connected to each other and whose routing direction is different from the first routing direction; determining a second segmentation direction, performing a segmentation and merging operation on at least one target graphic group along the second segmentation direction to obtain a processed second graphic set. In this way, the efficiency of graphic processing and the accuracy of parasitic resistance calculation are improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method for processing interconnection line graphics, a computing device, and a computer-readable storage medium. Background Art

[0002] In the process of digital circuit design, in order to evaluate the accuracy and reliability of the design, it is usually necessary to use parasitic parameter netlists for various simulations. Therefore, parasitic parameter extraction is an indispensable step in the entire design process. Parasitic resistance is a type of parasitic parameter. It is a non-ideal resistance in the circuit due to factors such as the resistance characteristics of the material and process effects. In order to help design engineers simulate circuit behavior more accurately, the correctness and accuracy of parasitic resistance extraction are crucial. Among them, the interconnection line pattern of the metal layer in the chip design layout can be obtained by processing the chip design layout, and then the interconnection line pattern can be divided and merged to calculate the parasitic resistance.

[0003] However, after the interconnection line pattern is divided and merged once according to the wiring direction of the metal layer, there may be a discrepancy between the pattern direction and the actual current direction, so that the error of the calculated parasitic resistance may be large. Summary of the invention

[0004] The purpose of the present application is to provide a method for processing interconnection line graphics, a computing device and a computer-readable storage medium to at least solve the problems in the related art.

[0005] To achieve the above objectives:

[0006] In a first aspect, an embodiment of the present application provides a method for processing an interconnection line pattern, the method comprising:

[0007] Acquire at least one interconnection line overlapping pattern group in the chip design layout;

[0008] Determining a first segmentation direction corresponding to the interconnection line overlapping pattern group according to a first routing direction of the interconnection line overlapping pattern group;

[0009] Performing a segmentation and merging operation on the interconnection line overlapping graphic group along the first segmentation direction to obtain a first graphic set that does not overlap each other;

[0010] Acquire at least one target graphic group in the first graphic set; the target graphic group includes graphics in the first graphic set that are sequentially connected to each other and whose routing direction is different from the first routing direction;

[0011] A second segmentation direction is determined, and a segmentation and merging operation is performed on the at least one target graphic group along the second segmentation direction to obtain a processed second graphic set.

[0012] In one embodiment, the first segmentation direction is perpendicular to the first routing direction;

[0013] The second dividing direction is perpendicular to the first dividing direction.

[0014] In one embodiment, the step of obtaining at least one interconnection line overlapping pattern group in the chip design layout includes:

[0015] Detect whether interconnection patterns in the chip design layout overlap or connect;

[0016] According to the obtained detection results, the interconnection line patterns that are sequentially overlapped or connected to each other are divided into the same interconnection line overlapping pattern group.

[0017] In one embodiment, the detecting whether interconnection line patterns in the chip design layout overlap or connect comprises:

[0018] Acquire line segment information of first line segments and second line segments relative to each interconnection line pattern in the chip design layout; the first line segments and the second line segments are determined based on the routing direction of the metal layer in the chip design layout;

[0019] According to the line segment information of the first line segment and the second line segment, it is detected whether the interconnection line patterns overlap or connect with each other to obtain a detection result.

[0020] In one embodiment, before determining the first segmentation direction corresponding to the interconnection line overlapping pattern group according to the first routing direction of the interconnection line overlapping pattern group, the method further includes:

[0021] Obtaining the minimum outer bounding rectangle of the interconnection line overlapping graphic group;

[0022] In response to the fact that the horizontal length of the smallest outer bounding rectangle of the interconnection line overlapping pattern group is greater than the vertical length, determining that the first routing direction of the interconnection line overlapping pattern group is horizontal;

[0023] In response to the fact that the horizontal length of the minimum outer bounding rectangle of the interconnection line overlapping pattern group is smaller than the vertical length, it is determined that the first routing direction of the interconnection line overlapping pattern group is the vertical direction.

[0024] In one embodiment, performing a segmentation and merging operation on the interconnection line overlapping graphic group along the first segmentation direction to obtain a first non-overlapping graphic set includes:

[0025] Determine a line segment set; the line segment set is an orderly arranged set of line segments parallel to the first segmentation direction in all interconnection line graphics included in the interconnection line overlapping graphic group;

[0026] Rectangular graphics are constructed for adjacent line segments in the line segment set, and a first graphic set that does not overlap with each other is generated based on the constructed rectangular graphics.

[0027] In one implementation, the acquiring the target graphic group in the first graphic set includes:

[0028] If the first routing direction is horizontal, then the longitudinal graphics in the first graphic set that are sequentially connected horizontally are divided into the same target graphic group; the longitudinal graphics are graphics in the first graphic set whose longitudinal length is greater than the horizontal length;

[0029] If the first routing direction is longitudinal, the transverse graphics in the first graphic set that are sequentially connected longitudinally are divided into the same target graphic group; the transverse graphics are graphics in the first graphic set whose transverse length is greater than the longitudinal length.

[0030] In one embodiment, performing a segmentation and merging operation on the target graphic group along the second segmentation direction to obtain a processed second graphic set includes:

[0031] Acquire target line segments parallel to the second segmentation direction in all graphics included in the target graphic group;

[0032] sorting the target line segments in ascending order according to their coordinate values ​​in the first segmentation direction to obtain an array generated after sorting;

[0033] Traverse the array in ascending order of the sorting numbers, and construct a rectangular figure between the target line segments with adjacent sorting numbers and different coordinate values;

[0034] The adjacent rectangular graphics whose coordinate values ​​of the target line segments in the second segmentation direction are consistent are merged to obtain a processed second graphic set.

[0035] In a second aspect, an embodiment of the present application provides a computing device, comprising: a processor and a memory storing a computer program, wherein when the processor runs the computer program, the method for processing an interconnection line graph described in the first aspect is implemented.

[0036] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for processing an interconnection line graph described in the first aspect above is implemented.

[0037] In the processing method of interconnection line graphics, computing device and computer-readable storage medium provided by the embodiments of the present application, after the interconnection line overlapping graphics grouped according to the overlapping situation are segmented and merged, unreasonable graphics areas in the generated non-overlapping graphics, namely, target graphics groups, are further determined, and the target graphics groups are segmented and merged again to correct the unreasonable graphics areas, so that the graphics obtained after the two segmentation and merging operations can restore the real current flow, thereby improving the graphics processing efficiency and the parasitic resistance calculation accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 The figure is a schematic diagram of the result of segmenting and merging overlapping graphics in the prior art.

[0039] Figure 2 A schematic flow chart of a method for processing interconnection line patterns provided in an embodiment of the present application.

[0040] Figure 3 This is a schematic diagram of the original connection of the interconnection line pattern in the embodiment of the present application.

[0041] Figure 4 Schematic diagram of grouping of interconnection line patterns in an embodiment of the present application.

[0042] Figure 5 It is a comparative schematic diagram before and after the cutting and merging operation is performed on the interconnection line pattern in the embodiment of the present application.

[0043] Figure 6 This is a schematic diagram of the optimized connection of the interconnection line pattern in the embodiment of the present application.

[0044] Figure 7 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0046] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0047] It should be understood that, although the terms first, second, third, etc. may be used to describe various information in this article, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this article, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "at the time of..." or "when..." or "in response to determination". Furthermore, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising", "including" indicate that there are described features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Thus, “A, B, or C” or “A, B and / or C” means “any of the following: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will occur only when a combination of elements, functions, steps, or operations are inherently mutually exclusive in some manner.

[0048] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and it can be performed in other orders. Moreover, at least a portion of the steps in the figure may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0049] It should be noted that, in this article, step codes such as S101, S102, etc. are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the sequence. When implementing the step, those skilled in the art may execute S102 first and then S101, etc., but these should all be within the scope of protection of this application.

[0050] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0051] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0052] like Figure 1 As shown in the figure, when the wiring direction of the metal layer in the chip design layout is horizontal, only the routing direction of most interconnection line patterns is horizontal, and there are still some interconnection line patterns in the local area with the routing direction being vertical, such as Figure 1 Therefore, after using the vertical scan line algorithm to perform segmentation and merging operations on the metal layer, the graphics result is not ideal. Figure 1 The arrangement of the figures (1), (2), and (3) shown in (b) is obviously inconsistent with the actual current flow, which will result in a large error in the calculated parasitic resistance.

[0053] For the above questions, see Figure 2 The embodiment of the present application provides a method for processing an interconnection line pattern. The method for processing an interconnection line pattern can be executed by a processing device for processing an interconnection line pattern provided by the embodiment of the present application. The processing device for processing an interconnection line pattern can be implemented in software and / or hardware, for example, it can be a computing device such as a computer or a server. The method for processing an interconnection line pattern provided by the embodiment includes:

[0054] Step S101, obtaining at least one interconnection line overlapping pattern group in a chip design layout.

[0055] Among them, there are many interconnection line graphics in the chip design layout, and some of the interconnection line graphics are overlapping, connected, separated, etc. In order to prevent the repeated calculation of parasitic resistance and the parasitic resistance calculation error caused by overlapping or connected graphics, it is necessary to split and merge these overlapping or connected interconnection line graphics and remove the overlapping parts. Therefore, it is necessary to first obtain at least one interconnection line overlapping graphic group in the chip design layout and then process it.

[0056] The interconnection line overlapping pattern group refers to a group of interconnection line patterns having overlapping or connected relationships in the chip layout pattern.

[0057] In one embodiment, obtaining at least one interconnection line overlapping pattern group in a chip design layout includes: detecting whether interconnection line patterns in the chip design layout overlap or connect; and according to the obtained detection results, classifying interconnection line patterns that overlap or connect to the same interconnection line overlapping pattern group.

[0058] The overlapping of interconnection line patterns may be the overlapping of the interconnection line patterns up and down, or the overlapping of the interconnection line patterns left and right, which is not specifically limited here. Since the interconnection line patterns in each chip layout have a certain regular shape, and are usually rectangular, and the coordinates of the line segments (also called edges) constituting each interconnection line pattern in the coordinate system are known, the coordinates of the edges can be used to detect whether the interconnection line patterns in the chip design layout overlap or connect, so as to obtain the detection result of whether the interconnection line patterns overlap or connect. The coordinates of the edges can be represented by the coordinates of the endpoints of the edges. The overlapping refers to the existence of overlapping parts between two interconnection line patterns, and the area of ​​the overlapping parts is greater than zero. Connecting refers to the connection of two interconnection line patterns but the area of ​​the overlapping parts is equal to zero. In this way, the division of the interconnection line overlapping pattern groups based on the detection result of whether the interconnection line patterns overlap or connect can realize accurate and fast grouping of the interconnection line patterns, further improving the efficiency of graphic processing.

[0059] In one embodiment, detecting whether interconnection line patterns in a chip design layout overlap or connect with each other includes:

[0060] Acquire line segment information of first line segments and line segment information of second line segments relative to each interconnection line pattern in the chip design layout; the first line segment and the second line segment are determined based on the routing direction of the metal layer where the interconnection line pattern in the chip design layout is located;

[0061] According to the line segment information of the first line segment and the line segment information of the second line segment, it is detected whether the interconnection line patterns overlap or connect with each other to obtain a detection result.

[0062] The routing direction of the metal layer in the chip design layout can also be called the wiring direction of the metal layer in the chip design layout. Taking the plane rectangular coordinate system as an example, the routing direction includes horizontal and vertical directions. Different metal layers have different wiring directions. It can be understood that the wiring direction of a certain metal layer is reflected in the routing direction of most interconnection line patterns on the metal layer. Here, the first line segment and the second line segment are generally the line segments of the interconnection line pattern in the routing direction of the metal layer to which they belong. Figure 3 As shown, the chip design layout is on a plane, with the direction facing the user as the reference, when the routing direction of the metal layer is horizontal, the first line segment and the second line segment are respectively the left line segment and the right line segment in the interconnection line pattern; and when the routing direction of the metal layer is vertical, the first line segment and the second line segment are respectively the upper line segment and the lower line segment in the interconnection line pattern. It can be understood that after the first line segment and the second line segment are determined according to the routing direction of the metal layer in the chip design layout, since the approximate position of the interconnection line pattern, that is, the position of the interconnection line pattern on the plane, can be known based on the first line segment and the second line segment, therefore, it can be detected whether the interconnection line patterns overlap or connect based on the line segment information of the first line segment and the line segment information of the second line segment.

[0063] In one embodiment, the line segment information may include coordinate values ​​of endpoints, serial number identifiers of interconnected line graphs, and line segment identifiers, wherein the coordinate values ​​of the endpoints include coordinate values ​​of a first endpoint and coordinate values ​​of a second endpoint; and according to the line segment information of the first line segment and the line segment information of the second line segment, detecting whether interconnected line graphs overlap or connect to obtain a detection result, including:

[0064] The first line segments and the second line segments corresponding to the interconnection line patterns are sorted according to their positions in the direction of the metal layer to obtain a line segment array generated after sorting; each element in the line segment array is a line segment, and has a corresponding serial number identifier and a line segment identifier; the serial number identifier is used to indicate the interconnection line pattern to which the line segment belongs, and the line segment identifier is used to indicate whether the line segment is the first line segment or the second line segment of the interconnection line pattern;

[0065] The line segments in the line segment array are traversed in sequence to determine whether there is an intersection with the line segments in the preset container in the position of the routing direction of the vertical metal layer. If so, it is determined that the interconnection line graphics corresponding to the two line segments with the intersection overlap or connect, wherein the overlapping or connected interconnection line graphics are determined according to the serial number identification of the line segments with the intersection, and the preset container stores the line segments that have an intersection with any line segment in the preset container from the line segments traversed in sequence, and deletes the line segments in the preset container that belong to the same interconnection line graphic as the traversed line segments.

[0066] Specifically, first select the line segment with the smallest sort number in the line segment array and add it to the preset container, and then select the other line segments in the line segment array except the line segment with the smallest sort number in order from the smallest to the largest sort number and perform the following operations:

[0067] If the line segment identifier of the current line segment is the second line segment, based on the serial number identifier of the interconnected line graph where the current line segment is located, the line segment in the preset container that belongs to the same interconnected line graph as the current line segment and whose line segment identifier is the first line segment is deleted;

[0068] If the line segment identifier of the current line segment is the first line segment, when it is determined that there is a target line segment in the preset container that intersects with the coordinate value range corresponding to the endpoint of the current line segment based on the coordinate value range of the current line segment, based on the serial number identifier of the interconnected line graphic where the current line segment is located and the serial number identifier of the interconnected line graphic where the target line segment is located, it is determined that there is an overlap between the interconnected line graphic where the current line segment is located and the interconnected line graphic where the target line segment is located, and the current line segment is added to the preset container.

[0069] Wherein, when the routing direction of the metal layer is horizontal, the first line segments and the second line segments corresponding to each interconnection line pattern are sorted according to the position in the direction of the metal layer, including sorting the first line segments and the second line segments corresponding to each interconnection line pattern according to the coordinate values ​​corresponding to the endpoints in the horizontal direction. When the routing direction of the metal layer is vertical, the first line segments and the second line segments corresponding to each interconnection line pattern are sorted according to the position in the direction of the metal layer, including sorting the first line segments and the second line segments corresponding to each interconnection line pattern according to the coordinate values ​​corresponding to the endpoints in the vertical direction. Each line segment includes a first endpoint and a second endpoint, the coordinate value of the first endpoint and the coordinate value of the second endpoint are obtained based on a preset rectangular coordinate system, the coordinate value of the first endpoint of the line segment includes the value of one endpoint of the line segment in the horizontal direction and the vertical direction, and the coordinate value of the second endpoint of the line segment includes the value of the other endpoint of the line segment in the vertical direction and the horizontal direction. The coordinate value range corresponding to the endpoint of the current line segment refers to the range between the coordinate value of the first endpoint of the current line segment and the coordinate value of the second endpoint. The serial number identifier of the interconnection line pattern is used to uniquely identify the interconnection line pattern, and can be identified based on the location of the interconnection line pattern, such as using numbers 1, 2, 3, etc. The line segment identifier is used to uniquely identify the line segment, such as L can be used to represent the first line segment, R can be used to represent the second line segment, etc.

[0070] Here, assuming that the coordinate value of the first endpoint in the direction perpendicular to the metal layer is smaller than that of the second endpoint, the first line segments and the second line segments corresponding to each interconnection line pattern can be sorted from small to large according to the coordinate values ​​of their respective first endpoints in the direction of the metal layer. If there is a situation where the coordinate values ​​of the first endpoints of a first line segment and a second line segment in the direction of the metal layer are equal, the second line segment is preferentially added to the line segment array, and then the first line segment is added to the line segment array, that is, when the coordinate values ​​of the first endpoints of the two line segments in the direction of the metal layer are equal, the line segment identified as the second line segment is arranged in front of the line segment identified as the first line segment in the line segment array. In addition, if there are two first line segments or two second line segments whose first endpoints have equal coordinate values ​​in the direction of the metal layer, the line segment whose second endpoint has a smaller coordinate value in the direction perpendicular to the metal layer is preferentially added to the line segment array, and then the line segment whose second endpoint has a larger coordinate value in the direction perpendicular to the metal layer is added to the line segment array. That is, when the first endpoints of two line segments with the same line segment identifier have equal coordinate values ​​in the direction of the metal layer, the line segment whose second endpoint has a smaller coordinate value in the direction perpendicular to the metal layer is arranged in front of the line segment whose second endpoint has a larger coordinate value in the direction perpendicular to the metal layer in the line segment array.

[0071] Among them, the preset container is a dynamic container, which is only used to store data and can also be replaced by other methods. It should be noted that each line segment in the line segment array has a sorting number, and the sorting numbers of each line segment increase from left to right. After adding the line segment with the smallest sorting number in the line segment array to the preset container, select the other line segments in the line segment array except the line segment with the smallest sorting number in the order of sorting numbers from small to large as the current line segment. If the line segment identifier of the current line segment is the second line segment, based on the serial number identifier of the interconnected line graph where the current line segment is located, query the line segment in the preset container that belongs to the same interconnected line graph as the current line segment and whose line segment identifier is the first line segment, and delete the line segment in the preset container that belongs to the same interconnected line graph as the current line segment and whose line segment identifier is the first line segment. If the line segment identifier of the current line segment is the first line segment, then according to the coordinate values ​​of the endpoints of the current line segment, it is detected whether there is a target line segment in the preset container that intersects with the coordinate value range corresponding to the endpoints of the current line segment, and when it is determined that there is a target line segment in the preset container that intersects with the coordinate value range corresponding to the endpoints of the current line segment, based on the serial number identifier of the interconnected line graph where the current line segment is located, it is determined that the interconnected line graph where the current line segment is located overlaps with the interconnected line graph where the target line segment is located, and the current line segment is added to the preset container to continue to perform the above operation on other line segments in the line segment array. Among them, the coordinate value range corresponding to the endpoints of the current line segment refers to the range of coordinate values ​​from the first endpoint to the second endpoint of the current line segment.

[0072] The following is a specific example to illustrate the process of obtaining the interconnection line overlapping pattern group, as follows:

[0073] based on Figure 3 The original interconnection line graphics in the chip design layout shown, find all the graphics with overlapping relationships. First, mark all the graphics with serial numbers, and save the left and right line segments of all the graphics in an array. The left and right line segments of each graphic are vertical. At the same time, each line segment needs to save its x coordinate, the y coordinates of the upper and lower endpoints (the lower endpoint is represented by y0, and the upper endpoint is represented by y1), the graphic serial number information, and the left and right side identification (i.e. the left line segment, the right line segment) information. Then, sort the line segments in the array by the size of the x coordinate. When the x coordinates are equal, the line segment marked as the right line segment is placed in front, and when the left and right side identifications are the same, they are sorted by the size of y0. At the same time, manage a dynamic container named segV. Finally, traverse each line segment in the array, directly put the first line segment in the array into segV, and for any line segment traversed later, if the line segment is the right line segment, find and delete the corresponding left line segment of the same figure from segV; if the line segment is the left line segment, search for all line segments in segV that have an intersection with the coordinate value range of the line segment in the y direction, indicating that the figures corresponding to the two line segments overlap, save the figure serial number corresponding to the intersecting line segments, and store the intersecting line segments in segV after the search is completed. In this way, the overlapping figures can be determined in sequence.

[0074] Assume that the left side of the graph is represented by n_L, the right side is represented by n_R, and n represents the graph number. Then the left and right sides of graph (1) are represented by 1_L and 1_R, respectively, and the left and right sides of graph (2) are represented by 2_L and 2_R, respectively, and so on. The corresponding array is {1_L, 2_L, 1_R, 3_L, 2_R, 4_L, 3_R, 5_L, 4_R, 5_R}. First, put 1_L into segV, then traverse to 2_L. Since the coordinate value ranges of 1_L and 2_L intersect in the y direction, it means that graphs (1) and (2) overlap, so 2_L is inserted into segV. Then traverse to 1_R. Since there is 1_L in segV that belongs to the same graph (1) as 1_R, 1_L can be deleted from segV. By continuing to traverse the above process, we can determine that graphics (1)(2) overlap, graphics (2)(3) overlap, graphics (3)(4) overlap, and graphics (4)(5) overlap, that is, graphics (1)(2)(3)(4)(5) overlap one another. Similarly, we can determine that graphics (6)(7) overlap. Therefore, based on the overlapping relationship between graphics, we can group graphics (1)(2)(3)(4)(5) as group 1 and graphics (6)(7) as group 2.

[0075] Step S102: determining a first segmentation direction corresponding to the interconnection line overlapping pattern group according to a first routing direction of the interconnection line overlapping pattern group.

[0076] In one embodiment, the first dividing direction is perpendicular to the first routing direction.

[0077] Specifically, when the routing direction of the interconnection overlapping pattern group is horizontal, the first segmentation direction corresponding to the interconnection overlapping pattern group is determined to be vertical; when the routing direction of the interconnection overlapping pattern group is vertical, the first segmentation direction corresponding to the interconnection overlapping pattern group is determined to be horizontal.

[0078] In one embodiment, before determining the first segmentation direction corresponding to the interconnection line overlapping pattern group according to the first routing direction of the interconnection line overlapping pattern group, the method further includes:

[0079] Get the minimum enclosing rectangle of the interconnection line overlapping graphic group;

[0080] In response to the fact that the horizontal length of the smallest outer bounding rectangle of the interconnection line overlapping pattern group is greater than the vertical length, determining that the first routing direction of the interconnection line overlapping pattern group is horizontal;

[0081] In response to the fact that the horizontal length of the minimum outer bounding rectangle of the interconnection line overlapping pattern group is smaller than the vertical length, the first routing direction of the interconnection line overlapping pattern group is determined to be the vertical direction.

[0082] Here, the minimum enclosing rectangle (also called the minimum circumscribed rectangle) of the interconnection line overlapping graphic group refers to the minimum range represented by two-dimensional coordinates that can accommodate all graphics in the interconnection line overlapping graphic group. The minimum enclosing rectangle of the interconnection line overlapping graphic group can be obtained by counting the largest first coordinate value and the second coordinate value and the smallest first coordinate value and the second coordinate value of all interconnection line graphics included in the interconnection line overlapping graphic group, and taking the largest first coordinate value and the second coordinate value and the smallest first coordinate value and the second coordinate value as the vertices of the minimum enclosing rectangle of the interconnection line overlapping graphic group, so as to obtain the minimum enclosing rectangle of the interconnection line overlapping graphic group.

[0083] When the horizontal length of the smallest outer rectangle of the interconnection overlapping pattern group is greater than the vertical length, it means that the smallest outer rectangle of the interconnection overlapping pattern group is set in the horizontal direction, and the first routing direction of the interconnection overlapping pattern group is determined to be the horizontal direction; when the horizontal length of the smallest outer rectangle of the interconnection overlapping pattern group is less than the vertical length, it means that the smallest outer rectangle of the interconnection overlapping pattern group is set in the vertical direction, and the first routing direction of the interconnection overlapping pattern group is determined to be the vertical direction. In this way, the routing direction of the interconnection overlapping pattern group can be accurately and quickly determined.

[0084] In some embodiments, the x-axis direction is horizontal and the y-axis direction is vertical. In other embodiments, the x-axis direction may be vertical and the y-axis direction may be horizontal. The direction of the metal layer and the direction of the interconnection line pattern may be consistent. Figure 3 Including two interconnection line pattern groups (group 1 and group 2), firstly, the maximum and minimum x-coordinates, the maximum and minimum y-coordinates of the interconnection line patterns in group 1 and group 2 are counted, so as to obtain the minimum outer rectangle of each group of patterns. Since the length of the minimum outer rectangle of group 1 in the x direction is greater than the length in the y direction, it can be determined that the routing direction of group 1 is horizontal, and the length of the minimum outer rectangle of group 2 in the x direction is less than the length in the y direction, it can be determined that the routing direction of group 2 is vertical.

[0085] Step S103: performing a splitting and merging operation on the interconnection line overlapping graphic group along the first splitting direction to obtain a first graphic set that does not overlap each other.

[0086] Here, in order to separate the interconnection line graphics that overlap with each other in sequence in the interconnection line overlapping graphic group, after determining the segmentation direction of each interconnection line overlapping graphic group, the corresponding interconnection line overlapping graphic group can be segmented and merged along the corresponding first segmentation direction to obtain a first graphic set that does not overlap with each other. It should be noted that in this embodiment, the segmentation and merging operation can be performed based on the existing scan line algorithm. Taking the segmentation direction as the longitudinal direction as an example, the working principle of the scan line algorithm is: first, the left and right side segments of all graphics are saved in an array and sorted according to the x coordinate value of each side segment; then, each side segment is traversed from left to right, and a rectangle is constructed between two adjacent side segments with unequal x values, thereby completing the cutting of the graphics and removing the overlapping area; finally, the adjacent graphics with the same y coordinates of the upper side and the lower side in the previous step are merged.

[0087] In one embodiment, performing a splitting and merging operation on the interconnection line overlapping graphic group along a first splitting direction to obtain a first graphic set that does not overlap each other includes:

[0088] Determine a line segment set; the line segment set is an orderly arranged set of line segments parallel to the first segmentation direction in all interconnection line graphics included in the interconnection line overlapping graphic group;

[0089] A rectangular graph is constructed for adjacent line segments in the line segment set, and a first graph set that does not overlap with each other is generated based on the constructed rectangular graph.

[0090] Specifically, the line segments parallel to the first segmentation direction in all interconnection line graphics included in the interconnection line overlapping graphic group are obtained, and each interconnection line graphic has two line segments parallel to the first segmentation direction; then, each line segment parallel to the first segmentation direction is sorted from small to large according to the coordinate value in the first routing direction, and an array generated after sorting is obtained; then, the line segments in the array are traversed in order of sorting number from small to large, and rectangular graphics are constructed between line segments with adjacent sorting numbers and different coordinate values ​​in the first routing direction; then, adjacent rectangular graphics with consistent line segment coordinate values ​​in the first segmentation direction are merged to obtain a first non-overlapping graphic set. In this way, the segmentation and merging operation of the interconnection line overlapping graphic group can be performed quickly and accurately, further improving the graphics processing efficiency and the parasitic resistance calculation accuracy.

[0091] Based on the above example, after determining that the routing direction of group 1 is horizontal and the routing direction of group 2 is vertical, the group 1 graphics are scanned from left to right using a vertical scan line to complete the segmentation and merging of the graphics, and the group 2 graphics are scanned from bottom to top using a horizontal scan line to complete the segmentation and merging of the graphics, and a first set of graphics that do not overlap each other is obtained, such as Figure 4 As shown. The following takes the segmentation and merging operation of group 1 graphics using a vertical scan line from left to right as an example for explanation. Assuming that the line segment identifier of the left line segment of the graphics is represented by n_L, and the line segment identifier of the right line segment is represented by n_R, and n represents the graphics sequence number, then the left and right side identifiers of graphics (1) are 1_L and 1_R respectively, and the left and right side identifiers of graphics (2) are 2_L and 2_R respectively, and so on, and the array sorted by the corresponding x-coordinate value is {1_L, 2_L, 1_R, 3_L, 2_R, 4_L, 3_R, 5_L, 4_R, 5_R}. First, traverse 1_L. Since 2_L and 1_L have adjacent sequence numbers and different x-coordinate values, a rectangular figure is constructed between 1_L and 2_L. Then, traverse 2_L. Since 2_L and 1_R have adjacent sequence numbers and different x-coordinate values, a rectangular figure is constructed between 1_R and 2_L. Then, traverse 1_R. Since 1_R and 3_L have adjacent sequence numbers and different x-coordinate values, a rectangular figure is constructed between 1_R and 3_L. This process is repeated until 5_R is traversed. Then, the adjacent rectangular figures with the same y-coordinates on the left line segments are merged to obtain the first non-overlapping graphic set.

[0092] Step S104, obtaining at least one target graphic group in the first graphic set; the target graphic group includes graphics in the first graphic set that are sequentially connected to each other and whose routing direction is different from the first routing direction.

[0093] It can be understood that since the routing direction of some graphics in the interconnection line overlapping graphic group may be inconsistent with the routing direction of the interconnection line overlapping graphic group, after the interconnection line overlapping graphic group is segmented and merged along the first segmentation direction, the part of the first graphic obtained may not be ideal, resulting in a large error when the parasitic resistance is calculated using the first graphic. Therefore, it is necessary to continue to obtain the target graphic group in the first graphic set, and the target graphic group includes graphics in the first graphic set that are sequentially connected to each other and have a routing direction different from the first routing direction. Here, the target graphic group can be regarded as a graphic set composed of unreasonable segmentation graphics.

[0094] In one embodiment, obtaining a target graphic group in the first graphic set includes:

[0095] If the first routing direction is horizontal, the longitudinal graphics in the first graphic set that are sequentially connected horizontally are divided into the same target graphic group; the longitudinal graphics are graphics in the first graphic set whose longitudinal length is greater than the horizontal length;

[0096] If the first routing direction is longitudinal, then the transverse graphics in the first graphic set that are sequentially connected longitudinally are divided into the same target graphic group; the transverse graphics are graphics in the first graphic set whose transverse length is greater than the longitudinal length.

[0097] Specifically, if the first routing direction of the interconnection line overlapping graphic group is horizontal, and the first segmentation direction corresponding to the interconnection line overlapping graphic group is vertical, then the vertical graphics that are sequentially connected horizontally in the first graphic set are divided into the same target graphic group; if the first routing direction of the interconnection line overlapping graphic group is vertical, and the first segmentation direction corresponding to the interconnection line overlapping graphic group is horizontal, then the horizontal graphics that are sequentially connected vertically in the first graphic set are divided into the same target graphic group.

[0098] It can be understood that for the interconnection line overlapping graphic group whose first routing direction is horizontal, the corresponding segmentation direction is the vertical direction, that is, the segmentation and merging operation will be selected to be performed in the vertical direction, so that a plurality of first graphics arranged in sequence in the horizontal direction are obtained, and they are mainly horizontal graphics. If there are a plurality of vertical graphics connected together in the horizontal direction, it can be considered as an unreasonable segmentation result. Therefore, for the first graphic set generated after the segmentation and merging operation is performed in the vertical direction, all the vertical graphics therein are selected, and the connection of these graphics is checked, and the vertical graphics that have a horizontal connection relationship are saved. Similarly, for the first graphic set generated after the segmentation and merging operation is performed in the horizontal direction, all the horizontal graphics therein are selected, and the graphics that have a vertical connection relationship are saved. Here, judging whether the graphics are connected is consistent with the aforementioned method of judging whether the graphics overlap, which will not be repeated here. In a specific embodiment, obtaining graphics having a connection relationship includes: if the horizontal direction is the x-axis direction, and the x coordinate of the right line segment of one graphic is equal to the x coordinate of the left line segment of another graphic, then the two graphics are determined to be horizontally connected; if the y coordinate of the upper line segment of one graphic is equal to the y coordinate of the lower line segment of another graphic, then the two graphics are determined to be vertically connected. Figure 4 From group 1, we can determine that the figures (2)(3)(4) are connected to each other from left to right, so we save these three figures separately as group 3. Figure 5 Although group 2 can select graph (5), there is only one graph and there are no multiple graphs connected vertically, so no processing is required.

[0099] Step S105 , determining a second segmentation direction, and performing a segmentation and merging operation on the target graphic group along the second segmentation direction to obtain a processed second graphic set.

[0100] Optionally, the second segmentation direction is perpendicular to the first segmentation direction.

[0101] In one embodiment, performing a segmentation and merging operation on the target graphic group along the second segmentation direction to obtain a processed second graphic set includes:

[0102] Obtain target line segments parallel to the second segmentation direction in all graphics included in the target graphic group;

[0103] Sort the target line segments in ascending order according to their coordinate values ​​in the first segmentation direction, and obtain an array generated after sorting;

[0104] Traverse the array in ascending order of sorting numbers, and construct a rectangular figure between target line segments with adjacent sorting numbers and different coordinate values;

[0105] Adjacent rectangular graphics whose target line segments have consistent coordinate values ​​in the second segmentation direction are merged to obtain a processed second graphic set.

[0106] Specifically, first, based on the second segmentation direction, the target line segments parallel to the second segmentation direction in all the graphics included in the target graphic group are obtained, and each graphic in the target graphic group has two target line segments parallel to the second segmentation direction. Then, according to the coordinate values ​​of the target line segments in the first segmentation direction perpendicular to the second segmentation direction, all the target line segments are sorted in ascending order to obtain an array generated after sorting. Then, the target line segments in the array are traversed in ascending order according to the sorting number, and it is detected whether the coordinate values ​​of the target line segments currently traversed are different from those of the target line segments traversed most recently. If they are different, a rectangular graphic is constructed between the target line segments currently traversed and the target line segments traversed most recently, so as to realize the construction of a rectangular graphic between target line segments with adjacent sorting numbers and different coordinate values. Finally, after traversing the array, according to the first coordinate values ​​of the target line segments constituting the rectangular graphics, it is detected whether the coordinate values ​​of the target line segments of the adjacent rectangular graphics in the second segmentation direction are consistent, and the adjacent rectangular graphics with the consistent coordinate values ​​of the target line segments in the second segmentation direction are merged to obtain a second graphic set. It should be noted that the second graphic set includes the graphics in the first graphic set except the target graphic group and the graphics obtained after performing the split and merge operation on the target graphic group. In this way, by performing the split and merge operation on the target graphic group, the unreasonable graphic area is corrected, thereby further improving the calculation accuracy of the parasitic resistance.

[0107] Based on the previous example, see Figure 5 As shown in (a), based on the group 3 generated by the graph (2)(3)(4) determined from group 1, it can be determined that the routing direction of group 3 is vertical, and the corresponding segmentation direction of group 3 is horizontal. Therefore, it is necessary to perform the segmentation and merging operation from bottom to top using the horizontal scanning line for group 3. The corresponding result is as follows: Figure 5 As shown in (b). Figure 6 As shown in FIG. 1 , the second graph set is generated by merging the results of two split and merge operations. By comparison, it can be seen that Figure 6 The connection relationship between the graphs can better reflect the actual current flow, so the calculation of parasitic resistance will have better accuracy.

[0108] In summary, in the method for processing interconnection line graphics provided by the above embodiment, after the interconnection line overlapping graphic groups grouped according to the overlapping or connecting conditions are segmented and merged, unreasonable graphic areas in the generated non-overlapping graphics, namely, target graphic groups, are further determined, and the target graphic groups are segmented and merged again to correct the unreasonable graphic areas, so that the graphics obtained after the two segmentation and merging operations can restore the real current flow, thereby improving the graphics processing efficiency and the parasitic resistance calculation accuracy.

[0109] Based on the same inventive concept as the above embodiments, an embodiment of the present invention provides a computing device, such as Figure 7 As shown, the computing device includes: a processor 310 and a memory 311 storing a computer program; wherein, Figure 7 The processor 310 shown in the figure is not used to indicate that the number of the processor 310 is one, but is only used to indicate the positional relationship of the processor 310 relative to other devices. In actual applications, the number of the processor 310 may be one or more; similarly, Figure 7 The memory 311 shown in the figure has the same meaning, that is, it is only used to refer to the position relationship of the memory 311 relative to other devices. In practical applications, the number of memories 311 can be one or more. When the processor 310 runs the computer program, the processing method of the interconnection line pattern applied to the above computing device is implemented.

[0110] The computing device may also include: at least one network interface 312. The various components in the electronic device are coupled together via a bus system 313. It is understood that the bus system 313 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 313 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, the bus system 313 is not used in the following examples. Figure 7 Various buses are labeled as bus system 313.

[0111] The memory 311 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAMbus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory 311 described in the embodiments of the present invention is intended to include but is not limited to these and any other suitable types of memories.

[0112] The memory 311 in the embodiment of the present invention is used to store various types of data to support the operation of the computing device. Examples of these data include: any computer program used to operate on the computing device, such as an operating system and an application; contact data; phone book data; messages; pictures; videos, etc. Among them, the operating system includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., which are used to implement various basic services and process hardware-based tasks. The application program may include various applications, such as a media player (Media Player), a browser (Browser), etc., which are used to implement various application services. Here, the program that implements the method of the embodiment of the present invention may be included in the application program.

[0113] Based on the same inventive concept as the above-mentioned embodiment, this embodiment further provides a computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium. The computer-readable storage medium may be a ferromagnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); or it may be various devices including one or any combination of the above-mentioned memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc. When the computer program stored in the computer-readable storage medium is executed by the processor, the above-mentioned method for processing the interconnection line graph is implemented. For the specific steps implemented when the computer program is executed by the processor, please refer to Figure 2 The description of the illustrated embodiment will not be repeated here.

[0114] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0115] In this document, the terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of elements other than those listed and may also include additional elements not expressly listed.

[0116] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for processing an interconnection line pattern, characterized in that: The method comprises: Acquire at least one interconnection line overlapping pattern group in the chip design layout; Determining a first segmentation direction corresponding to the interconnection line overlapping pattern group according to a first routing direction of the interconnection line overlapping pattern group; Performing a segmentation and merging operation on the interconnection line overlapping graphic group along the first segmentation direction to obtain a first graphic set that does not overlap each other; Acquire at least one target graphic group in the first graphic set; the target graphic group includes graphics in the first graphic set that are sequentially connected to each other and whose routing direction is different from the first routing direction; A second segmentation direction is determined, and a segmentation and merging operation is performed on the at least one target graphic group along the second segmentation direction to obtain a processed second graphic set.

2. The method according to claim 1, characterized in that The first segmentation direction is perpendicular to the first routing direction; The second dividing direction is perpendicular to the first dividing direction.

3. The method according to claim 1, characterized in that The step of obtaining at least one interconnection line overlapping pattern group in the chip design layout includes: Detect whether interconnection patterns in the chip design layout overlap or connect; According to the obtained detection results, the interconnection line patterns that are sequentially overlapped or connected to each other are divided into the same interconnection line overlapping pattern group.

4. The method according to claim 3, characterized in that: The detecting whether interconnection line patterns in the chip design layout overlap or connect comprises: Acquire line segment information of first line segments and second line segments relative to each interconnection line pattern in the chip design layout; the first line segments and the second line segments are determined based on the routing direction of the metal layer in the chip design layout; According to the line segment information of the first line segment and the second line segment, it is detected whether the interconnection line patterns overlap or connect with each other to obtain a detection result.

5. The method according to claim 1, characterized in that Before determining the first segmentation direction corresponding to the interconnection line overlapping pattern group according to the first routing direction of the interconnection line overlapping pattern group, the method further includes: Obtaining the minimum outer bounding rectangle of the interconnection line overlapping graphic group; In response to the fact that the horizontal length of the smallest outer bounding rectangle of the interconnection line overlapping pattern group is greater than the vertical length, determining that the first routing direction of the interconnection line overlapping pattern group is horizontal; In response to the fact that the horizontal length of the minimum outer bounding rectangle of the interconnection line overlapping pattern group is smaller than the vertical length, it is determined that the first routing direction of the interconnection line overlapping pattern group is the vertical direction.

6. The method according to claim 1, characterized in that The performing a segmentation and merging operation on the interconnection line overlapping graphic group along the first segmentation direction to obtain a first graphic set that does not overlap each other includes: Determine a line segment set; the line segment set is an orderly arranged set of line segments parallel to the first segmentation direction in all interconnection line graphics included in the interconnection line overlapping graphic group; Rectangular graphics are constructed for adjacent line segments in the line segment set, and a first graphic set that does not overlap with each other is generated based on the constructed rectangular graphics.

7. The method according to any one of claims 1 to 6, characterized in that The acquiring the target graphic group in the first graphic set includes: If the first routing direction is horizontal, then the longitudinal graphics in the first graphic set that are sequentially connected horizontally are divided into the same target graphic group; the longitudinal graphics are graphics in the first graphic set whose longitudinal length is greater than the horizontal length; If the first routing direction is longitudinal, the transverse graphics in the first graphic set that are sequentially connected longitudinally are divided into the same target graphic group; the transverse graphics are graphics in the first graphic set whose transverse length is greater than the longitudinal length.

8. The method according to claim 7, characterized in that The performing a segmentation and merging operation on the target graphic group along the second segmentation direction to obtain a processed second graphic includes: Acquire target line segments parallel to the second segmentation direction in all graphics included in the target graphic group; sorting the target line segments in ascending order according to their coordinate values ​​in the first segmentation direction to obtain an array generated after sorting; Traverse the array in ascending order of the sorting numbers, and construct a rectangular figure between the target line segments with adjacent sorting numbers and different coordinate values; The adjacent rectangular graphics whose coordinate values ​​of the target line segments in the second segmentation direction are consistent are merged to obtain a processed second graphic set.

9. A computing device, characterized in that The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the method for processing interconnection line patterns as claimed in any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the method for processing an interconnection line pattern according to any one of claims 1 to 8 is implemented.

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