Frequency conversion method for image acquisition and image acquisition device

Abstract

The present invention discloses a frequency conversion method and an image acquisition device for image acquisition. The method includes: obtaining the number of clock cycles required to perform a frequency conversion operation for a memory access rate; determining, in response to a start write signal of a current frame image, the amount of cached data to be written into an internal cache within the number of clock cycles of the current frame image; detecting in real time whether the remaining cache space of the internal cache is greater than the cached data amount; generating a first interrupt signal to allow the frequency conversion operation to be performed during at least one first frequency conversion period when the remaining cache space of the internal cache is greater than the cached data amount; and / or obtaining a frame blanking period between the current frame image and the next frame image; generating a first interrupt signal to allow the frequency conversion operation to be performed during a second frequency conversion period corresponding to a first set number of clock cycles after the start of the frame blanking period, the set number of clock cycles corresponding to the frame blanking period minus the number of clock cycles required for the frequency conversion operation.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing, and in particular to a frequency conversion method and an image acquisition device for image acquisition. Background Art

[0002] During image acquisition, the system typically performs DDR (Double Data Rate) frequency conversion based on bandwidth changes. When the system's DDR bandwidth increases significantly, the DDR PHY frequency is increased to meet the system's bandwidth requirements. When the system's DDR bandwidth decreases significantly, the DDR PHY frequency is decreased to reduce DDR PHY power consumption. DDR frequency conversion is performed jointly by the DDR controller and DDR PHY in the System on a Chip (SOC).

[0003] During DDR frequency conversion, the image acquisition module cannot output data via the bus. If the DDR frequency conversion time is too long, it may cause the internal buffer of the image acquisition module to overflow. Currently, there are two common approaches: one is to prevent DDR frequency conversion during image acquisition through mutual exclusion; the other is to reduce the frame rate of the image acquisition end to meet the DDR frequency conversion requirements. Both methods will lead to reduced system performance and affect the user experience. Summary of the Invention

[0004] The present invention provides a frequency conversion method and an image acquisition device for image acquisition, which can obtain sufficient bandwidth for memory access rate (such as DDR frequency conversion) while ensuring system performance and optimizing user experience.

[0005] In one aspect of the present invention, a frequency conversion method for image acquisition is provided. The method includes: obtaining the number of clock cycles required to perform a frequency conversion operation for a memory access rate; determining, in response to a start write signal for a current frame image, the amount of buffered data to be written into an internal buffer for the current frame image within the number of clock cycles; detecting in real time whether the remaining buffer space in the internal buffer is greater than the buffered data amount; and generating a first interrupt signal to enable execution of the frequency conversion operation during at least one first frequency conversion period when the remaining buffer space in the internal buffer is greater than the buffered data amount.

[0006] In another aspect of the present invention, a frequency conversion method for image acquisition is provided. The method includes: obtaining a number of clock cycles required to perform a frequency conversion operation for a memory access rate; obtaining a frame blanking period between a current frame image and a next frame image; and generating a first interrupt signal to enable the frequency conversion operation within a second frequency conversion period corresponding to a set number of clock cycles after the start of the frame blanking period, wherein the set number of clock cycles corresponds to the frame blanking period minus the number of clock cycles required for the frequency conversion operation.

[0007] In another aspect of the present invention, an image acquisition device is provided. The device includes: an acquisition module configured to acquire the number of clock cycles required to perform a frequency conversion operation for a memory access rate; and an intra-frame interrupt module configured to: in response to a start write signal for a current frame image, determine the amount of buffered data to be written into an internal buffer within the number of clock cycles for the current frame image; detect in real time whether the remaining buffer space in the internal buffer is greater than the buffered data amount; and generate a first interrupt signal to enable the frequency conversion operation during at least one first frequency conversion period when the remaining buffer space in the internal buffer is greater than the buffered data amount.

[0008] According to the technical solution of the present invention, during the continuous reception of images, the amount of cache data M to be written into the internal cache within the number of clock cycles of the frequency conversion operation for each frame of image is counted. When the remaining cache space of the internal cache is greater than the amount of cache data M, a first interrupt signal is generated to allow the system to trigger the DDR frequency conversion operation according to the bandwidth change during this period, thereby obtaining sufficient bandwidth. Since the remaining cache space of the internal cache is greater than the amount of cache data M, even if the system triggers the DRR frequency conversion operation at this time, since the remaining cache space can meet the amount of write data during the DDR frequency conversion operation, it will not cause the problem of internal cache overflow. In this way, during the writing process of each frame of image, the optimal interval that can meet the DDR frequency conversion operation is selected based on the amount of data written and the remaining space of the internal cache. There is no need to prevent DDR frequency conversion by mutual exclusion means or to meet the DDR frequency conversion requirements by reducing the frame rate of the image acquisition end, effectively ensuring system performance and optimizing user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Flowchart of a frequency conversion method for image acquisition according to an embodiment of the present invention;

[0010] Figure 2 This is a schematic diagram of an intra-frame variable frequency interval according to an embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram of an inter-frame variable frequency interval according to an embodiment of the present invention;

[0012] Figure 4 This is a schematic diagram of a final variable frequency interval according to an embodiment of the present invention;

[0013] Figure 5 Schematic diagram of the structure of an image acquisition device according to an embodiment of the present invention;

[0014] Figure 6 FIG. 4 is a schematic structural diagram of another image acquisition device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] To illustrate the technical content, achieved objectives and effects of the present invention in detail, the following description is given in conjunction with the embodiments and accompanying drawings.

[0016] In existing technologies, the image acquisition module cannot output data via the bus during DDR frequency conversion. If the DDR frequency conversion time is too long, it may cause the internal buffer of the image acquisition module to overflow. Currently, there are two common approaches: one is to prevent DDR frequency conversion during image acquisition through mutual exclusion; the other is to reduce the frame rate of the image acquisition end to meet the DDR frequency conversion requirements. Both methods will lead to reduced system performance and affect the user experience.

[0017] In order to solve at least the above-mentioned technical problems, the present disclosure provides a frequency conversion method for image acquisition. According to the present disclosure, during the continuous reception of images, the amount of cache data M to be written into the internal cache within the number of clock cycles of the frequency conversion operation for each frame of image is counted. When the remaining cache space of the internal cache is greater than the amount of cache data M, a first interrupt signal is generated to allow the system to trigger the DDR frequency conversion operation according to the bandwidth change during this period, thereby obtaining sufficient bandwidth. Since the remaining cache space of the internal cache is greater than the amount of cache data M, even if the system triggers the DRR frequency conversion operation at this time, since the remaining cache space can meet the amount of data written during the DDR frequency conversion operation, it will not cause the problem of internal cache overflow. In addition, within the variable frequency period corresponding to the first set number of clock cycles after the start of the frame blanking period, a first interrupt signal can also be generated to allow the system to trigger the DDR frequency conversion operation according to the bandwidth change during this period. Since no image data is input during the frame blanking period, it will not cause the problem of internal cache overflow.

[0018] In this way, according to the embodiment of the present disclosure, since the remaining cache space of the internal cache is greater than the amount of data M written to the image within the number of clock cycles, even if the system triggers the DRR frequency conversion operation at this time, since the remaining cache space can meet the amount of data written during the DDR frequency conversion operation, it will not cause the problem of internal cache overflow. During the writing process of each frame of the image, the present disclosure can determine the optimal interval for performing the DDR frequency conversion operation based on the amount of data written and the remaining space of the internal cache, and determine the variable frequency period corresponding to the previous set number of clock cycles during the frame blanking period as another optimal interval for performing the DDR frequency conversion operation. There is no need to prevent DDR frequency conversion through mutual exclusion means or to meet the DDR frequency conversion requirements by reducing the frame rate of the image acquisition end, effectively ensuring system performance and optimizing user experience.

[0019] According to the present disclosure, an image acquisition device obtains the number of clock cycles X required for a DDR frequency conversion operation from an external source (e.g., a CPU) (X is calculated by dividing the DDR frequency conversion time by the image acquisition device's clock cycle). The image acquisition device's internal logic circuit counts clock cycles during the idle period of each image frame (e.g., during vblank), with the count value being N. This count N is used to guide the interrupt setting for the next image frame. During the first N x clock cycles of the next image frame, an interrupt signal is pulled high to enable DDR frequency conversion. This process is referred to as the pre-frame blanking condition. At the beginning of each image frame, the image acquisition device's internal logic circuit counts the amount of data written to the internal buffer for the number of clock cycles X required for the DDR frequency conversion operation. If the amount of data written to the buffer within X clock cycles is N, then when the remaining space in the internal buffer is greater than N, the interrupt signal is pulled high to enable DDR frequency conversion. This process is referred to as the internal buffering condition. For both the pre-frame blanking condition and the internal buffering condition, DDR frequency conversion is enabled as long as either one of the two conditions is met.

[0020] It should be understood that, although the frequency conversion operation of the DDR memory access rate is described herein as a specific example, the technical solution of the present invention can be applied to scenarios of frequency conversion operation of any memory access rate.

[0021] Hereinafter, the technical solutions according to the present disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings.

[0022] Figure 1 FIG. 1 is a flow chart illustrating a frequency conversion method 100 for image acquisition according to an embodiment of the present disclosure. Figure 1 , the method 100 includes the following steps 102 to 108.

[0023] In step 102, the number of clock cycles required to perform a frequency conversion operation for a memory access rate is obtained.

[0024] In step 104 , in response to a start write signal of the current frame image, the amount of cache data of the current frame image to be written into the internal cache within the number of clock cycles is determined.

[0025] In step 106, it is detected in real time whether the remaining buffer space of the internal buffer is greater than the buffer data amount.

[0026] In step 108 , a first interrupt signal is generated to allow the frequency conversion operation to be performed within at least one first frequency conversion period when the remaining buffer space of the internal buffer is greater than the buffer data amount.

[0027] In some embodiments, generating a first interrupt signal to allow the frequency conversion operation to be performed during at least one first variable frequency period when the remaining buffer space in the internal buffer is greater than the buffered data volume includes generating the first interrupt signal to allow the frequency conversion operation to be performed during a predetermined number of clock cycles before the current frame image and the next frame image, wherein the predetermined number corresponds to the number of clock cycles required for the frequency conversion operation. In this manner, by performing the frequency conversion operation during the predetermined number of clock cycles, the problem of the buffered data volume exceeding a predetermined amount due to the prolonged frequency conversion operation, which could lead to a memory overflow, is avoided.

[0028] In some embodiments, in addition to or as an alternative to steps 104 to 108 associated with the internal buffering condition, method 100 may include: obtaining a frame blanking period between the current frame image and the next frame image; and generating the first interrupt signal to allow the frequency conversion operation to be performed during a second variable frequency period corresponding to a set number of clock cycles after the start of the frame blanking period, wherein the set number of clock cycles corresponds to the frame blanking period minus the number of clock cycles required for the frequency conversion operation. In this manner, during the frame blanking process between each frame image, by counting the frame blanking periods between each frame image and reserving a variable frequency period in each frame blanking time that satisfies the DDR frequency conversion operation based on the number of clock cycles, the first interrupt signal is generated during the variable frequency period to allow the system to perform the DDR frequency conversion operation during this period, thereby obtaining sufficient bandwidth and ensuring system performance.

[0029] In some embodiments, the method 100 may further include: determining a frame blanking period between the current image frame and the next image frame in response to a write-end signal for the current image frame; determining a second frequency-variable period based on the frame blanking period and the number of clock cycles; and generating the first interrupt signal within the second frequency-variable period in response to the write-end signal for the next image frame to enable the frequency-variable operation. In this manner, the frequency-variable period within which the DDR frequency-variable operation is permitted in the current system is determined by the frame blanking period and the number of clock cycles required for the frequency-variable operation, thereby ensuring that the DDR frequency-variable operation is implemented during the image frame blanking period.

[0030] In some embodiments, determining the second variable frequency period based on the frame blanking period and the number of clock cycles includes: calculating the difference between the frame blanking period and the number of clock cycles; and setting the period corresponding to the moment from the start of the frame blanking period to the time of the difference as the second variable frequency period. In this manner, calculating the difference between the frame blanking period and the number of clock cycles indicates that a number of clock cycles is reserved at the end of the current frame blanking time. Therefore, as long as the system triggers a DDR frequency conversion operation within the variable frequency time, the frequency conversion operation can be completed within the frame blanking period of the current frame, thereby avoiding affecting the capture and writing of the next frame of image.

[0031] In some embodiments, the method 100 may further include: determining, in response to a signal indicating the start of writing a next frame of image, the amount of buffered data to be written to the internal buffer within the number of clock cycles for the next frame of image; detecting in real time whether the remaining buffer space in the internal buffer is greater than the amount of buffered data corresponding to the next frame of image; and generating the first interrupt signal to enable execution of the frequency conversion operation during at least one third frequency conversion period when the remaining buffer space in the internal buffer is greater than the amount of buffered data corresponding to the next frame of image. In this manner, since the amount of data written varies for each frame of image, the amount of buffered data needs to be re-determined at the start of writing each frame of image, thereby preventing memory overflow during the DDR frequency conversion operation.

[0032] In some embodiments, method 100 may further include: if the current frame image is an initial frame image, generating a second interrupt signal after the start write signal of the current frame image and before the number of clock cycles to prohibit execution of the frequency conversion operation. In this manner, since it is impossible to determine the amount of data that can be written to the group of images within the number of clock cycles required for the frequency conversion operation before the initial frame image is written, it is impossible to determine whether an internal buffer overflow will occur if the DDR frequency conversion operation is triggered at this time. Therefore, before the initial frame image determines the amount of buffered data, a second interrupt signal is generated to prohibit the system from triggering the DDR frequency conversion operation based on bandwidth changes during this period, thereby avoiding internal buffer overflow when the system performs the DDR frequency conversion operation.

[0033] In some embodiments, method 100 may further include: generating a second interrupt signal during the frame blanking period in response to a write completion signal for the initial frame image to disable the frequency conversion operation. In this manner, since the frame blanking time of the group of images cannot be determined before the initial frame image, it is impossible to determine whether the DDR frequency conversion operation can be completed within the frame blanking time. Therefore, a second interrupt signal is generated during the frame blanking time of the initial frame image to disable the system from triggering the DDR frequency conversion operation based on bandwidth changes during this period, thereby avoiding affecting the acquisition and writing of the next frame image.

[0034] In some embodiments, the method 100 may further include: if a frame rate update signal is received before the start writing signal of the current frame image, marking the current frame image as the initial frame image; if the frame rate update signal is received after the start writing signal of the current frame image, marking the next frame image as the initial frame image. In this way, when the frame rate of image acquisition changes, the initial frame image is re-marked to determine the amount of buffered data at the current frame rate, thereby enabling the determination of DDR frequency conversion operation in the frame rate change scenario.

[0035] In some embodiments, method 100 may further include: if both the first and second interrupt signals are generated simultaneously, giving priority to responding to the first interrupt signal to allow the frequency conversion operation to be executed. In this manner, as long as the remaining buffer space in the internal cache is greater than the amount of buffered data, the DDR frequency conversion operation is permitted regardless of whether the current frequency conversion time period falls within the frame blanking period. Similarly, as long as the current frequency conversion period falls within the frame blanking period, the DDR frequency conversion operation is permitted regardless of whether the remaining buffer space in the internal cache is greater than the amount of buffered data. Determining the DDR frequency conversion range in these two ways effectively improves frequency conversion adaptability.

[0036] According to an embodiment of the present invention, the number of clock cycles required to perform a frequency conversion operation for a memory access rate is obtained. In response to a start write signal for a current frame image, the amount of cached data to be written to an internal cache within the number of clock cycles for the current frame image is determined; the remaining cache space in the internal cache is detected in real time to determine whether it is greater than the cached data amount; and a first interrupt signal is generated to enable the frequency conversion operation during at least one first variable frequency period when the remaining cache space in the internal cache is greater than the cached data amount. Additionally or alternatively, a frame blanking period is obtained between the current frame image and the next frame image; and a first interrupt signal is generated to enable the frequency conversion operation during a second variable frequency period corresponding to a set number of clock cycles after the start of the frame blanking period, where the set number of clock cycles corresponds to the frame blanking period minus the number of clock cycles required for the frequency conversion operation. In other words, the first interrupt signal is generated to enable the frequency conversion operation for the memory access rate during at least one first variable frequency period and / or the second variable frequency period.

[0037] Figure 2 FIG. 2 is a schematic diagram showing a frequency conversion interval within a frame of a frequency conversion method 200 for image acquisition according to an embodiment of the present invention. Figure 2 The method 200 indicates whether the system is currently allowed to perform a DDR frequency conversion operation based on the remaining buffer space of the internal buffer during the frame image writing period, and includes the following steps 202 to 210.

[0038] In step 202, the number of clock cycles required to perform a DDR frequency conversion operation is obtained through an external processor.

[0039] In some embodiments, the number of clock cycles required to perform the frequency conversion operation is determined based on the clock cycle of the current image acquisition. Specifically, if the clock cycle of the current image acquisition is T and the time to perform the DDR frequency conversion operation is t, then the number of clock cycles X = t / T, that is, the number of clock cycles X represents the number of clock cycles required to perform one DDR frequency conversion operation.

[0040] In step 204, in response to the start writing signal of the frame image Frame i, the frame image Frame i is counted from the start writing time t si After the number of clock cycles X, the amount of cache data M written to the internal cache i Wherein, i is an integer greater than or equal to 1. That is, the cache data volume M represents the amount of data collected by the image acquisition device during the execution of one DDR frequency conversion operation time.

[0041] In step 206, after determining that the frame image Frame i+1 starts writing at time t si+1 After the number of clock cycles X, the amount of cache data M written to the internal cache i+1 Previously, the remaining cache space of the current internal cache was detected in real time to see if it was greater than the cache data volume M.i .

[0042] In step 208, if the remaining buffer space of the current internal buffer is greater than the buffer data amount M i , the first interrupt signal is generated by pulling up the current DDR frequency conversion interrupt. If the first interrupt signal exists, the system is allowed to perform the DDR frequency conversion operation during this period.

[0043] In some embodiments, if the frame image Frame i is an initial frame image, the frame image Frame i is written from the time t si The second interrupt signal is generated by pulling down the current DDR frequency conversion interrupt within the interval of the number X of clock cycles. If the second interrupt signal exists, the system is not allowed to perform the DDR frequency conversion operation during this period.

[0044] In step 210, in response to the start writing signal of the frame image Frame i+1, the frame image Frame i+1 is counted from the start writing time t si+1 After the number of clock cycles X, the amount of cache data M written to the internal cache i+1 , real-time detection of whether the remaining cache space of the current internal cache is greater than the cache data volume M i+1 If so, a first interrupt signal is generated to allow the system to perform a DDR frequency conversion operation during this period.

[0045] Figure 3 FIG. 3 is a schematic diagram showing an inter-frame frequency conversion interval of a frequency conversion method 300 for image acquisition according to an embodiment of the present invention. Figure 3 The method 300 indicates whether the system is currently allowed to perform DDR frequency conversion operation based on the frame blanking time length in the blanking interval between frame images, including the following steps 302 to 306.

[0046] In step 302, in response to the end-writing signal of the frame image Frame i, the end-writing time t of the frame image Frame i is counted. oi To the start writing time t of frame image Frame i+1 si+1 The frame blanking period N between them.

[0047] In some embodiments, the frame blanking period is determined based on the clock cycle of the current image acquisition. Specifically, if the clock cycle of the current image acquisition is T and the frame blanking time is t', then the frame blanking period N = t' / T, that is, the frame blanking period N represents the number of clock cycles of the frame blanking.

[0048] In step 304, the variable frequency time length Y is determined according to the frame blanking period N and the number of clock cycles X.

[0049] In some embodiments, the variable frequency time length Y=NX.

[0050] In step 306, in response to the end-write signal of the frame image Frame i+1, the frame image Frame i+1 is started from the end-write time t oi+1 During the variable frequency time period Y, the first interrupt signal is generated by pulling the current DDR frequency conversion interrupt high. If the first interrupt signal exists, the system is allowed to perform the DDR frequency conversion operation during this period.

[0051] In some embodiments, if the frame image Frame i is the initial frame image, then the time t is written from the end of the frame image Frame i. oi To the start writing time t of frame image Frame i+1 si+1 During the interval, the second interrupt signal is generated by pulling down the current DDR frequency conversion interrupt. If the second interrupt signal exists, the system is not allowed to perform the DDR frequency conversion operation during this period.

[0052] Figure 4 FIG. 4 is a schematic diagram showing the final variable frequency interval of the frequency conversion method 400 for image acquisition according to an embodiment of the present invention. Figure 4 Method 400 simultaneously indicates whether the system currently allows DDR frequency conversion based on the remaining internal buffer space and the frame blanking time. If a first interrupt signal and a second interrupt signal are generated simultaneously, the first interrupt signal is prioritized to allow the frequency conversion. In other words, the current system allows DDR frequency conversion to occur within the union of the intra-frame frequency conversion interval determined by method 200 and the inter-frame frequency conversion interval determined by method 300.

[0053] In some embodiments, if, within the blanking interval between the frame image Frame i and the frame image Frame i+1, the above-mentioned method 200 is used to determine that the DDR frequency conversion interrupt is pulled low to generate the second interrupt signal, and at the same time, the above-mentioned method 300 is used to determine that the DDR frequency conversion interrupt is pulled high to generate the first interrupt signal, then in response to the instruction of method 300, the current DDR frequency conversion interrupt is pulled high to generate the first interrupt signal.

[0054] In some embodiments, if, within the blanking interval between the frame image Frame i and the frame image Frame i+1, the above-mentioned method 200 is used to determine that the DDR frequency conversion interrupt is pulled high to generate a first interrupt signal, and at the same time, the above-mentioned method 300 is used to determine that the DDR frequency conversion interrupt is pulled low to generate a second interrupt signal, then in response to the instruction of method 200, the current DDR frequency conversion interrupt is pulled high to generate the first interrupt signal.

[0055] In some embodiments, if in the blanking interval between the frame image Frame i and the frame image Frame i+1, it is determined by the above method 200 to raise the DDR frequency conversion interrupt to generate the first interrupt signal, and at the same time it is determined by the above method 300 to raise the DDR frequency conversion interrupt to generate the first interrupt signal, then the current DDR frequency conversion interrupt is raised to generate the first interrupt signal.

[0056] In some embodiments, if during the continuous writing of the frame image, the DDR frequency conversion interrupt is determined to be pulled down to generate a second interrupt signal through the above method 200, and the DDR frequency conversion interrupt is determined to be pulled down to generate a second interrupt signal through the above method 300, then the current DDR frequency conversion interrupt is pulled down to generate the second interrupt signal.

[0057] According to another aspect of the present invention, Figure 5 FIG. 5 is a schematic diagram showing the structure of an image acquisition device 500 according to an embodiment of the present invention. Figure 5 The device 500 includes an acquisition module 502 and an intra-frame interruption module 504.

[0058] The acquisition module 502 is configured to acquire the number of clock cycles required to perform a frequency conversion operation for a memory access rate.

[0059] The intra-frame interrupt module 504 is configured to, in response to a start write signal for a current frame image, determine the amount of buffered data to be written to the internal buffer within the number of clock cycles for the current frame image. The intra-frame interrupt module 504 is configured to detect in real time whether the remaining buffer space in the internal buffer is greater than the amount of buffered data. Furthermore, the intra-frame interrupt module 504 is configured to generate a first interrupt signal to enable the frequency conversion operation during at least one first frequency conversion period when the remaining buffer space in the internal buffer is greater than the amount of buffered data.

[0060] In some embodiments, the intra-frame interrupt module 504 may be further configured to generate a second interrupt signal to prohibit the frequency conversion operation after the start writing signal of the current frame image and before the number of clock cycles if the current frame image is an initial frame image.

[0061] Figure 6 FIG. 5 is a schematic diagram showing the structure of another image acquisition device 500 according to an embodiment of the present invention. Figure 6 In some embodiments, the acquisition module 502 is further configured to acquire a frame blanking period between a current frame image and a next frame image, and the apparatus 500 may further include an inter-frame interruption module 506 .

[0062] The interframe interrupt module 506 is configured to generate the first interrupt signal to allow the frequency conversion operation to be performed within a second variable frequency period corresponding to a first set number of clock cycles after the start of the frame blanking period, wherein the set number of clock cycles corresponds to the frame blanking period minus the number of clock cycles required for the frequency conversion operation.

[0063] In some embodiments, the inter-frame interrupt module 506 may be further configured to generate the second interrupt signal in response to the end-of-write signal of the initial frame image within the frame blanking period to prohibit the frequency conversion operation.

[0064] It should be understood that the intra-frame interruption module 504 and / or the inter-frame interruption module 506 may be configured to execute the corresponding steps or actions in the frequency conversion method described above, which will not be described in detail herein.

[0065] In summary, the frequency conversion method and image acquisition device provided by the present invention, during the continuous image acquisition process, counts the amount of buffered data written to the internal cache within the number of clock cycles of the DDR frequency conversion operation for each frame. When the remaining buffer space in the internal cache exceeds the buffered data amount, a first interrupt signal is generated to allow the system to trigger the DDR frequency conversion operation during this period based on bandwidth changes, thereby obtaining sufficient bandwidth. Because the remaining buffer space in the internal cache is greater than the amount of image data written within the number of clock cycles, even if the system triggers a DRR frequency conversion operation, the remaining buffer space can accommodate the amount of data written during the DDR frequency conversion operation, preventing internal buffer overflow. Simultaneously, the frame blanking period between each frame is counted, and a number of clock cycles is reserved at the end of the blanking period between each frame. Therefore, a first interrupt signal is generated during the variable frequency period during the frame blanking period to allow the system to trigger the DDR frequency conversion operation during this period based on bandwidth changes. Because the number of clock cycles is reserved at the end of the blanking period between frames, even if the system triggers a DRR frequency conversion operation, the frame blanking period can meet the execution time of the DDR frequency conversion operation, thus not affecting the writing of the next frame. In this way, the optimal range that can meet the DDR frequency conversion operation is selected based on the remaining buffer space and frame blanking time of the internal cache. There is no need to prevent DDR frequency conversion through mutual exclusion means or to meet DDR frequency conversion requirements by reducing the frame rate of the image acquisition end, which effectively guarantees system performance and optimizes user experience.

[0066] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's description and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A frequency conversion method for image acquisition, characterized in that: include: Obtaining the number of clock cycles required to perform a frequency conversion operation for a memory access rate; In response to a start write signal of a current frame image, determining a buffer data amount of the current frame image to be written into an internal buffer within the number of clock cycles; Real-time detection of whether the remaining cache space of the internal cache is greater than the cache data volume; as well as In at least one first frequency variable period when the remaining buffer space of the internal buffer is greater than the buffer data amount, a first interrupt signal is generated to allow the frequency variable operation to be performed.

2. The method according to claim 1, characterized in that Also includes: Obtaining a frame blanking period between the current frame image and the next frame image; as well as generating the first interrupt signal to allow the frequency conversion operation to be performed within a second frequency variable period corresponding to a first set number of clock cycles after the start of the frame blanking period, The set number of clock cycles corresponds to the frame blanking period minus the number of clock cycles required for the frequency conversion operation.

3. The method according to claim 1, characterized in that Generating a first interrupt signal to allow execution of the frequency conversion operation during at least one first frequency conversion period when the remaining buffer space of the internal buffer is greater than the buffer data amount includes: The first interrupt signal is generated in the at least one first variable frequency period to allow the frequency conversion operation to be performed within a predetermined number of clock cycles from the current frame image to the next frame image, and the predetermined number corresponds to the number of clock cycles required for the frequency conversion operation.

4. The method according to claim 3, characterized in that Also includes: In response to a start-write signal for a next frame of image, determining an amount of cache data of the next frame of image to be written into the internal cache within the number of clock cycles; detecting in real time whether the remaining buffer space of the internal buffer is greater than the buffer data amount corresponding to the next frame image; as well as In at least one third frequency variable period when the remaining buffer space of the internal buffer is greater than the buffer data amount corresponding to the next frame image, the first interrupt signal is generated to allow the frequency conversion operation to be performed.

5. The method according to claim 1, wherein Also includes: If the current frame image is an initial frame image, a second interrupt signal is generated after the start writing signal of the current frame image and before the number of clock cycles to prohibit the frequency conversion operation.

6. The method according to claim 5, characterized in that Also includes: If a frame rate update signal is received before the start writing signal of the current frame image, marking the current frame image as an initial frame image; If the frame rate update signal is received after the start writing signal of the current frame image, the next frame image is marked as the initial frame image.

7. The method according to claim 5, characterized in that Also includes: In response to a write-end signal of the current frame image, determining a frame blanking period between the current frame image and a next frame image; Determining a second variable frequency period according to the frame blanking period and the number of clock cycles; In response to the next frame image writing completion signal, the first interrupt signal is generated within the second frequency variable period to allow the frequency conversion operation to be performed.

8. The method according to claim 7, characterized in that Determining the second variable frequency period according to the frame blanking period and the number of clock cycles includes: Calculating a time difference between the frame blanking period and the number of clock cycles; and A period corresponding to a time from the start of the frame blanking period to the time of the time length difference is set as the second frequency variable period.

9. The method according to claim 7, characterized in that Also includes: In response to the write completion signal of the initial frame image, the second interrupt signal is generated during the frame blanking period to prohibit the frequency conversion operation.

10. The method according to claim 9, characterized in that Also includes: If the first interrupt signal and the second interrupt signal are generated at the same time, the first interrupt signal is responded to first to allow the frequency conversion operation to be performed.

11. An image acquisition device, characterized in that: include: An acquisition module configured to acquire the number of clock cycles required to perform a frequency conversion operation for a memory access rate; as well as The intra-frame interrupt module is configured as follows: In response to a start write signal of a current frame image, determining a buffer data amount of the current frame image to be written into an internal buffer within the number of clock cycles; Real-time detection of whether the remaining cache space of the internal cache is greater than the cache data volume; as well as In at least one first frequency variable period when the remaining buffer space of the internal buffer is greater than the buffer data amount, a first interrupt signal is generated to allow the frequency variable operation to be performed.

12. The device according to claim 11, characterized in that The acquisition module is further configured to acquire a frame blanking period between the current frame image and the next frame image, and the apparatus further includes: an interframe interrupt module configured to generate the first interrupt signal to allow the frequency conversion operation to be performed within a second variable frequency period corresponding to a first set number of clock cycles after the start of the frame blanking period, The set number of clock cycles corresponds to the frame blanking period minus the number of clock cycles required for the frequency conversion operation.

13. An electronic device, characterized in that: include: a memory configured to store an executable program; as well as The processor is configured to call the program so that the electronic device executes the method according to any one of claims 1 to 10.

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