Wafer regional failure detection method, system, electronic device and storage medium

Abstract

The present invention relates to the field of wafer testing technology, and specifically discloses a wafer regional failure detection method, system, electronic device, and storage medium. The method includes: obtaining a failed chip coordinate set in a MAP map of a wafer to be tested, calculating the Cartesian product of the failed chip coordinate set and itself, and calculating the Manhattan distance of each coordinate pair in the Cartesian product; determining a coordinate pair whose Manhattan distance is less than a first threshold as a target coordinate pair, and performing a set-check merge on all target coordinate pairs to determine whether a failed chip region is formed; if a failed chip region is formed, detecting whether the failed chip region has an abnormality based on the failure region type of any failed chip region and the number of failed chips in the failed chip region. The present invention can simply and efficiently implement wafer regional failure detection, help improve chip design and manufacturing processes, and improve product quality and customer satisfaction.

Description

Technical Field

[0001] The present invention relates to the field of wafer testing technology, and in particular to a wafer regional failure detection method, system, electronic equipment and storage medium. Background Art

[0002] In semiconductor manufacturing, wafer testing is a key link in ensuring product quality. It can promptly detect and screen out defective chips and avoid subsequent packaging waste. This link ensures the quality of chips entering the market and reduces manufacturing costs. The most important part of the wafer testing process is the MAP map that reflects the wafer condition. This MAP map is generated by the probe station during the testing process. The MAP map shows the coordinate position of each test chip, the test results, etc., including the coordinates of valid chips and failed chips. The existing technology for analyzing wafer test results mainly identifies individual failure problems (such as the number of failures, failure ratio, and failure category). It ignores regional failure problems. These regional failures may be caused by factors such as material defects, process deviations, or equipment failures, and indicate deeper production, manufacturing, and process problems. If not discovered in time, they will affect product performance and reliability. In addition, the effective test points 1 to 3 circles around a specific regional failure will be affected by the failure area and cannot be actually detected, resulting in the provision of failed chips to customers, causing significant economic losses.

[0003] Therefore, it is urgent to provide a technical solution to solve the above problems. Summary of the Invention

[0004] To solve the above technical problems, the present invention provides a method, system, electronic device and storage medium for detecting regional failures of wafers.

[0005] In a first aspect, the present invention provides a method for detecting regional wafer failures, the technical solution of which is as follows:

[0006] Obtaining a failed chip coordinate set in a MAP of the wafer to be tested, calculating a Cartesian product of the failed chip coordinate set and itself, and calculating a Manhattan distance of each coordinate pair in the Cartesian product;

[0007] Determine the coordinate pairs whose Manhattan distance is less than the first threshold as target coordinate pairs, and perform a union-lookup merge on all target coordinate pairs to determine whether a failed chip area is formed;

[0008] If a failed chip area is formed, whether the failed chip area is abnormal is detected according to the failed chip area type and the number of failed chips in the failed chip area.

[0009] The beneficial effects of the wafer regional failure detection method of the present invention are as follows:

[0010] The method of the present invention can simply and efficiently realize regional failure detection of wafers, help improve chip design and manufacturing processes, and enhance product quality and customer satisfaction.

[0011] Based on the above solution, the wafer regional failure detection method of the present invention can be further improved as follows.

[0012] In an optional manner, the step of determining the failure region type of any failed chip region includes:

[0013] Obtaining position coordinates of any failed chip coordinate in any failed chip region that are respectively away from a second threshold in different directions; if any position coordinate corresponding to the failed chip coordinate is outside the coordinates corresponding to the map, determining the failed chip coordinate as an edge point coordinate, until all edge point coordinates in the failed chip region are determined;

[0014] When the number of edge point coordinates in any failed chip area exceeds a third threshold, the failure area type of the failed chip area is determined to be an edge failure area; otherwise, the failure area type of the failed chip area is determined to be a center failure area.

[0015] In an optional manner, the step of detecting whether any failed chip area has an abnormality according to the failed area type and the number of failed chips in the failed chip area includes:

[0016] When the failure region type of any failed chip region is a marginal failure region, if the number of failed chips in the failed chip region exceeds a fourth threshold, it is determined that the failed chip region has an abnormality; otherwise, it is determined that the failed chip region has no abnormality;

[0017] When the failure area type of any failed chip area is a central failure area, if the number of failed chips in the failed chip area exceeds a fifth threshold, it is determined that the failed chip area has an abnormality; otherwise, it is determined that the failed chip area has no abnormality.

[0018] In an optional manner, the method further includes:

[0019] When any failed chip area has an abnormality, the chip area within a preset range around the failed chip area is determined as a target failed chip area and an early warning prompt message is output.

[0020] In a second aspect, the present invention provides a wafer regional failure detection system, the technical solution of which is as follows:

[0021] Includes: calculation module, processing module and detection module;

[0022] The calculation module is used to: obtain a failed chip coordinate set in a MAP of a wafer to be tested, calculate a Cartesian product of the failed chip coordinate set and itself, and calculate a Manhattan distance of each coordinate pair in the Cartesian product;

[0023] The processing module is configured to: determine a coordinate pair whose Manhattan distance is less than a first threshold as a target coordinate pair, and perform a union-lookup and merge on all target coordinate pairs to determine whether a failed chip area is formed;

[0024] The detection module is configured to: if a failed chip area is formed, detect whether the failed chip area has an abnormality according to the failed area type of any failed chip area and the number of failed chips in the failed chip area.

[0025] The beneficial effects of the wafer regional failure detection system of the present invention are as follows:

[0026] The system of the present invention can simply and efficiently realize regional failure detection of wafers, which helps to improve chip design and manufacturing processes, and enhance product quality and customer satisfaction.

[0027] Based on the above solution, the wafer regional failure detection system of the present invention can also be improved as follows.

[0028] In an optional manner, the method further includes: a determination module; the determination module is configured to:

[0029] Obtaining position coordinates of any failed chip coordinate in any failed chip region that are respectively away from a second threshold in different directions; if any position coordinate corresponding to the failed chip coordinate is outside the coordinates corresponding to the map, determining the failed chip coordinate as an edge point coordinate, until all edge point coordinates in the failed chip region are determined;

[0030] When the number of edge point coordinates in any failed chip area exceeds a third threshold, the failure area type of the failed chip area is determined to be an edge failure area; otherwise, the failure area type of the failed chip area is determined to be a center failure area.

[0031] In an optional manner, the detection module is specifically configured to:

[0032] When the failure region type of any failed chip region is a marginal failure region, if the number of failed chips in the failed chip region exceeds a fourth threshold, it is determined that the failed chip region has an abnormality; otherwise, it is determined that the failed chip region has no abnormality;

[0033] When the failure area type of any failed chip area is a central failure area, if the number of failed chips in the failed chip area exceeds a fifth threshold, it is determined that the failed chip area has an abnormality; otherwise, it is determined that the failed chip area has no abnormality.

[0034] In an optional manner, the system further includes an early warning module; the early warning module is configured to:

[0035] When any failed chip area has an abnormality, the chip area within a preset range around the failed chip area is determined as a target failed chip area and an early warning prompt message is output.

[0036] In a third aspect, the technical solution of an electronic device of the present invention is as follows:

[0037] The invention comprises a memory, a processor and a program stored in the memory and running on the processor. When the processor executes the program, the steps of the wafer regional failure detection method of the present invention are realized.

[0038] In a fourth aspect, the present invention provides a computer-readable storage medium having the following technical solution:

[0039] The computer-readable storage medium stores instructions. When the computer-readable storage medium reads the instructions, the computer-readable storage medium executes the steps of the wafer regional failure detection method of the present invention.

[0040] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are only used to illustrate the embodiments and are not to be considered as limiting the present invention. In addition, the same reference symbols are used to represent the same components throughout the drawings. In the drawings:

[0042] Figure 1 1 is a flow chart of a first embodiment of a method for detecting regional wafer failures according to the present invention;

[0043] Figure 2 MAP diagram of the wafer to be tested;

[0044] Figure 3 1 is a flow chart of a second embodiment of a wafer regional failure detection method according to the present invention;

[0045] Figure 4 It is a structural schematic diagram of an embodiment of a wafer regional failure detection system of the present invention;

[0046] Figure 5 The figure is a schematic structural diagram of an embodiment of an electronic device of the present invention. DETAILED DESCRIPTION

[0047] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0048] Figure 1 The flowchart of the first embodiment of a wafer regional failure detection method provided by the present invention is shown. The wafer regional failure detection method can be executed by an electronic device such as a terminal device or a server. The terminal device can be any fixed or mobile terminal such as a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. The server can be a single server or a server cluster composed of multiple servers. Any electronic device can implement the wafer regional failure detection method by calling the computer-readable instructions stored in the memory through the processor. As Figure 1 As shown, the following steps are included:

[0049] S1. Obtain the failed chip coordinate set in the MAP of the wafer to be tested, calculate the Cartesian product of the failed chip coordinate set and itself, and calculate the Manhattan distance of each coordinate pair in the Cartesian product. In S1, specifically:

[0050] 1) The wafer to be tested is the wafer that needs to be tested for regional failure in this embodiment. Figure 2 As shown, a MAP diagram reflecting the wafer test results is generated during wafer testing, and the coordinates of all test chips (DIEs), including valid or failed chips, are recorded in the MAP diagram.

[0051] 2) The coordinate set of the failed chip in the MAP is: S = {(x i ,y i )|i=1,2,…,n}; n represents the number of failed chips, x i represents the horizontal coordinate of the i-th failed chip, y i represents the vertical coordinate of the i-th failed chip, (x i ,y i ) represents the coordinates of the i-th failed chip, and S represents the set of failed chip coordinates.

[0052] 3) The formula for calculating the Cartesian product of the set of failed chip coordinates and itself is: S×S = {((x i , y i ), (x j , y j )) ∣ (x i , y i ), (x j , y j ) ∈ S, i ≠ j}; x j represents the abscissa of the j-th failed chip, y j represents the ordinate of the j-th failed chip, (x j , y j ) represents the coordinates of the j-th failed chip, and S×S represents the Cartesian product.

[0053] 4) The formula for calculating the Manhattan distance of each coordinate pair in the Cartesian product is: D {ij} = |x i - x j | + |y i - y j |; D {ij} is the Manhattan distance of the coordinate pair formed by the coordinates of the i-th failed chip and the j-th failed chip.

[0054] S2. Determine the target coordinate pairs with Manhattan distance less than the first threshold, and perform union-find set merging on all the target coordinate pairs to determine whether a failed chip region is formed. Specifically in S2:

[0055] 1) The formula for screening the coordinate pairs with Manhattan distance less than the first threshold is: P = {((x I , y I ), (x j , y j )) ∣ D {ij} < N}; P represents the set of target coordinate pairs, N represents the first threshold, and the first threshold is determined according to different product categories and wafer sizes and is not restricted here.

[0056] 2) Merge the target coordinate pairs P in the union-find set to form a failed region C k , where k represents the k-th failed region, C k = {(x i , y i ) ∣ (x i , y i ) ∈ S and (x i , y i ) belong to the same union-find set k. The union-find set is a tree-like data structure, and union-find set merging is used to handle the merging and query problems of some disjoint sets.

[0057] It should be noted that not every MAP image corresponding to the wafer to be tested can form a failed chip area, so it is necessary to determine whether a failed chip area can be formed.

[0058] S3. If a failed chip area is formed, detect whether the failed chip area has any abnormality based on the failed area type and the number of failed chips in the failed chip area. In S3, specifically:

[0059] 1) The types of failure regions include edge failure regions and center failure regions. If a failure chip region is formed, the number of the failure chip region is at least one.

[0060] 2) The step of determining the failure region type of any failed chip region comprises:

[0061] Obtain the position coordinates of any failed chip coordinate in any failed chip area that are respectively away from the second threshold in different directions. If any position coordinate corresponding to the failed chip coordinate is outside the coordinate corresponding to the MAP image, determine the failed chip coordinate as the edge point coordinate until all edge point coordinates in any failed chip area are determined.

[0062] The different directions refer to the four directions of the coordinates of the failed chip, the up, down, left, and right directions. The second threshold can be set according to the actual situation and is not limited here. k Each failed chip (x i ,y i ), calculate the M distance (x i +M,y i ),(x i –M,y i ),(x i ,y i +M),(x i ,y i –M), where M represents the second threshold.

[0063] When the number of edge point coordinates in any failed chip area exceeds a third threshold, the failure area type of the failed chip area is determined to be an edge failure area; otherwise, the failure area type of the failed chip area is determined to be a center failure area.

[0064] The third threshold is set to 50% by default, and can also be set according to actual conditions, and is not limited here.

[0065] 3) The step of detecting whether any failed chip area has an abnormality based on the failed chip area type and the number of failed chips in the failed chip area includes:

[0066] When the failure region type of any failed chip region is a marginal failure region, if the number of failed chips in the failed chip region exceeds a fourth threshold, it is determined that the failed chip region has an abnormality; otherwise, it is determined that the failed chip region has no abnormality.

[0067] When the failure area type of any failed chip area is a central failure area, if the number of failed chips in the failed chip area exceeds a fifth threshold, it is determined that the failed chip area has an abnormality; otherwise, it is determined that the failed chip area has no abnormality.

[0068] The fourth threshold and the fifth threshold are both positive integers, and their specific values ​​can be set according to actual conditions and are not limited here.

[0069] The technical solution of this embodiment can simply and efficiently realize regional failure detection of wafers, which helps to improve chip design and manufacturing processes, and enhance product quality and customer satisfaction.

[0070] Figure 3 FIG. 2 is a flow chart showing a second embodiment of a wafer regional failure detection method provided by the present invention. Figure 3 As shown, the following steps are included:

[0071] S10, obtaining a failed chip coordinate set in a MAP of the wafer to be tested, calculating a Cartesian product of the failed chip coordinate set and itself, and calculating a Manhattan distance of each coordinate pair in the Cartesian product.

[0072] S20, determining the coordinate pairs whose Manhattan distance is less than the first threshold as target coordinate pairs, and performing a union-lookup merge on all target coordinate pairs to determine whether a failed chip area is formed;

[0073] S30 : If a failed chip area is formed, detect whether the failed chip area is abnormal based on the failed chip area type and the number of failed chips in the failed chip area.

[0074] S40: When any failed chip area has an abnormality, the chip area within a preset range around the failed chip area is determined as a target failed chip area and an early warning prompt message is output. In S40, specifically:

[0075] 1) The preset range around the failed chip area represents a circle C around the failed chip area, where the value of C ranges from 0 to 3. For example, if the value of C is 1, all chips in a circle around the failed chip area are set as the target failed chip area. For example, if the value of C is 0, no setting is made and the failed chip area is directly determined as the target failed chip area.

[0076] 2) The warning message can be a text warning message or an audio warning message, and there is no restriction on the specific warning method. The warning message is sent to the target terminal to notify the relevant person in charge through the target terminal, analyze and process the test results, and intercept any possible abnormal problems.

[0077] The technical solution of this embodiment further provides timely alarm processing for regional failure problems, making the test results more stable and reliable. By analyzing the location of the failure area, regional failure detection of wafers can be achieved simply and efficiently, which helps to improve chip design and manufacturing processes, and enhance product quality and customer satisfaction.

[0078] Figure 4 FIG. 2 shows a schematic structural diagram of an embodiment of a wafer regional failure detection system 200 provided by the present invention. Figure 4 As shown, the system 200 includes: a calculation module 210, a processing module 220 and a detection module 230;

[0079] The calculation module 210 is used to: obtain a failed chip coordinate set in a MAP of a wafer to be tested, calculate a Cartesian product of the failed chip coordinate set and itself, and calculate a Manhattan distance of each coordinate pair in the Cartesian product;

[0080] The processing module 220 is configured to: determine the coordinate pairs whose Manhattan distance is less than a first threshold as target coordinate pairs, and perform a union-lookup and merge on all target coordinate pairs to determine whether a failed chip area is formed;

[0081] The detection module 230 is configured to: if a failed chip region is formed, detect whether the failed chip region has an abnormality according to the failed region type and the number of failed chips in the failed chip region.

[0082] In an optional manner, the method further includes: a determination module; the determination module is configured to:

[0083] Obtaining position coordinates of any failed chip coordinate in any failed chip region that are respectively away from a second threshold in different directions; if any position coordinate corresponding to the failed chip coordinate is outside the coordinates corresponding to the map, determining the failed chip coordinate as an edge point coordinate, until all edge point coordinates in the failed chip region are determined;

[0084] When the number of edge point coordinates in any failed chip area exceeds a third threshold, the failure area type of the failed chip area is determined to be an edge failure area; otherwise, the failure area type of the failed chip area is determined to be a center failure area.

[0085] In an optional manner, the detection module is specifically configured to:

[0086] When the failure region type of any failed chip region is a marginal failure region, if the number of failed chips in the failed chip region exceeds a fourth threshold, it is determined that the failed chip region has an abnormality; otherwise, it is determined that the failed chip region has no abnormality;

[0087] When the failure area type of any failed chip area is a central failure area, if the number of failed chips in the failed chip area exceeds a fifth threshold, it is determined that the failed chip area has an abnormality; otherwise, it is determined that the failed chip area has no abnormality.

[0088] In an optional manner, the system further includes an early warning module; the early warning module is configured to:

[0089] When any failed chip area has an abnormality, the chip area within a preset range around the failed chip area is determined as a target failed chip area and an early warning prompt message is output.

[0090] The technical solution of this embodiment can simply and efficiently realize regional failure detection of wafers, which helps to improve chip design and manufacturing processes, and enhance product quality and customer satisfaction.

[0091] The above parameters and steps for each module to implement corresponding functions in the wafer regional failure detection system 200 of this embodiment can refer to the parameters and steps in the embodiment of the wafer regional failure detection method above, and will not be repeated here.

[0092] like Figure 5 As shown, an electronic device 300 according to an embodiment of the present invention includes a processor 320, which is coupled to a memory 310. The memory 310 stores at least one computer program 330. The at least one computer program 330 is loaded and executed by the processor 320, so that the electronic device 300 implements any of the above-mentioned wafer regional failure detection methods. Specifically:

[0093] The electronic device 300 may have relatively large differences due to different configurations or performances, and may include one or more processors 320 (Central Processing Units, CPU) and one or more memories 310, wherein the one or more memories 310 store at least one computer program 330, and the at least one computer program 330 is loaded and executed by the one or more processors 320 to enable the electronic device 300 to implement any of the wafer regional failure detection methods provided in the above embodiments. Of course, the electronic device 300 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The electronic device 300 may also include other components for implementing device functions, which will not be described in detail here.

[0094] A computer-readable storage medium according to an embodiment of the present invention stores at least one computer program, which is loaded and executed by a processor to enable a computer to implement any of the above-mentioned wafer regional failure detection methods.

[0095] Alternatively, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, or the like.

[0096] In an exemplary embodiment, a computer program product or computer program is also provided. The computer program product or computer program includes computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform any of the aforementioned methods for detecting regional wafer failures.

[0097] It should be noted that the terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects and to define a specific order or precedence. Where appropriate, the order used for similar objects may be interchanged, such that the embodiments of the present application described herein can be implemented in an order other than the order shown or described.

[0098] Those skilled in the art will appreciate that the present invention may be implemented as a system, method, or computer program product. Therefore, the present disclosure may be implemented in the following forms: entirely in hardware, entirely in software (including firmware, resident software, microcode, etc.), or in a combination of hardware and software, generally referred to herein as a "circuit," "module," or "system." Furthermore, in some embodiments, the present invention may be implemented in the form of a computer program product embodied in one or more computer-readable media containing computer-readable program code.

[0099] Any combination of one or more computer-readable media can be used. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or device.

[0100] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A wafer regional failure detection method, characterized in that: include: Obtaining a failed chip coordinate set in a MAP of the wafer to be tested, calculating a Cartesian product of the failed chip coordinate set and itself, and calculating a Manhattan distance of each coordinate pair in the Cartesian product; Determine the coordinate pairs whose Manhattan distance is less than the first threshold as target coordinate pairs, and perform a union-lookup merge on all target coordinate pairs to determine whether a failed chip area is formed; If a failed chip area is formed, detecting whether the failed chip area is abnormal based on the failed chip area type and the number of failed chips in the failed chip area; The steps for determining the failure region type of any failed chip region include: Obtaining position coordinates of any failed chip coordinate in any failed chip region that are respectively away from a second threshold in different directions; if any position coordinate corresponding to the failed chip coordinate is outside the coordinates corresponding to the map, determining the failed chip coordinate as an edge point coordinate, until all edge point coordinates in the failed chip region are determined; When the number of edge point coordinates in any failed chip region exceeds a third threshold, determining the failure region type of the failed chip region as an edge failure region; otherwise, determining the failure region type of the failed chip region as a center failure region; The step of detecting whether there is an abnormality in any failed chip area according to the failure area type and the number of failed chips in the failed chip area includes: When the failure region type of any failed chip region is a marginal failure region, if the number of failed chips in the failed chip region exceeds a fourth threshold, it is determined that the failed chip region has an abnormality; otherwise, it is determined that the failed chip region has no abnormality; When the failure area type of any failed chip area is a central failure area, if the number of failed chips in the failed chip area exceeds a fifth threshold, it is determined that the failed chip area has an abnormality; otherwise, it is determined that the failed chip area has no abnormality.

2. The wafer regional failure detection method according to claim 1, characterized in that: Also includes: When any failed chip area has an abnormality, the chip area within a preset range around the failed chip area is determined as a target failed chip area and an early warning prompt message is output.

3. A wafer regional failure detection system, characterized in that: include: Computing module, processing module and detection module; The calculation module is used to: obtain a failed chip coordinate set in a MAP of a wafer to be tested, calculate a Cartesian product of the failed chip coordinate set and itself, and calculate a Manhattan distance of each coordinate pair in the Cartesian product; The processing module is configured to: determine a coordinate pair whose Manhattan distance is less than a first threshold as a target coordinate pair, and perform a union-lookup and merge on all target coordinate pairs to determine whether a failed chip area is formed; The detection module is configured to: if a failed chip area is formed, detect whether the failed chip area has an abnormality according to the failed chip area type and the number of failed chips in the failed chip area; The invention also includes: a determination module; the determination module is used to: Obtaining position coordinates of any failed chip coordinate in any failed chip region that are respectively away from a second threshold in different directions; if any position coordinate corresponding to the failed chip coordinate is outside the coordinates corresponding to the map, determining the failed chip coordinate as an edge point coordinate, until all edge point coordinates in the failed chip region are determined; When the number of edge point coordinates in any failed chip region exceeds a third threshold, determining the failure region type of the failed chip region as an edge failure region; otherwise, determining the failure region type of the failed chip region as a center failure region; The detection module is specifically used for: When the failure region type of any failed chip region is a marginal failure region, if the number of failed chips in the failed chip region exceeds a fourth threshold, it is determined that the failed chip region has an abnormality; otherwise, it is determined that the failed chip region has no abnormality; When the failure area type of any failed chip area is a central failure area, if the number of failed chips in the failed chip area exceeds a fifth threshold, it is determined that the failed chip area has an abnormality; otherwise, it is determined that the failed chip area has no abnormality.

4. The wafer regional failure detection system according to claim 3, characterized in that: Also includes: Early warning module; the early warning module is used to: When any failed chip area has an abnormality, the chip area within a preset range around the failed chip area is determined as a target failed chip area and an early warning prompt message is output.

5. An electronic device, characterized in that: The electronic device includes a processor, which is coupled to a memory. The memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor so that the electronic device implements the wafer regional failure detection method as described in claim 1 or 2.

6. A computer-readable storage medium, characterized in that The computer-readable storage medium stores at least one computer program, which is loaded and executed by a processor so that the computer-readable storage medium implements the wafer regional failure detection method according to claim 1 or 2.

Images