A chip test mode protection circuit and control method thereof

Abstract

The present invention discloses a chip test mode protection circuit and a control method thereof, comprising a pin switching safety circuit, a pin switching module, a test mode module and a normal function mode module. In the test mode, the first pin of the chip inputs a clock signal TCLK, and the second pin of the chip inputs a specific sequence signal TDI. The pin switching safety circuit matches the input specific sequence signal TDI with a pre-stored sequence signal stored internally. If the match is successful, the pin switching module is controlled to switch the connection between the test mode module and the normal function mode module and the first pin and the second pin of the chip. The present invention can ensure that the test mode can be safely entered without adding additional chip pins, and the test mode will not be entered during normal operation.

Description

Technical Field

[0001] The present invention relates to a protection circuit and a control method thereof, in particular to a protection circuit in a chip test mode and a control method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] Chip testing is a vital part of the semiconductor manufacturing process, ensuring that the produced chips meet the design specifications in terms of function and performance. As chip design becomes increasingly complex, the importance of testing also increases. Especially for chips used in mission-critical fields such as automobiles, medical care, and aviation, reliable and thorough testing is essential to avoid potentially catastrophic failures. Therefore, chip testing is not only an important part of ensuring product quality, but also has a significant impact on the efficiency and cost management of the entire supply chain.

[0003] Currently, chip manufacturers on the market are also aware of the importance of chip testing and will add chip test mode circuits to the chips to ensure that the chips are fully functional and performance tested before shipment after packaging to prevent package bonding, parasitic inductance, parasitic resistance, parasitic capacitance, etc. from affecting chip functions. If a problem is found in the chip during testing, the test mode can help locate the specific fault area, which is conducive to later fault analysis.

[0004] In chip circuit testing, testMode and functionMode are two different modes. TestMode is mainly used in the test phase, while functionMode is the normal operating mode. In current chip design, peripheral design tends to be minimalist. Due to the simplified design of chip pins, it is necessary not to add additional pins in the design of test mode. Since the two modes of the chip use the same pins, it is easy for the chip to enter the test mode by mistake during normal operation. Therefore, it is necessary to design a chip test mode protection circuit that can ensure that the test mode can be entered safely and will not enter the test mode during normal operation. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a chip test mode protection circuit and a control method thereof, which ensures safe entry into the test mode without increasing chip pins and effectively prevents the normal mode from mistakenly entering the test mode.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A chip test mode protection circuit comprises a pin switching safety circuit, a pin switching module, a test mode module and a normal function mode module, wherein a first input end of the pin switching safety circuit and a first input end of the pin switching module are connected to a first pin of the chip, a second input end of the pin switching safety circuit and a second input end of the pin switching module are connected to a second pin of the chip, an output end of the pin switching safety circuit is connected to a control end of the pin switching module, a first output end of the pin switching module is connected to a first input end of the test mode module, a second output end of the pin switching module is connected to a first input end of the normal function mode module, and a pin switching circuit is connected to a control end of the pin switching module. The third output end of the switching module is connected to the second input end of the test mode module, the fourth output end of the pin switching module is connected to the second input end of the normal function mode module, and the output end of the normal function mode is connected to the third input end of the pin switching safety circuit. In the test mode, the first pin of the chip inputs the clock signal TCLK, and the second pin of the chip inputs the specific sequence signal TDI. The pin switching safety circuit matches the input specific sequence signal TDI with the pre-stored sequence signal stored internally. If the match is successful, the pin switching module is controlled to switch the connection between the test mode module and the normal function mode module and the first pin and the second pin of the chip.

[0008] Furthermore, the pin switching safety circuit includes a sequence comparison module and a storage module. The storage module stores a pre-stored sequence signal for matching the input specific sequence signal TDI. The comparison module receives the specific sequence signal TDI input from the second pin of the chip. The comparison module simultaneously reads the pre-stored sequence signal stored in the storage module and matches the specific sequence signal TDI with the pre-stored sequence signal. If the match is successful, the comparison module outputs a control signal TEST_EN to the control end of the pin switching module.

[0009] Furthermore, the specific sequence signal TDI includes at least one specific sequence input key. Assuming the number of specific sequence input keys is n, the n specific sequence input keys are respectively specific sequence input key KEY1, specific sequence input key KEY2, ..., specific sequence input key KEYn.

[0010] Furthermore, the pre-stored sequence signal also includes n pre-stored sequence keys, and the n-segment specific sequence input keys are matched one by one with the n pre-stored sequence keys. When the n-segment specific sequence input keys are all matched with the n pre-stored sequence keys successfully, the comparison module outputs a control signal TEST_EN to the control end of the pin switching module.

[0011] Furthermore, all the specific sequence input keys in the n segments of specific sequence input keys are all the same, partially the same, or all different.

[0012] Furthermore, in the normal working mode, the normal function mode module periodically sends a reset signal to the pin switching safety circuit to clear the matching result data in the pin switching safety circuit.

[0013] A control method for a chip test mode protection circuit comprises the following steps:

[0014] S1, after the chip is powered on, delay time t until the power supply and clock inside the chip run stably;

[0015] S2, inputting a clock signal TCLK to the first pin of the chip, and inputting a specific sequence signal TDI to the second pin of the chip, wherein the specific sequence signal TDI includes a specific sequence input key KEY1, a specific sequence input key KEY2, ..., a specific sequence input key KEYn;

[0016] S3, the comparison module receives the specific sequence input key KEY1 input from the second pin of the chip, and the comparison module simultaneously reads the first pre-stored sequence key stored in the storage module and matches the specific sequence input key KEY1 with the first pre-stored sequence key. If the match is successful, the comparison module continues to receive the specific sequence input key KEY2 input from the second pin of the chip, and stops if the match fails.

[0017] S4, the comparison module receives the specific sequence input key KEY2 input from the second pin of the chip, and the comparison module simultaneously reads the second pre-stored sequence key stored in the storage module and matches the specific sequence input key KEY2 with the second pre-stored sequence key. If the match is successful, the comparison module continues to receive the specific sequence input key KEY3 input from the second pin of the chip, and stops if the match fails;

[0018] S5, using the same process as step S4 to sequentially match the specific sequence input key KEY3 until the specific sequence input key KEYn, when the specific sequence input key KEYn successfully matches the nth pre-stored sequence key, the comparison module waits for one clock cycle to confirm that the key match is successful and outputs a control signal TEST_EN to the control end of the pin switching module;

[0019] S6. The control end of the pin switching module receives the control signal TEST_EN, and controls the pin switching module to perform pin switching so that the first pin and the first pin of the chip are switched from the state of being connected to the normal function mode module to the state of being connected to the test mode module, and the chip safely enters the test mode.

[0020] Furthermore, the clock signal TCLK and the specific sequence signal TDI are offset by half a clock cycle.

[0021] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a chip test mode protection circuit and a control method thereof, which can ensure safe entry into the test mode without adding additional chip pins, and will not enter the test mode during normal operation; at the same time, the present invention not only ensures safe entry into the test mode, but also effectively prevents misoperation and malicious attacks by regularly clearing stored data and maintaining the output state during normal operation, thereby improving the overall security of the chip system. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of a chip test mode protection circuit of the present invention.

[0023] Figure 2 It is a flow chart of a control method of a chip test mode protection circuit of the present invention.

[0024] Figure 3 It is a signal waveform diagram of a protection circuit in a chip test mode of the present invention. DETAILED DESCRIPTION

[0025] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0026] like Figure 1As shown, a chip test mode protection circuit of the present invention comprises a pin switching safety circuit, a pin switching module, a test mode module and a normal function mode module, wherein a first input end of the pin switching safety circuit and a first input end of the pin switching module are connected to a first pin of the chip, a second input end of the pin switching safety circuit and a second input end of the pin switching module are connected to a second pin of the chip, an output end of the pin switching safety circuit is connected to a control end of the pin switching module, a first output end of the pin switching module is connected to a first input end of the test mode module, and a second output end of the pin switching module is connected to a first input end of the normal function mode module. The third output end of the pin switching module is connected to the second input end of the test mode module, the fourth output end of the pin switching module is connected to the second input end of the normal function mode module, and the output end of the normal function mode is connected to the third input end of the pin switching safety circuit. In the test mode, the first pin of the chip inputs the clock signal TCLK, and the second pin of the chip inputs the specific sequence signal TDI. The pin switching safety circuit matches the input specific sequence signal TDI with the pre-stored sequence signal stored internally. If the match is successful, the pin switching module is controlled to switch the connection between the test mode module and the normal function mode module and the first pin and the second pin of the chip.

[0027] The pin switching safety circuit includes a sequence comparison module and a storage module. The storage module stores a pre-stored sequence signal for matching the input specific sequence signal TDI. The comparison module receives the specific sequence signal TDI input from the second pin of the chip. The comparison module simultaneously reads the pre-stored sequence signal stored in the storage module and matches the specific sequence signal TDI with the pre-stored sequence signal. If the match is successful, the comparison module outputs a control signal TEST_EN to the control end of the pin switching module.

[0028] The specific sequence signal TDI includes at least one specific sequence input key. Assuming the number of the specific sequence input keys is n, the n specific sequence input keys are respectively specific sequence input key KEY1, specific sequence input key KEY2, ..., specific sequence input key KEYn.

[0029] The pre-stored sequence signal also includes n pre-stored sequence keys. The n-segment specific sequence input keys are matched one by one with the n pre-stored sequence keys. When the n-segment specific sequence input keys are all matched with the n pre-stored sequence keys, the comparison module outputs a control signal TEST_EN to the control end of the pin switching module.

[0030] All the specific sequence input keys in the n-segment specific sequence input keys are completely identical, partially identical, or completely different.

[0031] In the normal working mode, the normal function mode module periodically sends a reset signal to the pin switching safety circuit to clear the matching result data in the pin switching safety circuit.

[0032] like Figure 2 As shown, a control method for a chip test mode protection circuit comprises the following steps:

[0033] S1. After the chip is powered on, delay time t until the power supply and clock inside the chip are stable. This step ensures that all internal components are ready before the chip enters the test mode.

[0034] S2. Input a clock signal TCLK to the first pin of the chip, and input a specific sequence signal TDI to the second pin of the chip. The specific sequence signal TDI includes a specific sequence input key KEY1, a specific sequence input key KEY2, ..., a specific sequence input key KEYn.

[0035] like Figure 3 As shown, the clock signal TCLK and the specific sequence signal TDI are offset by half a clock cycle to ensure sampling at the middle position of the data, thereby ensuring accurate input and sampling of the data.

[0036] S3. The comparison module receives the specific sequence input key KEY1 input from the second pin of the chip. The comparison module simultaneously reads the first pre-stored sequence key stored in the storage module and matches the specific sequence input key KEY1 with the first pre-stored sequence key. If the match is successful, the comparison module continues to receive the specific sequence input key KEY2 input from the second pin of the chip. If the match fails, the comparison module stops.

[0037] S4. The comparison module receives the specific sequence input key KEY2 input from the second pin of the chip. The comparison module simultaneously reads the second pre-stored sequence key stored in the storage module and matches the specific sequence input key KEY2 with the second pre-stored sequence key. If the match is successful, the comparison module continues to receive the specific sequence input key KEY3 input from the second pin of the chip. If the match fails, the comparison module stops.

[0038] S5. Use the same process as step S4 to match the specific sequence input key KEY3 in sequence until the specific sequence input key KEYn. When the specific sequence input key KEYn successfully matches the nth pre-stored sequence key, the comparison module waits for one clock cycle to confirm that the key match is successful and outputs a control signal TEST_EN to the control end of the pin switching module.

[0039] S6. The control end of the pin switching module receives the control signal TEST_EN, and controls the pin switching module to perform pin switching so that the first pin and the first pin of the chip are switched from the state of being connected to the normal function mode module to the state of being connected to the test mode module, and the chip safely enters the test mode.

[0040] Once in the test mode, the chip will execute a series of preset test programs to verify its functions and performance. These test programs may include but are not limited to DC parameter testing, IDD testing, functional testing, and AC testing. The present invention realizes safe entry and effective testing of the chip test mode, ensuring the quality and reliability of the chip before leaving the factory.

[0041] After the test is complete, there usually needs to be a way to safely exit the test mode and resume normal operation. This can be achieved by entering a specific sequence again, resetting the chip, or other safety mechanisms.

[0042] The present invention requires multiple consecutive inputs of a specific sequence of input keys to enter the test mode, and the multiple specific sequence input keys must be continuous and uninterrupted. This design ensures that only strictly verified inputs can trigger the test mode to prevent misoperation or malicious attacks. In the normal function mode, the chip will periodically clear the stored data in the pin switching safety circuit to avoid entering the test function mode by mistake due to sequence accumulation. This periodic clearing mechanism ensures the stability and security of the system.

[0043] When the chip is working normally, the first pin and the second pin are in output state, and no clock and data are input to the pin to switch the security circuit, thereby avoiding entering the test mode by mistake. After the test mode module is connected to the pin, the preset test mode security key still needs to be entered to access the test mode.

[0044] The present invention provides a chip test mode protection circuit and a control method thereof, which can ensure safe entry into the test mode without adding additional chip pins, and will not enter the test mode during normal operation; at the same time, the present invention not only ensures safe entry into the test mode, but also effectively prevents misoperation and malicious attacks by regularly clearing stored data and maintaining the output state during normal operation, thereby improving the overall security of the chip system.

[0045] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A chip test mode protection circuit, characterized in that: The invention comprises a pin switching safety circuit, a pin switching module, a test mode module and a normal function mode module, wherein a first input end of the pin switching safety circuit and a first input end of the pin switching module are connected to a first pin of a chip, a second input end of the pin switching safety circuit and a second input end of the pin switching module are connected to a second pin of the chip, an output end of the pin switching safety circuit is connected to a control end of the pin switching module, a first output end of the pin switching module is connected to a first input end of the test mode module, a second output end of the pin switching module is connected to a first input end of the normal function mode module, a third output end of the pin switching module is connected to a second input end of the test mode module, a fourth output end of the pin switching module is connected to a second input end of the normal function mode module, and an output end of the normal function mode is connected to a third input end of the pin switching safety circuit. In the test mode, The first pin of the chip inputs a clock signal TCLK, the second pin of the chip inputs a specific sequence signal TDI, the pin switching safety circuit matches the input specific sequence signal TDI with the pre-stored sequence signal stored internally, and if the match is successful, the pin switching module is controlled to switch the connection between the test mode module and the normal function mode module and the first pin and the second pin of the chip; the pin switching safety circuit comprises a sequence comparison module and a storage module, the storage module stores a pre-stored sequence signal for matching the input specific sequence signal TDI, the comparison module receives the specific sequence signal TDI input by the second pin of the chip, the comparison module simultaneously reads the pre-stored sequence signal stored in the storage module and matches the specific sequence signal TDI with the pre-stored sequence signal, and if the match is successful, the comparison module outputs a control signal TEST_EN to the control end of the pin switching module.

2. The chip test mode protection circuit according to claim 1, characterized in that: The specific sequence signal TDI includes at least one specific sequence input key. Assuming the number of specific sequence input keys is n, the n specific sequence input keys are respectively specific sequence input key KEY1, specific sequence input key KEY2, ..., specific sequence input key KEYn.

3. The chip test mode protection circuit according to claim 2, characterized in that: The pre-stored sequence signal also includes n pre-stored sequence keys, and the n specific sequence input keys are matched one by one with the n pre-stored sequence keys. When the n specific sequence input keys are all matched with the n pre-stored sequence keys, the comparison module outputs a control signal TEST_EN to the control end of the pin switching module.

4. The chip test mode protection circuit according to claim 2, characterized in that: All the specific sequence input keys in the n segments of specific sequence input keys are completely identical, partially identical, or completely different.

5. The chip test mode protection circuit according to claim 1, characterized in that: In the normal working mode, the normal function mode module periodically sends a reset signal to the pin switching safety circuit to clear the matching result data in the pin switching safety circuit.

6. A method for controlling a chip test mode protection circuit according to any one of claims 1 to 5, characterized in that The following steps are involved: S1, after the chip is powered on, delay time t until the power supply and clock inside the chip run stably; S2, inputting a clock signal TCLK to the first pin of the chip, and inputting a specific sequence signal TDI to the second pin of the chip, wherein the specific sequence signal TDI includes a specific sequence input key KEY1, a specific sequence input key KEY2, ..., a specific sequence input key KEYn; S3, the comparison module receives the specific sequence input key KEY1 input from the second pin of the chip, and the comparison module simultaneously reads the first pre-stored sequence key stored in the storage module and matches the specific sequence input key KEY1 with the first pre-stored sequence key. If the match is successful, the comparison module continues to receive the specific sequence input key KEY2 input from the second pin of the chip, and stops if the match fails. S4, the comparison module receives the specific sequence input key KEY2 input from the second pin of the chip, and the comparison module simultaneously reads the second pre-stored sequence key stored in the storage module and matches the specific sequence input key KEY2 with the second pre-stored sequence key. If the match is successful, the comparison module continues to receive the specific sequence input key KEY3 input from the second pin of the chip, and stops if the match fails; S5, using the same process as step S4 to sequentially match the specific sequence input key KEY3 until the specific sequence input key KEYn, when the specific sequence input key KEYn successfully matches the nth pre-stored sequence key, the comparison module waits for one clock cycle to confirm that the key match is successful and outputs a control signal TEST_EN to the control end of the pin switching module; S6. The control end of the pin switching module receives the control signal TEST_EN, and controls the pin switching module to switch the pins so that the first pin and the second pin of the chip are switched from the state of being connected to the normal function mode module to the state of being connected to the test mode module, and the chip safely enters the test mode.

7. The control method according to claim 6, characterized in that: The clock signal TCLK and the specific sequence signal TDI are offset by half a clock cycle.

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