Display panel and display device

Abstract

The present application relates to a display panel and a display device, and relates to the field of display. The display panel includes: a display area, the display area includes multiple first scan lines and multiple second scan lines; a non-display area, the non-display area includes at least two shift register groups, each shift register group includes multiple cascaded shift registers, the i-th stage shift register output end in the first shift register group is electrically connected to the first scan line connected to the 2i-1 row pixel circuit, and the i+m-th stage shift register output end in the first shift register group is electrically connected to the second scan line connected to the 2i-1 row pixel circuit; the i-th stage shift register output end in the second shift register group is electrically connected to the first scan line connected to the 2i row pixel circuit, and the i+m-th stage shift register output end in the second shift register group is electrically connected to the second scan line connected to the 2i row pixel circuit, where i is greater than or equal to 1 and m is greater than or equal to 2. The present application can improve display performance.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, organic light-emitting display panels are increasingly being used in mobile phones, computers, televisions, automotive display panels, wearable devices and other display panels due to their advantages such as self-luminescence, low driving voltage, high luminous efficiency, fast response speed, thinness and high contrast. However, the display performance of these panels is currently poor. Summary of the Invention

[0003] Based on this, it is necessary to provide a display panel and a display device that can improve display performance.

[0004] In a first aspect, an embodiment of the present application provides a display panel, comprising:

[0005] a display area, the display area including a plurality of pixel circuits arranged in an array, the pixel circuits being configured to drive light-emitting elements to emit light, the pixel circuits including a reset module and a data write module; the display area including a plurality of first scan lines and a plurality of second scan lines, the first scan lines being electrically connected to control terminals of the reset modules of at least some of the pixel circuits located in the same row, and the second scan lines being electrically connected to control terminals of the data write modules of at least some of the pixel circuits located in the same row;

[0006] A non-display area, wherein the non-display area includes at least two shift register groups, each of the shift register groups includes multiple cascaded shift registers, wherein the output end of the i-th shift register in the first shift register group is electrically connected to the first scan line connected to the 2i-1-th row of pixel circuits, and the output end of the i+m-th shift register in the first shift register group is electrically connected to the second scan line connected to the 2i-1-th row of pixel circuits; the output end of the i-th shift register in the second shift register group is electrically connected to the first scan line connected to the 2i-th row of pixel circuits, and the output end of the i+m-th shift register in the second shift register group is electrically connected to the second scan line connected to the 2i-th row of pixel circuits, wherein i is greater than or equal to 1, and m is greater than or equal to 2.

[0007] In a second aspect, an embodiment of the present application provides a display device, comprising the display panel as described above.

[0008] In the above-mentioned display panel and display device, the i-th stage shift register in the first shift register group is electrically connected to the reset module of the 2i-1-th row pixel circuit through the first scan line, and the i+m-th stage shift register in the first shift register group is electrically connected to the data writing module of the 2i-1-th row pixel circuit through the second scan line, the i-th stage shift register in the second shift register group is electrically connected to the reset module of the 2i-th row pixel circuit through the first scan line, and the i+m-th stage shift register in the second shift register group is electrically connected to the data writing module of the 2i-th row pixel circuit through the second scan line, so that the pixels in the same pixel circuit are electrically connected to the reset module of the 2i-th row pixel circuit. The two shift registers connected to the reset module and the data writing module are spaced m levels apart. Since the shift registers in the same shift register group are cascaded, there is a time interval between the enable pulses of the scanning signals generated by the two shift registers spaced m levels apart, and the larger m is, the larger the time interval between the first scanning signal received by the reset module and the second scanning signal received by the data writing module. That is, by designing the m value, the timing relationship between the reset module and the data writing module of the same pixel circuit can be adjusted and controlled, thereby meeting the timing design requirements between different modules in the pixel circuit, and further achieving the purpose of improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1 A schematic structural diagram of a display panel provided in this application;

[0011] Figure 2 A schematic structural diagram of a pixel circuit and a light-emitting element provided in this application;

[0012] Figure 3a A schematic structural diagram of another display panel provided in this application;

[0013] Figure 3b A schematic structural diagram of another display panel provided in this application;

[0014] Figure 4 A schematic structural diagram of another pixel circuit and light-emitting element provided in this application;

[0015] Figure 5 A timing diagram of multiple signals received by two rows of pixel circuits in a display panel provided by the present application;

[0016] Figure 6 A schematic diagram of a bright line under black text on a display panel and the potentials of driving transistors corresponding to two pixel circuits;

[0017] Figure 7 A schematic diagram of the timing of multiple signals received by a pixel circuit of a display panel using DDL technology when a bright line is under a black character;

[0018] Figure 8 A schematic diagram of first frame brightness testing corresponding to various staggered connection methods of a display panel provided in an embodiment of the present application;

[0019] Figure 9 A schematic diagram of the timing of multiple signals received by two rows of pixel circuits in a display panel;

[0020] Figure 10a A timing diagram of two rows of pixel circuits in a display panel provided by the present application receiving multiple signals;

[0021] Figure 10b A timing diagram of two rows of pixel circuits receiving multiple signals in another display panel provided by the present application;

[0022] Figure 11 A schematic structural diagram of another display panel provided in this application;

[0023] Figure 12 A timing diagram of a first control signal, a first scanning signal, and a second scanning signal provided in this application;

[0024] Figure 13 A schematic structural diagram of another display panel provided in this application;

[0025] Figure 14 A schematic structural diagram of another display panel provided in this application;

[0026] Figure 15 A timing diagram of multiple signals in a display panel provided by this application;

[0027] Figure 16 This is a schematic structural diagram of a display device provided in this application.

[0028] Description of reference numerals:

[0029] Pixel circuit 10, reset module 11, data writing module 12, bias module 13, shift register group 20, first shift register group 21, second shift register group 22, third shift register group 23, fourth shift register group 24, first scan line 31, second scan line 32, third scan line 33, first gating module 40, first sub-gating unit 41, second sub-gating unit 42, second gating module 50, second gating unit 51, data line 70, first data line 71, second data line 72, third data line 73, fourth data line 74, multiplexer 60, switch module 80, first switch module 81, second switch module 82, third switch module 83, fourth switch module 84, selection line 90, first selection line 91, second selection line 91, third selection line 92, fourth selection line 93, display panel 100, cascade signal line 101, transmission signal line 102, cascade signal line 103, display device 200. DETAILED DESCRIPTION

[0030] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0032] It will be understood that the terms "first," "second," etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first data line may be referred to as a second data line, and similarly, a second data line may be referred to as a first data line, without departing from the scope of this application. Both the first data line and the second data line are data lines, but they are not the same data line. In the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other. "At least one" means one or more, and "plurality" means two or more. "At least a portion of an element" means part or all of an element. When used herein, the singular forms "a," "an," and "said / the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprising" or "having" etc. specify the presence of stated features, integers, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0033] As described in the background section, display panels in related art exhibit poor display performance. The display panel is provided with a shift register group, which includes multiple cascaded shift registers (VSRs). Each shift register is used to provide a scan signal to a pixel circuit, controlling the row-by-row drive of the pixel circuits in the display panel. However, in related art, the connection method between the shift register and the pixel circuit cannot meet the timing requirements of the pixel circuit, resulting in poor display quality on the display panel. For example, problems such as horizontal stripes and bright lines under black text are prone to occur.

[0034] Based on the above technical problems, the inventors have discovered that by electrically connecting the reset module and the data writing module of the pixel circuit in the same row to two shift registers separated by m levels in the same shift register group, the timing relationship between the signal received by the reset module and the signal received by the data writing module of the same pixel circuit can be regulated by the m value, thereby meeting the timing requirements of the pixel circuit and improving the display effect.

[0035] Based on the above, the inventors further studied the technical solutions of the embodiments of the present application. Specifically, the display panel provided by the embodiments of the present application includes a display area and a non-display area, the display area includes a plurality of pixel circuits arranged in an array, the pixel circuit is used to drive the light-emitting element to emit light, and the pixel circuit includes a reset module and a data writing module; the display area includes a plurality of first scan lines and a plurality of second scan lines, the first scan line is electrically connected to the control end of the reset module of at least part of the pixel circuits in the same row, and the second scan line is electrically connected to the control end of the data writing module of at least part of the pixel circuits in the same row; the non-display area includes at least two shift register groups, each shift register group includes a plurality of cascaded shift registers. A device, wherein the output end of the i-th stage shift register in the first shift register group is electrically connected to the first scan line connected to the 2i-1-th row pixel circuit, and the output end of the i+m-th stage shift register in the first shift register group is electrically connected to the second scan line connected to the 2i-1-th row pixel circuit; the output end of the i-th stage shift register in the second shift register group is electrically connected to the first scan line connected to the 2i-th row pixel circuit, and the output end of the i+m-th stage shift register in the second shift register group is electrically connected to the second scan line connected to the 2i-th row pixel circuit, wherein i is greater than or equal to 1, and m is greater than or equal to 2.

[0036] By adopting the above technical solution, by setting two groups of shift registers and pixel circuits in staggered connection, the reset module and data writing module of the same pixel circuit are respectively connected to two shift registers in the same shift register group with an interval of m levels. Since the shift registers in the same shift register group are cascaded, there is a time interval between the enable pulses of the scanning signal generated by the two shift registers with an interval of m levels, and the larger m is, the larger the time interval between the first scanning signal received by the reset module and the second scanning signal received by the data writing module. That is, by designing the m value, the timing relationship between the reset module and the data writing module of the same pixel circuit can be adjusted and controlled, thereby meeting the timing design requirements between different modules in the pixel circuit, and further achieving the purpose of improving the display effect of the display panel.

[0037] The above is the core concept of this application. The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of this application.

[0038] Figure 1 A schematic structural diagram of a display panel provided in an embodiment of the present application is shown in FIG. Figure 2 This is a schematic diagram of the structure of a pixel circuit 10 and a light-emitting element D provided in an embodiment of the present application. Figure 1 and Figure 2In one embodiment, the present application provides a display panel, which includes a display area AA and a non-display area.

[0039] The display area AA includes a plurality of pixel circuits 10 arranged in an array. The pixel circuits 10 are electrically connected to the light emitting elements and are used to drive the light emitting elements to emit light. That is, the pixel circuits 10 do not include dummy pixel circuits.

[0040] The pixel circuit 10 includes a reset module 11 and a data writing module 12. Exemplarily, the pixel circuit 10 further includes a driving transistor M0, wherein a gate of the driving transistor M0 is electrically connected to a first terminal of the reset module 11, a first electrode of the driving transistor M0 is electrically connected to a second terminal of the data writing module 12, a second electrode of the driving transistor M0 is electrically connected to a light-emitting element D, a second terminal of the reset module 11 receives a reset signal Vref1, a control terminal of the reset module 11 receives a first scan signal Scan1, a first terminal of the data writing module 12 receives a data signal Vdata, and a control terminal of the data writing module 12 receives a second scan signal Scan2. For ease of description, the connection node between the gate of the driving transistor M0 and the first terminal of the reset module 11 is denoted as node N1, and the connection node between the first electrode of the driving transistor M0 and the data writing module 12 is denoted as node N2. Exemplarily, the reset module 11 includes a reset transistor. For example, the reset transistor can be a thin film transistor (TFT), such as a low temperature polysilicon transistor (LTPS) or a low temperature polycrystalline oxide transistor (LTPO), or other types of transistors, which are not limited here. At the same time, the number of the reset transistors can be one or more. Exemplarily, the data write module 12 includes a data write transistor. For example, the data write transistor can be a thin film transistor, such as an LTPS TFT, or other types of transistors, which are not limited here.

[0041] The display area AA includes a plurality of first scan lines 31 and a plurality of second scan lines 32. The first scan lines 31 are electrically connected to the control terminals of the reset modules 11 of at least some of the pixel circuits 10 located in the same row, and the second scan lines 32 are electrically connected to the control terminals of the data write modules 12 of at least some of the pixel circuits 10 located in the same row. Exemplarily, each row of pixel circuits 10 is provided with one first scan line 31 and one second scan line 32, wherein the number of first scan lines 31 and second scan lines 32 is greater than or equal to the number of rows of pixel circuits 10 in the display area AA. Exemplarily, the first scan lines 31 are electrically connected to the control terminals of the reset modules 11 of some of the pixel circuits 10 located in the same row, or the first scan lines 31 are electrically connected to the control terminals of the reset modules 11 of all the pixel circuits 10 located in the same row. Exemplarily, the second scan lines 32 are electrically connected to the control terminals of the data write modules 12 of some of the pixel circuits 10 located in the same row, or the second scan lines 32 are electrically connected to the control terminals of the data write modules 12 of all the pixel circuits 10 located in the same row. In applications, which pixel circuits 10 located in the same row the first scan line 31 and the second scan line 32 are electrically connected to can be set according to specific scenarios and are not limited here.

[0042] The non-display area includes at least two shift register groups 20. Each shift register group 20 includes a plurality of cascaded shift registers. Figure 1 The display panel shown includes a first shift register group 21 and a second shift register group 22, wherein the first shift register group 21 includes a plurality of cascaded shift registers 1-scan(x), and the second shift register group 22 includes a plurality of cascaded shift registers 2-scan(x), wherein x represents the xth stage, and x is a positive integer. In the same shift register group, two adjacent shift registers can be electrically connected via a cascade signal line to achieve cascading. Exemplarily, the output end of the current shift register is electrically connected to the input end of the next-stage shift register via a cascade signal line. In another exemplary embodiment, the intermediate node of the current shift register is electrically connected to the input end of the next-stage shift register via a cascade signal line. For example, the shift register is a partitioned frequency division circuit, and the intermediate node is the intermediate node of the partitioned frequency division circuit. The output signal of the intermediate node can be used to control the partitioned frequency division display of the display panel. The intermediate node can be specifically determined according to the actual application scenario. This is only an exemplary explanation and should not be understood as a specific limitation on the cascade between two adjacent shift registers. Figure 1Taking the second shift register group 22 in the example, the output end or intermediate node of the first-stage shift register 2-scan (1) is electrically connected to the input end of the second-stage shift register 2-scan (2) via the cascade signal line 101, and the output end of the second-stage shift register 2-scan (2) is electrically connected to the input end of the third-stage shift register 2-scan (3) via the cascade signal line 103, and so on, until the last stage of the shift register, thereby realizing the cascade connection between the shift registers in the same group. The cascade method of the second shift register 22 is similar to that of the first shift register group 21, and will not be repeated here.

[0043] The output end of the i-th shift register in the first shift register group 21 is electrically connected to the first scan line 31 connected to the pixel circuit 10 in the 2i-1th row, and the output end of the i+m-th shift register in the first shift register group 21 is electrically connected to the second scan line 32 connected to the pixel circuit 10 in the 2i-1th row. The output end of the i-th shift register in the second shift register group 22 is electrically connected to the first scan line 31 connected to the pixel circuit 10 in the 2i-th row, and the output end of the i+m-th shift register in the second shift register group 22 is electrically connected to the second scan line 32 connected to the pixel circuit 10 in the 2i-th row. That is, the first shift register group 21 is electrically connected to the pixel circuits 10 in the odd-numbered rows in the display area AA, and the second shift register group 22 is electrically connected to the pixel circuits 10 in the even-numbered rows in the display area AA. In addition, the reset module 11 and the data writing module 12 in the odd-numbered row pixel circuit 10 are connected to two shift registers in the first shift register group 21 that are spaced m apart, and the reset module 11 and the data writing module 12 in the even-numbered row pixel circuit 10 are connected to two shift registers in the second shift register group 22 that are spaced m apart, that is, the two shift registers connected by the reset module 11 and the data writing module 12 in the pixel circuit 10 are spaced m apart. Wherein, i is greater than or equal to 1, and i is less than or equal to half the number of rows of the pixel circuit 10. The display panel includes N rows of pixel circuits 10, then i can traverse from 1 to N / 2. Wherein, m is greater than or equal to 2, for example, m can be 2, 3, 4 or other positive integers greater than or equal to 2. In application, m can select a suitable value based on factors such as timing design requirements and narrow frame design requirements, which are not limited here.

[0044] It can be understood that, for the first shift register group 21, the output end of the i+m-th stage shift register is electrically connected not only to the second scan line 32 connected to the pixel circuit 10 in the 2i-1th row, but also to the first scan line 31 connected to the pixel circuit 10 in the 4i+2m-3th row. For the second shift register group 22, the output end of the i+m-th stage shift register is electrically connected not only to the second scan line 32 connected to the pixel circuit 10 in the 2i-th row, but also to the first scan line 31 connected to the pixel circuit 10 in the 4i+2m-2th row. That is, the scan signal generated by one shift register can be provided to the reset module 11 of one pixel circuit 10 and the data write module 12 of another pixel circuit 10, respectively. This achieves multiplexing of the shift registers by different pixel circuits 10, reduces the number of shift registers, and helps achieve a narrow frame.

[0045] For example, if Figure 1As shown, the first scan line 31 is electrically connected to the control end of the reset module 11 of all pixel circuits 10 located in the same row, and the second scan line 32 is electrically connected to the control end of the data writing module 12 of all pixel circuits 10 in the same row; taking m=2 as an example, when i=1, the first-stage shift register 1-scan(1) in the first shift register group 21 is electrically connected to the first scan line 31 connected to the pixel circuit 10 in the first row, and the third-stage shift register 1-scan(3) in the first shift register group 21 is electrically connected to the second-stage shift register 1-scan(4) connected to the pixel circuit 10 in the first row. The first-stage shift register 2-scan(1) in the second shift register group 22 is electrically connected to the first scan line 31 connected to the second-row pixel circuit 10, and the third-stage shift register 2-scan(3) in the second shift register group 22 is electrically connected to the second scan line 32 connected to the second-row pixel circuit 10; when i=2, the second-stage shift register 1-scan(2) in the first shift register group 21 is electrically connected to the first scan line 31 connected to the third-row pixel circuit 10, and the fourth-stage shift register 2-scan(3) in the first shift register group 21 is electrically connected to the second scan line 32 connected to the second-row pixel circuit 10. The bit register 1-scan (4) is electrically connected to the second scan line 32 connected to the pixel circuit 10 in the third row, the second-stage shift register 2-scan (2) in the second shift register group 22 is electrically connected to the first scan line 31 connected to the pixel circuit 10 in the fourth row, and the fourth-stage shift register 2-scan (4) in the second shift register group 22 is electrically connected to the second scan line 32 connected to the pixel circuit 10 in the fourth row; when i=3, the third-stage shift register 1-scan (3) in the first shift register group 21 is connected to the pixel circuit 10 in the fifth row. The first scan line 31 of the first shift register group 21 is electrically connected to the first scan line 31, the fifth shift register 1-scan (5) in the first shift register group 21 is electrically connected to the second scan line 32 connected to the fifth row of pixel circuits 10, the third shift register 2-scan (3) in the second shift register group 22 is electrically connected to the first scan line 31 connected to the sixth row of pixel circuits 10, the fifth shift register 2-scan (5) in the second shift register group 22 is electrically connected to the second scan line 32 connected to the sixth row of pixel circuits 10; and so on, until the last row of pixel circuits 10.

[0046] It should be noted that the display panel may further include at least two start signal lines, wherein the first-stage shift register in the shift register group is electrically connected to the start signal line, and different start signal lines are connected to different shift registers and provide different start signals. For example, the display panel further includes a first start signal line and a second start signal line, wherein the input end of the first-stage shift register in the first shift register group 21 is electrically connected to the first start signal line, and the first start signal line provides a first start signal STV1 to start the first shift register group 21; the input end of the first-stage shift register in the second shift register 22 is electrically connected to the second start signal line, and the second start signal line provides a first start signal STV2 to start the second shift register group 22. The first start signal STV1 and the second start signal STV2 can be set accordingly according to the actual display requirements of the display panel, and are not further defined herein.

[0047] In addition, the output end of each shift register and the corresponding scan line (including the first scan line 31 and / or the second scan line 32) can be electrically connected through a transmission signal line. Figure 1 Taking the second-stage shift register 2-scan (2) of the second shift register group 22 as an example, the output end of the second-stage shift register 2-scan (2) is electrically connected to the first scan line 31 connected to the pixel circuit of the fourth row through the transmission signal line 102. It should be noted that, for the same shift register group, the cascade signal line and the transmission signal line may be electrically connected or not electrically connected. For example, when the output end of the first-stage shift register 2-scan (1) is electrically connected to the input end of the second-stage shift register 2-scan (2) through the cascade signal line 101, the cascade signal line 101 and the transmission signal line 102 may be electrically connected; when the intermediate node of the first-stage shift register 2-scan (1) is electrically connected to the input end of the second-stage shift register 2-scan (2) through the cascade signal line 101, the cascade signal line 101 and the transmission signal line 102 are not electrically connected. In applications, the specific method can be determined based on the cascade mode of the shift register group, the connection mode between the shift register and the scan line, etc., and will not be further limited here.

[0048] In this embodiment, the i-th stage shift register in the first shift register group 21 is electrically connected to the reset module 11 of the 2i-1-th row pixel circuit 10 through the first scan line 31, and the i+m-th stage shift register in the first shift register group 21 is electrically connected to the data writing module 12 of the 2i-1-th row pixel circuit 10 through the second scan line 32, the i-th stage shift register in the second shift register group 22 is electrically connected to the reset module 11 of the 2i-th row pixel circuit 10 through the first scan line 31, and the i+m-th stage shift register in the second shift register group 22 is electrically connected to the data writing module 12 of the 2i-th row pixel circuit 10 through the second scan line 32, so that the pixels in the same pixel circuit 10 are electrically connected to the reset module 11 of the 2i-th row pixel circuit 10. The two shift registers connected to the reset module 11 and the data writing module 12 are spaced m levels apart. Since the shift registers in the same shift register group 20 are cascaded, there is a time interval between the enable pulses of the scan signals generated by the two shift registers spaced m levels apart, and the larger m is, the larger the time interval between the first scan signal Scan1 received by the reset module 11 and the second scan signal Scan2 received by the data writing module 12. That is, by designing the m value, the timing relationship between the reset module 11 and the data writing module 12 of the same pixel circuit 10 can be adjusted and controlled, thereby meeting the timing design requirements between different modules in the pixel circuit 10, and further achieving the purpose of improving the display effect of the display panel.

[0049] Furthermore, in the embodiment of the present application, since m is greater than or equal to 2, the two shift registers connected to the reset module 11 and the data writing module 12 in the same pixel circuit 10 are spaced at least two levels apart. Therefore, the time interval between the enable pulses received by the reset module 11 and the data writing module 12 in the same pixel circuit 10 is at least greater than the stage transmission time between the two-stage shift registers. Compared with the connection mode in which the reset module 11 and the data writing module 12 in the same pixel circuit 10 are respectively connected to two shift registers that are only one level apart or adjacent, the present application increases the number of interval levels of the shift registers. That is, by increasing the m value, the number of interval levels between the two shift registers connected to the reset module 11 and the data writing module 12 in the same pixel circuit 10 is increased, thereby increasing the time interval between the enable pulses received by the reset module 11 and the data writing module 12 in the same pixel circuit 10. This can avoid the problem of poor display performance caused by a small time interval, thereby meeting the timing design requirements of the signals received by the reset module 11 and the data writing module 12, and achieving the purpose of improving the display effect.

[0050] Figure 3a A schematic structural diagram of a display panel provided in an embodiment of the present application is shown in FIG. Figure 3a This is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Figure 4This is a schematic diagram of the structure of a pixel circuit 10 and a light-emitting element D provided in an embodiment of the present application. Figure 3a 、 Figure 3b and Figure 4 In one embodiment, the pixel circuit 10 further includes a bias module 13, wherein a first end of the bias module 13 is electrically connected to a first electrode of the driving transistor M0 and a second end of the data writing module 12, respectively, and a second end of the bias module 13 receives a bias signal DVH. The bias module 13 is configured to transmit the bias signal DVH to the first electrode of the driving transistor M0, i.e., the second node N2, in the on state, and reset the potential of the second node N2 to adjust the bias state of the driving transistor M0 so that the driving transistor M0 is in an on-bias (OBS) state, thereby helping to improve display uniformity. Exemplarily, the bias module 13 includes a bias transistor. For example, the bias transistor may be a thin film transistor, such as an LTPS TFT, or other types of transistors, which are not limited herein.

[0051] The display area AA also includes a plurality of third scan lines 33, which are electrically connected to the control terminals of the bias modules 13 of at least some of the pixel circuits 10 located in the same row. Exemplarily, each row of pixel circuits 10 is provided with a corresponding third scan line 33, and the number of third scan lines 33 is greater than or equal to the number of rows of pixel circuits 10 in the display area AA. Exemplarily, the third scan line 33 is electrically connected to the control terminals of the bias modules 13 of some of the pixel circuits 10 located in the same row, or the third scan line 33 is electrically connected to the control terminals of the bias modules 13 of all the pixel circuits 10 located in the same row. In application, which pixel circuits 10 located in the same row the third scan line 33 is electrically connected to can be set according to the specific scenario and is not limited here.

[0052] The non-display area further includes a third shift register group 23, which includes a plurality of cascaded shift registers. Figure 3a and Figure 3bIn the display panel shown, the third shift register group 23 includes a plurality of cascaded shift registers SP*(i), where i represents the i-th stage. The output end of the i-th stage shift register in the third shift register group 23 is electrically connected to the third scan line 33 connected to the 2i-1-th row and the 2i-th row pixel circuit 10, respectively. Wherein, i is greater than or equal to 1, and i is less than or equal to half the number of rows of pixel circuits 10. It should be noted that the display panel may further include a third start signal line, wherein the first stage shift register in the third shift register group 23 may be electrically connected to the third start signal line, and the third start signal line provides a third start signal STV3 to start the third shift register group 23. In addition, the shift registers SP*(i) in the third shift register group 23 can be cascaded through cascade signal lines, and each shift register SP*(i) can be electrically connected to the corresponding third scan line 33 through a transmission signal line. The way in which the third shift register group 23 is cascaded and electrically connected to the third scan line 33 is similar to that of the first shift register group 21 and the second shift register group 22. For details, please refer to the above-mentioned relevant introduction, which will not be repeated here.

[0053] For example, Figure 3a and Figure 3b As shown, taking m=2 as an example, when i=1, the output end of the first-stage shift register SP*(1) in the third shift register group 23 is electrically connected to the third scan line 33 connected to the first and second rows of pixel circuits 10 respectively; when i=2, the output end of the second-stage shift register SP*(2) in the third shift register group 23 is electrically connected to the third scan line 33 connected to the third and fourth rows of pixel circuits 10 respectively; when i=3, the output end of the third-stage shift register SP*(3) in the third shift register group 23 is electrically connected to the third scan line 33 connected to the fifth and sixth rows of pixel circuits 10 respectively; and so on, until the last row of pixel circuits 10.

[0054] It should be noted that the shift register groups provided in the embodiments of the present application can drive pixel circuits using either a unilateral drive method or a bilateral drive method. The drive methods of different shift register groups can be the same or different. In practical applications, the appropriate drive method for each shift register group can be selected based on requirements, and this is not further limited herein.

[0055] Exemplarily, each shift register in a shift register group includes one shift register, and each shift register in the same shift register group is disposed on the same side of display area AA. The pixel circuits in the corresponding row are driven by the single shift register, thereby achieving single-sided driving. In another exemplary embodiment, each shift register in a shift register group includes two shift registers, and the two shift registers in each shift register group are disposed on opposite sides of display area AA. The pixel circuits in the corresponding row are driven simultaneously by the two shift registers in each shift register group, thereby achieving double-sided driving.

[0056] For example, Figure 3a In the display panel shown, each level of shift register 1-scan(i) in the first shift register group 21, each level of shift register 2-scan(i) in the second shift register group 22, and each level of shift register SP*(i) in the third shift register group 21 respectively include a corresponding shift register, wherein the each level of shift register 1-scan(i) in the first shift register group 21 and the each level of shift register 2-scan(i) in the second shift register group are respectively arranged on the left side of the display area AA, and the each level of shift register SP*(i) in the third shift register group 23 are respectively arranged on the right side of the display area AA, and each shift register group drives the pixel circuit of the corresponding row through a single shift register to realize unilateral drive.

[0057] For example, Figure 3b As shown, each level of shift register 1-scan(i) in the first shift register group 21 includes two shift registers, and each level of shift register 2-scan(i) in the second shift register group 22 includes two shift registers. The two shift registers of each level of shift register are respectively arranged on the left and right sides of the display area AA. Each level of shift register in the first shift register group 21 and the second shift register group 22 drives the pixel circuit of the corresponding row simultaneously through the two shift registers, thereby realizing bilateral driving; each level of shift register SP*(i) in the third shift register group 21 includes one shift register, and is respectively arranged on the right side of the display area AA. The pixel circuit of the corresponding row is driven by a single shift register, thereby realizing unilateral driving.

[0058] In this embodiment, the i-th stage shift register in the third shift register group 23 is electrically connected to the bias modules 13 of the 2i-1-th row and the 2i-th row pixel circuits 10 through the third scan line 33, so that one shift register in the third shift register group 23 can simultaneously drive two adjacent rows of pixel circuits 10, that is, the bias module 13 of the pixel circuit 10 is driven in a one-drive-two manner, thereby realizing the multiplexing of the shift registers in the third shift register group 23 by the bias module 13, further reducing the number of shift registers, and helping to achieve a narrow frame.

[0059] Please continue reading Figure 2 and Figure 4 In one embodiment, the pixel circuit 10 further includes a first emission control transistor M4, a second emission control transistor M5, a threshold compensation transistor M6, an initialization transistor M7, and a capacitor Cst. The gates of the first emission control transistor M4 and the second emission control transistor M5 each receive an emission control signal EM. A first electrode of the first emission control transistor M4 is connected to the first end of the capacitor Cst and receives the first power signal PVDD. A second electrode of the first emission control transistor M4 is connected to the second node N2. A first electrode of the second emission control transistor M5 is connected to the second electrode of the threshold compensation transistor M4 and the second electrode of the driving transistor M0. A second electrode of the second emission control transistor M5 is connected to the second electrode of the initialization transistor M7 and the anode of the light-emitting element D. A first electrode of the threshold compensation transistor M6 is connected to the second end of the capacitor Cst, the gate of the driving transistor M0, the second end of the reset module 11, and the first node N1. A first electrode of the initialization transistor M7 receives the initialization signal Vref2, and a cathode of the light-emitting element D receives the second power signal PVEE. The number of threshold compensation transistors M6 can be one or more.

[0060] Figure 2 The pixel circuit 10 shown is a 7T1C structure, in which the gate of the threshold compensation transistor M6 receives the second scan signal Scan2, that is, the threshold compensation transistor M6 and the data writing module 12 multiplex the second scan signal Scan2, which can reduce the number of scan lines in the display panel; the gate of the initialization transistor M7 receives the first scan signal Scan1, that is, the initialization transistor M7 and the reset module 11 multiplex the first scan signal Scan1, which can further reduce the number of scan lines in the display panel. Figure 4 The pixel circuit 10 shown has an 8T1C structure, wherein the gate of the threshold compensation transistor M6 receives the second scan signal Scan2, that is, the threshold compensation transistor M6 and the data writing module 12 reuse the second scan signal Scan2, which can reduce the number of scan lines in the display panel; the gate of the initialization transistor M7 receives the third scan signal SP*, that is, the initialization transistor M7 and the bias module 13 reuse the third scan signal SP*, which can further reduce the number of scan lines in the display panel. It should be noted that the above is only an example. In actual applications, the pixel circuit 10 can also have other structures, such as 9T2C, 10T3C, etc., and is not further limited here.

[0061] Figure 5 This is a timing diagram of multiple signals received by a two-row pixel circuit 10 according to an embodiment of the present application. Figures 1 to 5In one embodiment, the first scan line 31 provides a first scan signal Scan1, wherein the first scan signal Scan1 includes an enable pulse (Pulse) within one frame time. In this embodiment, the first scan signal Scan1 can be referred to as a single pulse signal or a 1Pulse signal. The reset module 11 in the pixel circuit 10 is turned on in response to the enable pulse of the first scan signal Scan1 to reset the gate of the driving transistor M0, i.e., the N1 node, through the reset signal. The effective level of the enable pulse of the first scan signal Scan1 is related to the reset module 11. For example, the reset module 11 includes a P-type transistor, and correspondingly, the effective level of the enable pulse of the first scan signal Scan1 is a low level. For another example, the reset module 11 includes an N-type transistor, and correspondingly, the effective level of the enable pulse of the first scan signal Scan1 is a high level.

[0062] Please continue reading Figures 1 to 5 In one embodiment, the second scan line 32 provides a second scan signal Scan2, wherein the second scan signal Scan2 includes an enable pulse within one frame time, and similarly, the second scan signal Scan2 is also a 1Pulse signal. The data write module 12 in the pixel circuit 10 is turned on in response to the enable pulse of the second scan signal Scan2 to refresh the gate of the driving transistor M0 through the reset signal. The effective level of the enable pulse of the second scan signal Scan2 is related to the data write module 12. For example, the data write module 12 includes a P-type transistor, and correspondingly, the effective level of the enable pulse of the second scan signal Scan2 is a low level. For another example, the data write module 12 includes an N-type transistor, and correspondingly, the effective level of the enable pulse of the second scan signal Scan2 is a high level.

[0063] In an application, the first scan signal Scan1 and the second scan signal Scan2 have the same number of enable pulses in one frame. In the above embodiment, the first scan signal Scan1 and the second scan signal Scan2 have one enable pulse in one frame, that is, the first scan signal Scan1 and the second scan signal Scan2 are both 1-pulse signals. Setting the first scan signal Scan1 and the second scan signal Scan2 to be single-pulse signals can reduce power consumption of the display panel.

[0064] In this embodiment, the first scanning signal Scan1 and the second scanning signal Scan2 are respectively set to 1Pulse signals, so that the gate of the driving transistor M0 is reset and written once within one frame time, thereby avoiding the difference in gate potential of the driving transistors M0 of different rows due to multiple resets or multiple virtual writes before normal writing (such as Figure 6As shown, ① indicates abnormal, ② indicates normal), the gate potential difference of the driving transistor M0 corresponding to the black and white color areas in the display panel is reduced or eliminated, avoiding the problem of bright lines under black characters and bright bars at the junction of black characters, thereby improving the display effect of the display panel.

[0065] Furthermore, the display panel using the DDL (Dual Data Line) technology lengthens the pulse width of the scanning signal used to drive the pixel circuit 10, or in other words, prolongs the duration of the enable pulse of the scanning signal. Therefore, the display panel using the DDL technology uses a multi-pulse signal to drive the pixel circuit 10, and the number of pixel circuits 10 with bright stripes is greater (e.g., Figure 7 As shown in the figure, arrow 1 indicates an abnormality, and arrow 2 indicates a normal state. The bright lines are more noticeable. To address this, this embodiment sets the first scan signal Scan1 and the second scan signal Scan2 to 1Pulse signals, respectively. This reduces or even eliminates the gate potential difference between the drive transistor M0 corresponding to the black and white areas of the display panel, thereby avoiding the problem of bright lines under black text and significantly improving the display quality of the display panel. For more information about DDL technology, please refer to the relevant introduction below.

[0066] Furthermore, in this embodiment, the two shift registers connected to the reset module 11 and the data writing module 12 in the same pixel circuit 10 are spaced m levels apart, and m is set to be greater than or equal to 2. That is, by increasing the m value, the number of interval levels between the two shift registers connected to the reset module 11 and the data writing module 12 in the same pixel circuit 10 can be increased, thereby increasing the time interval between the enable pulses received by the reset module 11 and the data writing module 12 in the same pixel circuit 10, and thus the time for the reset module 11 of the pixel circuits 10 in different rows to reset the N1 node can be lengthened, that is, the duration of the enable pulse of the first scanning signal Scan1 can be extended, thereby ensuring the display brightness of the first frame of the display panel and avoiding the problem of worsening ghosting when the scanning signal is set to 1Pulse, so as to achieve the purpose of improving the display effect.

[0067] Table 1 provides the performance of a conventional display panel, i.e., a display panel using SDL (Single Data Line) technology, 1 Pulse signal drive, and non-VSR misalignment, a display panel using DDL technology and multi-Pulse signal drive, and the display panel of the present application using DDL technology, VSR misaligned m-level connection combined with 1 Pulse signal drive, in different indicators.

[0068] Table 1

[0069] Long / short residual First frame brightness Black text bright strips conventional ★ ★ ★★ DDL+Multi-Pulse ★★ ★★ ★ DDL+dislocation m level+1Pulse ★★★ ★ ★★★

[0070] The more ★, the better the performance. As can be seen from the table above, this application uses DDL technology, VSR staggered m-level and combined with 1Pulse signal drive to optimize the long and short residual and black character brightness problems, and the first frame brightness is comparable to that of conventional display panels. Figure 8 It can be seen that when m=4, that is, ΔT=8H, the brightness of the first frame of the display panel is the best.

[0071] It can be understood that the larger the value of m, the greater the number of stages between the two shift registers connected to the reset module 11 and the data writing module 12 in the same pixel circuit 10, and the longer the time interval between the enable pulses received by the reset module 11 and the data writing module 12 in the same pixel circuit 10. Therefore, before the data writing module 12 responds to the enable pulse of the second scanning signal to transmit the data signal Vdata, the reset module 11 is allowed to respond to the enable pulse of the first scanning signal to reset the gate of the drive transistor M0, i.e., the first node N1. In other words, the reset module 11 is allowed to remain in the conductive state for a longer period of time. Taking m=4 as an example, ΔT=8H, that is, the time interval between the enable pulses received by the reset module 11 and the data writing module 12 in the same pixel circuit 10 is 8H, which is 6H longer than the time interval of 2T corresponding to m=1. Because a single-pulse signal resets the gate potential of the drive transistor M0 less frequently than a multi-pulse signal, the smear problem may be exacerbated. In this regard, the embodiment of the present application adopts an m-level staggered connection to connect the reset module 11 and the data writing module 12 in the same pixel circuit 10, and by setting the m value to be greater than or equal to 2, compared with the case of m=0 or 1, the present application can extend the reset time of the gate of the driving transistor M0 by the reset module 11 in the pixel circuit 10, thereby increasing the gate reset time of the driving transistor M0, so that the gate potential of the driving transistor M0 can also be fully reset when using a 1Pulse signal, thereby effectively improving the afterimage problem.

[0072] Please continue reading Figures 1 to 5In one embodiment, the third scan line 33 provides a third scan signal SP*, wherein the third scan signal SP* includes at least one enable pulse within one frame time. The bias module 13 in the pixel circuit 10 is turned on in response to the enable pulse of the third scan signal SP*, so as to refresh the N2 node through the bias signal, thereby adjusting the bias state of the driving transistor M0, which is also the OBS (ON Bias Stress) process. The effective level of the enable pulse of the third scan signal SP* is related to the bias module 13. For example, the bias module 13 includes a P-type transistor, and correspondingly, the effective level of the enable pulse of the third scan signal SP* is a low level. For another example, the bias module 13 includes an N-type transistor, and correspondingly, the effective level of the enable pulse of the third scan signal SP* is a high level.

[0073] In this embodiment, the shift register in the third shift register group 23 and the third scan line 33 are used to provide the bias module 13 of the pixel circuit 10 with a third scan signal SP* having an enable pulse, so that the bias module 13 can bias and reset the driving transistor M0 in response to the enable pulse of the third scan signal SP*, and reduce the threshold voltage offset of the driving transistor M0 by adjusting the potential of the N2 node, thereby improving the display effect.

[0074] Please continue reading Figures 1 to 5 In one embodiment, within one frame time, the enable pulse provided by the first scan line 31 connected to the pixel circuit 10 in the 2i-1th row is the first enable pulse, the enable pulse provided by the first scan line 31 connected to the pixel circuit 10 in the 2i-th row is the second enable pulse, and the enable pulse provided by the third scan line 33 connected to the pixel circuits 10 in the 2i-1th row and the 2i-th row is the third enable pulse. The third enable pulse covers the first enable pulse and the second enable pulse, that is, the start time of the first enable pulse and the start time of the second enable pulse are no earlier than the start time of the third enable pulse, respectively, and the end time of the first enable pulse and the end time of the second enable pulse are no later than the end time of the third enable pulse, respectively.

[0075] For example, Figure 2 and Figure 4 In the pixel circuit 10 shown in FIG. 1 , the bias module 13, the data writing module 12, and the bias module 13 each include a PTFT. The effective levels of the enable pulses of the first scanning signal Scan1, the second scanning signal Scan2, and the third scanning signal SP* are all low. Based on this, as shown in FIG. Figure 5As shown, within one frame time, the low level start time of the third enable pulse is earlier than the low level start time of the first enable pulse and the low level start time of the second enable pulse, and the low level end time of the third enable pulse is later than the low level end time of the first enable pulse and the low level end time of the second enable pulse.

[0076] It is understandable that the use of DDL technology in the display panel will result in a longer pulse width of the scanning signal driving the pixel circuit 10, that is, the duration of the enable pulse of the scanning signal is prolonged. Figure 5 As shown, in a conventional display panel using SDL technology, the duration of the enable pulse of the scan signal (including the first scan signal Scan1 and the second scan signal Scan2) is relatively short. For example, the duration of the enable pulse of the first scan signal Scan1 of the first row of pixel circuits is t. However, in a display panel using DDL technology, the duration of the enable pulse of the scan signal can be lengthened. For example, the duration of the enable pulse of the first scan signal Scan1 of the first row of pixel circuits is T11, where T11>t. Based on this, in a display panel using DDL technology in the related art, there is a problem in which the scan signal multiplexed by the bias module 13 of two adjacent rows of pixel circuits 10 cannot completely cover the first enable pulse of the scan signal received by the reset module 11 of the two rows of pixel circuits 10. For example, there is a difference in the bias adjustment of the two rows of pixel circuits 10 through the bias module 13, resulting in the problem of fine horizontal stripes. For example, as Figure 9 As shown, the enable pulse of the scanning signal SP*' received by the bias module 13 of the first and second rows of pixel circuits 10 covers the enable pulse Scan1' of the scanning signal received by the reset module 11 of the first row of pixel circuits 10, but partially overlaps with the enable pulse Scan2' of the scanning signal received by the reset module 11 of the second row of pixel circuits 10. There is a difference in the process of resetting the gate of the driving transistor M0 by the reset module 11 of the first and second rows of pixel circuits 10, that is, there is a difference in OBS.

[0077] In response to the above problem, in this embodiment, the third enable pulse received by the bias module 13 of the pixel circuit 10 in the 2i-1 row and the 2i row respectively covers the first enable pulse received by the reset module 11 of the pixel circuit 10 in the 2i-1 row, and the second enable pulse received by the reset module 11 of the pixel circuit 10 in the 2i row, so that the process of resetting the gate of the driving transistor M0 by the bias module 13 of the pixel circuit 10 in the 2i-1 row and the 2i row, that is, the OBS, remains consistent, eliminating the fine horizontal stripes of the odd and even rows caused by the OBS difference, thereby improving the display effect.

[0078] It should be noted that, in this embodiment, the output end of the i-th shift register in the first shift register group 21 is electrically connected to the first scan line 31 connected to the 2i-1 row pixel circuit 10, and the output end of the i+m-th shift register in the first shift register group 21 is electrically connected to the second scan line 32 connected to the 2i-1 row pixel circuit 10; the output end of the i-th shift register in the second shift register group 22 is electrically connected to the first scan line 31 connected to the 2i row pixel circuit 10, and the output end of the i+m-th shift register in the second shift register group 22 is electrically connected to the second scan line 32 connected to the 2i row pixel circuit 10, that is, by adopting the VSR staggered m-level connection method, the time interval between the first enable pulse and the second enable pulse can be lengthened, thereby lengthening the pulse width or duration of the third enable pulse to completely cover the first enable pulse and the second enable pulse, thereby achieving the purpose of improving the display effect.

[0079] Please continue reading Figure 5 In one embodiment, the duration of the first enable pulse is T11, the duration of the second enable pulse is T12, and the duration of the third enable pulse is T13. Wherein, T13>T11, T13>T12. In the T11 stage, the reset module 11 of the 2i-1th row of pixel circuits 10 remains on in response to the first enable pulse. In the T12 stage, the reset module 11 of the 2i-1th row of pixel circuits 10 remains on in response to the second enable pulse. In the T13 stage, the bias modules 13 of the 2i-1th row and the 2i-th row of pixel circuits 10 respectively remain on in response to the corresponding third enable pulse. That is, in the same frame, the duration for which the bias modules 13 of the two rows of pixel circuits 10 driven by the same level shift register in the third shift register group 23 remain on is longer than the duration for which the reset modules 11 of the two rows of pixel circuits 10 remain on.

[0080] In this embodiment, by designing the duration T13 of the third enable pulse to be greater than the duration T11 of the first enable pulse and the duration T12 of the second enable pulse, it is ensured that the third enable pulse can cover the first enable pulse and the second enable pulse within one frame time, thereby avoiding the difference in OBS processes between different rows of pixel circuits 10 due to the inability of the third enable pulse to cover the first enable pulse and the second enable pulse, thereby avoiding the generation of display horizontal stripes, thereby achieving the purpose of improving the display effect.

[0081] Please continue reading Figure 5In one embodiment, T11=T12. That is, the duration T11 of the first enable pulse is consistent with the duration T12 of the second enable pulse. In other words, in the same frame, the reset modules 11 of the pixel circuits 10 in each row remain in the on state for the same duration. This ensures that the pixel circuits 10 in different rows receive the enable pulse of the first scan signal Scan1 via the first scan line 31 for the same duration, ensuring that the pixel circuits 10 in different rows reset the N1 node for the same duration, thereby ensuring display uniformity of the display panel.

[0082] Please continue reading Figure 5 In one embodiment, within one frame time, the enable pulse provided by the second scan line 32 connected to the 2i-1th row of pixel circuits 10 is the fourth enable pulse, and the enable pulse provided by the second scan line 32 connected to the 2ith row of pixel circuits 10 is the fifth enable pulse, wherein the first non-enable phase between two adjacent third enable pulses covers the fourth enable pulse and the fifth enable pulse.

[0083] Among them, the data writing module 12 in the pixel circuit 10 is turned on in response to the enable pulse provided by the second scan line 32, and writes the data signal Vdata. The third scan signal SP* is a non-enable pulse in the first non-enable phase, or in other words, the third scan signal SP* is an invalid level. It can be understood that the third enable pulse corresponds to the OBS phase, and the first non-enable phase between two adjacent third enable pulses is the non-OBS phase, that is, the bias module 13 is disconnected in response to the non-enable pulse of the third scan signal SP*. The first non-enable phase covers the fourth enable pulse and the fifth enable pulse. It can be understood that the start time of the fourth enable pulse and the start time of the fifth enable pulse are not earlier than the start time of the first non-enable phase, and the end time of the fourth enable pulse and the end time of the fifth enable pulse are not later than the end time of the first non-enable phase.

[0084] In this embodiment, within one frame time, the first non-enable phase between two adjacent third enable pulses covers the fourth enable pulse and the fifth enable pulse, ensuring that the data writing modules 12 in different rows of pixel circuits 10 are turned on in response to the fourth enable pulse or the fifth enable pulse to perform the data writing process, and the bias module 13 remains in the disconnected state, thereby achieving the independence between the data writing process and the OBS process, and ensuring the normal display of the display panel.

[0085] Please continue reading Figure 5In one embodiment, the duration of the fourth enable pulse is T14, the duration of the fifth enable pulse is T15, and the duration of the first non-enable phase is T21, T21>T14, T21>T15. During the T14 phase, the data write module 12 of the 2i-1th row of pixel circuits 10 remains on in response to the fourth enable pulse. During the T15 phase, the data write module 12 of the 2i-th row of pixel circuits 10 remains on in response to the fifth enable pulse. During the T21 phase, the bias modules 13 of the 2i-1th row and the 2i-th row of pixel circuits 10 respectively remain off in response to the corresponding third enable pulse. That is, in the same frame, the duration that the bias modules 13 of the two rows of pixel circuits 10 driven by the same level shift register in the third shift register group 23 remain in the off state is longer than the duration that the data write modules 12 of the two rows of pixel circuits 10 remain in the on state.

[0086] In this embodiment, by designing the duration T21 of the first non-enabling phase to be greater than the duration T14 of the fourth enabling pulse and the duration T15 of the fifth enabling pulse, it is ensured that the first non-enabling phase can cover the fourth enabling pulse and the fifth enabling pulse within one frame time, thereby ensuring the independence of the data writing process and the OBS process, and ensuring the normal display of the display panel.

[0087] Please continue reading Figure 5 In one embodiment, T14=T15. That is, the duration T14 of the fourth enable pulse is consistent with the duration T15 of the fifth enable pulse. In other words, in the same frame, the duration for which the data write module 12 of each row of pixel circuits 10 remains in the on state ensures that the pixel circuits 10 in different rows receive the enable pulse of the second scan signal Scan2 via the second scan line 32 for the same duration. This ensures that the pixel circuits 10 in different rows refresh the N2 node for the same duration, thereby ensuring display uniformity of the display panel.

[0088] However, in some embodiments, for a display panel with a higher brightness requirement in the first frame, it is necessary to set the first scan signal Scan1 and the second scan signal Scan2 to multiple pulses. Figure 10a This is a timing diagram of multiple signals received by two rows of pixel circuits 10 provided in an embodiment of the present application. Figure 10b This is another timing diagram of multiple signals received by two rows of pixel circuits 10 provided in an embodiment of the present application. Figures 1 to 4 、 Figure 10a as well as Figure 10b In one embodiment, the first scan line 31 provides a first scan signal Scan1, wherein within one frame time, the first scan signal Scan1 includes at least two enable pulses. In this embodiment, the first scan signal Scan1 can be called a multi-pulse signal. For example, Figure 10a In the example, the number of enable pulses included in the first scan signal Scan1 within one frame time is 3; Figure 10b In the embodiment, the number of enable pulses included in the first scan signal Scan1 within one frame time is 4; the number of enable pulses included in the first scan signal Scan1 within one frame time may also be 2 or other values ​​greater than or equal to 2, which is not limited here.

[0089] Please continue reading Figures 1 to 4 、 Figure 10a as well as Figure 10b In one embodiment, the second scan line 32 provides a second scan signal Scan2, wherein within one frame time, the second scan signal Scan2 includes at least two enable pulses. Similarly, the second scan signal Scan2 is also a multi-pulse signal. For example, Figure 10a In the example, the number of enable pulses included in the second scan signal Scan2 within one frame time is 3; Figure 10b In the embodiment, the number of enable pulses included in the second scan signal Scan2 within one frame time is 4; the number of enable pulses included in the second scan signal Scan2 within one frame time may also be 2 or other values ​​greater than or equal to 2, and is not limited here. Furthermore, the first scan signal Scan1 and the second scan signal Scan2 include the same number of enable pulses.

[0090] In this embodiment, by setting the first scan signal Scan1 and the second scan signal Scan2 as multi-pulse signals respectively, the gate of the driving transistor M0 is reset multiple times and virtually written at least once before normal writing, thereby improving the brightness of the first frame of the display panel, optimizing the ghosting problem, and improving the display effect of the display panel.

[0091] Please continue reading Figures 1 to 4 、 Figure 10a as well as Figure 10b In one embodiment, within one frame time, the enable pulse provided by the first scan line 31 connected to the pixel circuit 10 in the 2i-1th row is the sixth enable pulse, the enable pulse provided by the first scan line 31 connected to the pixel circuit 10 in the 2i-th row is the seventh enable pulse, and the enable pulse provided by the third scan line 33 connected to the pixel circuits 10 in the 2i-1th row and the 2i-th row is the eighth enable pulse, wherein one eighth enable pulse at least covers the first sixth enable pulse and the first seventh enable pulse, that is, the start time of the first sixth enable pulse and the start time of the first seventh enable pulse are no earlier than the start time of one eighth enable pulse, and the end time of the first sixth enable pulse and the end time of the first seventh enable pulse are no later than the end time of the eighth enable pulse.

[0092] For example, Figure 2and Figure 4 In the pixel circuit 10 shown in FIG. 1 , the bias module 13, the data writing module 12, and the bias module 13 each include a PTFT. The effective levels of the enable pulses of the first scanning signal Scan1, the second scanning signal Scan2, and the third scanning signal SP* are all low. Based on this, as shown in FIG. Figure 10a and Figure 10b As shown, within one frame time, the low level start time of an eighth enable pulse is earlier than the low level start time of the first sixth enable pulse and the low level start time of the first seventh enable pulse, and the low level end time of the eighth enable pulse is later than the low level end time of the first sixth enable pulse and the low level end time of the first seventh enable pulse.

[0093] Exemplarily, an eighth enable pulse covers the first p sixth enable pulses and the first p seventh enable pulses, where p is a positive integer, for example, p can be 1, 2, 3 or other integers greater than or equal to 1, which is not limited here. Figure 10a As shown, an eighth enable pulse covers the first sixth enable pulse and the first seventh enable pulse, that is, p=1; as shown in FIG. Figure 10b As shown, one eighth enable pulse covers the first two sixth enable pulses and the first two seventh enable pulses, that is, p=2.

[0094] In this embodiment, the eighth enable pulse received by the bias module 13 of the pixel circuit 10 in the 2i-1 row and the 2i row respectively covers the first sixth enable pulse received by the reset module 11 of the pixel circuit 10 in the 2i-1 row, and the first seventh enable pulse received by the reset module 11 of the pixel circuit 10 in the 2i row, so that the process in which the bias modules 13 of the pixel circuits 10 in the 2i-1 row and the 2i row reset the gate of the driving transistor M0, that is, the OBS, remains consistent, eliminating the fine horizontal stripes caused by the OBS difference and improving the display effect.

[0095] Please continue reading Figures 1 to 4 、 Figure 10a as well as Figure 10bIn one embodiment, the duration of the sixth enable pulse is T16, the duration of the seventh enable pulse is T17, and the duration of the eighth enable pulse is T18, where T18>T16 and T18>T17. During the T16 phase, the reset module 11 of the pixel circuit 10 in the 2i-1th row remains on in response to the sixth enable pulse. During the T17 phase, the reset module 11 of the pixel circuit 10 in the 2i-1th row remains on in response to the seventh enable pulse. During the T18 phase, the bias modules 13 of the pixel circuits 10 in the 2i-1th row and the 2i-th row remain on in response to the corresponding eighth enable pulse, respectively. That is, in the same frame, the duration for which the bias modules 13 of the two rows of pixel circuits 10 driven by the same level shift register in the third shift register group 23 remain on is longer than the duration for which the reset modules 11 of the two rows of pixel circuits 10 remain on.

[0096] In this embodiment, by designing the duration T18 of the eighth enable pulse to be greater than the duration T16 of the first sixth enable pulse and the duration T17 of the first seventh enable pulse, it is ensured that the eighth enable pulse can cover the sixth enable pulse and the seventh enable pulse within one frame time, thereby avoiding the difference in OBS processes between different rows of pixel circuits 10 due to the inability of the eighth enable pulse to cover the first sixth enable pulse and the first seventh enable pulse, thereby avoiding the generation of display horizontal stripes, thereby achieving the purpose of improving the display effect.

[0097] Please continue reading Figures 1 to 4 、 Figure 10a as well as Figure 10b In one embodiment, T16 = T17. That is, the duration T16 of the sixth enable pulse is consistent with the duration T17 of the seventh enable pulse. In other words, in the same frame, the duration for which the reset module 11 of each row of pixel circuits 10 remains in the on state ensures that the pixel circuits 10 in different rows receive the enable pulse of the first scan signal Scan1 via the first scan line 31 for the same duration. This ensures that the pixel circuits 10 in different rows reset the N1 node for the same duration, thereby ensuring display uniformity of the display panel.

[0098] Please continue reading Figures 1 to 4 、 Figure 10a as well as Figure 10b In one embodiment, within one frame time, the enable pulse provided by the second scan line 32 connected to the pixel circuit 10 in the 2i-1th row is the ninth enable pulse, the enable pulse provided by the second scan line 32 connected to the pixel circuit 10 in the 2i-th row is the tenth enable pulse, and the second non-enable phase between two adjacent eighth enable pulses covers the remaining sixth enable pulse, the remaining seventh enable pulse, each ninth enable pulse and each tenth enable pulse.

[0099] The third scan signal SP* is a non-enable pulse in the second non-enable phase, or in other words, a non-OBS phase. That is, the bias module 13 is turned off in response to the non-enable pulse of the third scan signal SP*. The second non-enable phase covers the remaining sixth enable pulse, the remaining seventh enable pulse, each ninth enable pulse, and each tenth enable pulse. It can be understood that the start time of the remaining sixth enable pulse, the remaining seventh enable pulse, each ninth enable pulse, and each tenth enable pulse is no earlier than the start time of the second non-enable phase, and the end time of the remaining sixth enable pulse, the remaining seventh enable pulse, each ninth enable pulse, and each tenth enable pulse is no later than the end time of the second non-enable phase.

[0100] In this embodiment, within one frame time, the second non-enable phase between two adjacent eighth enable pulses covers the remaining sixth enable pulse, the remaining seventh enable pulse, each ninth enable pulse and each tenth enable pulse, thereby ensuring that the reset modules 11 in different rows of pixel circuits 10 perform the reset process in response to the sixth enable pulse or the seventh enable pulse, and that the data write modules 12 in different rows of pixel circuits 10 perform the data write process in response to the ninth enable pulse or the tenth enable pulse, and the bias modules 13 remain in the disconnected state, thereby achieving the independence of the reset process and the data write process from the OBS process, thereby ensuring the normal display of the display panel.

[0101] Please continue reading Figures 1 to 4 、 Figure 10a as well as Figure 10b In one embodiment, the duration of the ninth enable pulse is T19, the duration of the tenth enable pulse is T110, and the duration of the second non-enable phase is T22, wherein T22>(np)*T16, T22>(np)*T17, T22>n*T19, and T22>n*T110, where n represents the number of enable pulses included in the first scan signal Scan1 within a frame time, and p represents the number of pulses that the eighth enable pulse covers the sixth enable pulse and the seventh enable pulse, and p is a positive integer. Among them, (np)*T16 represents the duration of the remaining sixth enable pulse within a frame time, (np)*T17 represents the duration of the remaining seventh enable pulse within a frame time, n*T19 represents the duration of all ninth enable pulses within a frame time, and n*T110 represents the duration of all tenth enable pulses within a frame time.

[0102] During the T19 phase, the data write module 12 of the pixel circuits 10 in the 2i-1th row remains on in response to the ninth enable pulse. During the T110 phase, the data write module 12 of the pixel circuits 10 in the 2i-th row remains on in response to the tenth enable pulse. During the T22 phase, the bias modules 13 of the pixel circuits 10 in the 2i-1th row and the 2i-th row respectively remain off in response to the eighth enable pulse. That is, in the same frame, the duration that the bias modules 13 of the two rows of pixel circuits 10 driven by the same stage of shift registers in the third shift register group 23 remain off is longer than the duration that the data write modules 12 of the two rows of pixel circuits 10 remain on.

[0103] In an application, within one frame time, the eighth enable pulse covers the sixth enable pulse and the seventh enable pulse by 1, that is, p=1. Taking n=3 as an example, within one frame time, the sixth enable pulse, the seventh enable pulse, the ninth enable pulse, and the tenth enable pulse each include 3 enable pulses, then T22>2*T16, T22>2*T17, T22>3*T19, and T22>3*T110.

[0104] In this embodiment, by designing T22>(np)*T16, T22>(np)*T17, T22>n*T19, T22>n*T110, the second non-enabling stage covers the remaining sixth enabling pulse, the remaining seventh enabling pulse, each ninth enabling pulse and each tenth enabling pulse, thereby ensuring that the reset modules 11 in different rows of pixel circuits 10 respond to the sixth enabling pulse or the seventh enabling pulse to perform the reset process, and the data writing modules 12 in different rows of pixel circuits 10 respond to the ninth enabling pulse or the tenth enabling pulse to perform the data writing process, and the bias modules 13 remain in the disconnected state, thereby achieving the mutual independence of the reset process and the data writing process from the OBS process, thereby ensuring the normal display of the display panel.

[0105] Please continue reading Figure 5 、 Figure 10a and Figure 10bIn one embodiment, for the first scan line 31 and the second scan line 32 electrically connected to the same pixel circuit 10, the first scan line 31 provides a first scan signal Scan1, and the second scan line 32 provides a second scan signal Scan2. Within one frame time, the time interval between the start time of the first enable pulse of the first scan signal Scan1 and the start time of the first enable pulse of the second scan signal Scan2 received by the same pixel circuit 10 is ΔT. Wherein, ΔT=2m*H, H represents the unit time length. For example, H can be understood as the ratio between one frame time of the display panel and the number of rows of pixel circuits 10 in the display panel. For example, if the effective level of the enable pulse is a low level, then within one frame time, the time interval between the falling edge of the first enable pulse of the first scan signal Scan1 and the falling edge of the first enable pulse of the second scan signal Scan2 received by the same pixel circuit 10 is ΔT. For another example, if the effective level of the enable pulse is high, then within one frame time, the time interval between the rising edge of the first enable pulse of the first scan signal Scan1 and the rising edge of the first enable pulse of the second scan signal Scan2 received by the same pixel circuit 10 is ΔT. In this way, an appropriate value of m can be set according to timing design requirements, that is, using a VSR staggered m-stage connection, so that the time interval between the start time of the first enable pulse of the first scan signal Scan1 and the start time of the first enable pulse of the second scan signal Scan2 received by the same pixel circuit 10 is 2m*H, thereby achieving the purpose of improving display effect.

[0106] For example, taking the effective level of the enable pulse as a low level, if m=2, the time interval △T between the falling edge of the first enable pulse of the first scan signal Scan1 received by the same pixel circuit 10 and the falling edge of the first enable pulse of the second scan signal Scan2 is 4H; for another example, if m=3, the time interval △T between the falling edge of the first enable pulse of the first scan signal Scan1 received by the same pixel circuit 10 and the falling edge of the first enable pulse of the second scan signal Scan2 is 6H; for another example, if m=4, the time interval △T between the falling edge of the first enable pulse of the first scan signal Scan1 and the falling edge of the first enable pulse of the second scan signal Scan2 is 8H.

[0107] It should be noted that the above is only an exemplary description. In applications, the value of m can be set according to factors such as the timing design requirements of the reset module 11, the data writing module 12 and the bias module 13 and the display requirements of the display panel, and is not limited here.

[0108] Figure 11 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 11In one embodiment, the display area AA includes N rows of pixel circuits 10, and the non-display area further includes multiple first gating modules 40, each of which includes N first gating units. In the same first gating module 40, the control end of the first gating module 40 is electrically connected to the control ends of the N first gating units, the 2j-1th first gating unit is electrically connected to the output end of the m+jAth stage shift register in the first shift register group 21 and the second scan line 32 connected to the jth row of pixel circuits 10, and the 2jth first gating module 40 is electrically connected to the output end of the m+jAth stage shift register in the second shift register group 22 and the second scan line 32 connected to the j+1th row of pixel circuits 10. Where 1≤j≤N / 2, j ranges from 1 to N / 2, and j is a positive integer. 0≤A<m, A is an integer. For example, if m=3, A can be 0, 1, or 2. Different first gating modules 40 correspond to different A, wherein A corresponding to at least one first gating module 40 is equal to 0. m and A determine the number of VSR staggered connections between the reset module 11 and the data writing module 12 in the same pixel circuit 10, and the number of A is the same as the number of VSR staggered connections that can be implemented on the display panel.

[0109] The non-display area also includes multiple first control lines, each of which is electrically connected to the control terminal of a corresponding first gating module 40. The first control line provides a first control signal ctrl, which includes an enable pulse and a disable pulse. During the gating phase of a frame, the first control signal ctrl provided to the control terminal of the first target gating module is an enable pulse, which is any one of the multiple first gating modules 40. The first control signal ctrl provided to the control terminals of the remaining first gating modules 40 is a disable pulse. That is, each first gating module 40 is turned on in a time-sharing manner in response to the enable pulse of the corresponding first control signal ctrl. Furthermore, the N first gating units in the same first gating module 40 are simultaneously turned on in response to the enable pulse of the same first control signal ctrl, thereby providing a scan signal to the corresponding pixel circuit 10 through the shift register connected to the first gating module 40. The N first gating units in the same first gating module 40 are turned off in response to the disable pulse of the same first control signal ctrl. In application, according to the staggered requirements, that is, the shift registers connected to the reset module 11 and the data writing module 12 in the same pixel circuit 10 need to be separated by several levels, the corresponding first selection module 40, that is, the first target selection module, can be turned on, and the remaining first selection modules 40 can be disconnected, so as to realize switching of different staggered connection modes.

[0110] For example, take m=3, and the display panel includes two first gating modules 40, namely the first sub-gating module and the second sub-gating module, and the display panel also includes two first control lines, namely the first sub-control line and the second sub-control line, as an example, wherein A=0, the first sub-gating module includes N first sub-gating units 41, the control end of the first sub-gating module is electrically connected to the control end and the first sub-control line of the N first sub-gating units 41, the first sub-control line provides a first sub-control signal, the 2j-1th first sub-gating unit 41 is electrically connected to the m+jth stage shift register output end in the first shift register group 21 and the second scanning line 32 connected to the jth row pixel circuit 10, the 2jth first sub-gating module is electrically connected to the m+jth stage shift register output end in the second shift register group 22, and the second scanning line 32 connected to the jth row pixel circuit 10. The m+j-th level shift register output end is electrically connected to the second scan line 32 connected to the j+1-th row pixel circuit 10; A=1, the second sub-selection module includes N second sub-selection units 42, the control end of the second sub-selection module is electrically connected to the control end of the N second sub-selection units 42 and the second sub-control line, the second sub-control line provides a second sub-control signal, the 2j-1-th second sub-selection unit 42 is electrically connected to the m+j-1-th level shift register output end in the first shift register group 21 and the second scan line 32 connected to the j-th row pixel circuit 10, and the 2j-th second sub-selection module is electrically connected to the m+j-1-th level shift register output end in the second shift register group 22 and the second scan line 32 connected to the j+1-th row pixel circuit 10.

[0111] The pixel circuit 10 in the jth row is electrically connected not only to the m+jth shift register in the first shift register group 21 via the 2j-1th first sub-selection unit 41, but also to the m+j-1th shift register in the first shift register group 21 via the 2j-1th second sub-selection unit 42. Furthermore, the pixel circuit 10 in the j+1th row is electrically connected not only to the m+jth shift register in the second shift register group 22 via the 2jth first sub-selection unit 41, but also to the m+j-1th shift register in the second shift register group 22 via the 2jth second sub-selection unit 42. In other words, two VSR interval connection modes, 2 and 3 levels, can be implemented, i.e., ΔT = 4H and 6H.

[0112] The first sub-gating module is turned on in time-sharing mode in response to an enable pulse of a first sub-control signal provided by a first sub-control line, and the second sub-gating module is turned on in time-sharing mode in response to an enable pulse of a second sub-control signal provided by a second sub-control line. The N first sub-gating units 41 in the first sub-gating module are turned on simultaneously in response to an enable pulse of the first sub-control signal, and the N first sub-gating units 41 in the first sub-gating module are turned off in response to a non-enable pulse of the first sub-control signal. The N second sub-gating units 42 in the second sub-gating module are turned on simultaneously in response to an enable pulse of the second sub-control signal, and the N second sub-gating units 42 in the second sub-gating module are turned off in response to a non-enable pulse of the second sub-control signal.

[0113] In application, for example, the first sub-selection module is turned on in response to the enable pulse of the first sub-control signal provided by the first sub-control line, and the second sub-selection module is turned off in response to the non-enable pulse of the second sub-control signal provided by the second sub-control line. In this case, the two shift registers connected to the reset module 11 and the data write module 12 of the same pixel circuit 10 are spaced 3 levels apart, that is, △T=6H; for another example, the first sub-selection module is turned off in response to the enable pulse of the first sub-control signal provided by the first sub-control line, and the second sub-selection module is turned on in response to the non-enable pulse of the second sub-control signal provided by the second sub-control line. In this case, the two shift registers connected to the reset module 11 and the data write module 12 of the same pixel circuit 10 are spaced 2 levels apart, that is, △T=4H.

[0114] In this embodiment, a plurality of first gating modules 40 are provided, and in the same first gating module 40, the control end of the first gating module 40 is electrically connected to the control ends of N first gating units, the 2j-1 first gating unit is electrically connected to the output end of the m+jA-th level shift register in the first shift register group 21 and the second scan line 32 connected to the j-th row pixel circuit 10, and the 2j-th first gating module 40 is electrically connected to the output end of the m+jA-th level shift register in the second shift register group 22 and the second scan line 32 connected to the j+1-th row pixel circuit 10. In the gating phase of one frame, the control end of the first target gating module is electrically connected to the output end of the m+jA-th level shift register in the second shift register group 22 and the second scan line 32 connected to the j+1-th row pixel circuit 10. The first control signal ctrl provided is an enable pulse, and the first control signal ctrl provided to the control end of the remaining first selection modules 40 is a non-enable pulse. Since A corresponding to different first selection modules 40 is different, and A corresponding to at least one first selection module 40 is equal to 0, it is possible to realize a variety of VSR staggered connection modes by time-sharing the first selection module 40. Therefore, the time interval between the first enable pulse of the scanning signal received by the reset module 11 and the data writing module 12 of the pixel circuit 10 in the display panel can be adjusted according to the display requirements to meet the signal timing design requirements, which can further improve the display performance of the display panel.

[0115] Figure 12 A timing diagram of the first control signal ctrl, the first scan signal Scan1 and the second scan signal Scan2 of the display panel provided in the embodiment of the present application. Figure 11 and Figure 12 In one embodiment, the first scan line 31 provides a first scan signal Scan1, and the second scan line 32 provides a second scan signal Scan2. The first scan signal Scan1 and the second scan signal Scan2 respectively include an enable pulse and a non-enable pulse. The gating phase covers the provision of the enable pulses of the first scan signal Scan1 and the second scan signal Scan2 to the first pixel circuit. That is, the start time of the enable pulses of the first scan signal Scan1 and the second scan signal Scan2 received by the first pixel circuit is no earlier than the start time of the gating phase, and the end time of the enable pulses of the first scan signal Scan1 and the second scan signal Scan2 received by the first pixel circuit is no later than the end time of the gating phase. The first pixel circuit includes a pixel circuit 10 connected to a first target gating module. In this way, the path between the shift register and the scan line (the first scan line 31 and the second scan line 32) is turned on through the first target gating module to ensure that the pixel circuit 10 is reset and data is written, thereby ensuring the display performance of the display panel.

[0116] Please continue reading Figure 11 In one embodiment, the first selection unit includes a first transistor, the gate of the first transistor is electrically connected to the control terminal of the corresponding control module, the first electrode of the first transistor is electrically connected to the corresponding shift register, and the second electrode of the first transistor is electrically connected to the corresponding first scan line 31 or second scan line 32. Exemplarily, the first transistor includes a MOS tube or a TFT, and can also be other types of transistors, which are not limited in detail here. In this way, by selecting the path between the shift register and the first scan line 31 or the second scan line 32 through the first transistor, multiple VSR staggered connections can be achieved, thereby improving the display performance of the display panel.

[0117] Please continue reading Figure 11In one embodiment, the first scan line 31 provides a first scan signal Scan1, and the second scan line 32 provides a second scan signal Scan2. The first scan signal Scan1 and the second scan signal Scan2 respectively include an enable pulse and a non-enable pulse. In one frame time, the time interval between the start time of the first enable pulse of the first scan signal Scan1 and the start time of the first enable pulse of the second scan signal Scan2 received by the same pixel circuit 10 is △T, then 2*(m-Amax)*H≤△T≤2*(m-Amin)*H. In one frame time, Amax represents the maximum value of A in the multiple first gating modules 40, and Amin represents the minimum value of A in the multiple first gating modules 40. H represents the unit time length. For example, H can be understood as the ratio between one frame time of the display panel and the number of rows of pixel circuits 10 in the display panel.

[0118] For example, taking m=3 as an example, then 0≤A≤2. If the display panel includes three first selection modules 40, corresponding to A=0, 1, and 2 respectively, then 2H≤△T≤6H; when A=0, △T=6H, within one frame time, the time interval between the start time of the first enable pulse of the first scanning signal Scan1 received by the same pixel circuit 10 and the start time of the first enable pulse of the second scanning signal Scan2 is 6H. In this case, the two shift registers connected to the reset module 11 and the data writing module 12 of the same pixel circuit 10 are spaced 3 levels apart, that is, the VSR adopts a 3-level staggered connection mode; when A=1, △T=4H, within one frame time, the first enable pulse of the first scanning signal Scan1 received by the same pixel circuit 10 is 6H. The time interval between the start moment of the first enable pulse of the first scanning signal Scan1 received by the same pixel circuit 10 and the start moment of the first enable pulse of the second scanning signal Scan2 is 4H. In this case, the two shift registers connected to the reset module 11 and the data writing module 12 of the same pixel circuit 10 are spaced 2 levels apart, that is, the VSR adopts a connection method of staggered 2 levels; when A=2, △T=2H, within one frame time, the time interval between the start moment of the first enable pulse of the first scanning signal Scan1 received by the same pixel circuit 10 and the start moment of the first enable pulse of the second scanning signal Scan2 is 2. In this case, the two shift registers connected to the reset module 11 and the data writing module 12 of the same pixel circuit 10 are spaced 1 level apart, that is, the VSR adopts a connection method of staggered 1 level.

[0119] In this embodiment, the values ​​of parameters m and A can be set accordingly according to the timing design requirements between the reset module 11 and the data writing module 12 in the pixel circuit 10, so that a variety of VSR staggered connection modes can be realized. In combination with multiple first selection modules 40, switching of a variety of different VSR connection modes can be realized to meet the various display requirements of the display panel.

[0120] Figure 13 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 13 In one embodiment, the non-display area further includes a fourth shift register group 24, and the fourth shift register group 24 includes a plurality of cascaded shift registers. Figure 13 In the display panel shown, the fourth shift register group 24 includes a plurality of cascaded shift registers 3-scan(q), where q represents the qth stage. The output end of the qth stage shift register in the fourth shift register group 24 is electrically connected to the second scan line 32 connected to the qth row of pixel circuits 10. Where 1≤q≤N, q traverses from 1 to N. It should be noted that the display panel may further include a fourth start signal line, wherein the first stage shift register in the fourth shift register group 24 may be electrically connected to the fourth start signal line, and the fourth start signal line STV4 provides a fourth start signal to start the fourth shift register group 24. In addition, the shift registers 3-scan(q) in the fourth shift register group 24 can be cascaded through cascade signal lines, and each shift register 3-scan(q) can be electrically connected to the corresponding second scan line 32 through a transmission signal line. The way in which the fourth shift register group 24 is cascaded and electrically connected to the second scan line 32 is similar to that of the first shift register group 21 and the second shift register group 22. For details, please refer to the above-mentioned related introduction, which will not be repeated here.

[0121] For example, Figure 13 As shown, the output end of the first-stage shift register 3-scan(1) in the fourth shift register group 24 is electrically connected to the second scan line 32 connected to the first row of pixel circuits 10, the output end of the second-stage shift register 3-scan(2) in the fourth shift register group 24 is electrically connected to the second scan line 32 connected to the second row of pixel circuits 10, the output end of the third-stage shift register 3-scan(3) in the fourth shift register group 24 is electrically connected to the second scan line 32 connected to the third row of pixel circuits 10, and so on, until the last row of pixel circuits 10.

[0122] The display area AA includes N rows of pixel circuits 10, and the non-display area also includes a second gating module 50. The second gating module 50 includes N second gating units 51. The 2k-1th second gating unit 51 is electrically connected to the output end of the k+mth stage shift register in the first shift register group 21 and the second scan line 32 connected to the 2k-1th row of pixel circuits 10; the 2kth second gating unit 51 is electrically connected to the output end of the k+mth stage shift register in the second shift register group 22 and the second scan line 32 connected to the 2kth row of pixel circuits 10. Wherein, 1≤k≤N / 2, k traverses from 1 to N / 2. For example, Figure 13As shown, taking m=2 as an example, the first second gating unit 51 is electrically connected to the output end of the third-stage shift register in the first shift register group 21 and the second scan line 32 connected to the first row of pixel circuits 10, the second second gating unit 51 is electrically connected to the output end of the third-stage shift register in the second shift register group 22 and the second scan line 32 connected to the second row of pixel circuits 10, the third second gating unit 51 is electrically connected to the output end of the fourth-stage shift register in the first shift register group 21 and the second scan line 32 connected to the third row of pixel circuits 10, the fourth second gating unit 51 is electrically connected to the output end of the fourth-stage shift register in the second shift register group 22 and the second scan line 32 connected to the fourth row of pixel circuits 10, and so on, until the last row of pixel circuits 10.

[0123] The N second gating units 51 have the same on-off state, and the time period during which the second gating units 51 are in the on state does not overlap with the time period during which the fourth shift register group 24 outputs the enable pulse of the fourth scanning signal. That is, when the N second gating units 51 in the second gating module 50 are respectively on, the fourth shift register outputs a non-enable pulse of the fourth scanning signal. In this case, the shift registers in the first shift register group 21 and the second shift register group 22 provide the scanning signal to the data writing module 12 of the pixel circuit 10. When the fourth shift register outputs the enable pulse of the fourth scanning signal, the N second gating units 51 in the second gating module 50 are respectively off. In this case, the shift registers in the fourth shift register group 24 provide the scanning signal to the data writing module 12 of the pixel circuit 10.

[0124] In this embodiment, a fourth shift register group 24 is additionally provided, and the output end of the i-th stage shift register in the fourth shift register group 24 is electrically connected to the second scan line 32 connected to the i-th row pixel circuit 10, and a second gating module 50 including N second gating units 51 is provided, and the 2k-1-th second gating unit 51 is respectively electrically connected to the output end of the k+m-th stage shift register in the first shift register group 21 and the second scan line 32 connected to the 2k-1-th row pixel circuit 10; the 2k-th second gating unit 51 is respectively electrically connected to the output end of the k+m-th stage shift register in the second shift register group 22 and the second scan line 32 connected to the 2k-th row pixel circuit 10. Based on this, by controlling the on-off state of the second gating module 50, the selection The paths between the shift registers in the first shift register group 21 and the second shift register group 22 and the second scan line 32 are selectively connected, thereby selecting the first shift register group 21 and the second shift register group 22 to jointly provide scan signals to the data write module 12 of the pixel circuit 10, that is, using a VSR staggered connection method of m levels to set the scan signal timing of the pixel circuit 10, or selecting the fourth shift register group 24 to provide scan signals to the data write module 12 of the pixel circuit 10, so that the timing relationship between the scan signals received by the reset module 11 and the data write module 12 in the pixel circuit 10 is controlled by the fourth shift register group 24, and other types of signal timing different from the staggered m levels can be provided, thereby meeting the various signal timing requirements of the display panel. In applications, the timing relationship between the fourth scan signal output by the fourth shift register group 24 and the first scan signal Scan1 received by the reset module 11 of the pixel circuit 10 can be set according to the signal timing requirements. For example, it can be designed to be ΔT = (m-1)*H, (m+1)*H, etc. to meet design requirements, and no further limitations are given here.

[0125] Please continue reading Figure 13In one embodiment, the control terminal of the second gating module 50 is electrically connected to the control terminals of N second gating units 51, respectively. The non-display area further includes a second control line electrically connected to the control terminal of the second gating module 50. The second gating unit 51 is turned on in response to an enable pulse of a second control signal provided by the second control line. The time interval between the start time of the first enable pulse of the first scan signal Scan1 and the start time of the first enable pulse of the second scan signal Scan2 received by the same pixel circuit 10 is ΔT, and ΔT = 2m*H, where H represents a unit time length. The second gating unit 51 is turned off in response to a non-enable pulse of the second control signal provided by the second control line. In this case, ΔT ≠ 2m*H. In this way, by providing a second control signal to the control terminal of the second gating module 50 via the second control line, the on and off states of the N second gating units 51 in the second gating module 50 can be controlled by the second control signal, thereby achieving multiple VSR staggered connections, meeting the various display requirements of the display panel, and improving display performance.

[0126] Figure 14 A schematic structural diagram of a display panel provided in an embodiment of the present application is shown in FIG. Figure 15 A timing diagram of multiple signals in a display panel provided in an embodiment of the present application. Figure 14 and Figure 15 In one embodiment, the display panel further includes a data terminal DATA, a data line 70 and a demultiplexer 60 .

[0127] The data terminal DATA provides a data signal. Exemplarily, the data terminal DATA is electrically connected to a driver chip (DIC), and the data terminal DATA provides the data signal through the driver chip.

[0128] The data lines 70 extend along the column direction of the pixel circuits 10 and are arranged along the row direction of the pixel circuits 10. The data lines 70 are electrically connected to the pixel circuits 10 located in the same column. Exemplarily, each pixel circuit 10 column is provided with two data lines 70. For the same pixel circuit 10 column, one data line 70 is electrically connected to a portion of the pixel circuits 10 in the pixel circuit 10 column, and the other data line 70 is electrically connected to at least the remaining portion of the pixel circuits 10. That is, one pixel circuit 10 column is charged using two data lines 70 (Dual Data Line, DDL). For example, for the same pixel circuit 10 column, one data line 70 is electrically connected to the pixel circuits 10 in odd-numbered rows in the pixel circuit 10 column, and the other data line 70 is electrically connected to the pixel circuits 10 in even-numbered rows in the pixel circuit 10 column.

[0129] The input end of the demultiplexer 60 is electrically connected to the data terminal DATA, and the input end of the demultiplexer 60 receives the data signal provided by the data terminal DATA. The output end of the demultiplexer 60 is electrically connected to n data lines 70. Wherein, n is a positive integer, and n ≥ 2. For example, n can be 2, 4, or 6, or other positive integers greater than or equal to 2, which are not limited here. The number of output ends of the demultiplexer 60 is n, and each output end of the demultiplexer 60 is electrically connected to a data line 70, and different output ends of the demultiplexer 60 are electrically connected to different data lines 70.

[0130] The demultiplexer 60 includes n switch modules 80. Each switch module 80 is electrically connected to the input and output of the demultiplexer 60. Different switch modules 80 correspond to different outputs of the demultiplexer 60. A switch module 80 is used to select a path between the input and output of the demultiplexer 60 to which it is connected. The n switch modules 80 of the same demultiplexer 60 are turned on in a time-sharing manner. That is, the on-time periods of the n switch modules 80 of the demultiplexer 60 do not overlap within the same frame.

[0131] In this embodiment, by setting a multiplexer 60 in the display panel, multiple data lines 70 can share the same data terminal DATA, which can help reduce the number of data terminals DATA set in the non-display area of ​​the display panel. In addition, by setting multiple switch modules 80, the multiplexer 60 can select the path between the input end and the output end of the multiplexer 60 connected to it through the switch module 80, thereby realizing effective control of the charging process of the data line 70.

[0132] Please continue reading Figure 14 and Figure 15 In one embodiment, the display panel further includes n selection lines 90. In the same demultiplexer 60, the control terminals of the n switch modules 80 are electrically connected to the n selection lines 90 in a one-to-one correspondence, wherein the control terminals of different switch modules 80 are connected to different selection lines 90. The selection line 90 provides a selection signal, which includes an enable pulse and a disable pulse. The switch module 80 is turned on in response to the enable pulse of the selection signal. In this case, the data signal provided by the data terminal DATA is charged into the data line 70 through the switch module 80. The switch module 80 is turned off in response to the disable signal of the selection signal, and the connection between the data terminal DATA and the data line 70 connected to the switch module 80 is disconnected. The time periods of the enable pulses of the selection signals provided by the n selection lines 90 do not overlap, so that the n switch modules 80 of the same demultiplexer 60 conduct the path between the input terminal and the n output terminals in a time-sharing manner, so as to charge the n data lines 70 in a time-sharing manner.

[0133] Exemplarily, when n=4, the multiplexer 60 includes four switch modules 80, namely, a first switch module 81, a second switch module 82, a third switch module 83 and a fourth switch module 84; the display panel includes four selection lines 90, namely, a first selection line 91, a second selection line 92, a third selection line 93 and a fourth selection line 94, then the first switch module 81 is electrically connected to the input end of the multiplexer 60, the first data line 71 and the first selection line 91, respectively, the second switch module 82 is electrically connected to the input end of the multiplexer 60, the second data line 72 and the second selection line 92, respectively, the third switch module 83 is electrically connected to the input end of the multiplexer 60, the third data line 73 and the third selection line 93, respectively, and the fourth switch module 84 is electrically connected to the input end of the multiplexer 60, the fourth data line 74 and the fourth selection line 94, respectively. In this way, the switch modules 80 of different demultiplexers 60 can reuse the same selection line 90, reducing the number of selection lines 90 in the display panel, which helps to further achieve a narrow frame.

[0134] Please continue reading Figure 14 and Figure 15 In one embodiment, the switch module 80 includes a second transistor, a gate of the second transistor is electrically connected to the select line 90, a first electrode of the second transistor is electrically connected to the data terminal DATA, and a second electrode of the second transistor is electrically connected to the data line 70. Exemplarily, the second transistor includes a MOS transistor, a TFT, or other types of transistors, which are not further defined herein.

[0135] In application, the second transistor responds to the selection signal to select the path between the data terminal DATA and the output end of the multiplexer 60 connected to the second transistor, thereby selecting the path between the data terminal DATA and the data line 70 connected to the output end, thereby realizing effective control of the charging process of the data line 70.

[0136] Please continue reading Figure 14 and Figure 15 In one embodiment, n=4. In this case, a demultiplexer 60 includes four output terminals. The four output terminals of the demultiplexer 60 are electrically connected to a first data line 71, a second data line 72, a third data line 73, and a fourth data line 74, respectively. The first data line 71 and the second data line 72 are located on either side of a first pixel circuit column, respectively. The third data line 73 and the fourth data line 74 are located on either side of a second pixel circuit column, respectively. The first pixel circuit column and the second pixel circuit column are adjacent to each other. The first pixel circuit column and the second pixel circuit column are arranged alternately along the row direction of the pixel circuit 10. The first data line 71, the second data line 72, the third data line 73, and the fourth data line 74 are periodically arranged along the row direction of the pixel circuit 10.

[0137] For the same first pixel circuit column, each pixel circuit 10 located in the odd rows is electrically connected to the same first data line 71, and each pixel circuit 10 located in the even rows is electrically connected to the same second data line 72; for the same second pixel circuit 10 column, each pixel circuit 10 located in the odd rows is electrically connected to the same third data line 73, and each pixel circuit 10 located in the even rows is electrically connected to the same fourth data line 74; that is, DDL 1:4.

[0138] It can be understood that when n=4, the multiplexer 60 includes four switch modules 80, namely the first switch module 81, the second switch module 82, the third switch module 83 and the fourth switch module 84. The first switch module 81 is electrically connected to the input end of the multiplexer 60 and the first data line 71, respectively, the second switch module 82 is electrically connected to the input end of the multiplexer 60 and the second data line 72, respectively, the third switch module 83 is electrically connected to the input end of the multiplexer 60 and the third data line 73, respectively, and the fourth switch module 84 is electrically connected to the input end of the multiplexer 60 and the fourth data line 74, respectively.

[0139] Exemplarily, when scanning signals (S1, S2, S3 and S4) are provided to each pixel circuit 10 row by row, the selection line 90 electrically connected to the first switch module 81 in each multiplexer 60 is turned on under the control of the selection signal MUX1 transmitted, so that the data signal provided by the data terminal DATA is sequentially transmitted through the turned-on first switch module 81 and the first data line 71 to the pixel circuit 10 of the corresponding row and column; the selection line 90 electrically connected to the second switch module 82 in each multiplexer 60 is turned on under the control of the selection signal MUX2 transmitted, so that the data signal provided by the data terminal DATA is sequentially transmitted through the turned-on second switch module 82 and the second data line 72 to the pixel circuit 10 of the corresponding row and column; The block 83 is electrically connected to a selection line 90 and is turned on under the control of a selection signal MUX3 transmitted therefrom, so that the data signal provided by the data terminal DATA is sequentially transmitted through the third switch module 83 that is turned on and the third data line 73 to the pixel circuit 10 of the corresponding row and column; the block 83 is electrically connected to a fourth switch module 84 in each multiplexer 60 and is turned on under the control of a selection signal MUX4 transmitted therefrom, so that the data signal provided by the data terminal DATA is sequentially transmitted through the fourth switch module 84 that is turned on and the fourth data line 74 to the pixel circuit 10 of the corresponding row and column; in this way, the data signal can be written into the pixel circuits 10 of each row and column one by one, so that each pixel circuit 10 can drive the corresponding light-emitting element D for display according to the data signal it receives.

[0140] Please continue reading Figures 1 to 4 、 Figure 14 and Figure 15In one embodiment, in a first pixel circuit column, the light-emitting elements D electrically connected to the pixel circuits 10 in odd-numbered rows emit the same color, and the light-emitting elements D electrically connected to the pixel circuits 10 in even-numbered rows emit the same color. In a second pixel circuit column, the light-emitting elements D electrically connected to the pixel circuits 10 in odd-numbered rows emit the same color, and the light-emitting elements D electrically connected to the pixel circuits 10 in even-numbered rows emit the same color. Exemplarily, the light-emitting colors of the light-emitting elements D include red, blue, and green.

[0141] Since the voltages of the data signals required for light-emitting elements D of different colors to achieve the same display brightness are different, by making the pixel circuits 10 electrically connected to the light-emitting elements D of the same light-emitting color share the data line 70, and the pixel circuits 10 electrically connected to the light-emitting elements D of different light-emitting colors are electrically connected to different data lines 70, it is possible to prevent large voltage jumps from occurring when the pixel circuits 10 sharing the common data line 70 write to the data signal line, thereby affecting the charging capacity and charging time, thereby ensuring that each data signal is accurately written to each pixel circuit 10, so that each pixel circuit 10 drives each light-emitting element D to accurately display the corresponding color and brightness, thereby improving the display effect of the display panel.

[0142] Please continue reading Figure 14 and Figure 15 In one embodiment, the light-emitting element D and the corresponding pixel circuit 10 form a sub-pixel. Multiple sub-pixels with different luminous colors form a pixel unit. For example, the number of sub-pixels included in the pixel unit is 3.

[0143] Each pixel unit includes a first sub-pixel P1 emitting a first color, a second sub-pixel P2 emitting a second color, and a third sub-pixel P3 emitting a third color. For example, the first color is red, the second color is blue, and the third color is green.

[0144] In three adjacent multiplexers 60, the first data line 71 in each multiplexer 60 is electrically connected to the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 belonging to different pixel units; the second data line 72 in each multiplexer 60 is electrically connected to the third sub-pixel P3, the first sub-pixel P1 and the second sub-pixel P2 belonging to different pixel units; the third data line 73 in each multiplexer 60 is electrically connected to the second sub-pixel P2, the first sub-pixel P1 and the third sub-pixel P3 belonging to different pixel units; the fourth data line 74 in each multiplexer 60 is electrically connected to the third sub-pixel P3, the second sub-pixel P2 and the first sub-pixel P1 belonging to different pixel units.

[0145] In this way, in three adjacent multiplexers 60, when the switch modules 80 respectively connected to the same type of data line 70 (the first data line 71, the second data line 72, the third data line 73 or the fourth data line 74) are turned on at the same time, data signals can be written to sub-pixels of different colors respectively to prevent display abnormalities due to the fact that the written data signal is only the data signal corresponding to the sub-pixel of one color, thereby further improving the display effect of the display panel.

[0146] Based on the same application concept, an embodiment of the present application also provides a display device. Figure 16 This is a schematic diagram of the structure of the display device 200 provided in an embodiment of the present application, as shown in FIG. Figure 16 As shown, the display device 200 includes the display panel 100 in any of the above embodiments. Figure 16 As shown, the display device 200 includes a display panel 100. Therefore, the display device 200 also has the beneficial effects of the display panel 100 in the above embodiment. The similarities can be understood by referring to the above explanation of the display panel 100, which will not be repeated below.

[0147] The display device 200 provided in the embodiment of the present application can be Figure 16 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of this application do not specifically limit this.

[0148] In the description of this specification, the descriptions with reference to the terms "some embodiments", "other embodiments", etc. mean that the specific features, structures, materials or features described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. The various technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the various technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. The above-mentioned embodiments only express several implementation methods of the present application, and their descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that for ordinary technicians in this field, without departing from the concept of the present application, several variations and improvements can be made, which all fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be based on the attached claims.

Claims

1. A display panel, characterized in that: include: a display area, the display area including a plurality of pixel circuits arranged in an array, the pixel circuits being configured to drive light-emitting elements to emit light, the pixel circuits including a reset module and a data write module; the display area including a plurality of first scan lines and a plurality of second scan lines, the first scan lines being electrically connected to control terminals of the reset modules of at least some of the pixel circuits located in the same row, and the second scan lines being electrically connected to control terminals of the data write modules of at least some of the pixel circuits located in the same row; A non-display area, wherein the non-display area includes at least two shift register groups, each of the shift register groups includes multiple cascaded shift registers, wherein the output end of the i-th shift register in the first shift register group is electrically connected to the first scan line connected to the 2i-1-th row of pixel circuits, and the output end of the i+m-th shift register in the first shift register group is electrically connected to the second scan line connected to the 2i-1-th row of pixel circuits; the output end of the i-th shift register in the second shift register group is electrically connected to the first scan line connected to the 2i-th row of pixel circuits, and the output end of the i+m-th shift register in the second shift register group is electrically connected to the second scan line connected to the 2i-th row of pixel circuits, wherein i is greater than or equal to 1, and m is greater than or equal to 2.

2. The display panel according to claim 1, wherein: The pixel circuit further includes a bias module, and the display area further includes a plurality of third scan lines, wherein the third scan lines are electrically connected to control terminals of the bias modules of at least some of the pixel circuits located in the same row; The non-display area also includes a third shift register group, which includes multiple cascaded shift registers. The output end of the i-th stage shift register in the third shift register group is electrically connected to the third scan line connected to the 2i-1 row and the 2i row pixel circuit respectively.

3. The display panel according to claim 2, wherein: The first scan line provides a first scan signal, wherein within one frame time, the first scan signal includes an enable pulse.

4. The display panel according to claim 3, wherein: Within one frame time, the enable pulse provided by the first scan line connected to the 2i-1th row pixel circuit is the first enable pulse, the enable pulse provided by the first scan line connected to the 2ith row pixel circuit is the second enable pulse, and the enable pulse provided by the third scan line connected to the 2i-1th row and 2ith row pixel circuits is the third enable pulse, wherein the third enable pulse covers the first enable pulse and the second enable pulse.

5. The display panel according to claim 4, wherein: The duration of the first enable pulse is T11, the duration of the second enable pulse is T12, and the duration of the third enable pulse is T13, wherein T13>T11 and T13>T12.

6. The display panel according to claim 5, wherein: T11=T12.

7. The display panel according to claim 4, wherein: The second scan line provides a second scan signal, wherein within one frame time, the second scan signal includes an enable pulse.

8. The display panel according to claim 7, wherein: Within one frame time, the enable pulse provided by the second scan line connected to the 2i-1th row pixel circuit is the fourth enable pulse, and the enable pulse provided by the second scan line connected to the 2ith row pixel circuit is the fifth enable pulse, wherein the first non-enable phase between two adjacent third enable pulses covers the fourth enable pulse and the fifth enable pulse.

9. The display panel according to claim 8, wherein: The duration of the fourth enable pulse is T14, the duration of the fifth enable pulse is T15, and the duration of the first non-enable phase is T21, wherein T21>T14, T21>T15.

10. The display panel according to claim 9, wherein: T14=T15.

11. The display panel according to claim 2, wherein: The first scan line provides a first scan signal, wherein within one frame time, the first scan signal includes at least two enable pulses.

12. The display panel according to claim 11, wherein: Within one frame time, the enable pulse provided by the first scan line connected to the 2i-1th row pixel circuit is the sixth enable pulse, the enable pulse provided by the first scan line connected to the 2ith row pixel circuit is the seventh enable pulse, and the enable pulse provided by the third scan line connected to the 2i-1th row and 2ith row pixel circuits is the eighth enable pulse, wherein one of the eighth enable pulses at least covers the first of the sixth enable pulse and the first of the seventh enable pulse.

13. The display panel according to claim 12, wherein: The duration of the sixth enable pulse is T16, the duration of the seventh enable pulse is T17, and the duration of the eighth enable pulse is T18, wherein T18>T16 and T18>T17.

14. The display panel according to claim 13, wherein: T16=T17.

15. The display panel according to claim 12, wherein: The second scan line provides a second scan signal, wherein within one frame time, the second scan signal includes at least two enable pulses, and the first scan signal and the second scan signal include the same number of enable pulses.

16. The display panel according to claim 15, wherein: Within one frame time, the enable pulse provided by the second scan line connected to the 2i-1th row of pixel circuits is the ninth enable pulse, and the enable pulse provided by the second scan line connected to the 2ith row of pixel circuits is the tenth enable pulse, wherein the second non-enable phase between two adjacent eighth enable pulses covers the remaining sixth enable pulses, the remaining seventh enable pulses, each of the ninth enable pulses and each of the tenth enable pulses.

17. The display panel according to claim 16, wherein: The duration of the ninth enable pulse is T19, the duration of the tenth enable pulse is T110, and the duration of the second non-enable phase is T22, wherein T22>(np)*T16, T22>(np)*T17, T22>n*T19, T22>n*T110, n represents the number of enable pulses included in the first scanning signal within one frame time, p represents the number of pulses of the sixth enable pulse and the seventh enable pulse covered by the eighth enable pulse, and p is a positive integer.

18. The display panel according to any one of claims 2 to 17, wherein: For the first scan line and the second scan line electrically connected to the same pixel circuit, the first scan line provides a first scan signal and the second scan line provides a second scan signal. Within one frame time, the time interval between the start moment of the first enable pulse of the first scan signal received by the same pixel circuit and the start moment of the first enable pulse of the second scan signal is △T, where △T=2m*H, where H represents the unit time length.

19. The display panel according to claim 1, wherein The display area includes N rows of pixel circuits, and the non-display area further includes a plurality of first gating modules, each of the first gating modules including N first gating units; in the same first gating module, a control end of the first gating module is electrically connected to the control ends of the N first gating units, the 2j-1th first gating unit is electrically connected to the output end of the m+jAth stage shift register in the first shift register group and the second scan line connected to the jth row of pixel circuits, and the 2jth first gating unit is electrically connected to the output end of the m+jAth stage shift register in the second shift register group and the second scan line connected to the j+1th row of pixel circuits; wherein 1≤j≤N / 2, 0≤A<m, and A corresponding to different first gating modules is different; The non-display area also includes multiple first control lines, one of the first control lines is electrically connected to the control end of one of the first gating modules, and the first control line provides a first control signal, which includes an enable pulse and a non-enable pulse; in the gating stage of a frame, the first control signal provided to the control end of the first target gating module is an enable pulse, the first target gating module is any one of the multiple first gating modules, and the first control signal provided to the control end of the remaining first gating modules is a non-enable pulse.

20. The display panel according to claim 19, wherein The first scan line provides a first scan signal, the second scan line provides a second scan signal, the first scan signal and the second scan signal respectively include an enable pulse and a non-enable pulse; The gating phase covers providing enable pulses of the first scanning signal and the second scanning signal to the first pixel circuit; wherein the first pixel circuit includes a pixel circuit connected to the first target gating module.

21. The display panel according to claim 19, wherein The first selection unit includes a first transistor, the gate of the first transistor is electrically connected to the control end of the corresponding control module, the first electrode of the first transistor is electrically connected to the corresponding shift register, and the second electrode of the first transistor is electrically connected to the corresponding first scan line or second scan line.

22. The display panel according to claim 19, wherein The first scan line provides a first scan signal, the second scan line provides a second scan signal, the first scan signal and the second scan signal respectively include an enable pulse and a non-enable pulse; wherein, The first time when the first scanning signal provided to the pixel circuit of the i-th row jumps from the non-enable pulse to the enable pulse is t1, and the first time when the second scanning signal provided to the pixel circuit of the i-th row jumps from the non-enable pulse to the enable pulse is t2, and 2*(mA max )*H≤t2-t1≤2*(mA min )*H; where A max represents the maximum value of A in the plurality of first gating modules, A min represents the minimum value of A in the plurality of first gating modules, and H represents the unit time length.

23. The display panel according to claim 1, wherein The non-display area further includes a fourth shift register group, the fourth shift register group including a plurality of cascaded shift registers; the output end of the qth stage shift register in the fourth shift register group is electrically connected to the second scan line connected to the qth row of pixel circuits; The display area includes N rows of pixel circuits, and the non-display area further includes a second gating module, the second gating module includes N second gating units, the 2k-1th second gating unit is electrically connected to the output end of the k+mth stage shift register in the first shift register group and the second scan line connected to the 2k-1th row of pixel circuits; the 2kth second gating unit is electrically connected to the output end of the k+mth stage shift register in the second shift register group and the second scan line connected to the 2kth row of pixel circuits; wherein 1≤k≤N / 2; The on-off states of the N second gating units are the same, and a time period in which the second gating units are in the on state does not overlap with a time period in which the fourth shift register group outputs the fourth scanning signal as an enable pulse.

24. The display panel according to claim 23, wherein: The control end of the second gating module is electrically connected to the control ends of the N second gating units respectively, and the non-display area further includes a second control line, and the second control line is electrically connected to the control end of the second gating module; The first scan line provides a first scan signal, the second scan line provides a second scan signal, the second gating unit is turned on in response to an enable pulse of a second control signal provided by the second control line, and a time interval between a start time of a first enable pulse of the first scan signal and a start time of a first enable pulse of the second scan signal received by the same pixel circuit is ΔT, and ΔT=2m*H, where H represents a unit time length; The second gating unit is turned off in response to a non-enable pulse of a second control signal provided by the second control line.

25. The display panel according to claim 1, wherein The display panel further includes data terminals, data lines and a demultiplexer; The data terminal provides a data signal; the data line extends along the column direction of the pixel circuit, the data line is arranged along the row direction of the pixel circuit, and the data line is electrically connected to the pixel circuit located in the same column; The input end of the multiplexer is electrically connected to the data terminal, and the output end of the multiplexer is electrically connected to n data lines, where n is a positive integer and n≥2; the multiplexer includes n switch modules, which are respectively electrically connected to the input end and output end of the multiplexer, different switch modules correspond to different output ends of the multiplexer, and the n switch modules of the same multiplexer are turned on in time-sharing manner.

26. The display panel according to claim 25, wherein: n=4, the four output terminals of the demultiplexer are electrically connected to a first data line, a second data line, a third data line, and a fourth data line, respectively, the first data line and the second data line are located on either side of a first pixel circuit column, the third data line and the fourth data line are located on either side of a second pixel circuit column, and the first pixel circuit column and the second pixel circuit column are adjacent to each other; For the same first pixel circuit column, each of the pixel circuits located in odd rows is electrically connected to the same first data line, and each of the pixel circuits located in even rows is electrically connected to the same second data line; for the same second pixel circuit column, each of the pixel circuits located in odd rows is electrically connected to the same third data line, and each of the pixel circuits located in even rows is electrically connected to the same fourth data line.

27. The display panel according to claim 26, wherein: In the first pixel circuit column, the light emitting elements electrically connected to the pixel circuits in odd rows emit the same light emitting color, and the light emitting elements electrically connected to the pixel circuits in even rows emit the same light emitting color; In the second pixel circuit column, the light emitting elements electrically connected to the pixel circuits in odd rows emit the same light color, and the light emitting elements electrically connected to the pixel circuits in even rows emit the same light color.

28. The display panel according to claim 27, wherein: The light-emitting element and the corresponding electrically connected pixel circuit constitute a sub-pixel; a plurality of sub-pixels with different luminous colors constitute a pixel unit; Each of the pixel units includes a first sub-pixel emitting a first color, a second sub-pixel emitting a second color, and a third sub-pixel emitting a third color; In the three adjacent multiplexers, the first data line in each multiplexer is electrically connected to the first sub-pixel, the second sub-pixel and the third sub-pixel belonging to different pixel units; the second data line in each multiplexer is electrically connected to the third sub-pixel, the first sub-pixel and the second sub-pixel belonging to different pixel units; the third data line in each multiplexer is electrically connected to the second sub-pixel, the first sub-pixel and the third sub-pixel belonging to different pixel units; the fourth data line in each multiplexer is electrically connected to the third sub-pixel, the second sub-pixel and the first sub-pixel belonging to different pixel units.

29. The display panel according to claim 25, wherein: The display panel also includes n selection lines, and the control ends of the n switch modules of the same multiplexer are electrically connected to the n selection lines one by one. The selection lines provide selection signals, and the selection signals include enable pulses and disable pulses. The time periods of the enable pulses of the selection signals provided by the n selection lines do not overlap.

30. The display panel according to claim 29, wherein: The switch module includes a second transistor, a gate of the second transistor is electrically connected to the selection line, a first electrode of the second transistor is electrically connected to the data terminal, and a second electrode of the second transistor is electrically connected to the data line.

31. A display device, characterized in that: Comprising the display panel according to any one of claims 1-30.

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