Semiconductor device and method for manufacturing the same, and method for designing a semiconductor device

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof, and a design method of a semiconductor device, comprising: an IGBT cell and a current sensor cell, the IGBT cell and the current sensor cell are integrated on the same drift region, the IGBT cell and the current sensor cell share a gate; a barrier layer, the barrier layer is located in the drift region, the barrier layer divides the semiconductor device into a first cell region, a second cell region and a transition region, the transition region is located between the first cell region and the second cell region, the barrier layer is located in the drift region of the transition region, the first cell region is the IGBT cell region, and the second cell region is the current sensor cell region. The second cell region shares a gate with the first cell region, and the transition region has a barrier layer that can increase the base concentration of the parasitic bipolar transistor between the second cell region and the first cell region, so that the interference to the current sensor can be reduced, thereby improving the accuracy of the current output by the current sensor. The technical solution of the present invention improves the success rate of the initial design of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a design method of a semiconductor device. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) is a voltage-driven power semiconductor device that integrates a bipolar junction transistor (BJT) and an insulated gate field effect transistor (MOSFET). It is widely used in the field of power electronics. With the development of semiconductor manufacturing technology, the integration of semiconductor devices is getting higher and higher, and the operating current is also increasing. For the safety of the circuit system, it is necessary to set an overcurrent protection function in the peripheral circuit to prevent the semiconductor device from failing due to excessive current. IGBT devices usually need to monitor the current of semiconductor devices through current sensors.

[0003] When designing current sensors, engineers need to consider the errors introduced by factors such as the negative feedback effect of the detection resistor and appropriately increase the number of cells to compensate. However, the current design of semiconductor devices requires one or more layout modifications to adjust the number of cells, and modifying the layout requires re-tapeout, which seriously affects the R&D cost and progress of semiconductor devices. Therefore, how to improve the success rate of the initial design of semiconductor devices is an urgent problem to be solved. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, and a design method of a semiconductor device, in which an IGBT cell and a current sensor cell are integrated on the same drift region, and the success rate of the initial design of the semiconductor device is improved.

[0005] To achieve the above object, the present invention provides a semiconductor device, comprising:

[0006] An IGBT cell and a current sensor cell, wherein the IGBT cell and the current sensor cell are integrated on the same drift region, and the IGBT cell and the current sensor cell share a gate;

[0007] A barrier layer of a first doping type, the barrier layer is located in a drift region of the first doping type, the barrier layer divides the semiconductor device into a first cell region, a second cell region and a transition region, the second cell region is located in the middle of the semiconductor device, the first cell region is located around the semiconductor device, the transition region is located between the first cell region and the second cell region, the barrier layer is located in the drift region of the transition region, the first cell region is an IGBT cell region, and the second cell region is a current sensor cell region;

[0008] Preferably, a plurality of well regions of the second doping type, the well regions extending from the front side of the drift region into the drift region and being located above the barrier layer;

[0009] A plurality of first implantation regions of a second doping type, the first implantation regions being respectively located in respective well regions;

[0010] A second injection region of the first doping type, wherein the second injection regions at both ends of the first injection region in the well region of the first cell region serve as IGBT emitter regions, and the second injection regions at both ends of the first injection region in the well region of the second cell region serve as current sensor current detection regions;

[0011] A gate, the gate is connected across two adjacent well regions, and the gate is insulated from the IGBT emitter region, the current sensor current detection region and the first injection region by a gate dielectric layer;

[0012] An insulating dielectric layer, the insulating dielectric layer covers the gate and the well region and exposes the first injection region of the first cell region and part of the IGBT emitter region through a first through hole, and the insulating dielectric layer exposes the first injection region of the second cell region and part of the current sensor current detection region through a second through hole;

[0013] IGBT emitter, the IGBT emitter region is led out of the first metal layer through the first through hole to form the IGBT emitter;

[0014] A current sensor current detection electrode, wherein the current sensor current detection region leads out of the second metal layer through a second through hole to form a current sensor current detection electrode;

[0015] An IGBT collector region of a second doping type, the IGBT collector region being located at the back of the drift region;

[0016] IGBT collector, the IGBT collector region leads out the third metal layer as the IGBT collector.

[0017] Optionally, the doping concentration of the barrier layer is 1E15 cm -3 ~1E18cm -3 .

[0018] Optionally, the barrier layer has a thickness of 1 μm to 10 μm.

[0019] Optionally, the semiconductor device further comprises:

[0020] The field stop region of the first doping type is located between the collector region and the drift region of the IGBT.

[0021] Optionally, the first doping type is N-type, and the second doping type is P-type; or the first doping type is P-type, and the second doping type is N-type.

[0022] Optionally, a gate is connected above two adjacent well regions, and the gate is insulated from the IGBT emitter region, the IGBT emitter, the current sensor current detection region, the current sensor current detection electrode and the first injection region by a gate dielectric layer, and the gate and the IGBT emitter are located on the front side of the semiconductor device.

[0023] Optionally, the gate dielectric layer is located in the groove, the groove is located between two adjacent well regions, the groove extends from the front side of the drift region to the drift region, the depth of the groove is greater than the depth of the well region, the insulating dielectric layer covers the gate, the gate dielectric layer and the well region, and the insulating dielectric layer exposes the first injection region and part of the IGBT emitter region of the first cell region through the first through hole, the insulating dielectric layer exposes the first injection region and part of the current sensor current detection region of the second cell region through the second through hole, the gate is insulated from the IGBT emitter region, the IGBT emitter, the current sensor current detection region, the current sensor current detection electrode and the first injection region through the gate dielectric layer, and the gate and the IGBT emitter are located on the front side of the semiconductor device.

[0024] Optionally, the well regions are spaced at equal distances from each other.

[0025] The present invention also provides a design method for a semiconductor device, wherein a current sensor is externally connected to a detection resistor, the detection resistor is connected between a current detection electrode of the current sensor and ground, an IGBT emitter is grounded, a first voltage source is connected between a gate and ground, and a second voltage source is connected between an IGBT collector and ground; the design method for a semiconductor device comprises:

[0026] Establishing a first numerical model of the output current of the first cell region, wherein the variables of the first numerical model are the gate-emitter voltage Vge and the collector-emitter voltage Vce;

[0027] Establishing a second numerical model of the output current of the second cell region, the variables of the second numerical model are the gate-emitter voltage Vge, the collector-emitter voltage Vce and the voltage drop Vs of the detection resistor;

[0028] Step S3, according to the first numerical model, the second numerical model, and the current flowing through the detection resistor that simultaneously satisfies the current characteristics of the second cell area and the characteristics of Ohm's law, calculate and obtain the output current of the first cell area, the output current of the second cell area, and the voltage drop Vs of the detection resistor under the set test conditions and the design value of the ratio of the number of cells of the first cell area to the number of cells of the second cell area, and then calculate and obtain the ratio of the output current of the first cell area to the output current of the second cell area;

[0029] Step S4, comparing the calculated voltage drop Vs of the detection resistor and the ratio of the output current of the first cell area to the output current of the second cell area with the corresponding design indicators to determine whether they meet the preset convergence conditions; if so, the ratio N of the number of cells in the first cell area to the second cell area meets the design indicators, so that the semiconductor device structure design stage can be entered; if not, the design value of the ratio N of the number of cells in the first cell area to the second cell area is replaced, and steps S3 and S4 are repeatedly executed in a loop until it is determined that the preset convergence conditions are met.

[0030] Optionally, the output currents of the first cell region and the second cell region are respectively the output currents of the first cell region and the second cell region operating in a saturation region.

[0031] Optionally, the first numerical model is Ice=f (Vge, Vce), Vge is a set value, so that Ice=a Vce+b; where Ice is the output current of the first cell region, Vge is the gate-emitter voltage, Vce is the collector-emitter voltage, a is the slope, and b is the intercept.

[0032] Optionally, a=c1 Vge+d1,b=c2 Vge+d2,c1=K (1+β), d1=-K (1+β) Vth, c2 = -K (1+β) Vpn,d2=K (1+β) VPN Vth; wherein, K is the size and physical related parameters of the semiconductor device, β is the coefficient of the gain factor of the bipolar transistor composed of the IGBT collector region, drift region and well region, Vth is the threshold voltage of the semiconductor device, and Vpn is the voltage drop of the diode composed of the IGBT collector region and drift region.

[0033] Optionally, the second numerical model is:

[0034] Is = f (Vge-Vs, Vce-Vs) / N = {[c1 (Vge-Vs)+d1] (Vce-Vs)+c2 (Vge-Vs)+d2} / N;

[0035] Wherein, Is is the output current of the second cell region, Vs is the voltage drop of the detection resistor, and N is the ratio of the number of cells in the first cell region to the number of cells in the second cell region.

[0036] Optionally, step S3 includes:

[0037] According to the characteristics that the current flowing through the detection resistor satisfies the current characteristics of the second cell region and Ohm's law at the same time, the formula f(Vge-Vs, Vce-Vs) / N=Vs / Rs is obtained, where Rs is the resistance value of the detection resistor;

[0038] Under the set test conditions and the design value of the ratio of the number of cells in the first cell area to the number of cells in the second cell area, Vce, Vge, Rs and N are set values, and the voltage drop of the detection resistor is calculated according to the formula f(Vge-Vs, Vce-Vs) / N=Vs / Rs, and the voltage drop of the detection resistor is calculated according to the formula Ice=a Vce+b is calculated to obtain the output current of the first cell area;

[0039] The output current of the second cell region is calculated according to Is=Vs / Rs, and then the ratio of the output current of the first cell region to the output current of the second cell region is calculated.

[0040] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0041] An IGBT cell and a current sensor cell are manufactured. The IGBT cell and the current sensor cell are integrated on the same drift region. The IGBT cell and the current sensor cell share a gate.

[0042] Forming a barrier layer of a first doping type, the barrier layer is located in the drift region of the first doping type, the barrier layer divides the semiconductor device into a first cell region, a second cell region and a transition region, the second cell region is located in the middle of the semiconductor device, the first cell region is located around the semiconductor device, the transition region is located between the first cell region and the second cell region, the barrier layer is located in the drift region of the transition region, the first cell region is an IGBT cell region, and the second cell region is a current sensor cell region;

[0043] Optionally,

[0044] forming a plurality of well regions of a second doping type, wherein the well regions extend from the front side of the drift region into the drift region and are located on the barrier layer;

[0045] forming a plurality of first implantation regions of a second doping type, wherein the first implantation regions are respectively located in the respective well regions;

[0046] forming a second injection region of the first doping type, wherein the second injection regions at both ends of the first injection region in the well region of the first cell region serve as the IGBT emitter region, and the second injection regions at both ends of the first injection region in the well region of the second cell region serve as current sensor current detection regions;

[0047] Forming a gate, the gate being connected across two adjacent well regions, and the gate being insulated from the IGBT emitter region, the current sensor current detection region, and the first injection region by a gate dielectric layer;

[0048] forming an insulating dielectric layer, wherein the insulating dielectric layer covers the gate and the well region and the insulating dielectric layer exposes the first injection region of the first cell region and a portion of the IGBT emitter region through a first through hole, and the insulating dielectric layer exposes the first injection region of the second cell region and a portion of the current sensor current detection region through a second through hole;

[0049] An IGBT emitter is formed, wherein the IGBT emitter region is led out of the first metal layer through the first through hole to form the IGBT emitter;

[0050] forming a current sensor current detection electrode, wherein the current sensor current detection region leads out a second metal layer through the second through hole to form the current sensor current detection electrode;

[0051] forming an IGBT collector region of a second doping type, wherein the IGBT collector region is located at the back side of the drift region;

[0052] An IGBT collector is formed, and the IGBT collector region leads out the third metal layer as the IGBT collector.

[0053] Optionally, the doping concentration of the barrier layer is 1E15cm -3 ~1E18cm -3 .

[0054] Optionally, the barrier layer has a thickness of 1 μm to 10 μm.

[0055] Optionally, a field stop region of a first doping type is formed and located between the IGBT collector region and the drift region.

[0056] Optionally, the first doping type is N-type, and the second doping type is P-type; or the first doping type is P-type, and the second doping type is N-type.

[0057] Optionally, the gate is connected above the two adjacent well regions, and the gate is insulated from the IGBT emitter region, the IGBT emitter, the current sensor current detection region and the first injection region by a gate dielectric layer. The gate and the IGBT emitter are located on the front side of the semiconductor device, and the IGBT collector is located on the back side of the semiconductor device.

[0058] Optionally, the gate dielectric layer is located in a groove, the groove is located between the two adjacent well regions, the groove extends from the front side of the drift region to the drift region, the depth of the groove is greater than the depth of the well region, the insulating dielectric layer covers the gate, the gate dielectric layer and the well region, and the insulating dielectric layer exposes the first injection region of the first cell region and part of the IGBT emitter region through a first through hole, the insulating dielectric layer exposes the first injection region of the second cell region and part of the current sensor current detection region through a second through hole, the gate is insulated from the IGBT emitter region, the IGBT emitter, the current sensor current detection region, the current sensor current detection electrode and the first injection region through the gate dielectric layer, and the gate and the IGBT emitter are located on the front side of the semiconductor device.

[0059] Optionally, the spacing distances between the well regions are equal.

[0060] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0061] 1. The semiconductor device and the manufacturing method thereof of the present invention include: an IGBT cell and a current sensor cell, the IGBT cell and the current sensor cell are integrated on the same drift region, the IGBT cell and the current sensor cell share a gate, the integration of the IGBT cell and the current sensor cell is realized, and the area is saved. The semiconductor device includes a barrier layer of a first doping type, the barrier layer is located in the drift region of the first doping type, the barrier layer divides the semiconductor device into a first cell region, a second cell region and a transition region, the second cell region is located in the middle of the semiconductor device, the first cell region is located around the semiconductor device, the transition region is located between the first cell region and the second cell region, the barrier layer is located in the drift region of the transition region, The first cell region is an IGBT cell region, and the second cell region is a current sensor cell region; a plurality of well regions of the second doping type, the well region extending from the front side of the drift region to the drift region and being located on the barrier layer; a plurality of first injection regions of the second doping type, the first injection regions being located in respective well regions; a second injection region of the first doping type, wherein the second injection regions at both ends of the first injection region in the well region of the first cell region serve as IGBT emitter regions, and the second injection regions at both ends of the first injection region in the well region of the second cell region serve as current sensor current detection regions; a gate, the gate being connected across two adjacent well regions, and the gate being insulated from the IGBT emitter region, the current sensor current detection region and the first injection region by a gate dielectric layer; Insulating dielectric layer, the insulating dielectric layer covers the gate and the well region and exposes the first injection region and part of the IGBT emitter region of the first cell region through the first through hole, and the insulating dielectric layer exposes the first injection region and part of the current sensor current detection region of the second cell region through the second through hole; IGBT emitter, the IGBT emitter region leads out of the first metal layer through the first through hole to form the IGBT emitter; current sensor current detection electrode, the current sensor current detection region leads out of the second metal layer through the second through hole to form the current sensor current detection electrode; IGBT collector region of the second doping type, the IGBT collector region is located on the back of the drift region; IGBT collector, the IGBT collector region leads out of the third metal layer as the IGBT collector. The second cell region (current sensor) shares a gate with the first cell region, and the transition region has a blocking layer that can increase the base concentration of the parasitic bipolar transistor (such as a PNP bipolar transistor) between the second cell region and the first cell region, so that the interference to the current sensor can be reduced, thereby improving the accuracy of the current output by the current sensor.

[0062] 2. The design method of the semiconductor device of the present invention comprises: establishing a first numerical model of the output current of the first cell region, the variables of the first numerical model are the gate-emitter voltage Vge and the collector-emitter voltage Vce; establishing a second numerical model of the output current of the second cell region, the variables of the second numerical model are the gate-emitter voltage Vge, the collector-emitter voltage Vce and the voltage drop Vs of the detection resistor; step S3, according to the first numerical model, the second numerical model and the current flowing through the detection resistor that satisfies the current characteristics of the second cell region and the characteristics of Ohm's law, calculating and obtaining the output current of the first cell region and the output current of the second cell region under the set test conditions and the design value of the ratio of the number of cells of the first cell region to the number of cells of the second cell region The output current and the voltage drop Vs of the detection resistor are calculated, and then the ratio of the output current of the first cell area to the output current of the second cell area is calculated; step S4, the calculated voltage drop Vs of the detection resistor and the ratio of the output current of the first cell area to the output current of the second cell area are compared with the corresponding design indicators respectively to determine whether the preset convergence conditions are met; if so, the ratio N of the number of cells of the first cell area to the second cell area meets the design indicators, so that the semiconductor device structure design stage can be entered; if not, the design value of the ratio N of the number of cells of the first cell area to the second cell area is replaced, and steps S3 and S4 are repeatedly executed in a cycle until it is determined that the preset convergence conditions are met, thereby improving the success rate of the initial design of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 It is a schematic diagram of the working principle of a semiconductor device;

[0064] Figure 2 is a schematic diagram of the layout structure of a semiconductor device according to an embodiment of the present invention;

[0065] Figure 3 When the semiconductor device of one embodiment of the present invention is a planar gate structure, Figure 2 Schematic diagram of the cross-sectional structure along the AA' direction;

[0066] Figure 4 When the semiconductor device of one embodiment of the present invention is a planar gate structure, Figure 2 Schematic diagram of the cross-sectional structure along the BB' direction;

[0067] Figure 5 When the semiconductor device of one embodiment of the present invention is a trench gate structure, Figure 2 Schematic diagram of the cross-sectional structure along the AA' direction;

[0068] Figure 6 When the semiconductor device of one embodiment of the present invention is a trench gate structure, Figure 2 Schematic diagram of the cross-sectional structure along the BB' direction;

[0069] Figure 7 The flowchart of the semiconductor device design method according to one embodiment of the present invention is shown in FIG.

[0070] Among them, Figure 1 to Figure 7 The reference numerals are described as follows:

[0071] 111-IGBT collector region; 112-field stop region; 113-drift region; 114-well region; 115-second injection region; 116-first injection region; 12-blocking layer; 13-gate; 131-gate dielectric layer; 14-IGBT emitter; 141-first through hole; 142-first extension portion; 15-current sensor current detection electrode; 151-second through hole; 152-second extension portion; 1521-first portion; 1522-second portion; 16-IGBT collector; 17-insulating dielectric layer. DETAILED DESCRIPTION

[0072] like Figure 1 As shown, the output current of the current sensor IS terminal is Is, and a voltage drop Vs is formed on the external detection resistor RS to monitor the current. When the output current Ice of the semiconductor device flowing from the collector C to the emitter E increases, the output current Is of the current sensor IS terminal increases accordingly, and the voltage drop Vs on the detection resistor RS increases, which can be detected by the overcurrent protection circuit and the semiconductor device can be shut down in time through the control system to prevent overcurrent damage to the semiconductor device. Among them, since the current sensor extracts a certain proportion of the IGBT cell (IGBT basic unit) common gate G, the current sensor is essentially a small semiconductor device, and can therefore provide real-time feedback on the current state of the semiconductor device.

[0073] The voltage drop Vs of the detection resistor RS and the current ratio Rcs are important design indicators for measuring current sensors. The current ratio Rcs is the ratio of the output current Ice of the emitter E to the output current Is of the current sensor IS terminal under a given gate-emitter voltage Vge, the output current Ice of the emitter E, and the resistance Rs of the detection resistor RS. Due to the negative feedback effect of the detection resistor RS, the gate-emitter voltage drop of the current sensor changes from Vge to Vge-Vs, and the collector-emitter voltage drop changes from Vce to Vce-Vs, resulting in a decrease in the output current Is, which leads to a deviation between the design value and the measured value.

[0074] The output current Ice of the IGBT device flowing from the collector C to the emitter E can be expressed as a function of the gate-emitter voltage Vge and the collector-emitter voltage Vce, that is, Ice = f(Vge, Vce). According to the characteristics of semiconductor devices, Ice increases with the increase of Vge and Vce. The current sensor uses the same cell structure as the IGBT device itself. Microscopically, the current characteristics of the single cells inside the two are the same. Therefore, based on the corresponding current relationship of the IGBT device, considering the influence of the cell number ratio N (the ratio of the number of cells of the IGBT device itself and the current sensor cell number) and the voltage drop Vs on the detection resistor RS, the expression of the output current Is can be expressed as Is = f(Vge-Vs, Vce-Vs) / N, then, the current ratio Rcs=Ice / Is=N f(Vge,Vce) / f(Vge-Vs,Vce-Vs).

[0075] According to the above formula, under given test conditions (Vge and Vce are fixed), Rcs is determined by the cell number ratio N and the voltage drop Vs. When Rs=0, Vs=0, so that the output current Is reaches the maximum value f(Vge, Vce) / N, and the current ratio Rcs is the cell number ratio N. As the resistance Rs of the detection resistor RS increases, the negative feedback effect of the detection resistor RS intensifies, causing the output current Is to further decrease, which in turn causes the measured value of the current ratio Rcs to deviate from the design value and be greater than the cell number ratio N.

[0076] Furthermore, current may flow out of the current sensor in the semiconductor device from the outer area of ​​the current sensor, thereby interfering with the output current Is of the current sensor, thereby causing the measured value of the current ratio Rcs to deviate from the designed value.

[0077] Therefore, when designing current sensors, engineers need to consider the errors introduced by factors such as the negative feedback effect of the detection resistor RS and appropriately increase the number of cells N to compensate. However, there is currently a lack of effective methods on the design side to estimate the voltage drop Vs and current ratio Rcs, resulting in the need to modify the layout once or even multiple times to adjust the number of cells N in semiconductor device design. Modifying the layout requires re-taping, which seriously affects the R&D cost and progress of semiconductor devices.

[0078] Therefore, there is a need to improve the success rate of initial design of semiconductor devices.

[0079] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and its manufacturing method, and the design method of the semiconductor device proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0080] An embodiment of the present invention provides a semiconductor device. Figure 1 to Figure 6 The semiconductor device provided by this embodiment is introduced in more detail.

[0081] The semiconductor device includes an IGBT (Insulated Gate Bipolar Transistor) cell and a current sensor cell. The IGBT cell and the current sensor cell are integrated on the same drift region 113 . The IGBT cell and the current sensor cell share a gate 13 .

[0082] A barrier layer 12 of the first doping type is located in a drift region 113 of the first doping type. The barrier layer 12 divides the semiconductor device into a first cell region A1, a second cell region A3 and a transition region A2. The second cell region A3 is located in the middle of the semiconductor device. The first cell region A1 is located around the semiconductor device. The transition region A2 is located between the first cell region A1 and the second cell region A3. The barrier layer 12 is located in the drift region 113 of the transition region A2. The first cell region A1 is an IGBT cell region, and the second cell region A3 is a current sensor cell region.

[0083] The first cell area A1 and the second cell area A3 both include a plurality of cells arranged in an array, and the second cell area A3 is used to form a current sensor.

[0084] The barrier layer 12 is formed by high energy ion implantation into the drift region 113 and annealing. In one embodiment, the doping concentration of the barrier layer 12 is 1E15 cm -3 ~1E18cm -3 .

[0085] In one embodiment, the thickness of the barrier layer 12 is 1 μm-10 μm.

[0086] A plurality of well regions 114 of the second doping type extend from the front surface of the drift region 113 to the inside of the drift region 113 and are located on the barrier layer 12. The first cell region A1, the transition region A2 and the second cell region A3 are all formed with well regions 114.

[0087] Preferably, the spacing distances between the well regions 114 are equal.

[0088] A plurality of first implantation regions 116 of the second doping type are respectively located in respective well regions 114 .

[0089] A second injection region 115 of the first doping type, wherein the second injection regions 115 at both ends of the first injection region 116 in the well region 114 of the first cell region A1 serve as IGBT emitter regions, and the second injection regions 115 at both ends of the first injection region 116 in the well region 114 of the second cell region A3 serve as current detection regions of the current sensor.

[0090] The gate 13 is connected between two adjacent well regions 114 , and the gate 13 is insulated from the IGBT emitter region, the current sensor current detection region, and the first injection region 116 by a gate dielectric layer 131 ;

[0091] In one embodiment, the gate dielectric layer 131 may be, for example, an oxide layer, and the gate 13 may be, for example, a polysilicon gate.

[0092] The doping concentration of the first injection region 116 is greater than the doping concentration of the well region 114. Since the doping concentration of the well region 114 is very low, the diode formed by the well region 114 and the second injection region 115 can be turned on when the current flowing to the well region 114 is very small; by forming the first injection region 116 with a large doping concentration in the well region 114, the resistance of the well region 114 is reduced, so that the diode formed by the well region 114 and the second injection region 115 can be turned on only when the current flowing to the well region 114 is very large.

[0093] The insulating dielectric layer 17 covers the gate 13 and the well region 114 and exposes the first injection region 116 of the first cell region A1 and part of the IGBT emitter region through the first through hole 141 . The insulating dielectric layer 17 exposes the first injection region 116 of the second cell region A3 and part of the current sensor current detection region through the second through hole 151 .

[0094] The insulating dielectric layer 17 may be made of various appropriate insulating materials, such as silicon oxide, phospho-silicate glass (PSG), etc.

[0095] The IGBT emitter 14 is formed by leading the IGBT emitter region out of the first metal layer through the first through hole 141 .

[0096] The first metal layer includes a portion filled in the first through hole 141 and a first extending portion 142 extending onto the insulating dielectric layer 17 .

[0097] The current sensor current detection electrode 15 , the current sensor current detection region is led out of the second metal layer through the second through hole 151 to form the current sensor current detection electrode 15 .

[0098] The second metal layer includes a portion filled in the second through hole 151 and a second extending portion 152 extending onto the insulating dielectric layer 17 .

[0099] The first metal layer is not connected to the second metal layer.

[0100] Preferably, the IGBT emitter 14 and the current sensor current detection electrode 15 are formed simultaneously using the same process to simplify the process.

[0101] The material of the IGBT emitter 14 and the current sensor current detection electrode 15 can be any conductive material such as metal materials or alloy materials suitable for electrodes.

[0102] The IGBT collector region 111 of the second doping type is located at the back side of the drift region 113 .

[0103] IGBT collector 16 , the IGBT collector region 111 leads out the third metal layer as the IGBT collector 16 .

[0104] The semiconductor device further includes a field stop region 112 of the first doping type, located between the IGBT collector region 111 and the drift region 113 .

[0105] The first doping type is N-type, and the second doping type is P-type; or the first doping type is P-type, and the second doping type is N-type.

[0106] In one embodiment, if Figure 3 and Figure 4 As shown, when the semiconductor device is a planar gate structure, the gate 13 is connected above two adjacent well regions 114, and the gate 13 is insulated from the IGBT emitter region, the IGBT emitter 14, the current sensor current detection region, the current sensor current detection electrode and the first injection region 116 through the gate dielectric layer 131. The gate and the IGBT emitter are located on the front side of the semiconductor device, and the IGBT collector is located on the back side of the semiconductor device.

[0107] In another embodiment, if Figure 5 and Figure 6 As shown, when the semiconductor device is a trench gate structure, the gate dielectric layer 131 is located in the trench, the trench is located between two adjacent well regions 114, the trench extends from the front side of the drift region 113 to the drift region 113, the depth of the trench is greater than the depth of the well region 114, the insulating dielectric layer 17 covers the gate 13, the gate dielectric layer 131 and the well region 114, and the insulating dielectric layer 17 exposes the first injection region 116 of the first cell region A1 and part of the IGBT emitter region through the first through hole 141, the insulating dielectric layer 17 exposes the first injection region 116 of the second cell region A3 and part of the current sensor current detection region through the second through hole 151, the gate is insulated from the IGBT emitter region, the IGBT emitter, the current sensor current detection region, the current sensor current detection electrode and the first injection region through the gate dielectric layer, and the gate and the IGBT emitter are located on the front side of the semiconductor device.

[0108] In one embodiment, if Figure 2 As shown, the gate 13, the first through hole 141 and the second through hole 151 extend along the first direction X, and the second extending portion 152 includes a first portion 1521 extending along the first direction X (as shown in FIG. Figure 2 The “—” portion of the T-shaped dotted line frame shown in FIG. 1 ) and the second portion 1522 extending along the second direction Y (such as Figure 2 The first portion 1521 is located in the second cell area A3, that is, the area where the first portion 1521 is located is the second cell area A3. The second portion 1522 extends along the second direction Y to connect to a bonding point.

[0109] In one embodiment, if Figure 2 As shown, transition zone A2 (such as Figure 2 The region where the barrier layer 12 is located as shown in the figure) includes a third portion extending along the first direction X and a fourth portion extending along the second direction Y, the third portion surrounds the first portion 1521, the second portion 1522 is located within the range of the fourth portion, and the first extension portion 142 (as shown in the figure) Figure 2 The area around the barrier layer 12 shown is the area where the first extension portion 142 is located, and is also the first cell area A1) located around the transition area A2. In other embodiments, the transition area A2 may only include the third portion extending along the first direction X, and not include the fourth portion extending along the second direction Y.

[0110] In one embodiment, the first direction X is perpendicular to the second direction Y.

[0111] It should be noted that the layout of the first cell area A1, the transition area A2 and the second cell area A3 is not limited to Figure 2 The embodiment shown.

[0112] It can be seen from the above that the first cell region A1 and the second cell region A3 have the same cell structure and share a gate 13 , so that the internal single cell current characteristics of the first cell region A1 and the second cell region A3 are the same.

[0113] When the current flows from the IGBT collector 16 of the first cell region A1, the transition region A2 and the second cell region A3 through the IGBT collector region 111 and the drift region 113 to the well region 114, the current of the first cell region A1 and the second cell region A3 will flow out from the IGBT emitter 14 and the current sensor current detection electrode 15 respectively through the second injection region 115; while the transition region A2 has no electrode formed, part of the current of the bipolar transistor (for example, a PNP bipolar transistor) formed by the IGBT collector region 111, the drift region 113 (or the drift region 113 and the field stop region 112) and the well region 114 (or the well region 114 and the first injection region 116) of the transition region A2 will flow to the second cell region A3 and flow out from the current sensor current detection electrode 15 of the second cell region A3, thereby causing the output current of the second cell region A3 ( That is, the output current of the current sensor is inaccurate; in the present invention, by forming a barrier layer 12 in the drift region 113 of the transition region A2, the doping concentration of the drift region 113 is increased, and the coefficient of the gain factor of the bipolar transistor in the transition region A2 is reduced, thereby reducing the current in the transition region A2, that is, the current of the bipolar transistor in the transition region A2 is suppressed, so that the current flowing from the bipolar transistor in the transition region A2 to the second cell region A3 is reduced, reducing the interference with the output current of the second cell region A3, and thereby improving the accuracy of the output current of the second cell region A3, thereby improving the accuracy of the ratio of the output current of the first cell region A1 to the output current of the second cell region A3 (that is, the current ratio Rcs), avoiding the actual measured value of the current ratio Rcs from deviating from the design value, and improving the success rate of the initial design of the semiconductor device.

[0114] In addition, since the second injection region 115 is not formed in the well region 114 of the transition region A2, the formation of a bipolar transistor (for example, an NPN bipolar transistor) consisting of the drift region 113 (or the drift region 113 and the field stop region 112), the well region 114 and the second injection region 115 in the transition region A2 can be avoided, thereby improving the anti-latch capability of the semiconductor device.

[0115] An embodiment of the present invention provides a method for designing a semiconductor device. Figure 7 ,from Figure 7 As can be seen, the design methods of semiconductor devices include:

[0116] Step S1, establishing a first numerical model of the output current of the first cell region, wherein the variables of the first numerical model are the gate-emitter voltage Vge and the collector-emitter voltage Vce;

[0117] Step S2, establishing a second numerical model of the output current of the second cell region, wherein the variables of the second numerical model are the gate-emitter voltage Vge, the collector-emitter voltage Vce and the voltage drop Vs of the detection resistor;

[0118] Step S3, according to the first numerical model, the second numerical model, and the current flowing through the detection resistor that simultaneously satisfies the current characteristics of the second cell area and Ohm's law, calculate and obtain the output current of the first cell area, the output current of the second cell area, and the voltage drop Vs of the detection resistor under the set test conditions and the design value of the ratio of the number of cells of the first cell area to the number of cells of the second cell area, and then calculate and obtain the ratio of the output current of the first cell area to the output current of the second cell area;

[0119] Step S4, compare the calculated voltage drop Vs of the detection resistor and the ratio of the output current of the first cell area to the output current of the second cell area with the corresponding design indicators to determine whether they meet the preset convergence conditions; if so, the ratio N of the number of cells in the first cell area to the second cell area meets the design indicators, so that the semiconductor device structure design stage can be entered; if not, replace the design value of the ratio N of the number of cells in the first cell area to the second cell area, and repeat the cycle of steps S3 and S4 until it is determined that the preset convergence conditions are met.

[0120] See below Figure 1 to Figure 6 The design method of the semiconductor device provided by this embodiment is introduced in more detail.

[0121] The structure of the semiconductor device is as described above and will not be described in detail here.

[0122] like Figure 1 As shown, the current sensor is externally connected to a detection resistor RS, the detection resistor RS is connected between the current detection electrode IS end of the current sensor (i.e., the current detection electrode 15 of the current sensor) and the ground GND, the IGBT emitter E (i.e., the IGBT emitter 14) is grounded, the first voltage source V1 is connected between the gate G (i.e., the gate 13) and the ground GND, and the second voltage source V2 is connected between the IGBT collector C (i.e., the IGBT collector 16) and the ground GND.

[0123] The first voltage source V1 is used to provide a gate-emitter voltage Vge, and the second voltage source V2 is used to provide a collector-emitter voltage Vce.

[0124] According to step S1 , a first numerical model of the output current of the first cell area A1 is established, and the variables of the first numerical model are the gate-emitter voltage Vge and the collector-emitter voltage Vce.

[0125] The first numerical model is Ice=f(Vge, Vce), which is to solve the analytical expression of Ice and the variables Vge and Vce. Among them, Ice is the output current of the first cell area A1, Vge is the gate-emitter voltage, and Vce is the collector-emitter voltage.

[0126] The output current of the first cell region A1 is the output current of the first cell region A1 working in the saturation region (i.e., the main working region in the application of semiconductor devices). When the IGBT device is in the on state, the first cell region A1 works in the saturation region, and Ice under different Vge conditions is a linear function of Vce.

[0127] When Vge is a set value (i.e. a known fixed value), Ice=a Vce+b; where a is the slope and b is the intercept.

[0128] Based on the characteristics of semiconductor devices, a and b can be linear functions of Vge, and we get a=c1 Vge+d1,b=c2 Vge+d2, so that the first numerical model of the output current of the first cell area A1 can be finally expressed as Ice=(c1 Vge+d1) Vce+c2 Vge+d2.

[0129] Among them, c1, d1, c2 and d2 can also be obtained by numerical fitting, and c1= K (1+β), d1=-K (1+β) Vth, c2 = -K (1+β) Vpn,d2=K (1+β) VPN Vth.

[0130] Wherein, K is the size and physical related parameters of the semiconductor device (such as the thickness, aspect ratio and other parameters of the gate dielectric layer 131 and the gate 13), β is the coefficient of the gain factor of the bipolar transistor (such as a PNP bipolar transistor) composed of the IGBT collector region 111, the drift region 113 and the well region 114, Vth is the threshold voltage of the semiconductor device, and Vpn is the voltage drop of the diode composed of the IGBT collector region 111 and the drift region 113. K, β, Vth and Vpn are all set values, so c1, d1, c2 and d2 can be calculated according to the above formula.

[0131] In other embodiments, when the semiconductor device further includes a field stop region 112, β is a bipolar transistor composed of the IGBT collector region 111, the field stop region 112, the drift region 113 and the well region 114, and Vpn is a voltage drop of a diode composed of the IGBT collector region 111, the field stop region 112 and the drift region 113.

[0132] In one embodiment, the threshold voltage Vth is generally 5V-6V, and the voltage drop Vpn of the diode is generally 0.7V-1V.

[0133] According to step S2, a second numerical model of the output current of the second cell area A3 is established, and the variables of the second numerical model are the gate-emitter voltage Vge, the collector-emitter voltage Vce and the voltage drop Vs of the detection resistor.

[0134] Since the cell structures of the first cell region A1 and the second cell region A3 are the same, the first cell region A1 and the second cell region A3 share a gate, the internal single cell current characteristics of the first cell region A1 and the second cell region A3 are the same, and the current sensor is externally connected to a detection resistor RS, the gate G-IS terminal voltage of the current sensor (i.e., the voltage drop across the gate 13 of the second cell region A3 and the current detection electrode 15 of the current sensor) is Vge-Vs, and the collector C-IS terminal voltage of the current sensor (i.e., the voltage drop across the IGBT collector 16 of the second cell region A3 and the current detection electrode 15 of the current sensor) is Vce-Vs, and thus the second numerical model is Is=f(Vge-Vs, Vce-Vs) / N; wherein Is is the output current of the second cell region A3, Vs is the voltage drop of the detection resistor RS, and N is the ratio of the number of cells of the first cell region A1 to that of the second cell region A3.

[0135] Furthermore, the output current of the second cell region A3 is the output current of the second cell region A3 operating in the saturation region (i.e., the main operating region in the application of semiconductor devices), so that when Vge is a set value, f(Vge-Vs, Vce-Vs)=[c1 (Vge-Vs)+d1] (Vce-Vs)+c2 (Vge-Vs)+d2, so that the second numerical model of the output current of the second cell area A3 can be finally expressed as Is={[c1 (Vge-Vs)+d1] (Vce-Vs)+c2 (Vge-Vs)+d2} / N.

[0136] According to step S3, based on the first numerical model, the second numerical model and the current flowing through the detection resistor RS that simultaneously satisfies the current characteristics of the second cell area A3 and the characteristics of Ohm's law, the output current of the first cell area A1, the output current of the second cell area A3 and the voltage drop of the detection resistor RS under the set test conditions and the design value of the ratio of the number of cells of the first cell area A1 to the second cell area A3 are calculated, and then the ratio of the output current of the first cell area A1 to the output current of the second cell area A3 is calculated.

[0137] Step S3 includes:

[0138] Step S31, according to the current flowing through the detection resistor RS satisfying the current characteristics of the second cell area A3 and the characteristics of Ohm's law, a formula f(Vge-Vs, Vce-Vs) / N=Vs / Rs is obtained, where Rs is the resistance value of the detection resistor RS;

[0139] Step S32: Under the set test conditions and the design value of the ratio of the number of cells in the first cell area A1 to the number of cells in the second cell area A3, Vce, Vge, Rs and N are set values, and the voltage drop Vs of the detection resistor RS is calculated according to the formula f(Vge-Vs, Vce-Vs) / N=Vs / Rs, and the voltage drop Vs of the detection resistor RS is calculated according to the formula Ice=a Vce+b is calculated to obtain the output current Ice of the first cell area A1;

[0140] Step S33, according to Is=Vs / Rs, the output current Is of the second cell area A3 is calculated, and then the ratio Rcs of the output current of the first cell area A1 to the output current of the second cell area A3 is calculated, Rcs=Ice / Is.

[0141] In step S31, when the current flowing through the detection resistor RS satisfies Ohm's law, Is=Vs / Rs; when the current flowing through the detection resistor RS satisfies the current characteristics of the second cell area A3, Is=f(Vge-Vs, Vce-Vs) / N, so that the formula f(Vge-Vs, Vce-Vs) / N=Vs / Rs can be obtained;

[0142] In step S32, for f(Vge-Vs, Vce-Vs) / N, when Vs=0, there is no influence of the negative feedback effect of the detection resistor RS, and Is is the largest; as Vs increases, Vge-Vs and Vce-Vs decrease, the negative feedback effect of the detection resistor RS intensifies, Is decreases, and f(Vge-Vs, Vce-Vs) / N shows a monotonically decreasing characteristic of Vs; for Vs / Rs, it is a monotonically increasing function with respect to Vs, so the formula f(Vge-Vs, Vce-Vs) / N=Vs / Rs must have a unique solution within Vs>0, that is, Vs can be obtained.

[0143] And, according to step S32 and step S2, it can be obtained that {[c1 (Vge-Vs)+d1] (Vce-Vs)+c2 (Vge-Vs)+d2} / N=Vs / Rs; wherein Vce, Vge, Rs and N are set values, and c1, d1, c2 and d2 have been calculated in step S1, then the voltage drop Vs of the detection resistor RS can be calculated according to this formula.

[0144] And, according to step S32 and step S1, the formula Ice=a Vce+b=(c1 Vge+d1) Vce+c2 Vge+d2 is calculated to obtain the output current Ice of the first cell area A1; wherein Vce and Vge are set values, and c1, d1, c2 and d2 have been calculated in step S1.

[0145] According to step S4, the calculated voltage drop Vs of the detection resistor RS and the ratio of the output current of the first cell area A1 to the output current of the second cell area A3 are compared with the corresponding design indicators to determine whether they meet the preset convergence conditions; if so, the ratio N of the number of cells of the first cell area A1 to the second cell area A3 meets the design indicators, and the required design parameter N is obtained, so that the semiconductor device structure design stage can be entered; if not, the design value of the ratio N of the number of cells of the first cell area A1 to the second cell area A3 is replaced, and steps S3 and S4 are repeatedly executed in a loop until it is determined that the preset convergence conditions are met.

[0146] It should be noted that, in the above step S3, the initial design value N of the ratio of the number of cells in the first cell area A1 to the number of cells in the second cell area A3 can be defined according to the experience of the designer.

[0147] The convergence condition means that the difference between the calculated value of the voltage drop of the detection resistor RS and the ratio of the output current of the first cell area A1 to the output current of the second cell area A3 and the design index is within the set specification.

[0148] After obtaining the ratio N of the number of cells in the first cell area A1 and the second cell area A3 that meets the design specification, the semiconductor device can be designed according to the N.

[0149] From the above content, it can be known that by establishing a first numerical model of the output current of the first cell area A1 and a second numerical model of the output current of the second cell area A3, and according to the first numerical model, the second numerical model and the current flowing through the detection resistor RS that simultaneously satisfies the current characteristics of the second cell area A3 and the characteristics of Ohm's law, the voltage drop of the detection resistor RS and the ratio of the output current of the first cell area A1 to the output current of the second cell area A3 are calculated, and the calculated voltage drop of the detection resistor RS and the ratio of the output current of the first cell area A1 to the output current of the second cell area A3 are respectively compared with corresponding design indicators to determine whether a preset convergence condition is met, and when the preset convergence condition is not met, the design value of the ratio of the number of cells of the first cell area A1 to the second cell area A3 is replaced, and steps S3 and S4 are repeatedly executed in a loop until it is determined that the preset convergence condition is met. The convergence condition set in advance enables the design value of the ratio of the number of cells of the first cell area A1 to the second cell area A3 that meets the design index to be obtained by calculation, and there is no need to find the design value of the ratio of the number of cells of the first cell area A1 to the second cell area A3 that meets the design index through multiple tape-outs, which reduces the number of tape-outs, reduces the R&D cost and speeds up the R&D progress; and, since in the above-mentioned process of calculating the ratio of the output current of the first cell area A1 to the output current of the second cell area A3, it is also considered that the current flowing through the detection resistor RS satisfies the current characteristics of the second cell area A3 and the characteristics of Ohm's law at the same time, so that the calculated ratio of the output current of the first cell area A1 to the output current of the second cell area A3 is more accurate, so that the finally obtained design value of the ratio of the number of cells of the first cell area A1 to the second cell area A3 that meets the design index is more accurate. Therefore, the success rate of the initial design of the semiconductor device is improved.

[0150] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 1 to Figure 6 The manufacturing method of the semiconductor device provided in this embodiment is introduced in more detail.

[0151] An IGBT (Insulated Gate Bipolar Transistor) cell and a current sensor cell are manufactured. The IGBT cell and the current sensor cell are integrated on the same drift region 113 . The IGBT cell and the current sensor cell share a gate 13 .

[0152] A barrier layer 12 of the first doping type is located in a drift region 113 of the first doping type. The barrier layer 12 divides the semiconductor device into a first cell region A1, a second cell region A3 and a transition region A2. The second cell region A3 is located in the middle of the semiconductor device. The first cell region A1 is located around the semiconductor device. The transition region A2 is located between the first cell region A1 and the second cell region A3. The barrier layer 12 is located in the drift region 113 of the transition region A2. The first cell region A1 is an IGBT cell region, and the second cell region A3 is a current sensor cell region.

[0153] The first cell area A1 and the second cell area A3 both include a plurality of cells arranged in an array, and the second cell area A3 is used to form a current sensor.

[0154] The barrier layer 12 is formed by high energy ion implantation into the drift region 113 and annealing. In one embodiment, the doping concentration of the barrier layer 12 is 1E15 cm -3 ~1E18cm -3 .

[0155] In one embodiment, the thickness of the barrier layer 12 is 1 μm-10 μm.

[0156] A plurality of well regions 114 of the second doping type extend from the front surface of the drift region 113 to the inside of the drift region 113 and are located on the barrier layer 12. The first cell region A1, the transition region A2 and the second cell region A3 are all formed with well regions 114.

[0157] The well region 114 is formed by ion implantation into the front side of the drift region 113 and annealing.

[0158] Preferably, the spacing distances between the well regions 114 are equal.

[0159] A plurality of first implantation regions 116 of the second doping type are respectively located in respective well regions 114 .

[0160] A second injection region 115 of the first doping type, wherein the second injection regions 115 at both ends of the first injection region 116 in the well region 114 of the first cell region A1 serve as IGBT emitter regions, and the second injection regions 115 at both ends of the first injection region 116 in the well region 114 of the second cell region A3 serve as current detection regions of the current sensor.

[0161] The first implantation region 116 and the second implantation region 115 are formed by performing ion implantation into the front surface of the well region 114 and performing annealing.

[0162] The gate 13 is connected across two adjacent well regions 114. The gate 13 is insulated from the IGBT emitter region, the IGBT emitter, the current sensor current detection region, the current sensor current detection electrode and the first injection region 116 by a gate dielectric layer 131. The gate and the IGBT emitter are located on the front side of the semiconductor device, and the IGBT collector is located on the back side of the semiconductor device.

[0163] In one embodiment, the gate dielectric layer 131 may be, for example, an oxide layer, and the gate 13 may be, for example, a polysilicon gate.

[0164] The doping concentration of the first injection region 116 is greater than the doping concentration of the well region 114. Since the doping concentration of the well region 114 is very low, the diode formed by the well region 114 and the second injection region 115 can be turned on when the current flowing to the well region 114 is very small; by forming the first injection region 116 with a large doping concentration in the well region 114, the resistance of the well region 114 is reduced, so that the diode formed by the well region 114 and the second injection region 115 can be turned on only when the current flowing to the well region 114 is very large.

[0165] The insulating dielectric layer 17 covers the gate 13 and the well region 114 and exposes the first injection region 116 of the first cell region A1 and part of the IGBT emitter region through the first through hole 141 . The insulating dielectric layer 17 exposes the first injection region 116 of the second cell region A3 and part of the current sensor current detection region through the second through hole 151 .

[0166] The insulating dielectric layer 17 may be made of various suitable insulating materials, such as silicon oxide, phospho-silicate glass (PSG), etc. The insulating dielectric layer 17 may be formed by a deposition process.

[0167] The IGBT emitter 14 is formed by leading the IGBT emitter region out of the first metal layer through the first through hole 141 .

[0168] The first metal layer includes a portion filled in the first through hole 141 and a first extending portion 142 extending onto the insulating dielectric layer 17 .

[0169] The current sensor current detection electrode 15 , the current sensor current detection region is led out of the second metal layer through the second through hole 151 to form the current sensor current detection electrode 15 .

[0170] The second metal layer includes a portion filled in the second through hole 151 and a second extending portion 152 extending onto the insulating dielectric layer 17 .

[0171] The first metal layer is not connected to the second metal layer.

[0172] Preferably, the IGBT emitter 14 and the current sensor current detection electrode 15 are formed simultaneously using the same process to simplify the process.

[0173] The material of the IGBT emitter 14 and the current sensor current detection electrode 15 can be any conductive material such as metal materials or alloy materials suitable for electrodes.

[0174] Among them, the insulating dielectric layer 17 can be etched first to form the first through hole 141 and the second through hole 151, and then a conductive material can be deposited into the first through hole 141 and the second through hole 151, and the conductive material also covers the insulating dielectric layer 17. After that, the conductive material on the insulating dielectric layer 17 is etched to obtain the IGBT emitter 14 and the current sensor current detection electrode 15.

[0175] The IGBT collector region 111 of the second doping type is located at the back side of the drift region 113 .

[0176] The IGBT collector region 111 is formed by performing ion implantation on the back side of the drift region 113 and performing annealing.

[0177] IGBT collector 16 , the IGBT collector region 111 leads out the third metal layer as the IGBT collector 16 .

[0178] The method further includes: a field stop region 112 of the first doping type is located between the IGBT collector region 111 and the drift region 113 .

[0179] The first doping type is N-type, and the second doping type is P-type; or the first doping type is P-type, and the second doping type is N-type.

[0180] In one embodiment, if Figure 3 and Figure 4 As shown, when the semiconductor device is a planar gate structure, the gate 13 is connected above two adjacent well regions 114, and the gate 13 is insulated from the IGBT emitter region, the current sensor current detection region, and the first injection region 116 by the gate dielectric layer 131. At this time, the gate dielectric layer 131 and the gate 13 can be formed by first depositing corresponding materials and then etching the corresponding materials.

[0181] In another embodiment, if Figure 5 and Figure 6As shown, when the semiconductor device is a trench gate structure, the gate dielectric layer 131 is located in the trench, the trench is located between two adjacent well regions 114, the trench extends from the front side of the drift region 113 to the drift region 113, the depth of the trench is greater than the depth of the well region 114, the insulating dielectric layer 17 covers the gate 13, the gate dielectric layer 131 and the well region 114, and the insulating dielectric layer 17 exposes the first injection region 116 of the first cell region A1 and part of the IGBT emitter region through the first through hole 141, the insulating dielectric layer 17 exposes the first injection region 116 of the second cell region A3 and part of the current sensor current detection region through the second through hole 151, the gate 13 is insulated from the IGBT emitter region, the IGBT emitter, the current sensor current detection region, the current sensor current detection electrode and the first injection region through the gate dielectric layer 131, and the gate and the IGBT emitter are located on the front side of the semiconductor device. At this time, the drift region 113 between two adjacent well regions 114 may be etched first to form a trench, and then the gate dielectric layer 131 and the gate 13 may be deposited in the trench in sequence.

[0182] In one embodiment, if Figure 2 As shown, the gate 13, the first through hole 141 and the second through hole 151 extend along the first direction X, and the second extending portion 152 includes a first portion 1521 extending along the first direction X (as shown in FIG. Figure 2 The “—” portion of the T-shaped dotted line frame shown in FIG. 1 ) and the second portion 1522 extending along the second direction Y (such as Figure 2 The first portion 1521 is located in the second cell area A3, that is, the area where the first portion 1521 is located is the second cell area A3. The second portion 1522 extends along the second direction Y to connect to a bonding point.

[0183] In one embodiment, if Figure 2 As shown, transition zone A2 (such as Figure 2 The region where the barrier layer 12 is located as shown in the figure) includes a third portion extending along the first direction X and a fourth portion extending along the second direction Y, the third portion surrounds the first portion 1521, the second portion 1522 is located within the range of the fourth portion, and the first extension portion 142 (as shown in the figure) Figure 2 The area around the barrier layer 12 shown is the area where the first extension portion 142 is located, and is also the first cell area A1) located around the transition area A2. In other embodiments, the transition area A2 may only include the third portion extending along the first direction X, and not include the fourth portion extending along the second direction Y.

[0184] In one embodiment, the first direction X is perpendicular to the second direction Y.

[0185] It should be noted that the layout of the first cell area A1, the transition area A2 and the second cell area A3 is not limited to Figure 2The embodiment shown.

[0186] It can be seen from the above that the first cell region A1 and the second cell region A3 have the same cell structure and share a gate 13 , so that the internal single cell current characteristics of the first cell region A1 and the second cell region A3 are the same.

[0187] When the current flows from the IGBT collector 16 of the first cell region A1, the transition region A2 and the second cell region A3 through the IGBT collector region 111 and the drift region 113 to the well region 114, the current of the first cell region A1 and the second cell region A3 will flow out from the IGBT emitter 14 and the current sensor current detection electrode 15 respectively through the second injection region 115; while the transition region A2 has no electrode formed, part of the current of the bipolar transistor (for example, a PNP bipolar transistor) formed by the IGBT collector region 111, the drift region 113 (or the drift region 113 and the field stop region 112) and the well region 114 (or the well region 114 and the first injection region 116) of the transition region A2 will flow to the second cell region A3 and flow out from the current sensor current detection electrode 15 of the second cell region A3, thereby causing the output current of the second cell region A3 ( That is, the output current of the current sensor is inaccurate; in the present invention, by forming a barrier layer 12 in the drift region 113 of the transition region A2, the doping concentration of the drift region 113 is increased, and the coefficient of the gain factor of the bipolar transistor in the transition region A2 is reduced, thereby reducing the current in the transition region A2, that is, the current of the bipolar transistor in the transition region A2 is suppressed, so that the current flowing from the bipolar transistor in the transition region A2 to the second cell region A3 is reduced, reducing the interference with the output current of the second cell region A3, and thereby improving the accuracy of the output current of the second cell region A3, thereby improving the accuracy of the ratio of the output current of the first cell region A1 to the output current of the second cell region A3 (that is, the current ratio Rcs), avoiding the actual measured value of the current ratio Rcs from deviating from the design value, and improving the success rate of the initial design of the semiconductor device.

[0188] In addition, since the second injection region 115 is not formed in the well region 114 of the transition region A2, the formation of a bipolar transistor (for example, an NPN bipolar transistor) consisting of the drift region 113 (or the drift region 113 and the field stop region 112), the well region 114 and the second injection region 115 in the transition region A2 can be avoided, thereby improving the anti-latch capability of the semiconductor device.

[0189] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: An IGBT cell and a current sensor cell, wherein the IGBT cell and the current sensor cell are integrated on the same drift region, and the IGBT cell and the current sensor cell share a gate; a barrier layer of a first doping type, the barrier layer being located in the drift region of the first doping type, the barrier layer dividing the semiconductor device into a first cell region, a second cell region and a transition region, the barrier layer being formed in the drift region of the transition region so that the doping concentration of the drift region is increased, the second cell region being located in the middle of the semiconductor device, the first cell region being located around the semiconductor device, the transition region being located between the first cell region and the second cell region, the barrier layer being located in the drift region of the transition region, the first cell region being an IGBT cell region, and the second cell region being a current sensor cell region; The semiconductor device comprises: a plurality of well regions of a second doping type, the well regions extending from the front side of the drift region into the drift region and being located on the barrier layer; A plurality of first implantation regions of a second doping type, wherein the first implantation regions are respectively located in the respective well regions; A second injection region of the first doping type, wherein the second injection regions at both ends of the first injection region in the well region of the first cell region serve as IGBT emitter regions, and the second injection regions at both ends of the first injection region in the well region of the second cell region serve as current sensor current detection regions; A gate, the gate being connected across two adjacent well regions, and the gate being insulated from the IGBT emitter region, the current sensor current detection region, and the first injection region by a gate dielectric layer; An insulating dielectric layer, the insulating dielectric layer covers the gate and the well region and the insulating dielectric layer exposes the first injection region of the first cell region and a portion of the IGBT emitter region through a first through hole, and the insulating dielectric layer exposes the first injection region of the second cell region and a portion of the current sensor current detection region through a second through hole; IGBT emitter, the IGBT emitter region is led out of the first metal layer through the first through hole to form the IGBT emitter; A current sensor current detection electrode, wherein the current sensor current detection region leads out the second metal layer through the second through hole to form the current sensor current detection electrode; An IGBT collector region of a second doping type, the IGBT collector region being located at the back side of the drift region; IGBT collector, the IGBT collector region leads out the third metal layer as the IGBT collector.

2. The semiconductor device according to claim 1, wherein: The doping concentration of the barrier layer is 1E15 cm -3 ~1E18cm -3 .

3. The semiconductor device according to claim 1, wherein: The thickness of the barrier layer is 1 μm to 10 μm.

4. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A field stop region of the first doping type is located between the IGBT collector region and the drift region.

5. The semiconductor device according to claim 4, characterized in that The first doping type is N-type, and the second doping type is P-type; or the first doping type is P-type, and the second doping type is N-type.

6. The semiconductor device according to claim 1, wherein: The gate is connected above the two adjacent well regions, and the gate is insulated from the IGBT emitter region, the IGBT emitter, the current sensor current detection region, the current sensor current detection electrode and the first injection region by a gate dielectric layer. The gate and the IGBT emitter are located on the front side of the semiconductor device.

7. The semiconductor device according to claim 1, wherein: The gate dielectric layer is located in the groove, and the groove is located between the two adjacent well regions. The groove extends from the front side of the drift region to the drift region, and the depth of the groove is greater than the depth of the well region. The insulating dielectric layer covers the gate, the gate dielectric layer and the well region, and the insulating dielectric layer exposes the first injection region of the first cell region and part of the IGBT emitter region through a first through hole, and the insulating dielectric layer exposes the first injection region of the second cell region and part of the current sensor current detection region through a second through hole. The gate is insulated from the IGBT emitter region, the IGBT emitter, the current sensor current detection region, the current sensor current detection electrode and the first injection region through the gate dielectric layer, and the gate and the IGBT emitter are located on the front side of the semiconductor device.

8. The semiconductor device according to claim 1, wherein: The well regions are spaced at equal distances from each other.

9. A method for designing a semiconductor device according to any one of claims 1 to 8, characterized in that: The current sensor is externally connected to a detection resistor, the detection resistor is connected between the current detection electrode of the current sensor and the ground, the emitter of the IGBT is grounded, the gate is connected to the ground with a first voltage source, and the collector of the IGBT is connected to the ground with a second voltage source; the design method of the semiconductor device includes: Step S1, establishing a first numerical model of the output current of the first cell region, wherein the variables of the first numerical model are a gate-emitter voltage Vge and a collector-emitter voltage Vce; Step S2, establishing a second numerical model of the output current of the second cell region, wherein the variables of the second numerical model are the gate-emitter voltage Vge, the collector-emitter voltage Vce and the voltage drop Vs of the detection resistor; Step S3, according to the first numerical model, the second numerical model, and the current flowing through the detection resistor that simultaneously satisfies the current characteristics of the second cell area and Ohm's law, calculate and obtain the output current of the first cell area, the output current of the second cell area, and the voltage drop Vs of the detection resistor under set test conditions and the design value of the ratio of the number of cells of the first cell area to the number of cells of the second cell area, and then calculate and obtain the ratio of the output current of the first cell area to the output current of the second cell area; Step S4, comparing the calculated voltage drop Vs of the detection resistor and the ratio of the output current of the first cell area to the output current of the second cell area with the corresponding design indicators to determine whether they meet the preset convergence conditions; if so, the ratio N of the number of cells of the first cell area to the second cell area meets the design indicators, so that the semiconductor device structure design stage can be entered; if not, the design value of the ratio N of the number of cells of the first cell area to the second cell area is replaced, and the steps S3 and S4 are repeatedly executed in a loop until it is determined that the preset convergence conditions are met.

10. The method for designing a semiconductor device according to claim 9, wherein: The output currents of the first cell region and the second cell region are respectively the output currents of the first cell region and the second cell region when they operate in the saturation region.

11. The method for designing a semiconductor device according to claim 10, wherein: The first numerical model is Ice=f(Vge, Vce), Vge is a set value, so that Ice=a Vce+b; wherein Ice is the output current of the first cell region, Vge is the gate-emitter voltage, Vce is the collector-emitter voltage, a is the slope, and b is the intercept.

12. The method for designing a semiconductor device according to claim 11, wherein: a=c1 Vge+d1,b=c2 Vge+d2,c1=K (1+β), d1=-K (1+β) Vth, c2 = -K (1+β) Vpn,d2=K (1+β) VPN Vth; wherein, K is the size and physical related parameters of the semiconductor device, β is the coefficient of the gain factor of the bipolar transistor composed of the IGBT collector region, the drift region and the well region, Vth is the threshold voltage of the semiconductor device, and Vpn is the voltage drop of the diode composed of the IGBT collector region and the drift region.

13. The method for designing a semiconductor device according to claim 12, wherein: The second numerical model is: Is=f(Vge-Vs,Vce-Vs) / N={[c1 (Vge-Vs)+d1] (Vce-Vs)+c2 (Vge-Vs)+d2} / N; Wherein, Is is the output current of the second cell region, Vs is the voltage drop of the detection resistor, and N is the ratio of the number of cells in the first cell region to the number of cells in the second cell region.

14. The method for designing a semiconductor device according to claim 13, wherein: The step S3 comprises: According to the current flowing through the detection resistor satisfying the current characteristic of the second cell region and Ohm's law at the same time, a formula f(Vge-Vs, Vce-Vs) / N=Vs / Rs is obtained, where Rs is the resistance value of the detection resistor; Under the set test conditions and the design value of the ratio of the number of cells in the first cell area to the number of cells in the second cell area, Vce, Vge, Rs and N are set values, and the voltage drop of the detection resistor is calculated according to the formula f(Vge-Vs, Vce-Vs) / N=Vs / Rs, and the voltage drop of the detection resistor is calculated according to the formula Ice=a Vce+b is calculated to obtain the output current of the first cell region; The output current of the second cell region is obtained by calculation according to Is=Vs / Rs, and then the ratio of the output current of the first cell region to the output current of the second cell region is obtained by calculation.

15. A method for manufacturing a semiconductor device, characterized in that: include: Manufacturing an IGBT cell and a current sensor cell, wherein the IGBT cell and the current sensor cell are integrated on the same drift region, and the IGBT cell and the current sensor cell share a gate; Forming a barrier layer of a first doping type, the barrier layer being located in the drift region of the first doping type, the barrier layer dividing the semiconductor device into a first cell region, a second cell region and a transition region, and by forming the barrier layer in the drift region of the transition region, the doping concentration of the drift region is increased, the second cell region is located in the middle of the semiconductor device, the first cell region is located around the semiconductor device, the transition region is located between the first cell region and the second cell region, the barrier layer is located in the drift region of the transition region, the first cell region is an IGBT cell region, and the second cell region is a current sensor cell region; The method comprises: forming a plurality of well regions of a second doping type, wherein the well regions extend from the front side of the drift region into the drift region and are located on the barrier layer; forming a plurality of first implantation regions of a second doping type, wherein the first implantation regions are respectively located in the respective well regions; forming a second injection region of the first doping type, wherein the second injection regions at both ends of the first injection region in the well region of the first cell region serve as IGBT emitter regions, and the second injection regions at both ends of the first injection region in the well region of the second cell region serve as current sensor current detection regions; Forming a gate, the gate being connected across two adjacent well regions, and the gate being insulated from the IGBT emitter region, the current sensor current detection region, and the first injection region by a gate dielectric layer; forming an insulating dielectric layer, wherein the insulating dielectric layer covers the gate and the well region and the insulating dielectric layer exposes the first injection region of the first cell region and a portion of the IGBT emitter region through a first through hole, and the insulating dielectric layer exposes the first injection region of the second cell region and a portion of the current sensor current detection region through a second through hole; An IGBT emitter is formed, wherein the IGBT emitter region is led out of the first metal layer through the first through hole to form the IGBT emitter; forming a current sensor current detection electrode, wherein the current sensor current detection region leads out a second metal layer through the second through hole to form the current sensor current detection electrode; forming an IGBT collector region of a second doping type, wherein the IGBT collector region is located at the back side of the drift region; An IGBT collector is formed, and the IGBT collector region leads out the third metal layer as the IGBT collector.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The doping concentration of the barrier layer is 1E15 cm -3 ~1E18cm -3 .

17. The method for manufacturing a semiconductor device according to claim 15, wherein: The thickness of the barrier layer is 1 μm to 10 μm.

18. The method for manufacturing a semiconductor device according to claim 15, wherein: The method further comprises: A field stop region of a first doping type is formed between the IGBT collector region and the drift region.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The first doping type is N-type, and the second doping type is P-type; or the first doping type is P-type, and the second doping type is N-type.

20. The method for manufacturing a semiconductor device according to claim 15, wherein: The gate is connected above the two adjacent well regions, and the gate is insulated from the IGBT emitter region, the IGBT emitter, the current sensor current detection region, the current sensor current detection electrode and the first injection region by a gate dielectric layer. The gate and the IGBT emitter are located on the front side of the semiconductor device, and the IGBT collector is located on the back side of the semiconductor device.

21. The method for manufacturing a semiconductor device according to claim 15, wherein: The gate dielectric layer is located in the groove, and the groove is located between the two adjacent well regions. The groove extends from the front side of the drift region to the drift region, and the depth of the groove is greater than the depth of the well region. The insulating dielectric layer covers the gate, the gate dielectric layer and the well region, and the insulating dielectric layer exposes the first injection region of the first cell region and part of the IGBT emitter region through a first through hole, and the insulating dielectric layer exposes the first injection region of the second cell region and part of the current sensor current detection region through a second through hole. The gate is insulated from the IGBT emitter region, the IGBT emitter, the current sensor current detection region, the current sensor current detection electrode and the first injection region through the gate dielectric layer, and the gate and the IGBT emitter are located on the front side of the semiconductor device.

22. The method for manufacturing a semiconductor device according to claim 15, wherein: The well regions are spaced at equal distances from each other.

Images