Display device and electronic equipment

Abstract

The application provides a display device and an electronic equipment. The display device has a display light transmission area and a transition display area. The transition display area is located at the periphery of the display light transmission area. The display device comprises: a plurality of light emitting devices arranged in the display light transmission area; a plurality of pixel driving circuits arranged in the transition display area. Each pixel driving circuit comprises: a driving transistor comprising a gate; and a gate lead wire located above the driving transistor and electrically connected with the gate of the driving transistor; at least one transparent conductive layer located above the plurality of pixel driving circuits, the at least one transparent conductive layer comprising a plurality of transparent conductive lines electrically connected with the plurality of light emitting devices and part of the pixel driving circuits; and a shielding layer located between the plurality of gate lead wires and the at least one transparent conductive layer and arranged corresponding to the plurality of gate lead wires.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display device and electronic device. Background Technology

[0002] Currently, in the design of Active Metrix Organic Light Emitting Diode (AMOLED) display panels, using an under-display camera area for display has become a major trend. A common solution is to use transparent wires to electrically connect the pixels in the under-display camera area to improve the light transmittance of the camera area, thereby achieving a transparent display. However, because the transparent wires form parasitic capacitances with the gate leads of the driving transistors in the pixel driving circuit, and due to uneven distribution of the transparent wires, differences in parasitic capacitance between the transparent wires and the gate leads result in display differences in the pixels driven by the pixel driving circuit, leading to the problem of uneven brightness (mura) in the AMOLED display panel.

[0003] Therefore, it is necessary to propose a technical solution to solve the problem of uneven brightness in the display caused by the difference in parasitic capacitance between the transparent conductor and the gate lead. Summary of the Invention

[0004] The purpose of this application is to provide a display device and electronic device to improve the problem of uneven display brightness caused by the difference in parasitic capacitance between transparent conductors and gate leads.

[0005] A display device has a light-transmitting display area and a transition display area, the transition display area being located around the light-transmitting display area, the display device comprising:

[0006] Multiple light-emitting devices are disposed in the display light-transmitting area;

[0007] Multiple pixel driving circuits are disposed in the transition display area, each pixel driving circuit comprising:

[0008] A driving transistor, the driving transistor including a gate; and

[0009] A gate lead, the gate lead being located above the driving transistor, and the gate lead being electrically connected to the gate of the driving transistor;

[0010] At least one transparent conductive layer is located above the plurality of pixel driving circuits. The at least one transparent conductive layer includes a plurality of transparent wires electrically connecting the plurality of light-emitting devices and a portion of the pixel driving circuits.

[0011] A shielding layer is located between the plurality of gate leads and at least one of the transparent conductive layers, and is disposed corresponding to the plurality of gate leads.

[0012] In the above-described display device, in the thickness direction of the display device, the orthogonal projection of the plurality of gate leads on the substrate of the display device is located inside the orthogonal projection of the shielding layer on the substrate of the display device.

[0013] In the above-mentioned display device, the display device further includes a metal mesh for transmitting DC voltage signals. The metal mesh is disposed in the same layer as the shielding layer, and the metal mesh disposed in the transition display area and located above the plurality of pixel driving circuits extends out of the shielding layer.

[0014] In the above-mentioned display device, the display device further includes multiple DC power signal lines, the multiple DC power signal lines are disposed on the same layer as the multiple gate leads, and the metal mesh is electrically connected to the multiple DC power signal lines.

[0015] In the above-mentioned display device, the display device further includes a main display area, the transition display area is located between the main display area and the display light-transmitting area, an insulating layer is provided between the multiple DC power signal lines and the metal mesh, the insulating layer is provided with a via corresponding to the portion of the main display area, and the metal mesh and the multiple DC power signal lines are electrically connected through the via.

[0016] In the above-mentioned display device, the DC voltage signal is selected from either an initialization signal or a DC power supply signal.

[0017] In the above-described display device, each pixel driving circuit further includes a compensation transistor and an electrode plate, wherein the electrode plate is disposed corresponding to the gate of the driving transistor and the electrode plate is located between the gate lead and the gate of the driving transistor.

[0018] One end of the gate lead is electrically connected to the active layer of the compensation transistor of the pixel driving circuit, and the other end of the gate lead is connected to the gate of the driving transistor at least through a via on the electrode plate.

[0019] In the above-described display device, a portion of the transparent conductors extends from the transition display area to the display light-transmitting area, and a portion of the transparent conductors are located within the transition display area.

[0020] In the above-mentioned display device, the display device includes a plurality of transparent conductive layers, and the plurality of transparent wires are located in different transparent conductive layers.

[0021] In the above-described display device, the light-transmitting area is circular in shape, and the plurality of pixel driving circuits form a plurality of pixel driving circuit islands. The plurality of pixel driving circuit islands are arranged around the light-transmitting area, and the number of pixel driving circuits in at least two of the pixel driving circuit islands is different.

[0022] An electronic device includes the aforementioned display device and a photosensitive unit, wherein the photosensitive unit is disposed corresponding to the display light-transmitting area of ​​the display device.

[0023] Beneficial effects: This application shields the parasitic capacitance between the gate lead and the transparent wire through a shielding layer, avoiding the difference in parasitic capacitance affecting the potential difference of the gate of the driving transistor, improving the stability of the driving transistor driving the light-emitting device, and avoiding the problem of uneven brightness when the light-emitting device of the display device is displayed. Attached Figure Description

[0024] Figure 1 This is a plan view of the display device according to an embodiment of this application;

[0025] Figure 2 for Figure 1 A partially enlarged schematic diagram of the display device shown;

[0026] Figure 3 for Figure 2 A partial schematic diagram of the display device shown;

[0027] Figure 4 for Figure 3 The equivalent circuit diagram of the second pixel driving circuit is shown below.

[0028] Figure 5 for Figure 4 The driving timing diagram corresponding to the second pixel driving circuit is shown below;

[0029] Figure 6 This is a cross-sectional schematic diagram of the display device;

[0030] Figure 7 A planar schematic diagram of the second pixel driving circuit and the traces connected to the second pixel driving circuit;

[0031] Figures 8-12 To form Figure 7 The diagram shows a planar schematic of the second pixel driving circuit and the multiple film layers connected to the second pixel driving circuit. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0033] This application provides a display device, which can be a liquid crystal display device or an organic light-emitting diode (OLED) display device. Specifically, the display device is an organic light-emitting diode (OLED) display device.

[0034] Please see Figure 1 and Figure 2 As shown, Figure 1 This is a plan view of the display device according to an embodiment of this application. Figure 2 for Figure 1 A partially enlarged schematic diagram of the display device shown. Figure 3 for Figure 2 A partial schematic diagram of the display device is shown. The display device 100 has a light-transmitting display area 100a, a main display area 100c, and a transition display area 100b. The display device 100 includes a plurality of first display pixels, a plurality of first pixel driving circuits (not shown), a plurality of second display pixels, a plurality of pixel driving circuit islands 101, and a plurality of transparent wires 102.

[0035] The transition display area 100b is located outside the display light-transmitting area 100a, between the main display area 100c and the display light-transmitting area 100a. Both the main display area 100c and the transition display area 100b are used for display. The display light-transmitting area 100a, while serving as a display area, also possesses high light transmittance. The light transmittance of the display light-transmitting area 100a is greater than that of the main display area 100c and the transition display area 100b. The area of ​​the main display area 100c is greater than the area of ​​both the transition display area 100b and the display light-transmitting area 100a. The display light-transmitting area 100a is circular in shape, while the transition display area 100b is annular in shape. The display light-transmitting area 100a is symmetrical about axes of symmetry AA and BB, which are perpendicular to each other.

[0036] Multiple first display pixels are evenly disposed in the main display area 100c. Each first display pixel includes a first red sub-pixel 100c1, a first green sub-pixel 100c3, and a first blue sub-pixel 100c2. The first red sub-pixel 100c1, the first green sub-pixel 100c3, and the first blue sub-pixel 100c2 are distributed in a Pentile design in the main display area 100c. The first green sub-pixel 100c3 is elliptical in shape, while the first red sub-pixel 100c1 and the first blue sub-pixel 100c2 are octagonal.

[0037] Multiple first pixel driving circuits are also disposed in the main display area 100c. Each first pixel driving circuit drives one sub-pixel (one of the first red sub-pixel 100c1, the first green sub-pixel 100c3, and the first blue sub-pixel 100c2) of the main display area 100c to emit light. Each first pixel driving circuit includes multiple metal film layers, and the multiple first pixel driving circuits are arrayed in the main display area 100c, resulting in low light transmittance of the main display area 100c. The first red sub-pixel 100c1, the first green sub-pixel 100c3, and the first blue sub-pixel 100c2 all include light-emitting devices, which are organic light-emitting diodes.

[0038] Multiple second display pixels are uniformly disposed in the display light-transmitting area 100a and the transition display area 100b. Each second display pixel includes a second red sub-pixel 100a1, a second green sub-pixel 100a3, and a second blue sub-pixel 100a2. The second red sub-pixel 100a1, the second green sub-pixel 100a3, and the second blue sub-pixel 100a2 are all distributed in a Pentile design in both the display light-transmitting area 100a and the transition display area 100b. The second red sub-pixel 100a1, the second green sub-pixel 100a3, and the second blue sub-pixel 100a2 are all circular in shape. Each second red sub-pixel 100a1, the second green sub-pixel 100a3, and the second blue sub-pixel 100a2 includes a light-emitting device, which is an organic light-emitting diode (OLED). Each OLED includes an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0039] The size of the first red sub-pixel 100c1 is larger than the size of the second red sub-pixel 100a1, the size of the first green sub-pixel 100c3 is larger than the size of the second green sub-pixel 100a3, and the size of the first blue sub-pixel 100c2 is larger than the size of the second blue sub-pixel 100a2, to ensure that the light-transmitting area 100a has high light transmittance. From the main display area 100c to the transition display area 100b, the size of the subpixels decreases.

[0040] Since the size of a second red sub-pixel 100a1 is different from that of a first red sub-pixel 100c1, the driving power of their corresponding driving circuits is also different. Similarly, the driving power of the driving circuits of the first green sub-pixel 100c3 and the second green sub-pixel 100a3 is also different, and the driving power of the driving circuits of the first blue sub-pixel 100c2 and the second blue sub-pixel 100a2 is also different. Therefore, the first pixel driving circuit can only be used to drive the first red sub-pixel 100c1, the first green sub-pixel 100c3, and the first blue sub-pixel 100c2 in the main display area 100c, but cannot be used to drive the second red sub-pixel 100a1, the second green sub-pixel 100a3, and the second blue sub-pixel 100a2 in the transition display area 100b and the display light-transmitting area 100a.

[0041] Please combine Figure 2 and Figure 3 Multiple pixel driving circuit islands 101 are disposed in the transition display area 100b. Each pixel driving circuit island 101 includes multiple arrayed second pixel driving circuits 1011, with m rows and n columns, where m is greater than or equal to 2 and n is greater than or equal to 2, i.e., each pixel driving circuit island 101 is strip-shaped. The second pixel driving circuits 1011 of the multiple pixel driving circuit islands 101 are used to drive multiple second display pixels to emit light. That is, while driving the second display pixels in the transition display area 100b to emit light, the second pixel driving circuits 1011 of the multiple pixel driving circuit islands 101 are also used to drive the second display pixels in the display light-transmitting area 100a to emit light, so as to avoid the pixel driving circuit being disposed in the display light-transmitting area 100a and to avoid the metal film layer of the pixel driving circuit affecting the light transmittance of the display light-transmitting area 100a, thereby further improving the light transmittance of the display light-transmitting area 100a. Multiple second pixel driving circuits 1011 form multiple pixel driving circuit islands 101, which helps reduce the space required by the multiple second pixel driving circuits 1011 and facilitates the driving of the second display pixels corresponding to the light-transmitting area 100a by the second pixel driving circuits 1011. However, this results in the lines electrically connected to the second pixel driving circuits 1011 being concentrated in the area where the pixel driving circuit islands 101 are arranged. A pixel driving circuit island 101 refers to a multiple second pixel driving circuits 1011 being arranged in an island-like cluster, wherein the distance between two adjacent pixel driving circuit islands 101 is greater than the distance between two adjacent second pixel driving circuits 1011 within the same pixel driving circuit island 101.

[0042] Unlike the main display area 100c, a second pixel driving circuit 1011 drives at least two of the plurality of second red sub-pixels 100a1, second green sub-pixels 100a3, and second blue sub-pixels 100a2. This reduces the number of second pixel driving circuits 1011 and the space occupied by the pixel driving circuit islands 101, thereby allowing the size of the display light-transmitting area 100a to be increased or allowing the transition display area 100b to have more space without pixel driving circuit islands 101. The second pixel driving circuit 1011 can drive sub-pixels that emit the same color light and / or sub-pixels that emit different colors light among the plurality of second red sub-pixels 100a1, second green sub-pixels 100a3, and second blue sub-pixels 100a2. In the display light-transmitting area 100a, sub-pixels driven by the same second pixel driving circuit 1011 are electrically connected through transparent wires.

[0043] Specifically, the two second red sub-pixels 100a1 are driven by the same second pixel driving circuit 1011, the two second blue sub-pixels 100a2 are driven by the same second pixel driving circuit 1011, and the four second green sub-pixels 100a3 are driven by the same second pixel driving circuit 1011.

[0044] like Figure 2 As shown, multiple pixel driving circuit islands 101 are arranged around the display light-transmitting area 100a. The number of second pixel driving circuits 1011 in at least two pixel driving circuit islands 101 is different, so that the number of sub-pixels driven by the at least two pixel driving circuit islands 101 is different. This adapts to the situation where the number of sub-pixels in the display light-transmitting area 100a varies when the display light-transmitting area 100a is circular and a portion of the second pixel driving circuits 1011 of each pixel driving circuit island 101 is used to drive the corresponding sub-pixels in the display light-transmitting area 100a.

[0045] The plurality of pixel driving circuit islands 101 include a first group of pixel driving circuit islands 1012 (pixel driving circuit islands 101 above the axis of symmetry BB) and a second group of pixel driving circuit islands 1013 (pixel driving circuit islands 101 below the axis of symmetry BB). The pixel driving circuit islands 101 in the first group of pixel driving circuit islands 1012 and the pixel driving circuit islands 1013 in the second group of pixel driving circuit islands 1012 are symmetrically arranged about the axis of symmetry BB, the pixel driving circuit islands 101 in the first group of driving circuit islands 1012 are symmetrically arranged about the axis of symmetry AA, and the pixel driving circuit islands 101 in the second group of pixel driving circuit islands 1012 are symmetrically arranged about the axis of symmetry AA.

[0046] The number of second pixel driving circuits 1011 in some pixel driving circuit islands 101 of the first group of pixel driving circuit islands 1012 decreases from near the axis of symmetry AA to far from the axis of symmetry AA. Correspondingly, the number of second pixel driving circuits 1011 in some pixel driving circuit islands 1013 of the second group of pixel driving circuit islands decreases from near the axis of symmetry AA to far from the axis of symmetry AA. One pixel driving circuit island 101 in the first group of pixel driving circuit islands 1012 and one corresponding pixel driving circuit island 101 in the second group of pixel driving circuit islands 1013 drive the sub-pixels in their respective regions and between them in the light-transmitting area 100a, such as the sub-pixels in region 100d. Each pixel driving circuit island 101 in the first group of pixel driving circuit islands 1012 and the second group of pixel driving circuit islands 1013 drives the sub-pixels in its corresponding region and also drives the sub-pixels in the light-transmitting area 100a between the pixel driving circuit island 101 and its corresponding pixel driving circuit island in the second group of pixel driving circuit islands 1013.

[0047] like Figure 3 As shown, in order to improve the light transmittance of the light-transmitting area 100a, multiple second pixel driving circuits 1011 are electrically connected to the second red sub-pixel 100a1, the second blue sub-pixel 100a2, and the second green sub-pixel 100a3 of the light-transmitting area 100a via multiple transparent wires 102. Because the multiple second pixel driving circuits 101 are concentrated in an island-like distribution, the number of transparent wires 102 provided on the corresponding pixel driving circuit island 101 is relatively large. Some transparent wires 102 overlap with gate leads electrically connected to the gates of the driving transistors of the second pixel driving circuits 1011 in the pixel driving circuit island 101. Furthermore, the dense and varied distribution of the transparent wires 102 results in differences in the area of ​​overlap between different gate leads and transparent wires 102.

[0048] Please see Figures 4-6 , Figure 4 for Figure 3 The equivalent circuit diagram of the second pixel driving circuit is shown below. Figure 5 for Figure 4 The driving timing diagram corresponding to the second pixel driving circuit is shown below. Figure 6 This is a cross-sectional schematic diagram of the display device.

[0049] Each second pixel driving circuit 1011 includes a driving transistor M1, a switching transistor M2, a compensation transistor M3, an initialization transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, an anode reset transistor M7, and a capacitor C. The driving transistor M1, switching transistor M2, compensation transistor M3, initialization transistor M4, first light-emitting control transistor M5, second light-emitting control transistor M6, and anode reset transistor M7 are all P-type transistors.

[0050] The display device 100 also includes a plurality of traces electrically connected to the second pixel driving circuit 1011. These traces include an (n-1)th level scan signal line SCAN(n-1), an nth level scan signal line SCAN(n), a data line D(m), an initialization signal line VI, a DC power signal line VDD, and an nth level light emission control signal line EM(n), all disposed in the transition display area 100b. The (n-1)th level scan signal line SCAN(n-1) transmits the (n-1)th level scan signal. The nth level scan signal line SCAN(n) transmits the nth level scan signal. The data line D(m) transmits the data signal. The DC power signal line VDD transmits the DC power signal. The nth level light emission control signal line EM(n) transmits the nth level light emission control signal. The initialization signal line VI transmits an initialization signal or a reset signal.

[0051] The gate G1 of the driving transistor M1 is connected to the first electrode plate C1 of the capacitor C, the drain D3 of the compensation transistor M3, and the source S4 of the initialization transistor M4. The source S1 of the driving transistor M1 is connected to the DC power signal line VDD through the first light-emitting control transistor M5, and the source S1 of the driving transistor M1 is connected to the data line D(m) through the switching transistor M2. The drain D1 of the driving transistor M1 is connected to the light-emitting device OLED through the second light-emitting control transistor M6. When the switching transistor M2 is turned on, the driving transistor M1 receives the data signal transmitted by the data line D(m) and provides driving current to the light-emitting device OLED.

[0052] The gate G2 of switching transistor M2 is connected to the nth scan signal line SCAN(n), the source S2 of switching transistor M2 is connected to the data line D(m), and the drain D2 of switching transistor M2 is connected to the source S1 of driving transistor M1. The drain D2 of switching transistor M2 is also connected to the DC power supply signal line VDD through the first light-emitting control transistor M5. Switching transistor M2 is turned on or off according to the nth scan signal transmitted by the nth scan signal line SCAN(n), controlling whether the data signal transmitted by the data line D(m) is written to the source S1 of driving transistor M1.

[0053] The gate G3 of the compensation transistor M3 is connected to the nth-level scan signal line SCAN(n), and the source S3 of the compensation transistor M3 is connected to the drain D1 of the driving transistor M1. The source S3 of the compensation transistor M3 is also connected to the light-emitting device OLED through the second light-emitting control transistor M6. The drain D3 of the compensation transistor M3 is connected to the gate G1 of the driving transistor M1, the source S4 of the initialization transistor M4, and the first electrode plate C1 of the capacitor C. The compensation transistor M3 is turned on according to the nth-level scan signal transmitted by the nth-level scan signal line SCAN(n), and is electrically connected to the gate G1 and the drain D1 of the driving transistor M1.

[0054] The gate G4 of the initialization transistor M4 is connected to the (n-1)th level scan signal line SCAN(n-1). The drain D4 of the initialization transistor M4 is connected to the drain D7 of the anode reset transistor M7 and the initialization signal line VI. The source S4 of the initialization transistor M4 is connected to the gate G1 of the driving transistor M1, the drain D3 of the compensation transistor M3, and the first electrode plate C1 of the capacitor C. The initialization transistor M4 is turned on or off according to the (n-1)th level scan signal transmitted by the (n-1)th level scan signal line SCAN(n-1), controlling whether the initialization signal transmitted by the initialization signal line VI is written to the gate G1 of the driving transistor M1.

[0055] The gate G5 of the first light-emitting control transistor M5 is connected to the nth-level light-emitting control signal line EM(n). The source S5 of the first light-emitting control transistor M5 is connected to the DC power supply signal line VDD and the second electrode plate C2 of the capacitor C. The drain D5 of the first light-emitting control transistor M5 is connected to the source S1 of the driving transistor M1 and the drain D2 of the switching transistor M2. The first light-emitting control transistor M5 is turned on or off according to the nth-level light-emitting control signal transmitted by the nth-level light-emitting control signal line EM(n), controlling whether the DC power supply signal transmitted by the DC power supply signal line VDD is written to the source S1 of the driving transistor M1.

[0056] The gate G6 of the second light-emitting control transistor M6 is connected to the nth-level light-emitting control signal line EM(n). The source S6 of the second light-emitting control transistor M6 is connected to the drain D1 of the driving transistor M1 and the source S3 of the compensation transistor M3. The drain D6 of the second light-emitting control transistor M6 is connected to the anode of the OLED. The second light-emitting control transistor M6 is turned on or off according to the nth-level light-emitting control signal transmitted by the nth-level light-emitting control signal line EM(n), controlling whether the driving current flows into the OLED.

[0057] The gate G7 of the anode reset transistor M7 is connected to the nth-level scan signal line SCAN(n). The drain D7 of the anode reset transistor M7 is connected to the drain D4 of the initialization transistor M4 and the initialization signal line VI. The source S7 of the anode reset transistor M7 is connected to the anode of the OLED and the drain D6 of the second light-emitting control transistor M6. The anode reset transistor M7 is turned on or off according to the nth-level scan signal transmitted by the nth-level scan signal line SCAN(n), controlling whether the initialization signal transmitted by the initialization signal line VI is written to the anode of the OLED.

[0058] The first electrode plate C1 of capacitor C is connected to the gate G1 of driving transistor M1, the source S4 of initialization transistor M4, and the drain D3 of compensation transistor M3. The second electrode plate C2 of capacitor C is connected to the DC power supply signal line VDD and the source S5 of the first light-emitting control transistor M5. Capacitor C is used to maintain the gate voltage of driving transistor M1 when driving the OLED to emit light.

[0059] Combination Figure 5 During the initialization phase t1, the (n-1)th level scan signal line SCAN(n-1) receives a low-level (n-1)th level scan signal, the initialization transistor M4 is turned on, and the initialization signal transmitted by the initialization signal line VI is transmitted to the gate G1 of the driving transistor M1, thereby initializing the gate G1 of the driving transistor M1; the nth level scan signal line SCAN(n) receives a high-level (n)th level scan signal, the switching transistor M2, the compensation transistor M3, and the anode reset transistor M7 are all turned off; the nth level light emission control signal line EM(n) receives a high-level (n)th level light emission control signal, the first light emission control transistor M5 and the second light emission control transistor M6 are both turned off.

[0060] During the threshold voltage compensation and data voltage writing stage t2, the (n-1)th level scan signal line SCAN(n-1) receives a high-level (n-1)th level scan signal, and the initialization transistor M4 is turned off; the nth level scan signal line SCAN(n) receives a low-level (n)th level scan signal, and the switching transistor M2, compensation transistor M3, and anode reset transistor M7 are all turned on. The turned-on switching transistor M2 writes the data signal transmitted by the data line D(m) to the source of the driving transistor M1. The turned-on compensation transistor M3 electrically connects the gate G1 and the drain D1 of the driving transistor M1. The turned-on anode reset transistor M7 outputs the initialization signal transmitted by the initialization signal line VI to the anode of the OLED. The nth level light emission control signal line EM(n) receives a high-level (n)th level light emission control signal, and the first light emission control transistor M5 and the second light emission control transistor M6 are both turned off. During this stage, the threshold voltage compensation of the driving transistor M1, the writing of the data signal, and the initialization of the anode of the OLED are achieved.

[0061] During the light-emitting stage t3, the (n-1)th level scan signal line SCAN(n-1) receives a high-level (n-1)th level scan signal, and the initialization transistor M4 is turned off; the nth level scan signal line SCAN(n) receives a high-level (n)th level scan signal, and the switching transistor M2, compensation transistor M3, and anode reset transistor M7 are all turned off; the nth level light-emitting control signal line EM(n) receives a low-level (n)th level light-emitting control signal, and the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are both turned on, the driving transistor M1 is turned on and outputs driving current, and the OLED light-emitting device emits light.

[0062] like Figure 6 As shown, the display device 100 includes a substrate 111. Each second pixel driving circuit 1011 includes a driving transistor M1, a capacitor, a compensation transistor M3, and a second light-emitting control transistor M6. The display device 100 also includes at least one transparent conductive layer disposed on the transition display area 100b and the display light-transmitting area 100a. The at least one transparent conductive layer is located above the plurality of pixel driving circuit islands 101, and the at least one transparent conductive layer includes a plurality of transparent wires 102. The second pixel driving circuits 1011 and the at least one transparent conductive layer are both disposed on the substrate 111. The substrate 111 can be a flexible substrate or a glass substrate.

[0063] The driving transistor M1 includes a driving active layer P1 and a driving gate 121. The opposite ends of the driving active layer P1 are doped to form a driving source 111b and a driving drain 111c, respectively. The second light-emitting control transistor M6 includes a second light-emitting control active layer P6 and a second light-emitting control gate. The opposite ends of the second light-emitting control active layer P6 are doped to form a second light-emitting control source 116b and a second light-emitting control drain 116c, respectively. The driving active layer P1 and the second light-emitting control active layer P6 are disposed in the same layer. The driving gate 121 is disposed in the same layer as the second light-emitting control gate. The compensation active layer of the compensation transistor M3 is disposed in the same layer as the driving active layer P1, and the compensation gate of the compensation transistor M3 is disposed in the same layer as the driving gate 121. The capacitor C includes a first electrode plate C1 and a second electrode plate C2, where the first electrode plate C1 is the driving gate 121.

[0064] A driving active layer P1 is disposed on a substrate 111, and a driving gate 121 is disposed above the driving active layer P1, with a first insulating layer 107 disposed between the driving active layer P1 and the driving gate 121. A second electrode plate C2 is disposed directly above the first electrode plate C1, with a second insulating layer 108 disposed between the driving gate 121 and the second electrode plate C2. A gate lead 141 is located above the driving transistor M1 and above the second electrode plate C2, with a third insulating layer 109 disposed between the gate lead 141 and the second electrode plate C2. One end of each gate lead 141 is electrically connected to the compensation active layer of the compensation transistor M3 of the second pixel driving circuit 1011 through a via penetrating the first insulating layer 107, the second insulating layer 108, and the third insulating layer 109, and the other end of the gate lead 141 is electrically connected to the driving gate 121 through a via penetrating the third insulating layer 109, the second electrode plate C2, and the second insulating layer 108. Gate lead 141, first anode lead 144, and DC power signal line VDD are located on the same film layer. DC power signal line VDD inputs and transmits DC power signals, and is electrically connected to the second electrode plate C2 through a via penetrating the third insulating layer 109. The first anode lead 144 is electrically connected to the second light-emitting control drain 116c of the second light-emitting control transistor M6 through a via penetrating the third insulating layer 109, the second insulating layer 108, and the first insulating layer 107. The second anode lead 153 is located directly above the first anode lead 144. There is a fourth insulating layer 110 between the second anode lead 153 and the first anode lead 144. The second anode lead 153 and the first anode lead 144 are electrically connected through a via penetrating the fourth insulating layer 110. Multiple transparent wires 102 are located above the second anode lead 153. The multiple transparent wires 102 are electrically connected to the second anode lead 153 and are also electrically connected to the anode of the light-emitting device OLED, so that the multiple transparent wires 102 electrically connect multiple light-emitting devices OLED and part of the second pixel driving circuit 1011. The first insulating layer 107, the second insulating layer 108, and the third insulating layer 109 are all inorganic insulating layers, and the materials used to prepare the first insulating layer 107, the second insulating layer 108, and the third insulating layer 109 are selected from at least one of silicon nitride and silicon oxide. The fourth insulating layer 110 is an organic insulating layer, and the material used to prepare the organic insulating layer is selected from polyimide.

[0065] Multiple transparent wires 102 are located in multiple transparent conductive layers to increase the layout space of the transparent wires 102 and avoid short circuits between the transparent wires 102 due to insufficient layout space. The transparent wires 102 are made of at least one of indium tin oxide or indium zinc oxide. An organic insulating layer is provided between the transparent wires 102 located in adjacent film layers.

[0066] The display device includes a shielding layer 151 disposed in the transition display area 100b. The shielding layer 151 is located between multiple gate leads 141 and at least one transparent conductive layer, and is disposed corresponding to the gate leads 141. The shielding layer 151 shields the parasitic capacitance between the gate leads 141 and the transparent conductor 102, preventing the gate potential of the driving transistor M1 from becoming unstable due to parasitic capacitance, and preventing the parasitic capacitance difference from causing a large difference in the influence of the parasitic capacitance on the gate potential of the driving transistor M1, thereby improving the working stability of the driving transistor M1 and avoiding the problem of uneven display in the display light-transmitting area 100a of the display device.

[0067] In the thickness direction of the display device 100, the orthographic projection of the multiple gate leads 141 on the substrate 111 of the display device 100 is located inside the orthographic projection of the shielding layer 151 on the substrate 111 of the display device 100, so that the area of ​​the shielding layer 151 corresponding to the gate lead 141 is larger than the area of ​​the gate lead 141, so that the shielding layer 151 completely shields the corresponding gate lead 141, and completely avoids the generation of parasitic capacitance between the multiple gate leads 141 and the multiple transparent wires 102.

[0068] The display device 100 also includes a metal mesh 152 for transmitting DC voltage signals, with a shielding layer 151 disposed on the same layer as the metal mesh 152. A portion of the metal mesh 152 is disposed directly above the plurality of pixel driving circuit islands 101, and a portion of the metal mesh 152 is disposed in the main display area 100c, with the metal mesh 152 in the main display area 100c electrically connected to the metal mesh 152 directly above the plurality of pixel driving circuit islands 101. The metal mesh 152 is electrically connected to the DC power signal line VDD to reduce the resistance voltage drop of the DC power signal transmitted through the DC power line VDD. The metal mesh 152 is mesh-shaped. The material used to fabricate the metal mesh 152 is selected from at least one of molybdenum, aluminum, titanium, and copper.

[0069] A metal mesh 152, located in the transition display area 100b and above the images of multiple second pixel driving circuits 1011, extends a shielding layer 151 to transmit a fixed voltage signal. A parasitic capacitance is formed between the shielding layer 151 and the gate lead 141. However, the potential of the shielding layer 151 is stable, which also ensures the potential stability of the gate lead 141. This avoids the potential instability of the transparent wire 102, which leads to the potential instability of the gate lead 141. This improves the stability of the gate potential of the driving transistor M1, enhances the working stability of the driving transistor M1, and further improves the brightness uniformity of the sub-pixels driven by the driving transistor M1.

[0070] The DC voltage signal is selected from either an initialization signal or a DC power signal. Since the initialization signal is transmitted via the initialization signal line VI, it can be electrically connected to the metal mesh 152, allowing the metal mesh 152 to transmit the DC voltage signal. The initialization signal line VI is disposed on the same layer as the second electrode plate C2. The DC power signal is transmitted via the DC power signal line VDD, which can also be electrically connected to the metal mesh 152, allowing the metal mesh 152 to transmit the DC voltage signal, thus giving the shielding layer 151 a fixed voltage.

[0071] The display device 100 also includes multiple DC power signal lines VDD. As mentioned above, the multiple DC power signal lines VDD are disposed on the same layer as the multiple gate leads 141, and the metal mesh 152 is electrically connected to the multiple DC power signal lines VDD.

[0072] A portion of the DC power signal lines VDD are located in the transition display area 100b and correspond to multiple pixel driving circuit islands 101, and are electrically connected to the second pixel driving circuit 1011 of the multiple pixel driving circuit islands 101; a portion of the DC power signal lines VDD are located in the main display area 100c and are electrically connected to the first pixel driving circuit. A portion of the metal mesh 152 corresponding to the multiple pixel driving circuit islands 101 corresponds to multiple DC power signal lines VDD in the transition display area 100b, meaning that the portion of the metal mesh 152 corresponding to the multiple pixel driving circuit islands 101 is located directly above the multiple DC power signal lines VDD in the transition display area 100b, so that the traces transmitting the same signal are correspondingly arranged, avoiding electrical signal interference.

[0073] Because the driving power of the first pixel driving circuit in the main display area 100c is different from that of the second pixel driving circuit 1011 in the pixel driving circuit island 101, the width of the DC power signal line VDD in the main display area 100c is larger than that in the transition display area 100b. When the width of the DC power signal line VDD in the transition display area 100b is smaller, the fourth insulating layer 110 provides a via 110a in part of the main display area 100c. The DC power signal line VDD of the main display area 100c is electrically connected to the metal mesh 152 of the main display area 100c through the via 110a. And because the metal mesh 152 of the main display area 100c is connected to the metal mesh 152 of the transition display area 100b, the DC power signal line VDD of the transition display area 100b is electrically connected to the metal mesh 152 of the transition display area 100b. When the width of the DC power signal line VDD of the transition display area 100b is large, the DC power signal line VDD of the transition display area 100b and the metal mesh 152 of the transition display area 100b can also be electrically connected through the vias provided in the fourth insulating layer 110 corresponding to the transition display area 100b.

[0074] A portion of the transparent wire 102 extends from the transition display area 100b to the display light-transmitting area 100a, and the portion of the transparent wire 102 is located in the transition display area 100b, so that the transparent wire 102 connects the second pixel driving circuit 1011 of the transition display area 100b and the second display pixel of the display light-transmitting area 100a.

[0075] The above solution will be described in detail below with reference to specific embodiments. Figure 7 This is a planar schematic diagram of the second pixel driving circuit and the wiring connected to it. Figures 8-12 To form Figure 7 The diagram shows the second pixel driving circuit and the multiple film layers connected to the second pixel driving circuit. Figure 8 For patterned semiconductor layers, Figure 9 To pattern the first metal layer, Figure 10 To pattern the second metal layer, Figure 11 To pattern the third metal layer, Figure 12 For patterning the fourth metal layer. Figure 8 The patterned semiconductor layer shown Figure 9 The first insulating layer 107 is disposed between the patterned first metal layers shown. Figure 9 The patterned first metal layer shown Figure 10 The aforementioned second insulating layer 108 is disposed between the patterned second metal layers shown. Figure 10 The patterned second metal layer shown Figure 11 The aforementioned third insulating layer 109 is disposed between the patterned third metal layers shown. Figure 11 The patterned third metal layer shown Figure 12 The fourth insulating layer 110 is provided between the patterned fourth metal layers shown.

[0076] The traces connected to the second pixel driving circuit 1011 include data line D(m), initialization signal line VI, nth level scan signal line SCAN(n), (n-1)th level scan signal line SCAN(n-1), nth level light emission control signal line EM(n), and DC power supply signal line VDD.

[0077] The second pixel driving circuit 1011 includes a driving transistor M1, a switching transistor M2, a compensation transistor M3, an initialization transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, an anode reset transistor M7, and a capacitor.

[0078] The patterned semiconductor layer 11 includes a driving channel 111a for driving transistor M1, a switching channel 112a for switching transistor M2, a compensation channel 113a for compensation transistor M3, an initialization channel 114a for initialization transistor M4, a first light-emitting control channel 115a for first light-emitting control transistor M5, a second light-emitting control channel 116a for second light-emitting control transistor M6, and an anode reset channel 117a for anode reset transistor M7. The driving channel 111a, switching channel 112a, compensation channel 113a, initialization channel 114a, first light-emitting control channel 115a, second light-emitting control channel 116a, and anode reset channel 117a are all located in the same layer. The patterned semiconductor layer 11 can be fabricated using polycrystalline silicon. The patterned semiconductor layer 11 also includes a driving source 111b and a driving drain 111c for driving transistor M1. The patterned semiconductor layer 11 also includes a switching source 112b and a switching drain 112c for switching transistor M2. The patterned semiconductor layer 11 also includes a compensation source 113b and a compensation drain 113c for the compensation transistor M3. The patterned semiconductor layer 11 also includes an initialization source 114b and an initialization drain 114c. The patterned semiconductor layer 11 also includes a first light-emitting control source 115b and a first light-emitting control drain 115c for the first light-emitting control transistor M5. The patterned semiconductor layer 11 also includes a second light-emitting control source 116b and a second light-emitting control drain 116c for the second light-emitting control transistor M6. The patterned semiconductor layer 11 also includes an anode reset source 117b and an anode reset drain 117c for the anode reset transistor M7. The source and drain on the patterned semiconductor layer 11 are obtained by doping the active layer to achieve conductor formation.

[0079] The patterned first metal layer 12 includes a driving gate 121 of driving transistor M1, which is also the first electrode plate C1 of the capacitor. The switching gate 122 of switching transistor M2 and the compensation gate 123 of compensation transistor M3 are both part of the nth level scan signal line SCAN(n). The compensation gate 124 of initialization transistor M4 is part of the (n-1)th level scan signal line SCAN(n-1). The first light-emitting control gate 125 of the first light-emitting control transistor M5 and the second light-emitting control gate 126 of the second light-emitting control transistor M6 are both part of the nth level light-emitting control signal line EM(n). The anode reset gate 127 of anode reset transistor M7 is part of the nth level scan signal line SCAN(n). The (n-1)th level scan signal line SCAN(n-1), the nth level light emission control signal line EM(n), the two nth level scan signal lines SCAN(n), and the driving gate 121 of the driving transistor M1 all belong to the patterned first metal layer 12. The (n-1)th level scan signal line SCAN(n-1), the nth level light emission control signal line EM(n), and the nth level scan signal line SCAN(n) are all arranged in parallel with each other. The driving gate 121 of the driving transistor M1 is rectangular in shape. The material used to fabricate the patterned first metal layer 12 includes at least one of molybdenum, aluminum, titanium, and copper.

[0080] The patterned second metal layer 13 includes two initialization signal lines VI and a second electrode plate C2. The second electrode plate C2 is disposed corresponding to the driving gate 121 of the driving transistor M1, and the driving gate 121 and the second electrode plate C2 form a capacitor. A via C2a is disposed on the second electrode plate C2. The material used to fabricate the patterned second metal layer 13 includes at least one of molybdenum, aluminum, titanium, and copper.

[0081] The patterned third metal layer 14 includes a gate lead 141, a first initialization lead 142, a second initialization lead 143, a data line D(m), a DC power signal line VDD, and a first anode lead 144. One end of the gate lead 141 is electrically connected to the driving gate 121 of the driving transistor M1 through a first via 141a penetrating the third insulating layer 109, the second insulating layer 108, and the second electrode plate C2. The other end of the gate lead 141 is electrically connected to the compensation drain of the compensation transistor M3 through a second via 141b penetrating the third insulating layer 109, the first insulating layer 107, and the second insulating layer 108. One end of the first initialization lead 142 is electrically connected to the initialization signal line VI through a third via 142a penetrating the third insulating layer 109. The other end of the first initialization lead 142 is electrically connected to the initialization drain 114c of the initialization transistor M4 through a fourth via 142b penetrating the third insulating layer 109, the second insulating layer 108, and the first insulating layer 107. One end of the second initialization lead 143 is electrically connected to the initialization signal line VI through a fifth via 143a penetrating the third insulating layer 109. The other end of the second initialization lead 143 is electrically connected to the anode reset drain 117c of the anode reset transistor M7 through a sixth via 143b penetrating the third insulating layer 109, the second insulating layer 108, and the first insulating layer 107. The first anode lead 144 is electrically connected to the second light-emitting control drain 116c of the second light-emitting control transistor M6 through a seventh via 144a penetrating the third insulating layer 109, the second insulating layer 108, and the first insulating layer 107. The data line D(m) is electrically connected to the switching source 112b of the switching transistor M2 through an eighth via 145a penetrating the third insulating layer 109, the second insulating layer 108, and the first insulating layer 107. The DC power signal line VDD is electrically connected to the first light-emitting control source 115b of the first light-emitting control transistor M5 through a ninth via 146b that passes through the third insulating layer 109, the second insulating layer 108, and the first insulating layer 107. The DC power signal line VDD is also electrically connected to the second electrode plate C2 through a tenth via 146a that passes through the third insulating layer 109, allowing the second electrode plate C2 to receive the DC power signal. The material used to fabricate the patterned third metal layer 14 includes at least one of molybdenum, aluminum, titanium, and copper. The DC power signal line VDD is arranged parallel to the data line D(m), and the data line D(m) intersects perpendicularly with the initialization signal line VI and the nth level scan signal line SCAN(n).

[0082] The patterned fourth metal layer 15 includes a metal mesh 152, a shielding layer 151, and a second anode lead 153. The metal mesh 152 includes a vertical extension 1521 and a horizontal extension 1522, which intersect perpendicularly to form a mesh-like metal mesh 152. The vertical extension 1521 corresponds to the DC power signal line VDD, and the horizontal extension 1522 partially overlaps with the second electrode plate C2, so that the traces for transmitting the DC power signal are correspondingly arranged. The second anode lead 153 is disposed directly above the first anode lead 144 and connected to the first anode lead 144 through a via penetrating the fourth insulating layer 110. The aforementioned transparent conductive layer is located above the patterned fourth metal layer 15, and the transparent conductor 102 connects the second anode lead 153 and the anode of the OLED light-emitting device. The metal mesh 152 can be connected to the DC power signal line VDD through the via penetrating the fourth insulating layer 110 to introduce the DC power signal. The materials used to prepare the patterned fourth metal layer 15 include at least one of molybdenum, aluminum, titanium, and copper.

[0083] This application also provides an electronic device, which includes the aforementioned display device and a photosensitive unit, wherein the photosensitive unit is disposed corresponding to the display light-transmitting area of ​​the display device. The photosensitive unit is a camera.

[0084] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display device, characterized by comprising: The display device has a first display area and a second display area, the second display area is located at the periphery of the first display area, the light transmittance of the first display area is greater than that of the second display area, and the display device comprises: a substrate; a plurality of light emitting devices located on the substrate, and at least part of the light emitting devices are arranged in the first display area; a plurality of pixel driving circuits located on the substrate, at least one of the pixel driving circuits comprises: a driving transistor comprising a gate; and a gate lead wire located on the side of the driving transistor away from the substrate and connected with the gate of the driving transistor; at least one transparent conductive layer located on the side of the plurality of pixel driving circuits away from the substrate and comprising a plurality of transparent conductive lines, at least part of the transparent conductive lines connecting the light emitting devices of the first display area with at least part of the pixel driving circuits; and a metal layer located between the film layer where the gate lead wire is located and the at least one transparent conductive layer, and the orthogonal projection of the metal layer on the substrate overlaps with the orthogonal projection of the gate lead wire on the substrate; a metal mesh for transmitting a direct current voltage signal, the metal mesh is at least located in the second display area and extends out of the metal layer.

2. The display device according to claim 1, wherein The orthogonal projection of the plurality of gate lead wires on the substrate is located inside the orthogonal projection of the metal layer on the substrate.

3. The display device according to claim 1 or 2, wherein The plurality of pixel driving circuits are located in the second display area; The metal mesh comprises a vertical extension and a horizontal extension, the vertical extension and the horizontal extension are perpendicular to each other, and the metal layer is connected with the vertical extension and the horizontal extension.

4. The display device according to claim 1, wherein The display device further comprises a plurality of direct current power supply signal lines, the plurality of direct current power supply signal lines are arranged in the same layer as the plurality of gate lead wires, and the metal mesh is electrically connected with the plurality of direct current power supply signal lines.

5. The display device according to claim 4, wherein The display device further has a third display area, the second display area is located between the third display area and the first display area, the metal mesh is also located in the third display area, an insulating layer is arranged between the plurality of direct current power supply signal lines and the metal mesh, the insulating layer comprises a via located in the third display area, and the metal mesh is electrically connected with the plurality of direct current power supply signal lines through the via.

6. The display device according to claim 3, wherein The direct current voltage signal is selected from one of an initialization signal and a direct current power supply signal.

7. The display device according to claim 1, wherein The pixel driving circuit further comprises a compensation transistor and an electrode plate, the electrode plate is arranged corresponding to the gate of the driving transistor and is located between the gate lead wire and the gate of the driving transistor, one end of the gate lead wire is electrically connected with the active layer of the compensation transistor of the pixel driving circuit, and the other end of the gate lead wire is connected with the gate of the driving transistor through at least a via on the electrode plate.

8. The display device according to claim 1, wherein Part of the transparent conductive lines extend from the second display area to the first display area, and another part of the transparent conductive lines are located in the second display area.

9. The display device according to claim 1, wherein The display device comprises a plurality of transparent conductive layers, and the plurality of transparent conductive lines are located in different transparent conductive layers.

10. The display device according to claim 1, wherein A plurality of the pixel driving circuit forms a plurality of pixel driving circuit islands, a spacing between two adjacent pixel driving circuit islands is greater than a spacing between two adjacent pixel driving circuits in a pixel driving circuit island, and the plurality of pixel driving circuit islands are arranged around the first display area; and / or, The number of the pixel driving circuits in at least two pixel driving circuit islands is different; and / or, The first display area has a circular shape.

11. An electronic device, comprising: The electronic device comprises the display device according to any one of claims 1-10 and a photosensitive unit corresponding to the first display area of the display device.

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