Reference voltage circuit and semiconductor device

Abstract

Reference voltage circuit and semiconductor device. A reference voltage circuit includes a depletion transistor as a current source and an enhancement transistor as a load, the reference voltage circuit is composed of a plurality of transistors, the plurality of transistors have the depletion transistor composed of at least one depletion transistor including a first depletion transistor and the enhancement transistor composed of at least one enhancement transistor including a first enhancement transistor connected in series with the first depletion transistor, and the plurality of transistors in which the depletion transistors and the enhancement transistors exist mixed are arranged in a common centroid manner, the common centroid being a common center of gravity.

Description

[0001] This application is a divisional application of the invention patent application filed on May 30, 2018, with application number 201810535941.3 and title "Reference Voltage Circuit and Semiconductor Device". Technical Field

[0002] This invention relates to a reference voltage circuit and a semiconductor device. Background Technology

[0003] As a reference voltage circuit, it is known Figure 7 The reference voltage circuit 700 shown is a combination of a depletion-type transistor and an enhancement-type transistor (see, for example, Japanese Patent No. 2012-531825 1).

[0004] The reference voltage circuit 700 includes a depletion-type transistor 710, an enhancement-type transistor 720, and a terminal 730 for outputting the reference voltage VREF.

[0005] Reference Figure 8 The operation of the reference voltage circuit 700 will be explained below. If the threshold voltage of transistor 710 is set to VTND, then the voltage-current relationship of transistor 710 is expressed as in characteristic 801. If the threshold voltage of transistor 720 is set to VTNE, then the voltage-current relationship of transistor 720 is expressed as in characteristic 802. The voltage generated by the current flowing into enhancement-mode transistor 720, which is equal to the intercept value of characteristic 801, is output to terminal 730 as the reference voltage VREF.

[0006] Patent Document 1: Japanese Patent Publication No. 2012-531825 Summary of the Invention

[0007] Generally speaking, the characteristics of known semiconductor devices are affected by the stress generated by resin sealing (encapsulation).

[0008] For example, when a semiconductor device in which transistors 710 and 720 are arranged in the x-axis direction is sealed with resin, the characteristics of transistors 710 and 720 may deviate when stress is applied in the x-axis direction. That is, characteristics 801 and 802 may deviate from the desired characteristics.

[0009] The present invention was made to avoid the influence of characteristic changes caused by stress in the resin seals of semiconductor devices, and provides a semiconductor device having a reference voltage circuit with minimal product variation.

[0010] Methods for solving problems

[0011] The reference voltage circuit of the present invention is characterized in that: the depletion-type transistor and / or the enhancement-type transistor are composed of multiple transistors, and the depletion-type transistor and the enhancement-type transistor are configured in a common centroid manner, which is a common center of gravity.

[0012] Invention Effects

[0013] According to the reference voltage circuit of the present invention, a semiconductor device can be provided that has a reference voltage circuit that avoids the influence of characteristic changes caused by stress in the resin seal of the conductor device and has minimal product variation. Attached Figure Description

[0014] Figure 1 This is an explanatory diagram showing the reference voltage circuit of the first embodiment of the present invention.

[0015] Figure 2 This is an illustrative diagram showing another example of the reference voltage circuit of the first embodiment.

[0016] Figure 3 This is an illustrative diagram showing another example of the reference voltage circuit of the first embodiment.

[0017] Figure 4 This is an illustrative diagram showing another example of the reference voltage circuit of the first embodiment.

[0018] Figure 5 This is an illustrative diagram showing another example of the reference voltage circuit of the first embodiment.

[0019] Figure 6 This is an explanatory diagram showing the reference voltage circuit of the second embodiment of the present invention.

[0020] Figure 7 This is a circuit diagram showing a typical reference voltage circuit.

[0021] Figure 8 yes Figure 7 The diagram illustrates the operation of the reference voltage circuit.

[0022] Label Explanation

[0023] 110, 210, 410, 610: Depletion-type transistors; 120, 220, 420, 620: Enhancement-type transistors; 640, 650: Transistors; 130: Terminal. Detailed Implementation

[0024] Figure 1 This is an explanatory diagram showing the reference voltage circuit of the first embodiment of the present invention.

[0025] The reference voltage circuit 100 includes a depletion-type transistor 110, an enhancement-type transistor 120, and a terminal 130 for outputting the reference voltage VREF.

[0026] Transistor 110 is constructed by connecting two depletion-type transistors 111 and 112 in series. Transistor 120 is constructed by connecting two enhancement-type transistors 121 and 122 in series.

[0027] The reference voltage circuit 100 operates in the same way as a typical reference voltage circuit consisting of a depletion-type transistor 110 and an enhancement-type transistor 120, outputting the reference voltage VREF to terminal 130.

[0028] Here, transistors 111 and 112 of the reference voltage circuit 100 are of the same size (length W and length L), and transistors 121 and 122 are of the same size (length W and length L). Furthermore, as... Figure 1 As shown, transistors 111, 112, 121, and 122 are arranged in a manner that is approximately at the same centroid (common center of gravity) on the semiconductor device.

[0029] That is, transistors 111, 112, 121, and 122 are configured in a point-symmetric manner to achieve a common centroid (common center of mass).

[0030] In the reference voltage circuit 100 configured as described above, even if the characteristics of the transistors change in the x-axis or y-axis direction due to stress from resin sealing or the like, transistors 110 and 120 are affected in the same way. Therefore, transistors 110 and 120 can produce the same characteristic variation, thus having the effect of reducing the deviation of the varied characteristics from the desired voltage and current characteristics.

[0031] As described above, in the reference voltage circuit 100, transistors 110 and 120 are arranged in a manner that is approximately concentric on the semiconductor device. Therefore, it is possible to provide a semiconductor device that has a reference voltage circuit that avoids the influence of characteristic variations caused by stress from the resin seal of the semiconductor device, etc., and has minimal product variation.

[0032] Figure 2 This is an illustrative diagram showing another example of the reference voltage circuit of the first embodiment.

[0033] In the reference voltage circuit 200, three transistors each constitute a depletion-type transistor 210 and an enhancement-type transistor 220.

[0034] Transistor 210 is constructed by connecting three depletion-type transistors 211, 212, and 213 in series. Transistor 220 is constructed by connecting three transistors 221, 222, and 223 in series.

[0035] Here, the transistors are configured in the same way as in the reference voltage circuit 100, such as... Figure 2 As shown, they are arranged approximately at the same centroid (common center of gravity) on the semiconductor device. The reference voltage circuit 200 constructed in this way can also achieve the same effect.

[0036] In addition, the reference voltage circuit 200 can also be used as follows: Figure 3 As shown, they are arranged in a manner that is approximately at the same centroid (common center of gravity) on the semiconductor device. That is, transistors 211, 212, 223 and transistors 213, 221, 222 are arranged in a line-symmetrical manner to achieve a common centroid (common center of gravity).

[0037] Figure 4 This is an illustrative diagram showing another example of the reference voltage circuit of the first embodiment.

[0038] In the reference voltage circuit 400, two transistors each constitute a depletion-type transistor 410 and an enhancement-type transistor 420.

[0039] Transistor 410 is constructed by connecting two depletion-type transistors 411 and 412 in parallel. Transistor 420 is constructed by connecting two enhancement-type transistors 421 and 422 in parallel.

[0040] Reference voltage circuit 400 and Figure 1 The reference voltage circuit 100 is similarly configured in a manner that is approximately at the same centroid (common center of gravity) on the semiconductor device. The reference voltage circuit 400 configured in this way can also achieve the same effect.

[0041] In addition, in the reference voltage circuit 400, each transistor is configured by connecting two transistors in parallel, but more than two transistors can also be connected in parallel, and they are arranged in a manner that is approximately at the same centroid (common center of gravity) on the semiconductor device.

[0042] Figure 5 This is an illustrative diagram showing another example of the reference voltage circuit of the first embodiment.

[0043] The reference voltage circuit 500 includes a depletion-type transistor 110, an enhancement-type transistor 120, and a terminal 130 for outputting the reference voltage VREF. Transistor 120 is configured by connecting two enhancement-type transistors 121 and 122 in series.

[0044] exist Figure 1 In the reference voltage circuit 100, the depletion-type transistor 110 is constructed by connecting two depletion-type transistors 111 and 112 in series, but as Figure 5 As shown, even if it consists of a single transistor, it can be configured in a manner that is approximately at the common centroid (common center of gravity) on the semiconductor device.

[0045] In addition, Figure 5 In the reference voltage circuit 500, an example of a depletion-type transistor 110 consisting of a single transistor is illustrated, but an enhancement-type transistor 120 can also be consisting of a single transistor.

[0046] The reference voltage circuit of the first embodiment described above uses one to three transistors to form each transistor, but more than three transistors can be connected in series or in parallel and arranged in a manner that is approximately at the same centroid (common center of gravity) on the semiconductor device.

[0047] Figure 6 This is an explanatory diagram showing the reference voltage circuit of the second embodiment of the present invention.

[0048] The reference voltage circuit 600 includes a depletion-type transistor 610, an enhancement-type transistor 620, and transistors 640 and 650 constituting a current mirror circuit. The reference voltage circuit 600 is constructed by combining transistors 610 and 620 through a current mirror circuit, and its basic operation is the same as that of the reference voltage circuit in the first embodiment. Like the reference voltage circuit in the first embodiment, the reference voltage circuit 600 is composed of multiple transistors.

[0049] Transistor 610 is constructed by connecting two depletion-type transistors 611 and 612 in series. Transistor 620 is constructed by connecting two transistors 621 and 622 in series. Transistor 640 is constructed by connecting two transistors 641 and 642 in series. Transistor 650 is constructed by connecting two transistors 651 and 652 in series.

[0050] Each transistor is configured in the same manner as the reference voltage circuit in the first embodiment. Furthermore, for example, similar to the reference voltage circuit 100, transistors 610 and 620 are arranged in a manner that is substantially at the same centroid (common centroid) on the semiconductor device, and transistors 640 and 650 are arranged in a manner that is substantially at the same centroid (common centroid) on the semiconductor device. The reference voltage circuit 600 configured in this way can also achieve the same effect.

[0051] In addition, in the reference voltage circuit 600 of the second embodiment, each transistor is composed of two transistors, but two or more transistors may be connected in series or in parallel as in the first embodiment, and they may be arranged in such a way that they are approximately at the same centroid (common centroid) on the semiconductor device.

Claims

1. A reference voltage circuit comprising a depletion-mode transistor as a current source and an enhancement-mode transistor as a load, characterized in that, The reference voltage circuit is composed of multiple transistors, including depletion-type transistors and enhancement-type transistors. The depletion-type transistors are formed by connecting multiple first depletion-type transistors, and the enhancement-type transistors are formed by connecting multiple first enhancement-type transistors connected in series with the multiple first depletion-type transistors. The plurality of first depletion-type transistors are the same number as the plurality of first enhancement-type transistors, and the plurality of transistors, which are alternately mixed with the enhancement-type transistors, are configured in a common centroid manner, which is a common center of gravity.

2. The reference voltage circuit according to claim 1, wherein, The depletion-type transistor and the enhancement-type transistor are configured in a point-symmetric manner.

3. The reference voltage circuit according to claim 1, characterized in that, The depletion-type transistor and the enhancement-type transistor are configured in a line-symmetric manner.

4. The reference voltage circuit according to claim 1, characterized in that, The depletion-type transistor and the enhancement-type transistor are connected via a current mirror circuit.

5. The reference voltage circuit according to claim 4, characterized in that, The transistor constituting the current mirror circuit is composed of multiple transistors. The plurality of transistors are configured in a common centroid manner, which is a common center of gravity.

6. A semiconductor device comprising a reference voltage circuit according to any one of claims 1 to 5.

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